drivers/net/fm/p3060.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19 #include <common.h>
  20 #include <phy.h>
  21 #include <fm_eth.h>
  22 #include <asm/io.h>
  23 #include <asm/immap_85xx.h>
  24 #include <asm/fsl_serdes.h>
  25
  26 u32 port_to_devdisr[] = {
  27         [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
  28         [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
  29         [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
  30         [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
  31         [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
  32         [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
  33         [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
  34         [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
  35 };
  36
  37 static int is_device_disabled(enum fm_port port)
  38 {
  39         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  40         u32 devdisr2 = in_be32(&gur->devdisr2);
  41
  42         return port_to_devdisr[port] & devdisr2;
  43 }
  44
  45 void fman_disable_port(enum fm_port port)
  46 {
  47         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  48         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  49 }
  50
  51 phy_interface_t fman_port_enet_if(enum fm_port port)
  52 {
  53         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  54         u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
  55         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  56
  57         if (is_device_disabled(port))
  58                 return PHY_INTERFACE_MODE_NONE;
  59
  60         /* handle RGMII/MII first */
  61         if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
  62                 FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
  63                 return PHY_INTERFACE_MODE_RGMII;
  64
  65         if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  66                 FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
  67                 return PHY_INTERFACE_MODE_RGMII;
  68
  69         if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
  70                 FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
  71                 return PHY_INTERFACE_MODE_RGMII;
  72
  73         if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
  74                 FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_RGMII))
  75                 return PHY_INTERFACE_MODE_RGMII;
  76
  77         if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1_EXT) ==
  78                 FSL_CORENET_RCWSR13_EC1_EXT_FM1_DTSEC4_MII))
  79                 return PHY_INTERFACE_MODE_MII;
  80
  81         if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
  82                 FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_RGMII))
  83                 return PHY_INTERFACE_MODE_RGMII;
  84
  85         if ((port == FM2_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2_EXT) ==
  86                 FSL_CORENET_RCWSR13_EC2_EXT_FM2_DTSEC4_MII))
  87                 return PHY_INTERFACE_MODE_MII;
  88
  89         switch (port) {
  90         case FM1_DTSEC1:
  91         case FM1_DTSEC2:
  92         case FM1_DTSEC3:
  93         case FM1_DTSEC4:
  94                 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
  95                         return PHY_INTERFACE_MODE_SGMII;
  96                 break;
  97         case FM2_DTSEC1:
  98         case FM2_DTSEC2:
  99         case FM2_DTSEC3:
 100         case FM2_DTSEC4:
 101                 if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
 102                         return PHY_INTERFACE_MODE_SGMII;
 103                 break;
 104         default:
 105                 return PHY_INTERFACE_MODE_NONE;
 106         }
 107
 108         return PHY_INTERFACE_MODE_NONE;
 109 }