2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Andy Fleming <afleming@gmail.com>
4 * Roy Zang <tie-fei.zang@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
7 * Some part is taken from tsec.c
13 #include <asm/fsl_memac.h>
17 * Write value to the PHY for this device to the register at regnum, waiting
18 * until the write is done before it returns. All PHY configuration has to be
19 * done through the TSEC1 MIIM regs
21 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
22 int regnum, u16 value)
25 struct memac_mdio_controller *regs = bus->priv;
26 u32 c45 = 1; /* Default to 10G interface */
28 if (dev_addr == MDIO_DEVAD_NONE) {
29 c45 = 0; /* clause 22 */
30 dev_addr = regnum & 0x1f;
31 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
33 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
35 /* Wait till the bus is free */
36 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
39 /* Set the port and dev addr */
40 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
41 out_be32(®s->mdio_ctl, mdio_ctl);
43 /* Set the register address */
45 out_be32(®s->mdio_addr, regnum & 0xffff);
47 /* Wait till the bus is free */
48 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
51 /* Write the value to the register */
52 out_be32(®s->mdio_data, MDIO_DATA(value));
54 /* Wait till the MDIO write is complete */
55 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
62 * Reads from register regnum in the PHY for device dev, returning the value.
63 * Clears miimcom first. All PHY configuration has to be done through the
66 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
70 struct memac_mdio_controller *regs = bus->priv;
73 if (dev_addr == MDIO_DEVAD_NONE) {
74 if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
76 c45 = 0; /* clause 22 */
77 dev_addr = regnum & 0x1f;
78 clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
80 setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
82 /* Wait till the bus is free */
83 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
86 /* Set the Port and Device Addrs */
87 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
88 out_be32(®s->mdio_ctl, mdio_ctl);
90 /* Set the register address */
92 out_be32(®s->mdio_addr, regnum & 0xffff);
94 /* Wait till the bus is free */
95 while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
98 /* Initiate the read */
99 mdio_ctl |= MDIO_CTL_READ;
100 out_be32(®s->mdio_ctl, mdio_ctl);
102 /* Wait till the MDIO write is complete */
103 while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
106 /* Return all Fs if nothing was there */
107 if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
110 return in_be32(®s->mdio_data) & 0xffff;
113 int memac_mdio_reset(struct mii_dev *bus)
118 int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
120 struct mii_dev *bus = mdio_alloc();
123 printf("Failed to allocate FM TGEC MDIO bus\n");
127 bus->read = memac_mdio_read;
128 bus->write = memac_mdio_write;
129 bus->reset = memac_mdio_reset;
130 sprintf(bus->name, info->name);
132 bus->priv = info->regs;
135 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
136 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
137 * (much higher than 2.5MHz), violating the IEEE specs.
138 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
139 * is zero, so MDIO clock is disabled.
140 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
141 * be properly initialized.
143 setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat,
144 MDIO_STAT_CLKDIV(258));
146 return mdio_register(bus);