1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Andy Fleming <afleming@gmail.com>
5 * Roy Zang <tie-fei.zang@freescale.com>
6 * Some part is taken from tsec.c
12 #include <fsl_memac.h>
15 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
16 #define memac_out_32(a, v) out_le32(a, v)
17 #define memac_clrbits_32(a, v) clrbits_le32(a, v)
18 #define memac_setbits_32(a, v) setbits_le32(a, v)
20 #define memac_out_32(a, v) out_be32(a, v)
21 #define memac_clrbits_32(a, v) clrbits_be32(a, v)
22 #define memac_setbits_32(a, v) setbits_be32(a, v)
26 struct memac_mdio_controller *regs;
29 #define MAX_NUM_RETRIES 1000
31 static u32 memac_in_32(u32 *reg)
33 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
41 * Wait until the MDIO bus is free
43 static int memac_wait_until_free(struct memac_mdio_controller *regs)
45 unsigned int timeout = MAX_NUM_RETRIES;
47 while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--)
51 printf("timeout waiting for MDIO bus to be free\n");
59 * Wait till the MDIO read or write operation is complete
61 static int memac_wait_until_done(struct memac_mdio_controller *regs)
63 unsigned int timeout = MAX_NUM_RETRIES;
65 while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--)
69 printf("timeout waiting for MDIO operation to complete\n");
77 * Write value to the PHY for this device to the register at regnum, waiting
78 * until the write is done before it returns. All PHY configuration has to be
79 * done through the TSEC1 MIIM regs
81 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
82 int regnum, u16 value)
84 struct memac_mdio_controller *regs;
86 u32 c45 = 1; /* Default to 10G interface */
89 struct fm_mdio_priv *priv;
93 priv = dev_get_priv(bus->priv);
95 debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
96 regs, port_addr, dev_addr, regnum, value);
98 if (dev_addr == MDIO_DEVAD_NONE) {
99 c45 = 0; /* clause 22 */
100 dev_addr = regnum & 0x1f;
101 memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
103 memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
105 err = memac_wait_until_free(regs);
109 /* Set the port and dev addr */
110 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
111 memac_out_32(®s->mdio_ctl, mdio_ctl);
113 /* Set the register address */
115 memac_out_32(®s->mdio_addr, regnum & 0xffff);
117 err = memac_wait_until_free(regs);
121 /* Write the value to the register */
122 memac_out_32(®s->mdio_data, MDIO_DATA(value));
124 err = memac_wait_until_done(regs);
132 * Reads from register regnum in the PHY for device dev, returning the value.
133 * Clears miimcom first. All PHY configuration has to be done through the
136 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
139 struct memac_mdio_controller *regs;
144 struct fm_mdio_priv *priv;
148 priv = dev_get_priv(bus->priv);
151 if (dev_addr == MDIO_DEVAD_NONE) {
152 c45 = 0; /* clause 22 */
153 dev_addr = regnum & 0x1f;
154 memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
156 memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
158 err = memac_wait_until_free(regs);
162 /* Set the Port and Device Addrs */
163 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
164 memac_out_32(®s->mdio_ctl, mdio_ctl);
166 /* Set the register address */
168 memac_out_32(®s->mdio_addr, regnum & 0xffff);
170 err = memac_wait_until_free(regs);
174 /* Initiate the read */
175 mdio_ctl |= MDIO_CTL_READ;
176 memac_out_32(®s->mdio_ctl, mdio_ctl);
178 err = memac_wait_until_done(regs);
182 /* Return all Fs if nothing was there */
183 if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
186 return memac_in_32(®s->mdio_data) & 0xffff;
189 int memac_mdio_reset(struct mii_dev *bus)
194 #if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
195 static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
197 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
200 if (pdata && pdata->mii_bus)
201 return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
206 static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
209 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
212 if (pdata && pdata->mii_bus)
213 return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
218 static int fm_mdio_reset(struct udevice *dev)
220 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
223 if (pdata && pdata->mii_bus)
224 return memac_mdio_reset(pdata->mii_bus);
229 static const struct mdio_ops fm_mdio_ops = {
230 .read = fm_mdio_read,
231 .write = fm_mdio_write,
232 .reset = fm_mdio_reset,
235 static const struct udevice_id fm_mdio_ids[] = {
236 { .compatible = "fsl,fman-memac-mdio" },
240 static int fm_mdio_probe(struct udevice *dev)
242 struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
243 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
247 printf("%s dev = NULL\n", __func__);
251 printf("dev_get_priv(dev %p) = NULL\n", dev);
254 priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
255 debug("%s priv %p @ regs %p, pdata %p\n", __func__,
256 priv, priv->regs, pdata);
259 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
260 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
261 * (much higher than 2.5MHz), violating the IEEE specs.
262 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
263 * is zero, so MDIO clock is disabled.
264 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
265 * be properly initialized.
266 * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
267 * like T2080QDS, this bit default is '0', which leads to MDIO failure
268 * on XAUI PHY, so set this bit definitely.
270 if (priv && priv->regs && priv->regs->mdio_stat)
271 memac_setbits_32(&priv->regs->mdio_stat,
272 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
277 static int fm_mdio_remove(struct udevice *dev)
282 U_BOOT_DRIVER(fman_mdio) = {
285 .of_match = fm_mdio_ids,
286 .probe = fm_mdio_probe,
287 .remove = fm_mdio_remove,
289 .priv_auto = sizeof(struct fm_mdio_priv),
290 .plat_auto = sizeof(struct mdio_perdev_priv),
292 #endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */