1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 * Andy Fleming <afleming@gmail.com>
5 * Roy Zang <tie-fei.zang@freescale.com>
6 * Some part is taken from tsec.c
12 #include <fsl_memac.h>
15 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
16 #define memac_out_32(a, v) out_le32(a, v)
17 #define memac_clrbits_32(a, v) clrbits_le32(a, v)
18 #define memac_setbits_32(a, v) setbits_le32(a, v)
20 #define memac_out_32(a, v) out_be32(a, v)
21 #define memac_clrbits_32(a, v) clrbits_be32(a, v)
22 #define memac_setbits_32(a, v) setbits_be32(a, v)
27 struct memac_mdio_controller *regs;
31 #define MAX_NUM_RETRIES 1000
33 static u32 memac_in_32(u32 *reg)
35 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
43 * Wait until the MDIO bus is free
45 static int memac_wait_until_free(struct memac_mdio_controller *regs)
47 unsigned int timeout = MAX_NUM_RETRIES;
49 while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--)
53 printf("timeout waiting for MDIO bus to be free\n");
61 * Wait till the MDIO read or write operation is complete
63 static int memac_wait_until_done(struct memac_mdio_controller *regs)
65 unsigned int timeout = MAX_NUM_RETRIES;
67 while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) && timeout--)
71 printf("timeout waiting for MDIO operation to complete\n");
79 * Write value to the PHY for this device to the register at regnum, waiting
80 * until the write is done before it returns. All PHY configuration has to be
81 * done through the TSEC1 MIIM regs
83 int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
84 int regnum, u16 value)
86 struct memac_mdio_controller *regs;
88 u32 c45 = 1; /* Default to 10G interface */
94 struct fm_mdio_priv *priv;
98 priv = dev_get_priv(bus->priv);
100 debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
101 regs, port_addr, dev_addr, regnum, value);
104 if (dev_addr == MDIO_DEVAD_NONE) {
105 c45 = 0; /* clause 22 */
106 dev_addr = regnum & 0x1f;
107 memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
109 memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
111 err = memac_wait_until_free(regs);
115 /* Set the port and dev addr */
116 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
117 memac_out_32(®s->mdio_ctl, mdio_ctl);
119 /* Set the register address */
121 memac_out_32(®s->mdio_addr, regnum & 0xffff);
123 err = memac_wait_until_free(regs);
127 /* Write the value to the register */
128 memac_out_32(®s->mdio_data, MDIO_DATA(value));
130 err = memac_wait_until_done(regs);
138 * Reads from register regnum in the PHY for device dev, returning the value.
139 * Clears miimcom first. All PHY configuration has to be done through the
142 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
145 struct memac_mdio_controller *regs;
150 #ifndef CONFIG_DM_ETH
153 struct fm_mdio_priv *priv;
157 priv = dev_get_priv(bus->priv);
161 if (dev_addr == MDIO_DEVAD_NONE) {
162 #ifndef CONFIG_DM_ETH
163 if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
166 c45 = 0; /* clause 22 */
167 dev_addr = regnum & 0x1f;
168 memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
170 memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
172 err = memac_wait_until_free(regs);
176 /* Set the Port and Device Addrs */
177 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
178 memac_out_32(®s->mdio_ctl, mdio_ctl);
180 /* Set the register address */
182 memac_out_32(®s->mdio_addr, regnum & 0xffff);
184 err = memac_wait_until_free(regs);
188 /* Initiate the read */
189 mdio_ctl |= MDIO_CTL_READ;
190 memac_out_32(®s->mdio_ctl, mdio_ctl);
192 err = memac_wait_until_done(regs);
196 /* Return all Fs if nothing was there */
197 if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
200 return memac_in_32(®s->mdio_data) & 0xffff;
203 int memac_mdio_reset(struct mii_dev *bus)
208 #ifndef CONFIG_DM_ETH
209 int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info)
211 struct mii_dev *bus = mdio_alloc();
214 printf("Failed to allocate FM TGEC MDIO bus\n");
218 bus->read = memac_mdio_read;
219 bus->write = memac_mdio_write;
220 bus->reset = memac_mdio_reset;
221 strcpy(bus->name, info->name);
223 bus->priv = info->regs;
226 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
227 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
228 * (much higher than 2.5MHz), violating the IEEE specs.
229 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
230 * is zero, so MDIO clock is disabled.
231 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
232 * be properly initialized.
233 * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
234 * like T2080QDS, this bit default is '0', which leads to MDIO failure
235 * on XAUI PHY, so set this bit definitely.
238 &((struct memac_mdio_controller *)info->regs)->mdio_stat,
239 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
241 return mdio_register(bus);
244 #else /* CONFIG_DM_ETH */
245 #if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
246 static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
248 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
251 if (pdata && pdata->mii_bus)
252 return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
257 static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
260 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
263 if (pdata && pdata->mii_bus)
264 return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
269 static int fm_mdio_reset(struct udevice *dev)
271 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
274 if (pdata && pdata->mii_bus)
275 return memac_mdio_reset(pdata->mii_bus);
280 static const struct mdio_ops fm_mdio_ops = {
281 .read = fm_mdio_read,
282 .write = fm_mdio_write,
283 .reset = fm_mdio_reset,
286 static const struct udevice_id fm_mdio_ids[] = {
287 { .compatible = "fsl,fman-memac-mdio" },
291 static int fm_mdio_probe(struct udevice *dev)
293 struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
294 struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
298 printf("%s dev = NULL\n", __func__);
302 printf("dev_get_priv(dev %p) = NULL\n", dev);
305 priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
306 debug("%s priv %p @ regs %p, pdata %p\n", __func__,
307 priv, priv->regs, pdata);
310 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
311 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
312 * (much higher than 2.5MHz), violating the IEEE specs.
313 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
314 * is zero, so MDIO clock is disabled.
315 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
316 * be properly initialized.
317 * The default NEG bit should be '1' as per FMANv3 RM, but on platforms
318 * like T2080QDS, this bit default is '0', which leads to MDIO failure
319 * on XAUI PHY, so set this bit definitely.
321 if (priv && priv->regs && priv->regs->mdio_stat)
322 memac_setbits_32(&priv->regs->mdio_stat,
323 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
328 static int fm_mdio_remove(struct udevice *dev)
333 U_BOOT_DRIVER(fman_mdio) = {
336 .of_match = fm_mdio_ids,
337 .probe = fm_mdio_probe,
338 .remove = fm_mdio_remove,
340 .priv_auto = sizeof(struct fm_mdio_priv),
341 .plat_auto = sizeof(struct mdio_perdev_priv),
343 #endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
344 #endif /* CONFIG_DM_ETH */