drivers/net/fm/ls1046.c

   1 /*
   2  * Copyright 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <phy.h>
   8 #include <fm_eth.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/fsl_serdes.h>
  11
  12 #define FSL_CHASSIS2_RCWSR13_EC1                0xe0000000 /* bits 416..418 */
  13 #define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII   0x00000000
  14 #define FSL_CHASSIS2_RCWSR13_EC1_GPIO           0x20000000
  15 #define FSL_CHASSIS2_RCWSR13_EC1_FTM            0xa0000000
  16 #define FSL_CHASSIS2_RCWSR13_EC2                0x1c000000 /* bits 419..421 */
  17 #define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII   0x00000000
  18 #define FSL_CHASSIS2_RCWSR13_EC2_GPIO           0x04000000
  19 #define FSL_CHASSIS2_RCWSR13_EC2_1588           0x08000000
  20 #define FSL_CHASSIS2_RCWSR13_EC2_FTM            0x14000000
  21
  22 u32 port_to_devdisr[] = {
  23         [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
  24         [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
  25         [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
  26         [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
  27         [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
  28         [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
  29         [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
  30         [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
  31         [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
  32         [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
  33         [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
  34         [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
  35 };
  36
  37 static int is_device_disabled(enum fm_port port)
  38 {
  39         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  40         u32 devdisr2 = in_be32(&gur->devdisr2);
  41
  42         return port_to_devdisr[port] & devdisr2;
  43 }
  44
  45 void fman_disable_port(enum fm_port port)
  46 {
  47         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  48
  49         setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
  50 }
  51
  52 phy_interface_t fman_port_enet_if(enum fm_port port)
  53 {
  54         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  55         u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
  56
  57         if (is_device_disabled(port))
  58                 return PHY_INTERFACE_MODE_NONE;
  59
  60         if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
  61                 return PHY_INTERFACE_MODE_XGMII;
  62
  63         if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
  64                 return PHY_INTERFACE_MODE_NONE;
  65
  66         if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
  67                 return PHY_INTERFACE_MODE_XGMII;
  68
  69         if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
  70                 return PHY_INTERFACE_MODE_NONE;
  71
  72         if (port == FM1_DTSEC3)
  73                 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
  74                                 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII)
  75                         return PHY_INTERFACE_MODE_RGMII;
  76
  77         if (port == FM1_DTSEC4)
  78                 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
  79                                 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII)
  80                         return PHY_INTERFACE_MODE_RGMII;
  81
  82         /* handle SGMII, only MAC 2/5/6/9/10 available */
  83         switch (port) {
  84         case FM1_DTSEC2:
  85         case FM1_DTSEC5:
  86         case FM1_DTSEC6:
  87         case FM1_DTSEC9:
  88         case FM1_DTSEC10:
  89                 if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2))
  90                         return PHY_INTERFACE_MODE_SGMII;
  91                 break;
  92         default:
  93                 break;
  94         }
  95
  96         /* handle 2.5G SGMII, only MAC 5/9/10 available */
  97         switch (port) {
  98         case FM1_DTSEC5:
  99         case FM1_DTSEC9:
 100         case FM1_DTSEC10:
 101                 if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 +
 102                                          port - FM1_DTSEC5))
 103                         return PHY_INTERFACE_MODE_SGMII_2500;
 104                 break;
 105         default:
 106                 break;
 107         }
 108
 109         /* handle QSGMII, only MAC 1/5/6/10 available */
 110         switch (port) {
 111         case FM1_DTSEC1:
 112         case FM1_DTSEC5:
 113         case FM1_DTSEC6:
 114         case FM1_DTSEC10:
 115                 if (is_serdes_configured(QSGMII_FM1_A))
 116                         return PHY_INTERFACE_MODE_QSGMII;
 117                 break;
 118         default:
 119                 break;
 120         }
 121
 122         return PHY_INTERFACE_MODE_NONE;
 123 }