1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
12 #include <dm/device_compat.h>
13 #include <linux/errno.h>
14 #include <u-boot/crc.h>
18 #include <fsl_qe.h> /* For struct qe_firmware */
21 #include <spi_flash.h>
25 #include <asm/armv8/mmu.h>
26 #include <asm/arch/cpu.h>
29 struct fm_muram muram[CFG_SYS_NUM_FMAN];
31 void *fm_muram_base(int fm_idx)
33 return muram[fm_idx].base;
36 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
43 align_mask = align - 1;
44 save = muram[fm_idx].alloc;
46 off = (ulong)save & align_mask;
48 muram[fm_idx].alloc += (align - off);
49 off = size & align_mask;
51 size += (align - off);
52 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
53 muram[fm_idx].alloc = save;
54 printf("%s: run out of ram.\n", __func__);
58 ret = muram[fm_idx].alloc;
59 muram[fm_idx].alloc += size;
60 memset((void *)ret, 0, size);
65 static void fm_init_muram(int fm_idx, void *reg)
69 muram[fm_idx].base = base;
70 muram[fm_idx].size = CFG_SYS_FM_MURAM_SIZE;
71 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
72 muram[fm_idx].top = base + CFG_SYS_FM_MURAM_SIZE;
76 * fm_upload_ucode - Fman microcode upload worker function
78 * This function does the actual uploading of an Fman microcode
81 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
82 u32 *ucode, unsigned int size)
85 unsigned int timeout = 1000000;
87 /* enable address auto increase */
88 out_be32(&imem->iadd, IRAM_IADD_AIE);
89 /* write microcode to IRAM */
90 for (i = 0; i < size / 4; i++)
91 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
93 /* verify if the writing is over */
94 out_be32(&imem->iadd, 0);
95 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
98 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
100 /* enable microcode from IRAM */
101 out_be32(&imem->iready, IRAM_READY);
105 * Upload an Fman firmware
107 * This function is similar to qe_upload_firmware(), exception that it uploads
108 * a microcode to the Fman instead of the QE.
110 * Because the process for uploading a microcode to the Fman is similar for
111 * that of the QE, the QE firmware binary format is used for Fman microcode.
112 * It should be possible to unify these two functions, but for now we keep them
115 static int fman_upload_firmware(int fm_idx,
116 struct fm_imem *fm_imem,
117 const struct qe_firmware *firmware)
121 size_t calc_size = sizeof(struct qe_firmware);
123 const struct qe_header *hdr;
126 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
130 hdr = &firmware->header;
131 length = be32_to_cpu(hdr->length);
133 /* Check the magic */
134 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
135 (hdr->magic[2] != 'F')) {
136 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
141 /* Check the version */
142 if (hdr->version != 1) {
143 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
148 /* Validate some of the fields */
149 if ((firmware->count != 1)) {
150 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
154 /* Validate the length and check if there's a CRC */
155 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
157 for (i = 0; i < firmware->count; i++)
159 * For situations where the second RISC uses the same microcode
160 * as the first, the 'code_offset' and 'count' fields will be
161 * zero, so it's okay to add those.
163 calc_size += sizeof(u32) *
164 be32_to_cpu(firmware->microcode[i].count);
166 /* Validate the length */
167 if (length != calc_size + sizeof(u32)) {
168 printf("Fman%u: Invalid length in firmware header\n",
174 * Validate the CRC. We would normally call crc32_no_comp(), but that
175 * function isn't available unless you turn on JFFS support.
177 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
178 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
179 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
183 /* Loop through each microcode. */
184 for (i = 0; i < firmware->count; i++) {
185 const struct qe_microcode *ucode = &firmware->microcode[i];
187 /* Upload a microcode if it's present */
188 if (be32_to_cpu(ucode->code_offset)) {
191 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
192 fm_idx + 1, ucode->major, ucode->minor,
194 code = (void *)firmware +
195 be32_to_cpu(ucode->code_offset);
196 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
197 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
204 static u32 fm_assign_risc(int port_id)
207 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
208 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
209 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
214 static void fm_init_fpm(struct fm_fpm *fpm)
219 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
220 FMFPEE_CER | FMFPEE_DER);
222 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
224 /* offline/parser port */
225 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
226 port_id = OH_PORT_ID_BASE + i;
227 val = fm_assign_risc(port_id);
228 out_be32(&fpm->fpmprc, val);
231 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
232 port_id = RX_PORT_1G_BASE + i;
233 val = fm_assign_risc(port_id);
234 out_be32(&fpm->fpmprc, val);
237 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
238 port_id = TX_PORT_1G_BASE + i;
239 val = fm_assign_risc(port_id);
240 out_be32(&fpm->fpmprc, val);
243 port_id = RX_PORT_10G_BASE;
244 val = fm_assign_risc(port_id);
245 out_be32(&fpm->fpmprc, val);
247 port_id = TX_PORT_10G_BASE;
248 val = fm_assign_risc(port_id);
249 out_be32(&fpm->fpmprc, val);
251 /* disable the dispatch limit in IM case */
252 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
254 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
256 /* clear risc events */
257 for (i = 0; i < 4; i++)
258 out_be32(&fpm->fpmcev[i], 0xffffffff);
261 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
264 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
271 /* alloc free buffer pool in MURAM */
272 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
274 printf("%s: no muram for free buffer pool\n", __func__);
277 offset = base - fm_muram_base(fm_idx);
279 /* Need 128KB total free buffer pool size */
281 blk = FM_FREE_POOL_SIZE / 256;
282 /* in IM, we must not begin from offset 0 in MURAM */
283 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
284 out_be32(&bmi->fmbm_cfg1, val);
286 /* disable all BMI interrupt */
287 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
289 /* clear all events */
290 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
293 * set port parameters - FMBM_PP_x
294 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
295 * max dma 10G Rx/Tx=3, others is 1
296 * set port FIFO size - FMBM_PFS_x
297 * 4KB for all Rx and Tx ports
299 /* offline/parser port */
300 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
301 port_id = OH_PORT_ID_BASE + i - 1;
302 /* max tasks=1, max dma=1, no extra */
303 out_be32(&bmi->fmbm_pp[port_id], 0);
304 /* port FIFO size - 256 bytes, no extra */
305 out_be32(&bmi->fmbm_pfs[port_id], 0);
308 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
309 port_id = RX_PORT_1G_BASE + i - 1;
310 /* max tasks=4, max dma=1, no extra */
311 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
312 /* FIFO size - 4KB, no extra */
313 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
315 /* Tx 1G port FIFO size - 4KB, no extra */
316 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
317 port_id = TX_PORT_1G_BASE + i - 1;
318 /* max tasks=4, max dma=1, no extra */
319 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
320 /* FIFO size - 4KB, no extra */
321 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
324 port_id = RX_PORT_10G_BASE - 1;
325 /* max tasks=12, max dma=3, no extra */
326 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
327 /* FIFO size - 4KB, no extra */
328 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
331 port_id = TX_PORT_10G_BASE - 1;
332 /* max tasks=12, max dma=3, no extra */
333 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
334 /* FIFO size - 4KB, no extra */
335 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
337 /* initialize internal buffers data base (linked list) */
338 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
343 static void fm_init_qmi(struct fm_qmi_common *qmi)
345 /* disable all error interrupts */
346 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
347 /* clear all error events */
348 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
350 /* disable all interrupts */
351 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
352 /* clear all interrupts */
353 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
356 /* Init common part of FM, index is fm num# like fm as above */
357 #ifdef CONFIG_TFABOOT
358 int fm_init_common(int index, struct ccsr_fman *reg, const char *firmware_name)
362 enum boot_src src = get_boot_src();
364 if (src == BOOT_SOURCE_IFC_NOR) {
365 addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
366 CFG_SYS_FSL_IFC_BASE);
367 #ifdef CONFIG_CMD_NAND
368 } else if (src == BOOT_SOURCE_IFC_NAND) {
369 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
371 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
373 rc = nand_read(get_nand_dev_by_index(0),
374 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
375 &fw_length, (u_char *)addr);
376 if (rc == -EUCLEAN) {
377 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
378 CONFIG_SYS_FMAN_FW_ADDR, rc);
381 } else if (src == BOOT_SOURCE_QSPI_NOR) {
382 struct spi_flash *ucode_flash;
384 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
387 #if CONFIG_IS_ENABLED(DM_SPI_FLASH)
390 /* speed and mode will be read from DT */
391 ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
392 CONFIG_SF_DEFAULT_CS, &new);
394 ucode_flash = dev_get_uclass_priv(new);
396 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
398 CONFIG_ENV_SPI_MAX_HZ,
399 CONFIG_ENV_SPI_MODE);
402 printf("SF: probe for ucode failed\n");
404 ret = spi_flash_read(ucode_flash,
405 CONFIG_SYS_FMAN_FW_ADDR +
406 CFG_SYS_FSL_QSPI_BASE,
407 CONFIG_SYS_QE_FMAN_FW_LENGTH,
410 printf("SF: read for ucode failed\n");
411 spi_flash_free(ucode_flash);
413 } else if (src == BOOT_SOURCE_SD_MMC) {
414 int dev = CONFIG_SYS_MMC_ENV_DEV;
416 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
417 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
418 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
419 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
422 printf("\nMMC cannot find device for ucode\n");
424 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
427 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
434 /* Upload the Fman microcode if it's present */
435 rc = fman_upload_firmware(index, ®->fm_imem, addr);
438 env_set_addr("fman_ucode", addr);
440 fm_init_muram(index, ®->muram);
441 fm_init_qmi(®->fm_qmi_common);
442 fm_init_fpm(®->fm_fpm);
444 /* clear DMA status */
445 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
448 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
450 return fm_init_bmi(index, ®->fm_bmi_common);
453 int fm_init_common(int index, struct ccsr_fman *reg, const char *firmware_name)
456 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_FS)
457 struct udevice *fs_loader;
458 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
463 rc = get_fs_loader(&fs_loader);
465 debug("could not get fs loader: %d\n", rc);
470 firmware_name = "fman.itb";
472 rc = request_firmware_into_buf(fs_loader, firmware_name, addr,
473 CONFIG_SYS_QE_FMAN_FW_LENGTH, 0);
475 debug("could not request %s: %d\n", firmware_name, rc);
478 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
479 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
480 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
481 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
482 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
484 rc = nand_read(get_nand_dev_by_index(0),
485 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
486 &fw_length, (u_char *)addr);
487 if (rc == -EUCLEAN) {
488 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
489 CONFIG_SYS_FMAN_FW_ADDR, rc);
491 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
492 struct spi_flash *ucode_flash;
493 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
496 #if CONFIG_IS_ENABLED(DM_SPI_FLASH)
499 /* speed and mode will be read from DT */
500 ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS,
503 ucode_flash = dev_get_uclass_priv(new);
505 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
506 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
509 printf("SF: probe for ucode failed\n");
511 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
512 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
514 printf("SF: read for ucode failed\n");
515 spi_flash_free(ucode_flash);
517 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
518 int dev = CONFIG_SYS_MMC_ENV_DEV;
519 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
520 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
521 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
522 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
525 printf("\nMMC cannot find device for ucode\n");
527 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
530 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
533 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
534 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
539 rc = fit_check_format(addr, CONFIG_SYS_QE_FMAN_FW_LENGTH);
542 const void *new_addr;
544 rc = fit_get_data_conf_prop(addr, "fman", &new_addr, &unused);
547 addr = (void *)new_addr;
548 } else if (CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
550 * Using a (signed) FIT wrapper is mandatory if we are
551 * doing verified boot.
556 /* Upload the Fman microcode if it's present */
557 rc = fman_upload_firmware(index, ®->fm_imem, addr);
560 env_set_addr("fman_ucode", addr);
562 fm_init_muram(index, ®->muram);
563 fm_init_qmi(®->fm_qmi_common);
564 fm_init_fpm(®->fm_fpm);
566 /* clear DMA status */
567 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
570 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
572 return fm_init_bmi(index, ®->fm_bmi_common);
577 struct ccsr_fman *reg;
578 unsigned int fman_id;
581 static const struct udevice_id fman_ids[] = {
582 { .compatible = "fsl,fman" },
586 static int fman_probe(struct udevice *dev)
588 const char *firmware_name = NULL;
590 struct fman_priv *priv = dev_get_priv(dev);
592 priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
594 if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
595 printf("FMan node property cell-index missing\n");
599 ret = dev_read_string_index(dev, "firmware-name", 0, &firmware_name);
600 if (ret && ret != -EINVAL) {
601 dev_dbg(dev, "Could not read firmware-name\n");
605 return fm_init_common(priv->fman_id, priv->reg, firmware_name);
608 static int fman_remove(struct udevice *dev)
613 int fman_id(struct udevice *dev)
615 struct fman_priv *priv = dev_get_priv(dev);
617 return priv->fman_id;
620 void *fman_port(struct udevice *dev, int num)
622 struct fman_priv *priv = dev_get_priv(dev);
624 return &priv->reg->port[num - 1].fm_bmi;
627 void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
629 struct fman_priv *priv = dev_get_priv(dev);
633 #ifdef CONFIG_SYS_FMAN_V3
635 res = &priv->reg->memac[num].fm_memac_mdio;
639 res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
642 res = &priv->reg->mac_10g[num].fm_10gec_mdio;
649 U_BOOT_DRIVER(fman) = {
651 .id = UCLASS_SIMPLE_BUS,
652 .of_match = fman_ids,
654 .remove = fman_remove,
655 .priv_auto = sizeof(struct fman_priv),
656 .flags = DM_FLAG_ALLOC_PRIV_DMA,