2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
13 #include "../../qe/qe.h" /* For struct qe_firmware */
15 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
17 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
18 #include <spi_flash.h>
19 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
23 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
25 u32 fm_muram_base(int fm_idx)
27 return muram[fm_idx].base;
30 u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
36 align_mask = align - 1;
37 save = muram[fm_idx].alloc;
39 off = save & align_mask;
41 muram[fm_idx].alloc += (align - off);
42 off = size & align_mask;
44 size += (align - off);
45 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
46 muram[fm_idx].alloc = save;
47 printf("%s: run out of ram.\n", __func__);
50 ret = muram[fm_idx].alloc;
51 muram[fm_idx].alloc += size;
52 memset((void *)ret, 0, size);
57 static void fm_init_muram(int fm_idx, void *reg)
61 muram[fm_idx].base = base;
62 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
63 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
64 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
68 * fm_upload_ucode - Fman microcode upload worker function
70 * This function does the actual uploading of an Fman microcode
73 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
74 u32 *ucode, unsigned int size)
77 unsigned int timeout = 1000000;
79 /* enable address auto increase */
80 out_be32(&imem->iadd, IRAM_IADD_AIE);
81 /* write microcode to IRAM */
82 for (i = 0; i < size / 4; i++)
83 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
85 /* verify if the writing is over */
86 out_be32(&imem->iadd, 0);
87 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
90 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
92 /* enable microcode from IRAM */
93 out_be32(&imem->iready, IRAM_READY);
97 * Upload an Fman firmware
99 * This function is similar to qe_upload_firmware(), exception that it uploads
100 * a microcode to the Fman instead of the QE.
102 * Because the process for uploading a microcode to the Fman is similar for
103 * that of the QE, the QE firmware binary format is used for Fman microcode.
104 * It should be possible to unify these two functions, but for now we keep them
107 static int fman_upload_firmware(int fm_idx,
108 struct fm_imem *fm_imem,
109 const struct qe_firmware *firmware)
113 size_t calc_size = sizeof(struct qe_firmware);
115 const struct qe_header *hdr;
118 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
122 hdr = &firmware->header;
123 length = be32_to_cpu(hdr->length);
125 /* Check the magic */
126 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
127 (hdr->magic[2] != 'F')) {
128 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
133 /* Check the version */
134 if (hdr->version != 1) {
135 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
140 /* Validate some of the fields */
141 if ((firmware->count != 1)) {
142 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
146 /* Validate the length and check if there's a CRC */
147 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
149 for (i = 0; i < firmware->count; i++)
151 * For situations where the second RISC uses the same microcode
152 * as the first, the 'code_offset' and 'count' fields will be
153 * zero, so it's okay to add those.
155 calc_size += sizeof(u32) *
156 be32_to_cpu(firmware->microcode[i].count);
158 /* Validate the length */
159 if (length != calc_size + sizeof(u32)) {
160 printf("Fman%u: Invalid length in firmware header\n",
166 * Validate the CRC. We would normally call crc32_no_comp(), but that
167 * function isn't available unless you turn on JFFS support.
169 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
170 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
171 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
175 /* Loop through each microcode. */
176 for (i = 0; i < firmware->count; i++) {
177 const struct qe_microcode *ucode = &firmware->microcode[i];
179 /* Upload a microcode if it's present */
180 if (be32_to_cpu(ucode->code_offset)) {
183 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
184 fm_idx + 1, ucode->major, ucode->minor,
186 code = (void *)firmware +
187 be32_to_cpu(ucode->code_offset);
188 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
189 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
196 static u32 fm_assign_risc(int port_id)
199 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
200 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
201 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
206 static void fm_init_fpm(struct fm_fpm *fpm)
211 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
212 FMFPEE_CER | FMFPEE_DER);
214 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
216 /* offline/parser port */
217 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
218 port_id = OH_PORT_ID_BASE + i;
219 val = fm_assign_risc(port_id);
220 out_be32(&fpm->fpmprc, val);
223 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
224 port_id = RX_PORT_1G_BASE + i;
225 val = fm_assign_risc(port_id);
226 out_be32(&fpm->fpmprc, val);
229 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
230 port_id = TX_PORT_1G_BASE + i;
231 val = fm_assign_risc(port_id);
232 out_be32(&fpm->fpmprc, val);
235 port_id = RX_PORT_10G_BASE;
236 val = fm_assign_risc(port_id);
237 out_be32(&fpm->fpmprc, val);
239 port_id = TX_PORT_10G_BASE;
240 val = fm_assign_risc(port_id);
241 out_be32(&fpm->fpmprc, val);
243 /* disable the dispatch limit in IM case */
244 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
246 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
248 /* clear risc events */
249 for (i = 0; i < 4; i++)
250 out_be32(&fpm->fpmcev[i], 0xffffffff);
253 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
256 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
259 u32 val, offset, base;
261 /* alloc free buffer pool in MURAM */
262 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
264 printf("%s: no muram for free buffer pool\n", __func__);
267 offset = base - fm_muram_base(fm_idx);
269 /* Need 128KB total free buffer pool size */
271 blk = FM_FREE_POOL_SIZE / 256;
272 /* in IM, we must not begin from offset 0 in MURAM */
273 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
274 out_be32(&bmi->fmbm_cfg1, val);
276 /* disable all BMI interrupt */
277 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
279 /* clear all events */
280 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
283 * set port parameters - FMBM_PP_x
284 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
285 * max dma 10G Rx/Tx=3, others is 1
286 * set port FIFO size - FMBM_PFS_x
287 * 4KB for all Rx and Tx ports
289 /* offline/parser port */
290 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
291 port_id = OH_PORT_ID_BASE + i - 1;
292 /* max tasks=1, max dma=1, no extra */
293 out_be32(&bmi->fmbm_pp[port_id], 0);
294 /* port FIFO size - 256 bytes, no extra */
295 out_be32(&bmi->fmbm_pfs[port_id], 0);
298 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
299 port_id = RX_PORT_1G_BASE + i - 1;
300 /* max tasks=4, max dma=1, no extra */
301 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
302 /* FIFO size - 4KB, no extra */
303 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
305 /* Tx 1G port FIFO size - 4KB, no extra */
306 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
307 port_id = TX_PORT_1G_BASE + i - 1;
308 /* max tasks=4, max dma=1, no extra */
309 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
310 /* FIFO size - 4KB, no extra */
311 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
314 port_id = RX_PORT_10G_BASE - 1;
315 /* max tasks=12, max dma=3, no extra */
316 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
317 /* FIFO size - 4KB, no extra */
318 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
321 port_id = TX_PORT_10G_BASE - 1;
322 /* max tasks=12, max dma=3, no extra */
323 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
324 /* FIFO size - 4KB, no extra */
325 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
327 /* initialize internal buffers data base (linked list) */
328 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
333 static void fm_init_qmi(struct fm_qmi_common *qmi)
335 /* disable enqueue and dequeue of QMI */
336 clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN);
338 /* disable all error interrupts */
339 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
340 /* clear all error events */
341 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
343 /* disable all interrupts */
344 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
345 /* clear all interrupts */
346 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
349 /* Init common part of FM, index is fm num# like fm as above */
350 int fm_init_common(int index, struct ccsr_fman *reg)
353 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
354 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
355 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
356 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
357 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
359 rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
360 &fw_length, (u_char *)addr);
361 if (rc == -EUCLEAN) {
362 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
363 CONFIG_SYS_FMAN_FW_ADDR, rc);
365 #elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
366 struct spi_flash *ucode_flash;
367 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
370 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
371 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
373 printf("SF: probe for ucode failed\n");
375 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
376 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
378 printf("SF: read for ucode failed\n");
379 spi_flash_free(ucode_flash);
381 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
382 int dev = CONFIG_SYS_MMC_ENV_DEV;
383 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
384 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
385 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
386 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
389 printf("\nMMC cannot find device for ucode\n");
391 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
394 (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
395 /* flush cache after read */
396 flush_cache((ulong)addr, cnt * 512);
398 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
399 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
404 /* Upload the Fman microcode if it's present */
405 rc = fman_upload_firmware(index, ®->fm_imem, addr);
408 setenv_addr("fman_ucode", addr);
410 fm_init_muram(index, ®->muram);
411 fm_init_qmi(®->fm_qmi_common);
412 fm_init_fpm(®->fm_fpm);
414 /* clear DMA status */
415 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
418 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
420 return fm_init_bmi(index, ®->fm_bmi_common);