1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
10 #include <linux/errno.h>
11 #include <u-boot/crc.h>
17 #include <fsl_qe.h> /* For struct qe_firmware */
20 #include <spi_flash.h>
24 #include <asm/armv8/mmu.h>
25 #include <asm/arch/cpu.h>
28 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
30 void *fm_muram_base(int fm_idx)
32 return muram[fm_idx].base;
35 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
42 align_mask = align - 1;
43 save = muram[fm_idx].alloc;
45 off = (ulong)save & align_mask;
47 muram[fm_idx].alloc += (align - off);
48 off = size & align_mask;
50 size += (align - off);
51 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
52 muram[fm_idx].alloc = save;
53 printf("%s: run out of ram.\n", __func__);
57 ret = muram[fm_idx].alloc;
58 muram[fm_idx].alloc += size;
59 memset((void *)ret, 0, size);
64 static void fm_init_muram(int fm_idx, void *reg)
68 muram[fm_idx].base = base;
69 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
70 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
71 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
75 * fm_upload_ucode - Fman microcode upload worker function
77 * This function does the actual uploading of an Fman microcode
80 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
81 u32 *ucode, unsigned int size)
84 unsigned int timeout = 1000000;
86 /* enable address auto increase */
87 out_be32(&imem->iadd, IRAM_IADD_AIE);
88 /* write microcode to IRAM */
89 for (i = 0; i < size / 4; i++)
90 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
92 /* verify if the writing is over */
93 out_be32(&imem->iadd, 0);
94 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
97 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
99 /* enable microcode from IRAM */
100 out_be32(&imem->iready, IRAM_READY);
104 * Upload an Fman firmware
106 * This function is similar to qe_upload_firmware(), exception that it uploads
107 * a microcode to the Fman instead of the QE.
109 * Because the process for uploading a microcode to the Fman is similar for
110 * that of the QE, the QE firmware binary format is used for Fman microcode.
111 * It should be possible to unify these two functions, but for now we keep them
114 static int fman_upload_firmware(int fm_idx,
115 struct fm_imem *fm_imem,
116 const struct qe_firmware *firmware)
120 size_t calc_size = sizeof(struct qe_firmware);
122 const struct qe_header *hdr;
125 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
129 hdr = &firmware->header;
130 length = be32_to_cpu(hdr->length);
132 /* Check the magic */
133 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
134 (hdr->magic[2] != 'F')) {
135 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
140 /* Check the version */
141 if (hdr->version != 1) {
142 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
147 /* Validate some of the fields */
148 if ((firmware->count != 1)) {
149 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
153 /* Validate the length and check if there's a CRC */
154 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
156 for (i = 0; i < firmware->count; i++)
158 * For situations where the second RISC uses the same microcode
159 * as the first, the 'code_offset' and 'count' fields will be
160 * zero, so it's okay to add those.
162 calc_size += sizeof(u32) *
163 be32_to_cpu(firmware->microcode[i].count);
165 /* Validate the length */
166 if (length != calc_size + sizeof(u32)) {
167 printf("Fman%u: Invalid length in firmware header\n",
173 * Validate the CRC. We would normally call crc32_no_comp(), but that
174 * function isn't available unless you turn on JFFS support.
176 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
177 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
178 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
182 /* Loop through each microcode. */
183 for (i = 0; i < firmware->count; i++) {
184 const struct qe_microcode *ucode = &firmware->microcode[i];
186 /* Upload a microcode if it's present */
187 if (be32_to_cpu(ucode->code_offset)) {
190 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
191 fm_idx + 1, ucode->major, ucode->minor,
193 code = (void *)firmware +
194 be32_to_cpu(ucode->code_offset);
195 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
196 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
203 static u32 fm_assign_risc(int port_id)
206 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
207 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
208 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
213 static void fm_init_fpm(struct fm_fpm *fpm)
218 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
219 FMFPEE_CER | FMFPEE_DER);
221 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
223 /* offline/parser port */
224 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
225 port_id = OH_PORT_ID_BASE + i;
226 val = fm_assign_risc(port_id);
227 out_be32(&fpm->fpmprc, val);
230 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
231 port_id = RX_PORT_1G_BASE + i;
232 val = fm_assign_risc(port_id);
233 out_be32(&fpm->fpmprc, val);
236 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
237 port_id = TX_PORT_1G_BASE + i;
238 val = fm_assign_risc(port_id);
239 out_be32(&fpm->fpmprc, val);
242 port_id = RX_PORT_10G_BASE;
243 val = fm_assign_risc(port_id);
244 out_be32(&fpm->fpmprc, val);
246 port_id = TX_PORT_10G_BASE;
247 val = fm_assign_risc(port_id);
248 out_be32(&fpm->fpmprc, val);
250 /* disable the dispatch limit in IM case */
251 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
253 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
255 /* clear risc events */
256 for (i = 0; i < 4; i++)
257 out_be32(&fpm->fpmcev[i], 0xffffffff);
260 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
263 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
270 /* alloc free buffer pool in MURAM */
271 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
273 printf("%s: no muram for free buffer pool\n", __func__);
276 offset = base - fm_muram_base(fm_idx);
278 /* Need 128KB total free buffer pool size */
280 blk = FM_FREE_POOL_SIZE / 256;
281 /* in IM, we must not begin from offset 0 in MURAM */
282 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
283 out_be32(&bmi->fmbm_cfg1, val);
285 /* disable all BMI interrupt */
286 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
288 /* clear all events */
289 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
292 * set port parameters - FMBM_PP_x
293 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
294 * max dma 10G Rx/Tx=3, others is 1
295 * set port FIFO size - FMBM_PFS_x
296 * 4KB for all Rx and Tx ports
298 /* offline/parser port */
299 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
300 port_id = OH_PORT_ID_BASE + i - 1;
301 /* max tasks=1, max dma=1, no extra */
302 out_be32(&bmi->fmbm_pp[port_id], 0);
303 /* port FIFO size - 256 bytes, no extra */
304 out_be32(&bmi->fmbm_pfs[port_id], 0);
307 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
308 port_id = RX_PORT_1G_BASE + i - 1;
309 /* max tasks=4, max dma=1, no extra */
310 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
311 /* FIFO size - 4KB, no extra */
312 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
314 /* Tx 1G port FIFO size - 4KB, no extra */
315 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
316 port_id = TX_PORT_1G_BASE + i - 1;
317 /* max tasks=4, max dma=1, no extra */
318 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
319 /* FIFO size - 4KB, no extra */
320 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
323 port_id = RX_PORT_10G_BASE - 1;
324 /* max tasks=12, max dma=3, no extra */
325 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
326 /* FIFO size - 4KB, no extra */
327 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
330 port_id = TX_PORT_10G_BASE - 1;
331 /* max tasks=12, max dma=3, no extra */
332 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
333 /* FIFO size - 4KB, no extra */
334 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
336 /* initialize internal buffers data base (linked list) */
337 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
342 static void fm_init_qmi(struct fm_qmi_common *qmi)
344 /* disable all error interrupts */
345 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
346 /* clear all error events */
347 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
349 /* disable all interrupts */
350 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
351 /* clear all interrupts */
352 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
355 /* Init common part of FM, index is fm num# like fm as above */
356 #ifdef CONFIG_TFABOOT
357 int fm_init_common(int index, struct ccsr_fman *reg)
361 enum boot_src src = get_boot_src();
363 if (src == BOOT_SOURCE_IFC_NOR) {
364 addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
365 CONFIG_SYS_FSL_IFC_BASE);
366 #ifdef CONFIG_CMD_NAND
367 } else if (src == BOOT_SOURCE_IFC_NAND) {
368 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
370 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
372 rc = nand_read(get_nand_dev_by_index(0),
373 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
374 &fw_length, (u_char *)addr);
375 if (rc == -EUCLEAN) {
376 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
377 CONFIG_SYS_FMAN_FW_ADDR, rc);
380 } else if (src == BOOT_SOURCE_QSPI_NOR) {
381 struct spi_flash *ucode_flash;
383 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
386 #ifdef CONFIG_DM_SPI_FLASH
389 /* speed and mode will be read from DT */
390 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
391 CONFIG_ENV_SPI_CS, 0, 0, &new);
393 ucode_flash = dev_get_uclass_priv(new);
395 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
397 CONFIG_ENV_SPI_MAX_HZ,
398 CONFIG_ENV_SPI_MODE);
401 printf("SF: probe for ucode failed\n");
403 ret = spi_flash_read(ucode_flash,
404 CONFIG_SYS_FMAN_FW_ADDR +
405 CONFIG_SYS_FSL_QSPI_BASE,
406 CONFIG_SYS_QE_FMAN_FW_LENGTH,
409 printf("SF: read for ucode failed\n");
410 spi_flash_free(ucode_flash);
412 } else if (src == BOOT_SOURCE_SD_MMC) {
413 int dev = CONFIG_SYS_MMC_ENV_DEV;
415 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
416 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
417 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
418 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
421 printf("\nMMC cannot find device for ucode\n");
423 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
426 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
433 /* Upload the Fman microcode if it's present */
434 rc = fman_upload_firmware(index, ®->fm_imem, addr);
437 env_set_addr("fman_ucode", addr);
439 fm_init_muram(index, ®->muram);
440 fm_init_qmi(®->fm_qmi_common);
441 fm_init_fpm(®->fm_fpm);
443 /* clear DMA status */
444 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
447 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
449 return fm_init_bmi(index, ®->fm_bmi_common);
452 int fm_init_common(int index, struct ccsr_fman *reg)
455 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
456 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
457 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
458 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
459 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
461 rc = nand_read(get_nand_dev_by_index(0),
462 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
463 &fw_length, (u_char *)addr);
464 if (rc == -EUCLEAN) {
465 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
466 CONFIG_SYS_FMAN_FW_ADDR, rc);
468 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
469 struct spi_flash *ucode_flash;
470 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
473 #ifdef CONFIG_DM_SPI_FLASH
476 /* speed and mode will be read from DT */
477 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
480 ucode_flash = dev_get_uclass_priv(new);
482 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
483 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
486 printf("SF: probe for ucode failed\n");
488 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
489 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
491 printf("SF: read for ucode failed\n");
492 spi_flash_free(ucode_flash);
494 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
495 int dev = CONFIG_SYS_MMC_ENV_DEV;
496 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
497 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
498 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
499 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
502 printf("\nMMC cannot find device for ucode\n");
504 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
507 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
510 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
511 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
516 /* Upload the Fman microcode if it's present */
517 rc = fman_upload_firmware(index, ®->fm_imem, addr);
520 env_set_addr("fman_ucode", addr);
522 fm_init_muram(index, ®->muram);
523 fm_init_qmi(®->fm_qmi_common);
524 fm_init_fpm(®->fm_fpm);
526 /* clear DMA status */
527 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
530 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
532 return fm_init_bmi(index, ®->fm_bmi_common);
538 struct ccsr_fman *reg;
539 unsigned int fman_id;
542 static const struct udevice_id fman_ids[] = {
543 { .compatible = "fsl,fman" },
547 static int fman_probe(struct udevice *dev)
549 struct fman_priv *priv = dev_get_priv(dev);
551 priv->reg = (struct ccsr_fman *)(uintptr_t)dev_read_addr(dev);
553 if (dev_read_u32(dev, "cell-index", &priv->fman_id)) {
554 printf("FMan node property cell-index missing\n");
558 return fm_init_common(priv->fman_id, priv->reg);
561 static int fman_remove(struct udevice *dev)
566 int fman_id(struct udevice *dev)
568 struct fman_priv *priv = dev_get_priv(dev);
570 return priv->fman_id;
573 void *fman_port(struct udevice *dev, int num)
575 struct fman_priv *priv = dev_get_priv(dev);
577 return &priv->reg->port[num - 1].fm_bmi;
580 void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num)
582 struct fman_priv *priv = dev_get_priv(dev);
586 #ifdef CONFIG_SYS_FMAN_V3
588 res = &priv->reg->memac[num].fm_memac_mdio;
592 res = &priv->reg->mac_1g[num].fm_mdio.miimcfg;
595 res = &priv->reg->mac_10g[num].fm_10gec_mdio;
602 U_BOOT_DRIVER(fman) = {
604 .id = UCLASS_SIMPLE_BUS,
605 .of_match = fman_ids,
607 .remove = fman_remove,
608 .priv_auto_alloc_size = sizeof(struct fman_priv),
609 .flags = DM_FLAG_ALLOC_PRIV_DMA,
611 #endif /* CONFIG_DM_ETH */