1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
9 #include <linux/errno.h>
12 #include <fsl_qe.h> /* For struct qe_firmware */
15 #include <spi_flash.h>
17 #include <environment.h>
20 #include <asm/armv8/mmu.h>
21 #include <asm/arch/cpu.h>
24 struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
26 void *fm_muram_base(int fm_idx)
28 return muram[fm_idx].base;
31 void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
38 align_mask = align - 1;
39 save = muram[fm_idx].alloc;
41 off = (ulong)save & align_mask;
43 muram[fm_idx].alloc += (align - off);
44 off = size & align_mask;
46 size += (align - off);
47 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
48 muram[fm_idx].alloc = save;
49 printf("%s: run out of ram.\n", __func__);
53 ret = muram[fm_idx].alloc;
54 muram[fm_idx].alloc += size;
55 memset((void *)ret, 0, size);
60 static void fm_init_muram(int fm_idx, void *reg)
64 muram[fm_idx].base = base;
65 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
66 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
67 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
71 * fm_upload_ucode - Fman microcode upload worker function
73 * This function does the actual uploading of an Fman microcode
76 static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
77 u32 *ucode, unsigned int size)
80 unsigned int timeout = 1000000;
82 /* enable address auto increase */
83 out_be32(&imem->iadd, IRAM_IADD_AIE);
84 /* write microcode to IRAM */
85 for (i = 0; i < size / 4; i++)
86 out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
88 /* verify if the writing is over */
89 out_be32(&imem->iadd, 0);
90 while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
93 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
95 /* enable microcode from IRAM */
96 out_be32(&imem->iready, IRAM_READY);
100 * Upload an Fman firmware
102 * This function is similar to qe_upload_firmware(), exception that it uploads
103 * a microcode to the Fman instead of the QE.
105 * Because the process for uploading a microcode to the Fman is similar for
106 * that of the QE, the QE firmware binary format is used for Fman microcode.
107 * It should be possible to unify these two functions, but for now we keep them
110 static int fman_upload_firmware(int fm_idx,
111 struct fm_imem *fm_imem,
112 const struct qe_firmware *firmware)
116 size_t calc_size = sizeof(struct qe_firmware);
118 const struct qe_header *hdr;
121 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
125 hdr = &firmware->header;
126 length = be32_to_cpu(hdr->length);
128 /* Check the magic */
129 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
130 (hdr->magic[2] != 'F')) {
131 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
136 /* Check the version */
137 if (hdr->version != 1) {
138 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
143 /* Validate some of the fields */
144 if ((firmware->count != 1)) {
145 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
149 /* Validate the length and check if there's a CRC */
150 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
152 for (i = 0; i < firmware->count; i++)
154 * For situations where the second RISC uses the same microcode
155 * as the first, the 'code_offset' and 'count' fields will be
156 * zero, so it's okay to add those.
158 calc_size += sizeof(u32) *
159 be32_to_cpu(firmware->microcode[i].count);
161 /* Validate the length */
162 if (length != calc_size + sizeof(u32)) {
163 printf("Fman%u: Invalid length in firmware header\n",
169 * Validate the CRC. We would normally call crc32_no_comp(), but that
170 * function isn't available unless you turn on JFFS support.
172 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
173 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
174 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
178 /* Loop through each microcode. */
179 for (i = 0; i < firmware->count; i++) {
180 const struct qe_microcode *ucode = &firmware->microcode[i];
182 /* Upload a microcode if it's present */
183 if (be32_to_cpu(ucode->code_offset)) {
186 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
187 fm_idx + 1, ucode->major, ucode->minor,
189 code = (void *)firmware +
190 be32_to_cpu(ucode->code_offset);
191 ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
192 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
199 static u32 fm_assign_risc(int port_id)
202 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
203 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
204 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
209 static void fm_init_fpm(struct fm_fpm *fpm)
214 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
215 FMFPEE_CER | FMFPEE_DER);
217 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
219 /* offline/parser port */
220 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
221 port_id = OH_PORT_ID_BASE + i;
222 val = fm_assign_risc(port_id);
223 out_be32(&fpm->fpmprc, val);
226 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
227 port_id = RX_PORT_1G_BASE + i;
228 val = fm_assign_risc(port_id);
229 out_be32(&fpm->fpmprc, val);
232 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
233 port_id = TX_PORT_1G_BASE + i;
234 val = fm_assign_risc(port_id);
235 out_be32(&fpm->fpmprc, val);
238 port_id = RX_PORT_10G_BASE;
239 val = fm_assign_risc(port_id);
240 out_be32(&fpm->fpmprc, val);
242 port_id = TX_PORT_10G_BASE;
243 val = fm_assign_risc(port_id);
244 out_be32(&fpm->fpmprc, val);
246 /* disable the dispatch limit in IM case */
247 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
249 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
251 /* clear risc events */
252 for (i = 0; i < 4; i++)
253 out_be32(&fpm->fpmcev[i], 0xffffffff);
256 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
259 static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
266 /* alloc free buffer pool in MURAM */
267 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
269 printf("%s: no muram for free buffer pool\n", __func__);
272 offset = base - fm_muram_base(fm_idx);
274 /* Need 128KB total free buffer pool size */
276 blk = FM_FREE_POOL_SIZE / 256;
277 /* in IM, we must not begin from offset 0 in MURAM */
278 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
279 out_be32(&bmi->fmbm_cfg1, val);
281 /* disable all BMI interrupt */
282 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
284 /* clear all events */
285 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
288 * set port parameters - FMBM_PP_x
289 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
290 * max dma 10G Rx/Tx=3, others is 1
291 * set port FIFO size - FMBM_PFS_x
292 * 4KB for all Rx and Tx ports
294 /* offline/parser port */
295 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
296 port_id = OH_PORT_ID_BASE + i - 1;
297 /* max tasks=1, max dma=1, no extra */
298 out_be32(&bmi->fmbm_pp[port_id], 0);
299 /* port FIFO size - 256 bytes, no extra */
300 out_be32(&bmi->fmbm_pfs[port_id], 0);
303 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
304 port_id = RX_PORT_1G_BASE + i - 1;
305 /* max tasks=4, max dma=1, no extra */
306 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
307 /* FIFO size - 4KB, no extra */
308 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
310 /* Tx 1G port FIFO size - 4KB, no extra */
311 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
312 port_id = TX_PORT_1G_BASE + i - 1;
313 /* max tasks=4, max dma=1, no extra */
314 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
315 /* FIFO size - 4KB, no extra */
316 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
319 port_id = RX_PORT_10G_BASE - 1;
320 /* max tasks=12, max dma=3, no extra */
321 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
322 /* FIFO size - 4KB, no extra */
323 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
326 port_id = TX_PORT_10G_BASE - 1;
327 /* max tasks=12, max dma=3, no extra */
328 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
329 /* FIFO size - 4KB, no extra */
330 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
332 /* initialize internal buffers data base (linked list) */
333 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
338 static void fm_init_qmi(struct fm_qmi_common *qmi)
340 /* disable all error interrupts */
341 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
342 /* clear all error events */
343 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
345 /* disable all interrupts */
346 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
347 /* clear all interrupts */
348 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
351 /* Init common part of FM, index is fm num# like fm as above */
352 #ifdef CONFIG_TFABOOT
353 int fm_init_common(int index, struct ccsr_fman *reg)
357 enum boot_src src = get_boot_src();
359 if (src == BOOT_SOURCE_IFC_NOR) {
360 addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
361 CONFIG_SYS_FSL_IFC_BASE);
362 } else if (src == BOOT_SOURCE_IFC_NAND) {
363 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
365 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
367 rc = nand_read(get_nand_dev_by_index(0),
368 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
369 &fw_length, (u_char *)addr);
370 if (rc == -EUCLEAN) {
371 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
372 CONFIG_SYS_FMAN_FW_ADDR, rc);
374 } else if (src == BOOT_SOURCE_QSPI_NOR) {
375 struct spi_flash *ucode_flash;
377 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
380 #ifdef CONFIG_DM_SPI_FLASH
383 /* speed and mode will be read from DT */
384 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
385 CONFIG_ENV_SPI_CS, 0, 0, &new);
387 ucode_flash = dev_get_uclass_priv(new);
389 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
391 CONFIG_ENV_SPI_MAX_HZ,
392 CONFIG_ENV_SPI_MODE);
395 printf("SF: probe for ucode failed\n");
397 ret = spi_flash_read(ucode_flash,
398 CONFIG_SYS_FMAN_FW_ADDR +
399 CONFIG_SYS_FSL_QSPI_BASE,
400 CONFIG_SYS_QE_FMAN_FW_LENGTH,
403 printf("SF: read for ucode failed\n");
404 spi_flash_free(ucode_flash);
406 } else if (src == BOOT_SOURCE_SD_MMC) {
407 int dev = CONFIG_SYS_MMC_ENV_DEV;
409 addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
410 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
411 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
412 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
415 printf("\nMMC cannot find device for ucode\n");
417 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
420 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
427 /* Upload the Fman microcode if it's present */
428 rc = fman_upload_firmware(index, ®->fm_imem, addr);
431 env_set_addr("fman_ucode", addr);
433 fm_init_muram(index, ®->muram);
434 fm_init_qmi(®->fm_qmi_common);
435 fm_init_fpm(®->fm_fpm);
437 /* clear DMA status */
438 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
441 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
443 return fm_init_bmi(index, ®->fm_bmi_common);
446 int fm_init_common(int index, struct ccsr_fman *reg)
449 #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
450 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
451 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
452 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
453 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
455 rc = nand_read(get_nand_dev_by_index(0),
456 (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
457 &fw_length, (u_char *)addr);
458 if (rc == -EUCLEAN) {
459 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
460 CONFIG_SYS_FMAN_FW_ADDR, rc);
462 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
463 struct spi_flash *ucode_flash;
464 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
467 #ifdef CONFIG_DM_SPI_FLASH
470 /* speed and mode will be read from DT */
471 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
474 ucode_flash = dev_get_uclass_priv(new);
476 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
477 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
480 printf("SF: probe for ucode failed\n");
482 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
483 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
485 printf("SF: read for ucode failed\n");
486 spi_flash_free(ucode_flash);
488 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
489 int dev = CONFIG_SYS_MMC_ENV_DEV;
490 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
491 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
492 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
493 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
496 printf("\nMMC cannot find device for ucode\n");
498 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
501 (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
504 #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
505 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
510 /* Upload the Fman microcode if it's present */
511 rc = fman_upload_firmware(index, ®->fm_imem, addr);
514 env_set_addr("fman_ucode", addr);
516 fm_init_muram(index, ®->muram);
517 fm_init_qmi(®->fm_qmi_common);
518 fm_init_fpm(®->fm_fpm);
520 /* clear DMA status */
521 setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
524 setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
526 return fm_init_bmi(index, ®->fm_bmi_common);