1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
13 #include <dm/ofnode.h>
14 #include <linux/compat.h>
15 #include <phy_interface.h>
24 #include <fsl_dtsec.h>
26 #include <fsl_memac.h>
31 static struct eth_device *devlist[NUM_FM_PORTS];
32 static int num_controllers;
35 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
37 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
40 #define TBIANA_SGMII_ACK 0x4001
42 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
43 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
45 /* Configure the TBI for SGMII operation */
46 static void dtsec_configure_serdes(struct fm_eth *priv)
48 #ifdef CONFIG_SYS_FMAN_V3
51 bool sgmii_2500 = (priv->enet_if ==
52 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
56 bus.priv = priv->mac->phyregs;
58 bus.priv = priv->pcs_mdio;
60 bus.read = memac_mdio_read;
61 bus.write = memac_mdio_write;
62 bus.reset = memac_mdio_reset;
65 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
67 value = PHY_SGMII_CR_PHY_RESET |
68 PHY_SGMII_IF_SPEED_GIGABIT |
69 PHY_SGMII_IF_MODE_SGMII;
71 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
73 for (j = 0; j <= 3; j++)
74 debug("dump PCS reg %#x: %#x\n", j,
75 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
77 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
79 /* Dev ability according to SGMII specification */
80 value = PHY_SGMII_DEV_ABILITY_SGMII;
81 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
84 /* Adjust link timer for 2.5G SGMII,
85 * 1.6 ms in units of 3.2 ns:
86 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
88 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
89 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
91 /* Adjust link timer for SGMII,
92 * 1.6 ms in units of 8 ns:
93 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
95 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
96 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
100 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
101 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
103 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
108 struct dtsec *regs = priv->mac->base;
109 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
112 * Access TBI PHY registers at given TSEC register offset as
113 * opposed to the register offset used for external PHY accesses
115 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
117 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
119 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
120 TBI_CR, TBICR_SETTINGS);
124 static void dtsec_init_phy(struct fm_eth *fm_eth)
126 #ifndef CONFIG_SYS_FMAN_V3
127 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
129 /* Assign a Physical address to the TBI */
130 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
133 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
134 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
135 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
136 dtsec_configure_serdes(fm_eth);
139 #ifndef CONFIG_DM_ETH
141 static int tgec_is_fibre(struct fm_eth *fm)
145 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
147 return hwconfig_arg_cmp(phyopt, "xfi");
150 #endif /* CONFIG_DM_ETH */
153 static u16 muram_readw(u16 *addr)
155 ulong base = (ulong)addr & ~0x3UL;
156 u32 val32 = in_be32((void *)base);
160 byte_pos = (ulong)addr & 0x3UL;
162 ret = (u16)(val32 & 0x0000ffff);
164 ret = (u16)((val32 & 0xffff0000) >> 16);
169 static void muram_writew(u16 *addr, u16 val)
171 ulong base = (ulong)addr & ~0x3UL;
172 u32 org32 = in_be32((void *)base);
176 byte_pos = (ulong)addr & 0x3UL;
178 val32 = (org32 & 0xffff0000) | val;
180 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
182 out_be32((void *)base, val32);
185 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
187 int timeout = 1000000;
189 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
191 /* wait until the rx port is not busy */
192 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
195 printf("%s - timeout\n", __func__);
198 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
200 /* set BMI to independent mode, Rx port disable */
201 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
202 /* clear FOF in IM case */
203 out_be32(&rx_port->fmbm_rim, 0);
204 /* Rx frame next engine -RISC */
205 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
206 /* Rx command attribute - no order, MR[3] = 1 */
207 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
208 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
209 /* enable Rx statistic counters */
210 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
211 /* disable Rx performance counters */
212 out_be32(&rx_port->fmbm_rpc, 0);
215 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
217 int timeout = 1000000;
219 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
221 /* wait until the tx port is not busy */
222 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
225 printf("%s - timeout\n", __func__);
228 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
230 /* set BMI to independent mode, Tx port disable */
231 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
232 /* Tx frame next engine -RISC */
233 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
234 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
235 /* Tx command attribute - no order, MR[3] = 1 */
236 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
237 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
238 /* enable Tx statistic counters */
239 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
240 /* disable Tx performance counters */
241 out_be32(&tx_port->fmbm_tpc, 0);
244 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
246 struct fm_port_global_pram *pram;
247 u32 pram_page_offset;
248 void *rx_bd_ring_base;
250 u32 bd_ring_base_lo, bd_ring_base_hi;
252 struct fm_port_bd *rxbd;
253 struct fm_port_qd *rxqd;
254 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
257 /* alloc global parameter ram at MURAM */
258 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
259 FM_PRAM_SIZE, FM_PRAM_ALIGN);
261 printf("%s: No muram for Rx global parameter\n", __func__);
265 fm_eth->rx_pram = pram;
267 /* parameter page offset to MURAM */
268 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
270 /* enable global mode- snooping data buffers and BDs */
271 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
273 /* init the Rx queue descriptor pionter */
274 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
276 /* set the max receive buffer length, power of 2 */
277 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
279 /* alloc Rx buffer descriptors from main memory */
280 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
282 if (!rx_bd_ring_base)
285 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
288 /* alloc Rx buffer from main memory */
289 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
293 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
294 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
296 /* save them to fm_eth */
297 fm_eth->rx_bd_ring = rx_bd_ring_base;
298 fm_eth->cur_rxbd = rx_bd_ring_base;
299 fm_eth->rx_buf = rx_buf_pool;
301 /* init Rx BDs ring */
302 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
303 for (i = 0; i < RX_BD_RING_SIZE; i++) {
304 muram_writew(&rxbd->status, RxBD_EMPTY);
305 muram_writew(&rxbd->len, 0);
306 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
308 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
310 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
311 out_be32(&rxbd->buf_ptr_lo, buf_lo);
315 /* set the Rx queue descriptor */
317 muram_writew(&rxqd->gen, 0);
318 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
319 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
320 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
321 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
322 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
324 muram_writew(&rxqd->offset_in, 0);
325 muram_writew(&rxqd->offset_out, 0);
327 /* set IM parameter ram pointer to Rx Frame Queue ID */
328 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
333 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
335 struct fm_port_global_pram *pram;
336 u32 pram_page_offset;
337 void *tx_bd_ring_base;
338 u32 bd_ring_base_lo, bd_ring_base_hi;
339 struct fm_port_bd *txbd;
340 struct fm_port_qd *txqd;
341 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
344 /* alloc global parameter ram at MURAM */
345 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
346 FM_PRAM_SIZE, FM_PRAM_ALIGN);
348 printf("%s: No muram for Tx global parameter\n", __func__);
351 fm_eth->tx_pram = pram;
353 /* parameter page offset to MURAM */
354 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
356 /* enable global mode- snooping data buffers and BDs */
357 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
359 /* init the Tx queue descriptor pionter */
360 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
362 /* alloc Tx buffer descriptors from main memory */
363 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
365 if (!tx_bd_ring_base)
368 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
370 /* save it to fm_eth */
371 fm_eth->tx_bd_ring = tx_bd_ring_base;
372 fm_eth->cur_txbd = tx_bd_ring_base;
374 /* init Tx BDs ring */
375 txbd = (struct fm_port_bd *)tx_bd_ring_base;
376 for (i = 0; i < TX_BD_RING_SIZE; i++) {
377 muram_writew(&txbd->status, TxBD_LAST);
378 muram_writew(&txbd->len, 0);
379 muram_writew(&txbd->buf_ptr_hi, 0);
380 out_be32(&txbd->buf_ptr_lo, 0);
384 /* set the Tx queue decriptor */
386 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
387 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
388 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
389 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
390 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
392 muram_writew(&txqd->offset_in, 0);
393 muram_writew(&txqd->offset_out, 0);
395 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
396 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
401 static int fm_eth_init(struct fm_eth *fm_eth)
405 ret = fm_eth_rx_port_parameter_init(fm_eth);
409 ret = fm_eth_tx_port_parameter_init(fm_eth);
416 static int fm_eth_startup(struct fm_eth *fm_eth)
418 struct fsl_enet_mac *mac;
423 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
424 ret = fm_eth_init(fm_eth);
427 /* setup the MAC controller */
430 /* For some reason we need to set SPEED_100 */
431 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
432 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
433 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
435 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
437 /* init bmi rx port, IM mode and disable */
438 bmi_rx_port_init(fm_eth->rx_port);
439 /* init bmi tx port, IM mode and disable */
440 bmi_tx_port_init(fm_eth->tx_port);
445 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
447 struct fm_port_global_pram *pram;
449 pram = fm_eth->tx_pram;
450 /* graceful stop transmission of frames */
451 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
455 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
457 struct fm_port_global_pram *pram;
459 pram = fm_eth->tx_pram;
460 /* re-enable transmission of frames */
461 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
465 #ifndef CONFIG_DM_ETH
466 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
468 static int fm_eth_open(struct udevice *dev)
471 #ifndef CONFIG_DM_ETH
472 struct fm_eth *fm_eth = dev->priv;
474 struct eth_pdata *pdata = dev_get_platdata(dev);
475 struct fm_eth *fm_eth = dev_get_priv(dev);
477 unsigned char *enetaddr;
478 struct fsl_enet_mac *mac;
485 #ifndef CONFIG_DM_ETH
486 enetaddr = &dev->enetaddr[0];
488 enetaddr = pdata->enetaddr;
491 /* setup the MAC address */
492 if (enetaddr[0] & 0x01) {
493 printf("%s: MacAddress is multicast address\n", __func__);
495 enetaddr[5] = fm_eth->num;
497 mac->set_mac_addr(mac, enetaddr);
499 /* enable bmi Rx port */
500 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
501 /* enable MAC rx/tx port */
502 mac->enable_mac(mac);
503 /* enable bmi Tx port */
504 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
505 /* re-enable transmission of frame */
506 fmc_tx_port_graceful_stop_disable(fm_eth);
509 if (fm_eth->phydev) {
510 ret = phy_startup(fm_eth->phydev);
512 #ifndef CONFIG_DM_ETH
513 printf("%s: Could not initialize\n",
514 fm_eth->phydev->dev->name);
516 printf("%s: Could not initialize\n", dev->name);
524 fm_eth->phydev->speed = SPEED_1000;
525 fm_eth->phydev->link = 1;
526 fm_eth->phydev->duplex = DUPLEX_FULL;
529 /* set the MAC-PHY mode */
530 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
531 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
532 fm_eth->phydev->speed, fm_eth->phydev->link);
534 if (!fm_eth->phydev->link)
535 printf("%s: No link.\n", fm_eth->phydev->dev->name);
537 return fm_eth->phydev->link ? 0 : -1;
540 #ifndef CONFIG_DM_ETH
541 static void fm_eth_halt(struct eth_device *dev)
543 static void fm_eth_halt(struct udevice *dev)
546 struct fm_eth *fm_eth;
547 struct fsl_enet_mac *mac;
549 fm_eth = (struct fm_eth *)dev->priv;
552 /* graceful stop the transmission of frames */
553 fmc_tx_port_graceful_stop_enable(fm_eth);
554 /* disable bmi Tx port */
555 bmi_tx_port_disable(fm_eth->tx_port);
556 /* disable MAC rx/tx port */
557 mac->disable_mac(mac);
558 /* disable bmi Rx port */
559 bmi_rx_port_disable(fm_eth->rx_port);
563 phy_shutdown(fm_eth->phydev);
567 #ifndef CONFIG_DM_ETH
568 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
570 static int fm_eth_send(struct udevice *dev, void *buf, int len)
573 struct fm_eth *fm_eth;
574 struct fm_port_global_pram *pram;
575 struct fm_port_bd *txbd, *txbd_base;
579 fm_eth = (struct fm_eth *)dev->priv;
580 pram = fm_eth->tx_pram;
581 txbd = fm_eth->cur_txbd;
583 /* find one empty TxBD */
584 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
587 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
588 dev->name, muram_readw(&txbd->status));
593 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
594 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
595 muram_writew(&txbd->len, len);
597 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
600 /* update TxQD, let RISC to send the packet */
601 offset_in = muram_readw(&pram->txqd.offset_in);
602 offset_in += sizeof(struct fm_port_bd);
603 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
605 muram_writew(&pram->txqd.offset_in, offset_in);
608 /* wait for buffer to be transmitted */
609 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
612 printf("%s: Tx error, txbd->status = 0x%x\n",
613 dev->name, muram_readw(&txbd->status));
618 /* advance the TxBD */
620 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
621 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
623 /* update current txbd */
624 fm_eth->cur_txbd = (void *)txbd;
629 static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
630 struct fm_port_bd *rxbd)
632 struct fm_port_global_pram *pram;
633 struct fm_port_bd *rxbd_base;
636 pram = fm_eth->rx_pram;
638 /* clear the RxBDs */
639 muram_writew(&rxbd->status, RxBD_EMPTY);
640 muram_writew(&rxbd->len, 0);
645 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
646 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
650 offset_out = muram_readw(&pram->rxqd.offset_out);
651 offset_out += sizeof(struct fm_port_bd);
652 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
654 muram_writew(&pram->rxqd.offset_out, offset_out);
660 #ifndef CONFIG_DM_ETH
661 static int fm_eth_recv(struct eth_device *dev)
663 static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
666 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
667 struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
673 status = muram_readw(&rxbd->status);
675 while (!(status & RxBD_EMPTY)) {
676 if (!(status & RxBD_ERROR)) {
677 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
678 buf_lo = in_be32(&rxbd->buf_ptr_lo);
679 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
680 len = muram_readw(&rxbd->len);
681 #ifndef CONFIG_DM_ETH
682 net_process_received_packet(data, len);
688 printf("%s: Rx error\n", dev->name);
692 /* free current bd, advance to next one */
693 rxbd = fm_eth_free_one(fm_eth, rxbd);
695 /* read next status */
696 status = muram_readw(&rxbd->status);
698 fm_eth->cur_rxbd = (void *)rxbd;
704 static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
706 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
708 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
712 #endif /* CONFIG_DM_ETH */
714 #ifndef CONFIG_DM_ETH
715 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
717 struct fsl_enet_mac *mac;
719 void *base, *phyregs = NULL;
723 #ifdef CONFIG_SYS_FMAN_V3
724 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
725 if (fm_eth->type == FM_ETH_10G_E) {
726 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
727 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
728 * 10GEC1 uses mEMAC1 on T1024.
729 * so it needs to change the num.
731 if (fm_eth->num >= 2)
737 base = ®->memac[num].fm_memac;
738 phyregs = ®->memac[num].fm_memac_mdio;
740 /* Get the mac registers base address */
741 if (fm_eth->type == FM_ETH_1G_E) {
742 base = ®->mac_1g[num].fm_dtesc;
743 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
745 base = ®->mac_10g[num].fm_10gec;
746 phyregs = ®->mac_10g[num].fm_10gec_mdio;
750 /* alloc mac controller */
751 mac = malloc(sizeof(struct fsl_enet_mac));
754 memset(mac, 0, sizeof(struct fsl_enet_mac));
756 /* save the mac to fm_eth struct */
759 #ifdef CONFIG_SYS_FMAN_V3
760 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
762 if (fm_eth->type == FM_ETH_1G_E)
763 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
765 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
770 #else /* CONFIG_DM_ETH */
771 static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
773 #ifndef CONFIG_SYS_FMAN_V3
777 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
781 #ifndef CONFIG_SYS_FMAN_V3
782 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
783 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
786 switch (fm_eth->mac_type) {
787 #ifdef CONFIG_SYS_FMAN_V3
789 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
793 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
796 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
803 #endif /* CONFIG_DM_ETH */
805 static int init_phy(struct fm_eth *fm_eth)
808 u32 supported = PHY_GBIT_FEATURES;
809 #ifndef CONFIG_DM_ETH
810 struct phy_device *phydev = NULL;
813 if (fm_eth->type == FM_ETH_10G_E)
814 supported = PHY_10G_FEATURES;
815 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
816 supported |= SUPPORTED_2500baseX_Full;
819 if (fm_eth->type == FM_ETH_1G_E)
820 dtsec_init_phy(fm_eth);
824 #ifdef CONFIG_DM_MDIO
825 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
829 fm_eth->phydev->advertising &= supported;
830 fm_eth->phydev->supported &= supported;
832 phy_config(fm_eth->phydev);
834 #else /* CONFIG_DM_ETH */
837 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
840 printf("Failed to connect\n");
847 if (fm_eth->type == FM_ETH_1G_E) {
848 supported = (SUPPORTED_10baseT_Half |
849 SUPPORTED_10baseT_Full |
850 SUPPORTED_100baseT_Half |
851 SUPPORTED_100baseT_Full |
852 SUPPORTED_1000baseT_Full);
854 supported = SUPPORTED_10000baseT_Full;
856 if (tgec_is_fibre(fm_eth))
857 phydev->port = PORT_FIBRE;
860 phydev->supported &= supported;
861 phydev->advertising = phydev->supported;
863 fm_eth->phydev = phydev;
867 #endif /* CONFIG_DM_ETH */
871 #ifndef CONFIG_DM_ETH
872 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
874 struct eth_device *dev;
875 struct fm_eth *fm_eth;
876 int i, num = info->num;
879 /* alloc eth device */
880 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
883 memset(dev, 0, sizeof(struct eth_device));
885 /* alloc the FMan ethernet private struct */
886 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
889 memset(fm_eth, 0, sizeof(struct fm_eth));
891 /* save off some things we need from the info struct */
892 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
894 fm_eth->type = info->type;
896 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
897 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
899 /* set the ethernet max receive length */
900 fm_eth->max_rx_len = MAX_RXBUF_LEN;
902 /* init global mac structure */
903 ret = fm_eth_init_mac(fm_eth, reg);
907 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
908 if (fm_eth->type == FM_ETH_1G_E)
909 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
911 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
913 devlist[num_controllers++] = dev;
915 dev->priv = (void *)fm_eth;
916 dev->init = fm_eth_open;
917 dev->halt = fm_eth_halt;
918 dev->send = fm_eth_send;
919 dev->recv = fm_eth_recv;
921 fm_eth->bus = info->bus;
922 fm_eth->phyaddr = info->phy_addr;
923 fm_eth->enet_if = info->enet_if;
925 /* startup the FM im */
926 ret = fm_eth_startup(fm_eth);
932 /* clear the ethernet address */
933 for (i = 0; i < 6; i++)
934 dev->enetaddr[i] = 0;
939 #else /* CONFIG_DM_ETH */
941 phy_interface_t fman_read_sys_if(struct udevice *dev)
945 if_str = ofnode_read_string(dev->node, "phy-connection-type");
946 debug("MAC system interface mode %s\n", if_str);
948 return phy_get_interface_by_name(if_str);
952 static int fm_eth_bind(struct udevice *dev)
957 if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
958 printf("FMan node property cell-index missing\n");
962 if (dev && dev_read_u32(dev, "cell-index", &num)) {
963 printf("FMan MAC node property cell-index missing\n");
967 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
968 device_set_name(dev, mac_name);
970 debug("%s - binding %s\n", __func__, mac_name);
975 static struct udevice *fm_get_internal_mdio(struct udevice *dev)
977 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
978 struct udevice *mdiodev;
980 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
982 !ofnode_valid(phandle.node)) {
983 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
985 !ofnode_valid(phandle.node)) {
986 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
992 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
993 ofnode_get_parent(phandle.node),
995 printf("can't find MDIO bus for node %s\n",
996 ofnode_get_name(ofnode_get_parent(phandle.node)));
999 debug("Found internal MDIO bus %p\n", mdiodev);
1004 static int fm_eth_probe(struct udevice *dev)
1006 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
1007 struct ofnode_phandle_args args;
1011 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1012 (dev) ? dev->name : "-");
1015 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1020 fm_eth->fm_index = fman_id(dev->parent);
1021 reg = (void *)(uintptr_t)dev_read_addr(dev);
1022 fm_eth->mac_type = dev_get_driver_data(dev);
1023 #ifdef CONFIG_PHYLIB
1024 fm_eth->enet_if = fman_read_sys_if(dev);
1026 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1027 printf("%s: warning - unable to determine interface type\n", __func__);
1029 switch (fm_eth->mac_type) {
1030 #ifndef CONFIG_SYS_FMAN_V3
1032 fm_eth->type = FM_ETH_10G_E;
1037 /* default to 1G, 10G is indicated by port property in dts */
1039 fm_eth->type = FM_ETH_1G_E;
1043 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1044 printf("FMan MAC node property cell-index missing\n");
1048 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1050 goto ports_ref_failure;
1051 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1053 goto ports_ref_failure;
1054 fm_eth->rx_port = fman_port(dev->parent, index);
1056 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1057 fm_eth->type = FM_ETH_10G_E;
1059 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1061 goto ports_ref_failure;
1062 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1064 goto ports_ref_failure;
1065 fm_eth->tx_port = fman_port(dev->parent, index);
1067 /* set the ethernet max receive length */
1068 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1070 switch (fm_eth->enet_if) {
1071 case PHY_INTERFACE_MODE_QSGMII:
1072 /* all PCS blocks are accessed on one controller */
1073 if (fm_eth->num != 0)
1075 case PHY_INTERFACE_MODE_SGMII:
1076 case PHY_INTERFACE_MODE_SGMII_2500:
1077 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1083 /* init global mac structure */
1084 ret = fm_eth_init_mac(fm_eth, reg);
1088 /* startup the FM im */
1089 ret = fm_eth_startup(fm_eth);
1092 ret = init_phy(fm_eth);
1097 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1101 static int fm_eth_remove(struct udevice *dev)
1106 static const struct eth_ops fm_eth_ops = {
1107 .start = fm_eth_open,
1108 .send = fm_eth_send,
1109 .recv = fm_eth_recv,
1110 .free_pkt = fm_eth_free_pkt,
1111 .stop = fm_eth_halt,
1114 static const struct udevice_id fm_eth_ids[] = {
1115 #ifdef CONFIG_SYS_FMAN_V3
1116 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1118 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1119 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1124 U_BOOT_DRIVER(eth_fman) = {
1127 .of_match = fm_eth_ids,
1128 .bind = fm_eth_bind,
1129 .probe = fm_eth_probe,
1130 .remove = fm_eth_remove,
1132 .priv_auto_alloc_size = sizeof(struct fm_eth),
1133 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1134 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1136 #endif /* CONFIG_DM_ETH */