1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
15 #include <fsl_dtsec.h>
17 #include <fsl_memac.h>
21 static struct eth_device *devlist[NUM_FM_PORTS];
22 static int num_controllers;
24 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
26 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
29 #define TBIANA_SGMII_ACK 0x4001
31 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
32 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
34 /* Configure the TBI for SGMII operation */
35 static void dtsec_configure_serdes(struct fm_eth *priv)
37 #ifdef CONFIG_SYS_FMAN_V3
40 bus.priv = priv->mac->phyregs;
41 bool sgmii_2500 = (priv->enet_if ==
42 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
46 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
48 value = PHY_SGMII_CR_PHY_RESET |
49 PHY_SGMII_IF_SPEED_GIGABIT |
50 PHY_SGMII_IF_MODE_SGMII;
52 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
54 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
56 /* Dev ability according to SGMII specification */
57 value = PHY_SGMII_DEV_ABILITY_SGMII;
58 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
61 /* Adjust link timer for 2.5G SGMII,
62 * 1.6 ms in units of 3.2 ns:
63 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
65 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
66 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
68 /* Adjust link timer for SGMII,
69 * 1.6 ms in units of 8 ns:
70 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
72 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
73 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
77 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
78 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
80 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
85 struct dtsec *regs = priv->mac->base;
86 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
89 * Access TBI PHY registers at given TSEC register offset as
90 * opposed to the register offset used for external PHY accesses
92 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
94 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
96 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
97 TBI_CR, TBICR_SETTINGS);
101 static void dtsec_init_phy(struct fm_eth *fm_eth)
103 #ifndef CONFIG_SYS_FMAN_V3
104 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
106 /* Assign a Physical address to the TBI */
107 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
110 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
111 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
112 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
113 dtsec_configure_serdes(fm_eth);
117 static int tgec_is_fibre(struct fm_eth *fm)
121 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
123 return hwconfig_arg_cmp(phyopt, "xfi");
128 static u16 muram_readw(u16 *addr)
130 ulong base = (ulong)addr & ~0x3UL;
131 u32 val32 = in_be32((void *)base);
135 byte_pos = (ulong)addr & 0x3UL;
137 ret = (u16)(val32 & 0x0000ffff);
139 ret = (u16)((val32 & 0xffff0000) >> 16);
144 static void muram_writew(u16 *addr, u16 val)
146 ulong base = (ulong)addr & ~0x3UL;
147 u32 org32 = in_be32((void *)base);
151 byte_pos = (ulong)addr & 0x3UL;
153 val32 = (org32 & 0xffff0000) | val;
155 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
157 out_be32((void *)base, val32);
160 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
162 int timeout = 1000000;
164 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
166 /* wait until the rx port is not busy */
167 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
171 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
173 /* set BMI to independent mode, Rx port disable */
174 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
175 /* clear FOF in IM case */
176 out_be32(&rx_port->fmbm_rim, 0);
177 /* Rx frame next engine -RISC */
178 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
179 /* Rx command attribute - no order, MR[3] = 1 */
180 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
181 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
182 /* enable Rx statistic counters */
183 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
184 /* disable Rx performance counters */
185 out_be32(&rx_port->fmbm_rpc, 0);
188 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
190 int timeout = 1000000;
192 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
194 /* wait until the tx port is not busy */
195 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
199 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
201 /* set BMI to independent mode, Tx port disable */
202 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
203 /* Tx frame next engine -RISC */
204 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
205 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
206 /* Tx command attribute - no order, MR[3] = 1 */
207 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
208 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
209 /* enable Tx statistic counters */
210 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
211 /* disable Tx performance counters */
212 out_be32(&tx_port->fmbm_tpc, 0);
215 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
217 struct fm_port_global_pram *pram;
218 u32 pram_page_offset;
219 void *rx_bd_ring_base;
221 u32 bd_ring_base_lo, bd_ring_base_hi;
223 struct fm_port_bd *rxbd;
224 struct fm_port_qd *rxqd;
225 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
228 /* alloc global parameter ram at MURAM */
229 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
230 FM_PRAM_SIZE, FM_PRAM_ALIGN);
232 printf("%s: No muram for Rx global parameter\n", __func__);
236 fm_eth->rx_pram = pram;
238 /* parameter page offset to MURAM */
239 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
241 /* enable global mode- snooping data buffers and BDs */
242 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
244 /* init the Rx queue descriptor pionter */
245 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
247 /* set the max receive buffer length, power of 2 */
248 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
250 /* alloc Rx buffer descriptors from main memory */
251 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
253 if (!rx_bd_ring_base)
256 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
259 /* alloc Rx buffer from main memory */
260 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
264 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
265 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
267 /* save them to fm_eth */
268 fm_eth->rx_bd_ring = rx_bd_ring_base;
269 fm_eth->cur_rxbd = rx_bd_ring_base;
270 fm_eth->rx_buf = rx_buf_pool;
272 /* init Rx BDs ring */
273 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
274 for (i = 0; i < RX_BD_RING_SIZE; i++) {
275 muram_writew(&rxbd->status, RxBD_EMPTY);
276 muram_writew(&rxbd->len, 0);
277 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
279 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
281 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
282 out_be32(&rxbd->buf_ptr_lo, buf_lo);
286 /* set the Rx queue descriptor */
288 muram_writew(&rxqd->gen, 0);
289 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
290 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
291 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
292 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
293 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
295 muram_writew(&rxqd->offset_in, 0);
296 muram_writew(&rxqd->offset_out, 0);
298 /* set IM parameter ram pointer to Rx Frame Queue ID */
299 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
304 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
306 struct fm_port_global_pram *pram;
307 u32 pram_page_offset;
308 void *tx_bd_ring_base;
309 u32 bd_ring_base_lo, bd_ring_base_hi;
310 struct fm_port_bd *txbd;
311 struct fm_port_qd *txqd;
312 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
315 /* alloc global parameter ram at MURAM */
316 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
317 FM_PRAM_SIZE, FM_PRAM_ALIGN);
319 printf("%s: No muram for Tx global parameter\n", __func__);
322 fm_eth->tx_pram = pram;
324 /* parameter page offset to MURAM */
325 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
327 /* enable global mode- snooping data buffers and BDs */
328 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
330 /* init the Tx queue descriptor pionter */
331 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
333 /* alloc Tx buffer descriptors from main memory */
334 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
336 if (!tx_bd_ring_base)
339 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
341 /* save it to fm_eth */
342 fm_eth->tx_bd_ring = tx_bd_ring_base;
343 fm_eth->cur_txbd = tx_bd_ring_base;
345 /* init Tx BDs ring */
346 txbd = (struct fm_port_bd *)tx_bd_ring_base;
347 for (i = 0; i < TX_BD_RING_SIZE; i++) {
348 muram_writew(&txbd->status, TxBD_LAST);
349 muram_writew(&txbd->len, 0);
350 muram_writew(&txbd->buf_ptr_hi, 0);
351 out_be32(&txbd->buf_ptr_lo, 0);
355 /* set the Tx queue decriptor */
357 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
358 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
359 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
360 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
361 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
363 muram_writew(&txqd->offset_in, 0);
364 muram_writew(&txqd->offset_out, 0);
366 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
367 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
372 static int fm_eth_init(struct fm_eth *fm_eth)
376 ret = fm_eth_rx_port_parameter_init(fm_eth);
380 ret = fm_eth_tx_port_parameter_init(fm_eth);
387 static int fm_eth_startup(struct fm_eth *fm_eth)
389 struct fsl_enet_mac *mac;
394 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
395 ret = fm_eth_init(fm_eth);
398 /* setup the MAC controller */
401 /* For some reason we need to set SPEED_100 */
402 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
403 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
404 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
406 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
408 /* init bmi rx port, IM mode and disable */
409 bmi_rx_port_init(fm_eth->rx_port);
410 /* init bmi tx port, IM mode and disable */
411 bmi_tx_port_init(fm_eth->tx_port);
416 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
418 struct fm_port_global_pram *pram;
420 pram = fm_eth->tx_pram;
421 /* graceful stop transmission of frames */
422 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
426 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
428 struct fm_port_global_pram *pram;
430 pram = fm_eth->tx_pram;
431 /* re-enable transmission of frames */
432 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
436 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
438 struct fm_eth *fm_eth;
439 struct fsl_enet_mac *mac;
444 fm_eth = (struct fm_eth *)dev->priv;
447 /* setup the MAC address */
448 if (dev->enetaddr[0] & 0x01) {
449 printf("%s: MacAddress is multcast address\n", __func__);
452 mac->set_mac_addr(mac, dev->enetaddr);
454 /* enable bmi Rx port */
455 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
456 /* enable MAC rx/tx port */
457 mac->enable_mac(mac);
458 /* enable bmi Tx port */
459 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
460 /* re-enable transmission of frame */
461 fmc_tx_port_graceful_stop_disable(fm_eth);
464 if (fm_eth->phydev) {
465 ret = phy_startup(fm_eth->phydev);
467 printf("%s: Could not initialize\n",
468 fm_eth->phydev->dev->name);
475 fm_eth->phydev->speed = SPEED_1000;
476 fm_eth->phydev->link = 1;
477 fm_eth->phydev->duplex = DUPLEX_FULL;
480 /* set the MAC-PHY mode */
481 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
483 if (!fm_eth->phydev->link)
484 printf("%s: No link.\n", fm_eth->phydev->dev->name);
486 return fm_eth->phydev->link ? 0 : -1;
489 static void fm_eth_halt(struct eth_device *dev)
491 struct fm_eth *fm_eth;
492 struct fsl_enet_mac *mac;
494 fm_eth = (struct fm_eth *)dev->priv;
497 /* graceful stop the transmission of frames */
498 fmc_tx_port_graceful_stop_enable(fm_eth);
499 /* disable bmi Tx port */
500 bmi_tx_port_disable(fm_eth->tx_port);
501 /* disable MAC rx/tx port */
502 mac->disable_mac(mac);
503 /* disable bmi Rx port */
504 bmi_rx_port_disable(fm_eth->rx_port);
508 phy_shutdown(fm_eth->phydev);
512 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
514 struct fm_eth *fm_eth;
515 struct fm_port_global_pram *pram;
516 struct fm_port_bd *txbd, *txbd_base;
520 fm_eth = (struct fm_eth *)dev->priv;
521 pram = fm_eth->tx_pram;
522 txbd = fm_eth->cur_txbd;
524 /* find one empty TxBD */
525 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
528 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
529 dev->name, muram_readw(&txbd->status));
534 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
535 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
536 muram_writew(&txbd->len, len);
538 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
541 /* update TxQD, let RISC to send the packet */
542 offset_in = muram_readw(&pram->txqd.offset_in);
543 offset_in += sizeof(struct fm_port_bd);
544 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
546 muram_writew(&pram->txqd.offset_in, offset_in);
549 /* wait for buffer to be transmitted */
550 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
553 printf("%s: Tx error, txbd->status = 0x%x\n",
554 dev->name, muram_readw(&txbd->status));
559 /* advance the TxBD */
561 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
562 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
564 /* update current txbd */
565 fm_eth->cur_txbd = (void *)txbd;
570 static int fm_eth_recv(struct eth_device *dev)
572 struct fm_eth *fm_eth;
573 struct fm_port_global_pram *pram;
574 struct fm_port_bd *rxbd, *rxbd_base;
581 fm_eth = (struct fm_eth *)dev->priv;
582 pram = fm_eth->rx_pram;
583 rxbd = fm_eth->cur_rxbd;
584 status = muram_readw(&rxbd->status);
586 while (!(status & RxBD_EMPTY)) {
587 if (!(status & RxBD_ERROR)) {
588 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
589 buf_lo = in_be32(&rxbd->buf_ptr_lo);
590 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
591 len = muram_readw(&rxbd->len);
592 net_process_received_packet(data, len);
594 printf("%s: Rx error\n", dev->name);
598 /* clear the RxBDs */
599 muram_writew(&rxbd->status, RxBD_EMPTY);
600 muram_writew(&rxbd->len, 0);
605 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
606 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
608 /* read next status */
609 status = muram_readw(&rxbd->status);
612 offset_out = muram_readw(&pram->rxqd.offset_out);
613 offset_out += sizeof(struct fm_port_bd);
614 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
616 muram_writew(&pram->rxqd.offset_out, offset_out);
619 fm_eth->cur_rxbd = (void *)rxbd;
624 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
626 struct fsl_enet_mac *mac;
628 void *base, *phyregs = NULL;
632 #ifdef CONFIG_SYS_FMAN_V3
633 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
634 if (fm_eth->type == FM_ETH_10G_E) {
635 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
636 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
637 * 10GEC1 uses mEMAC1 on T1024.
638 * so it needs to change the num.
640 if (fm_eth->num >= 2)
646 base = ®->memac[num].fm_memac;
647 phyregs = ®->memac[num].fm_memac_mdio;
649 /* Get the mac registers base address */
650 if (fm_eth->type == FM_ETH_1G_E) {
651 base = ®->mac_1g[num].fm_dtesc;
652 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
654 base = ®->mac_10g[num].fm_10gec;
655 phyregs = ®->mac_10g[num].fm_10gec_mdio;
659 /* alloc mac controller */
660 mac = malloc(sizeof(struct fsl_enet_mac));
663 memset(mac, 0, sizeof(struct fsl_enet_mac));
665 /* save the mac to fm_eth struct */
668 #ifdef CONFIG_SYS_FMAN_V3
669 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
671 if (fm_eth->type == FM_ETH_1G_E)
672 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
674 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
680 static int init_phy(struct fm_eth *fm_eth)
683 struct phy_device *phydev = NULL;
687 if (fm_eth->type == FM_ETH_1G_E)
688 dtsec_init_phy(fm_eth);
692 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
695 printf("Failed to connect\n");
702 if (fm_eth->type == FM_ETH_1G_E) {
703 supported = (SUPPORTED_10baseT_Half |
704 SUPPORTED_10baseT_Full |
705 SUPPORTED_100baseT_Half |
706 SUPPORTED_100baseT_Full |
707 SUPPORTED_1000baseT_Full);
709 supported = SUPPORTED_10000baseT_Full;
711 if (tgec_is_fibre(fm_eth))
712 phydev->port = PORT_FIBRE;
715 phydev->supported &= supported;
716 phydev->advertising = phydev->supported;
718 fm_eth->phydev = phydev;
726 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
728 struct eth_device *dev;
729 struct fm_eth *fm_eth;
730 int i, num = info->num;
733 /* alloc eth device */
734 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
737 memset(dev, 0, sizeof(struct eth_device));
739 /* alloc the FMan ethernet private struct */
740 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
743 memset(fm_eth, 0, sizeof(struct fm_eth));
745 /* save off some things we need from the info struct */
746 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
748 fm_eth->type = info->type;
750 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
751 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
753 /* set the ethernet max receive length */
754 fm_eth->max_rx_len = MAX_RXBUF_LEN;
756 /* init global mac structure */
757 ret = fm_eth_init_mac(fm_eth, reg);
761 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
762 if (fm_eth->type == FM_ETH_1G_E)
763 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
765 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
767 devlist[num_controllers++] = dev;
769 dev->priv = (void *)fm_eth;
770 dev->init = fm_eth_open;
771 dev->halt = fm_eth_halt;
772 dev->send = fm_eth_send;
773 dev->recv = fm_eth_recv;
775 fm_eth->bus = info->bus;
776 fm_eth->phyaddr = info->phy_addr;
777 fm_eth->enet_if = info->enet_if;
779 /* startup the FM im */
780 ret = fm_eth_startup(fm_eth);
786 /* clear the ethernet address */
787 for (i = 0; i < 6; i++)
788 dev->enetaddr[i] = 0;