2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/fsl_dtsec.h>
17 #include <asm/fsl_tgec.h>
18 #include <fsl_memac.h>
22 static struct eth_device *devlist[NUM_FM_PORTS];
23 static int num_controllers;
25 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
27 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
30 #define TBIANA_SGMII_ACK 0x4001
32 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
33 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
35 /* Configure the TBI for SGMII operation */
36 static void dtsec_configure_serdes(struct fm_eth *priv)
38 #ifdef CONFIG_SYS_FMAN_V3
41 bus.priv = priv->mac->phyregs;
42 bool sgmii_2500 = (priv->enet_if ==
43 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
45 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
46 value = PHY_SGMII_IF_MODE_SGMII;
48 value |= PHY_SGMII_IF_MODE_AN;
50 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
52 /* Dev ability according to SGMII specification */
53 value = PHY_SGMII_DEV_ABILITY_SGMII;
54 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
56 /* Adjust link timer for SGMII -
57 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
58 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
59 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
62 value = PHY_SGMII_CR_DEF_VAL;
64 value |= PHY_SGMII_CR_RESET_AN;
65 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
67 struct dtsec *regs = priv->mac->base;
68 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
71 * Access TBI PHY registers at given TSEC register offset as
72 * opposed to the register offset used for external PHY accesses
74 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
76 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
78 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
79 TBI_CR, TBICR_SETTINGS);
83 static void dtsec_init_phy(struct eth_device *dev)
85 struct fm_eth *fm_eth = dev->priv;
86 #ifndef CONFIG_SYS_FMAN_V3
87 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
89 /* Assign a Physical address to the TBI */
90 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
93 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
94 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
95 dtsec_configure_serdes(fm_eth);
99 static int tgec_is_fibre(struct eth_device *dev)
101 struct fm_eth *fm = dev->priv;
104 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
106 return hwconfig_arg_cmp(phyopt, "xfi");
111 static u16 muram_readw(u16 *addr)
113 ulong base = (ulong)addr & ~0x3UL;
114 u32 val32 = in_be32((void *)base);
118 byte_pos = (ulong)addr & 0x3UL;
120 ret = (u16)(val32 & 0x0000ffff);
122 ret = (u16)((val32 & 0xffff0000) >> 16);
127 static void muram_writew(u16 *addr, u16 val)
129 ulong base = (ulong)addr & ~0x3UL;
130 u32 org32 = in_be32((void *)base);
134 byte_pos = (ulong)addr & 0x3UL;
136 val32 = (org32 & 0xffff0000) | val;
138 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
140 out_be32((void *)base, val32);
143 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
145 int timeout = 1000000;
147 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
149 /* wait until the rx port is not busy */
150 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
154 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
156 /* set BMI to independent mode, Rx port disable */
157 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
158 /* clear FOF in IM case */
159 out_be32(&rx_port->fmbm_rim, 0);
160 /* Rx frame next engine -RISC */
161 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
162 /* Rx command attribute - no order, MR[3] = 1 */
163 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
164 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
165 /* enable Rx statistic counters */
166 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
167 /* disable Rx performance counters */
168 out_be32(&rx_port->fmbm_rpc, 0);
171 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
173 int timeout = 1000000;
175 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
177 /* wait until the tx port is not busy */
178 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
182 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
184 /* set BMI to independent mode, Tx port disable */
185 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
186 /* Tx frame next engine -RISC */
187 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
188 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
189 /* Tx command attribute - no order, MR[3] = 1 */
190 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
191 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
192 /* enable Tx statistic counters */
193 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
194 /* disable Tx performance counters */
195 out_be32(&tx_port->fmbm_tpc, 0);
198 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
200 struct fm_port_global_pram *pram;
201 u32 pram_page_offset;
202 void *rx_bd_ring_base;
204 u32 bd_ring_base_lo, bd_ring_base_hi;
206 struct fm_port_bd *rxbd;
207 struct fm_port_qd *rxqd;
208 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
211 /* alloc global parameter ram at MURAM */
212 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
213 FM_PRAM_SIZE, FM_PRAM_ALIGN);
215 printf("%s: No muram for Rx global parameter\n", __func__);
219 fm_eth->rx_pram = pram;
221 /* parameter page offset to MURAM */
222 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
224 /* enable global mode- snooping data buffers and BDs */
225 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
227 /* init the Rx queue descriptor pionter */
228 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
230 /* set the max receive buffer length, power of 2 */
231 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
233 /* alloc Rx buffer descriptors from main memory */
234 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
236 if (!rx_bd_ring_base)
239 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
242 /* alloc Rx buffer from main memory */
243 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
247 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
248 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
250 /* save them to fm_eth */
251 fm_eth->rx_bd_ring = rx_bd_ring_base;
252 fm_eth->cur_rxbd = rx_bd_ring_base;
253 fm_eth->rx_buf = rx_buf_pool;
255 /* init Rx BDs ring */
256 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
257 for (i = 0; i < RX_BD_RING_SIZE; i++) {
258 muram_writew(&rxbd->status, RxBD_EMPTY);
259 muram_writew(&rxbd->len, 0);
260 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
262 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
264 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
265 out_be32(&rxbd->buf_ptr_lo, buf_lo);
269 /* set the Rx queue descriptor */
271 muram_writew(&rxqd->gen, 0);
272 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
273 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
274 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
275 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
276 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
278 muram_writew(&rxqd->offset_in, 0);
279 muram_writew(&rxqd->offset_out, 0);
281 /* set IM parameter ram pointer to Rx Frame Queue ID */
282 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
287 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
289 struct fm_port_global_pram *pram;
290 u32 pram_page_offset;
291 void *tx_bd_ring_base;
292 u32 bd_ring_base_lo, bd_ring_base_hi;
293 struct fm_port_bd *txbd;
294 struct fm_port_qd *txqd;
295 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
298 /* alloc global parameter ram at MURAM */
299 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
300 FM_PRAM_SIZE, FM_PRAM_ALIGN);
302 printf("%s: No muram for Tx global parameter\n", __func__);
305 fm_eth->tx_pram = pram;
307 /* parameter page offset to MURAM */
308 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
310 /* enable global mode- snooping data buffers and BDs */
311 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
313 /* init the Tx queue descriptor pionter */
314 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
316 /* alloc Tx buffer descriptors from main memory */
317 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
319 if (!tx_bd_ring_base)
322 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
324 /* save it to fm_eth */
325 fm_eth->tx_bd_ring = tx_bd_ring_base;
326 fm_eth->cur_txbd = tx_bd_ring_base;
328 /* init Tx BDs ring */
329 txbd = (struct fm_port_bd *)tx_bd_ring_base;
330 for (i = 0; i < TX_BD_RING_SIZE; i++) {
331 muram_writew(&txbd->status, TxBD_LAST);
332 muram_writew(&txbd->len, 0);
333 muram_writew(&txbd->buf_ptr_hi, 0);
334 out_be32(&txbd->buf_ptr_lo, 0);
338 /* set the Tx queue decriptor */
340 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
341 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
342 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
343 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
344 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
346 muram_writew(&txqd->offset_in, 0);
347 muram_writew(&txqd->offset_out, 0);
349 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
350 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
355 static int fm_eth_init(struct fm_eth *fm_eth)
359 ret = fm_eth_rx_port_parameter_init(fm_eth);
363 ret = fm_eth_tx_port_parameter_init(fm_eth);
370 static int fm_eth_startup(struct fm_eth *fm_eth)
372 struct fsl_enet_mac *mac;
377 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
378 ret = fm_eth_init(fm_eth);
381 /* setup the MAC controller */
384 /* For some reason we need to set SPEED_100 */
385 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
386 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
388 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
390 /* init bmi rx port, IM mode and disable */
391 bmi_rx_port_init(fm_eth->rx_port);
392 /* init bmi tx port, IM mode and disable */
393 bmi_tx_port_init(fm_eth->tx_port);
398 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
400 struct fm_port_global_pram *pram;
402 pram = fm_eth->tx_pram;
403 /* graceful stop transmission of frames */
404 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
408 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
410 struct fm_port_global_pram *pram;
412 pram = fm_eth->tx_pram;
413 /* re-enable transmission of frames */
414 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
418 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
420 struct fm_eth *fm_eth;
421 struct fsl_enet_mac *mac;
426 fm_eth = (struct fm_eth *)dev->priv;
429 /* setup the MAC address */
430 if (dev->enetaddr[0] & 0x01) {
431 printf("%s: MacAddress is multcast address\n", __func__);
434 mac->set_mac_addr(mac, dev->enetaddr);
436 /* enable bmi Rx port */
437 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
438 /* enable MAC rx/tx port */
439 mac->enable_mac(mac);
440 /* enable bmi Tx port */
441 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
442 /* re-enable transmission of frame */
443 fmc_tx_port_graceful_stop_disable(fm_eth);
446 if (fm_eth->phydev) {
447 ret = phy_startup(fm_eth->phydev);
449 printf("%s: Could not initialize\n",
450 fm_eth->phydev->dev->name);
457 fm_eth->phydev->speed = SPEED_1000;
458 fm_eth->phydev->link = 1;
459 fm_eth->phydev->duplex = DUPLEX_FULL;
462 /* set the MAC-PHY mode */
463 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
465 if (!fm_eth->phydev->link)
466 printf("%s: No link.\n", fm_eth->phydev->dev->name);
468 return fm_eth->phydev->link ? 0 : -1;
471 static void fm_eth_halt(struct eth_device *dev)
473 struct fm_eth *fm_eth;
474 struct fsl_enet_mac *mac;
476 fm_eth = (struct fm_eth *)dev->priv;
479 /* graceful stop the transmission of frames */
480 fmc_tx_port_graceful_stop_enable(fm_eth);
481 /* disable bmi Tx port */
482 bmi_tx_port_disable(fm_eth->tx_port);
483 /* disable MAC rx/tx port */
484 mac->disable_mac(mac);
485 /* disable bmi Rx port */
486 bmi_rx_port_disable(fm_eth->rx_port);
490 phy_shutdown(fm_eth->phydev);
494 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
496 struct fm_eth *fm_eth;
497 struct fm_port_global_pram *pram;
498 struct fm_port_bd *txbd, *txbd_base;
502 fm_eth = (struct fm_eth *)dev->priv;
503 pram = fm_eth->tx_pram;
504 txbd = fm_eth->cur_txbd;
506 /* find one empty TxBD */
507 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
510 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
511 dev->name, muram_readw(&txbd->status));
516 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
517 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
518 muram_writew(&txbd->len, len);
520 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
523 /* update TxQD, let RISC to send the packet */
524 offset_in = muram_readw(&pram->txqd.offset_in);
525 offset_in += sizeof(struct fm_port_bd);
526 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
528 muram_writew(&pram->txqd.offset_in, offset_in);
531 /* wait for buffer to be transmitted */
532 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
535 printf("%s: Tx error, txbd->status = 0x%x\n",
536 dev->name, muram_readw(&txbd->status));
541 /* advance the TxBD */
543 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
544 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
546 /* update current txbd */
547 fm_eth->cur_txbd = (void *)txbd;
552 static int fm_eth_recv(struct eth_device *dev)
554 struct fm_eth *fm_eth;
555 struct fm_port_global_pram *pram;
556 struct fm_port_bd *rxbd, *rxbd_base;
563 fm_eth = (struct fm_eth *)dev->priv;
564 pram = fm_eth->rx_pram;
565 rxbd = fm_eth->cur_rxbd;
566 status = muram_readw(&rxbd->status);
568 while (!(status & RxBD_EMPTY)) {
569 if (!(status & RxBD_ERROR)) {
570 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
571 buf_lo = in_be32(&rxbd->buf_ptr_lo);
572 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
573 len = muram_readw(&rxbd->len);
574 net_process_received_packet(data, len);
576 printf("%s: Rx error\n", dev->name);
580 /* clear the RxBDs */
581 muram_writew(&rxbd->status, RxBD_EMPTY);
582 muram_writew(&rxbd->len, 0);
587 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
588 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
590 /* read next status */
591 status = muram_readw(&rxbd->status);
594 offset_out = muram_readw(&pram->rxqd.offset_out);
595 offset_out += sizeof(struct fm_port_bd);
596 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
598 muram_writew(&pram->rxqd.offset_out, offset_out);
601 fm_eth->cur_rxbd = (void *)rxbd;
606 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
608 struct fsl_enet_mac *mac;
610 void *base, *phyregs = NULL;
614 #ifdef CONFIG_SYS_FMAN_V3
615 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
616 if (fm_eth->type == FM_ETH_10G_E) {
617 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
618 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
619 * 10GEC1 uses mEMAC1 on T1024.
620 * so it needs to change the num.
622 if (fm_eth->num >= 2)
628 base = ®->memac[num].fm_memac;
629 phyregs = ®->memac[num].fm_memac_mdio;
631 /* Get the mac registers base address */
632 if (fm_eth->type == FM_ETH_1G_E) {
633 base = ®->mac_1g[num].fm_dtesc;
634 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
636 base = ®->mac_10g[num].fm_10gec;
637 phyregs = ®->mac_10g[num].fm_10gec_mdio;
641 /* alloc mac controller */
642 mac = malloc(sizeof(struct fsl_enet_mac));
645 memset(mac, 0, sizeof(struct fsl_enet_mac));
647 /* save the mac to fm_eth struct */
650 #ifdef CONFIG_SYS_FMAN_V3
651 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
653 if (fm_eth->type == FM_ETH_1G_E)
654 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
656 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
662 static int init_phy(struct eth_device *dev)
664 struct fm_eth *fm_eth = dev->priv;
666 struct phy_device *phydev = NULL;
670 if (fm_eth->type == FM_ETH_1G_E)
675 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
678 printf("Failed to connect\n");
685 if (fm_eth->type == FM_ETH_1G_E) {
686 supported = (SUPPORTED_10baseT_Half |
687 SUPPORTED_10baseT_Full |
688 SUPPORTED_100baseT_Half |
689 SUPPORTED_100baseT_Full |
690 SUPPORTED_1000baseT_Full);
692 supported = SUPPORTED_10000baseT_Full;
694 if (tgec_is_fibre(dev))
695 phydev->port = PORT_FIBRE;
698 phydev->supported &= supported;
699 phydev->advertising = phydev->supported;
701 fm_eth->phydev = phydev;
709 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
711 struct eth_device *dev;
712 struct fm_eth *fm_eth;
713 int i, num = info->num;
716 /* alloc eth device */
717 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
720 memset(dev, 0, sizeof(struct eth_device));
722 /* alloc the FMan ethernet private struct */
723 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
726 memset(fm_eth, 0, sizeof(struct fm_eth));
728 /* save off some things we need from the info struct */
729 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
731 fm_eth->type = info->type;
733 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
734 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
736 /* set the ethernet max receive length */
737 fm_eth->max_rx_len = MAX_RXBUF_LEN;
739 /* init global mac structure */
740 ret = fm_eth_init_mac(fm_eth, reg);
744 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
745 if (fm_eth->type == FM_ETH_1G_E)
746 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
748 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
750 devlist[num_controllers++] = dev;
752 dev->priv = (void *)fm_eth;
753 dev->init = fm_eth_open;
754 dev->halt = fm_eth_halt;
755 dev->send = fm_eth_send;
756 dev->recv = fm_eth_recv;
758 fm_eth->bus = info->bus;
759 fm_eth->phyaddr = info->phy_addr;
760 fm_eth->enet_if = info->enet_if;
762 /* startup the FM im */
763 ret = fm_eth_startup(fm_eth);
769 /* clear the ethernet address */
770 for (i = 0; i < 6; i++)
771 dev->enetaddr[i] = 0;