2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/fsl_dtsec.h>
17 #include <asm/fsl_tgec.h>
18 #include <fsl_memac.h>
22 static struct eth_device *devlist[NUM_FM_PORTS];
23 static int num_controllers;
25 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
27 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
30 #define TBIANA_SGMII_ACK 0x4001
32 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
33 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
35 /* Configure the TBI for SGMII operation */
36 static void dtsec_configure_serdes(struct fm_eth *priv)
38 #ifdef CONFIG_SYS_FMAN_V3
41 bus.priv = priv->mac->phyregs;
42 bool sgmii_2500 = (priv->enet_if ==
43 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
45 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
46 value = PHY_SGMII_IF_MODE_SGMII;
48 value |= PHY_SGMII_IF_MODE_AN;
50 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
52 /* Dev ability according to SGMII specification */
53 value = PHY_SGMII_DEV_ABILITY_SGMII;
54 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
56 /* Adjust link timer for SGMII -
57 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
58 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
59 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
62 value = PHY_SGMII_CR_DEF_VAL;
64 value |= PHY_SGMII_CR_RESET_AN;
65 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
67 struct dtsec *regs = priv->mac->base;
68 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
71 * Access TBI PHY registers at given TSEC register offset as
72 * opposed to the register offset used for external PHY accesses
74 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
76 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
78 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
79 TBI_CR, TBICR_SETTINGS);
83 static void dtsec_init_phy(struct eth_device *dev)
85 struct fm_eth *fm_eth = dev->priv;
86 #ifndef CONFIG_SYS_FMAN_V3
87 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
89 /* Assign a Physical address to the TBI */
90 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
93 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
94 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
95 dtsec_configure_serdes(fm_eth);
98 static int tgec_is_fibre(struct eth_device *dev)
100 struct fm_eth *fm = dev->priv;
103 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
105 return hwconfig_arg_cmp(phyopt, "xfi");
109 static u16 muram_readw(u16 *addr)
111 ulong base = (ulong)addr & ~0x3UL;
112 u32 val32 = in_be32((void *)base);
116 byte_pos = (ulong)addr & 0x3UL;
118 ret = (u16)(val32 & 0x0000ffff);
120 ret = (u16)((val32 & 0xffff0000) >> 16);
125 static void muram_writew(u16 *addr, u16 val)
127 ulong base = (ulong)addr & ~0x3UL;
128 u32 org32 = in_be32((void *)base);
132 byte_pos = (ulong)addr & 0x3UL;
134 val32 = (org32 & 0xffff0000) | val;
136 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
138 out_be32((void *)base, val32);
141 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
143 int timeout = 1000000;
145 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
147 /* wait until the rx port is not busy */
148 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
152 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
154 /* set BMI to independent mode, Rx port disable */
155 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
156 /* clear FOF in IM case */
157 out_be32(&rx_port->fmbm_rim, 0);
158 /* Rx frame next engine -RISC */
159 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
160 /* Rx command attribute - no order, MR[3] = 1 */
161 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
162 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
163 /* enable Rx statistic counters */
164 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
165 /* disable Rx performance counters */
166 out_be32(&rx_port->fmbm_rpc, 0);
169 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
171 int timeout = 1000000;
173 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
175 /* wait until the tx port is not busy */
176 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
180 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
182 /* set BMI to independent mode, Tx port disable */
183 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
184 /* Tx frame next engine -RISC */
185 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
186 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
187 /* Tx command attribute - no order, MR[3] = 1 */
188 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
189 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
190 /* enable Tx statistic counters */
191 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
192 /* disable Tx performance counters */
193 out_be32(&tx_port->fmbm_tpc, 0);
196 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
198 struct fm_port_global_pram *pram;
199 u32 pram_page_offset;
200 void *rx_bd_ring_base;
202 u32 bd_ring_base_lo, bd_ring_base_hi;
204 struct fm_port_bd *rxbd;
205 struct fm_port_qd *rxqd;
206 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
209 /* alloc global parameter ram at MURAM */
210 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
211 FM_PRAM_SIZE, FM_PRAM_ALIGN);
213 printf("%s: No muram for Rx global parameter\n", __func__);
217 fm_eth->rx_pram = pram;
219 /* parameter page offset to MURAM */
220 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
222 /* enable global mode- snooping data buffers and BDs */
223 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
225 /* init the Rx queue descriptor pionter */
226 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
228 /* set the max receive buffer length, power of 2 */
229 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
231 /* alloc Rx buffer descriptors from main memory */
232 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
234 if (!rx_bd_ring_base)
237 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
240 /* alloc Rx buffer from main memory */
241 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
245 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
246 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
248 /* save them to fm_eth */
249 fm_eth->rx_bd_ring = rx_bd_ring_base;
250 fm_eth->cur_rxbd = rx_bd_ring_base;
251 fm_eth->rx_buf = rx_buf_pool;
253 /* init Rx BDs ring */
254 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
255 for (i = 0; i < RX_BD_RING_SIZE; i++) {
256 muram_writew(&rxbd->status, RxBD_EMPTY);
257 muram_writew(&rxbd->len, 0);
258 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
260 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
262 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
263 out_be32(&rxbd->buf_ptr_lo, buf_lo);
267 /* set the Rx queue descriptor */
269 muram_writew(&rxqd->gen, 0);
270 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
271 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
272 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
273 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
274 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
276 muram_writew(&rxqd->offset_in, 0);
277 muram_writew(&rxqd->offset_out, 0);
279 /* set IM parameter ram pointer to Rx Frame Queue ID */
280 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
285 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
287 struct fm_port_global_pram *pram;
288 u32 pram_page_offset;
289 void *tx_bd_ring_base;
290 u32 bd_ring_base_lo, bd_ring_base_hi;
291 struct fm_port_bd *txbd;
292 struct fm_port_qd *txqd;
293 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
296 /* alloc global parameter ram at MURAM */
297 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
298 FM_PRAM_SIZE, FM_PRAM_ALIGN);
300 printf("%s: No muram for Tx global parameter\n", __func__);
303 fm_eth->tx_pram = pram;
305 /* parameter page offset to MURAM */
306 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
308 /* enable global mode- snooping data buffers and BDs */
309 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
311 /* init the Tx queue descriptor pionter */
312 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
314 /* alloc Tx buffer descriptors from main memory */
315 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
317 if (!tx_bd_ring_base)
320 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
322 /* save it to fm_eth */
323 fm_eth->tx_bd_ring = tx_bd_ring_base;
324 fm_eth->cur_txbd = tx_bd_ring_base;
326 /* init Tx BDs ring */
327 txbd = (struct fm_port_bd *)tx_bd_ring_base;
328 for (i = 0; i < TX_BD_RING_SIZE; i++) {
329 muram_writew(&txbd->status, TxBD_LAST);
330 muram_writew(&txbd->len, 0);
331 muram_writew(&txbd->buf_ptr_hi, 0);
332 out_be32(&txbd->buf_ptr_lo, 0);
336 /* set the Tx queue decriptor */
338 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
339 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
340 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
341 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
342 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
344 muram_writew(&txqd->offset_in, 0);
345 muram_writew(&txqd->offset_out, 0);
347 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
348 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
353 static int fm_eth_init(struct fm_eth *fm_eth)
357 ret = fm_eth_rx_port_parameter_init(fm_eth);
361 ret = fm_eth_tx_port_parameter_init(fm_eth);
368 static int fm_eth_startup(struct fm_eth *fm_eth)
370 struct fsl_enet_mac *mac;
375 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
376 ret = fm_eth_init(fm_eth);
379 /* setup the MAC controller */
382 /* For some reason we need to set SPEED_100 */
383 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
384 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
386 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
388 /* init bmi rx port, IM mode and disable */
389 bmi_rx_port_init(fm_eth->rx_port);
390 /* init bmi tx port, IM mode and disable */
391 bmi_tx_port_init(fm_eth->tx_port);
396 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
398 struct fm_port_global_pram *pram;
400 pram = fm_eth->tx_pram;
401 /* graceful stop transmission of frames */
402 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
406 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
408 struct fm_port_global_pram *pram;
410 pram = fm_eth->tx_pram;
411 /* re-enable transmission of frames */
412 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
416 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
418 struct fm_eth *fm_eth;
419 struct fsl_enet_mac *mac;
424 fm_eth = (struct fm_eth *)dev->priv;
427 /* setup the MAC address */
428 if (dev->enetaddr[0] & 0x01) {
429 printf("%s: MacAddress is multcast address\n", __func__);
432 mac->set_mac_addr(mac, dev->enetaddr);
434 /* enable bmi Rx port */
435 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
436 /* enable MAC rx/tx port */
437 mac->enable_mac(mac);
438 /* enable bmi Tx port */
439 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
440 /* re-enable transmission of frame */
441 fmc_tx_port_graceful_stop_disable(fm_eth);
444 if (fm_eth->phydev) {
445 ret = phy_startup(fm_eth->phydev);
447 printf("%s: Could not initialize\n",
448 fm_eth->phydev->dev->name);
455 fm_eth->phydev->speed = SPEED_1000;
456 fm_eth->phydev->link = 1;
457 fm_eth->phydev->duplex = DUPLEX_FULL;
460 /* set the MAC-PHY mode */
461 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
463 if (!fm_eth->phydev->link)
464 printf("%s: No link.\n", fm_eth->phydev->dev->name);
466 return fm_eth->phydev->link ? 0 : -1;
469 static void fm_eth_halt(struct eth_device *dev)
471 struct fm_eth *fm_eth;
472 struct fsl_enet_mac *mac;
474 fm_eth = (struct fm_eth *)dev->priv;
477 /* graceful stop the transmission of frames */
478 fmc_tx_port_graceful_stop_enable(fm_eth);
479 /* disable bmi Tx port */
480 bmi_tx_port_disable(fm_eth->tx_port);
481 /* disable MAC rx/tx port */
482 mac->disable_mac(mac);
483 /* disable bmi Rx port */
484 bmi_rx_port_disable(fm_eth->rx_port);
487 phy_shutdown(fm_eth->phydev);
490 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
492 struct fm_eth *fm_eth;
493 struct fm_port_global_pram *pram;
494 struct fm_port_bd *txbd, *txbd_base;
498 fm_eth = (struct fm_eth *)dev->priv;
499 pram = fm_eth->tx_pram;
500 txbd = fm_eth->cur_txbd;
502 /* find one empty TxBD */
503 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
506 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
507 dev->name, muram_readw(&txbd->status));
512 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
513 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
514 muram_writew(&txbd->len, len);
516 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
519 /* update TxQD, let RISC to send the packet */
520 offset_in = muram_readw(&pram->txqd.offset_in);
521 offset_in += sizeof(struct fm_port_bd);
522 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
524 muram_writew(&pram->txqd.offset_in, offset_in);
527 /* wait for buffer to be transmitted */
528 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
531 printf("%s: Tx error, txbd->status = 0x%x\n",
532 dev->name, muram_readw(&txbd->status));
537 /* advance the TxBD */
539 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
540 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
542 /* update current txbd */
543 fm_eth->cur_txbd = (void *)txbd;
548 static int fm_eth_recv(struct eth_device *dev)
550 struct fm_eth *fm_eth;
551 struct fm_port_global_pram *pram;
552 struct fm_port_bd *rxbd, *rxbd_base;
559 fm_eth = (struct fm_eth *)dev->priv;
560 pram = fm_eth->rx_pram;
561 rxbd = fm_eth->cur_rxbd;
562 status = muram_readw(&rxbd->status);
564 while (!(status & RxBD_EMPTY)) {
565 if (!(status & RxBD_ERROR)) {
566 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
567 buf_lo = in_be32(&rxbd->buf_ptr_lo);
568 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
569 len = muram_readw(&rxbd->len);
570 net_process_received_packet(data, len);
572 printf("%s: Rx error\n", dev->name);
576 /* clear the RxBDs */
577 muram_writew(&rxbd->status, RxBD_EMPTY);
578 muram_writew(&rxbd->len, 0);
583 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
584 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
586 /* read next status */
587 status = muram_readw(&rxbd->status);
590 offset_out = muram_readw(&pram->rxqd.offset_out);
591 offset_out += sizeof(struct fm_port_bd);
592 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
594 muram_writew(&pram->rxqd.offset_out, offset_out);
597 fm_eth->cur_rxbd = (void *)rxbd;
602 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
604 struct fsl_enet_mac *mac;
606 void *base, *phyregs = NULL;
610 #ifdef CONFIG_SYS_FMAN_V3
611 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
612 if (fm_eth->type == FM_ETH_10G_E) {
613 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
614 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
615 * 10GEC1 uses mEMAC1 on T1024.
616 * so it needs to change the num.
618 if (fm_eth->num >= 2)
624 base = ®->memac[num].fm_memac;
625 phyregs = ®->memac[num].fm_memac_mdio;
627 /* Get the mac registers base address */
628 if (fm_eth->type == FM_ETH_1G_E) {
629 base = ®->mac_1g[num].fm_dtesc;
630 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
632 base = ®->mac_10g[num].fm_10gec;
633 phyregs = ®->mac_10g[num].fm_10gec_mdio;
637 /* alloc mac controller */
638 mac = malloc(sizeof(struct fsl_enet_mac));
641 memset(mac, 0, sizeof(struct fsl_enet_mac));
643 /* save the mac to fm_eth struct */
646 #ifdef CONFIG_SYS_FMAN_V3
647 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
649 if (fm_eth->type == FM_ETH_1G_E)
650 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
652 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
658 static int init_phy(struct eth_device *dev)
660 struct fm_eth *fm_eth = dev->priv;
661 struct phy_device *phydev = NULL;
665 if (fm_eth->type == FM_ETH_1G_E)
669 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
672 printf("Failed to connect\n");
679 if (fm_eth->type == FM_ETH_1G_E) {
680 supported = (SUPPORTED_10baseT_Half |
681 SUPPORTED_10baseT_Full |
682 SUPPORTED_100baseT_Half |
683 SUPPORTED_100baseT_Full |
684 SUPPORTED_1000baseT_Full);
686 supported = SUPPORTED_10000baseT_Full;
688 if (tgec_is_fibre(dev))
689 phydev->port = PORT_FIBRE;
692 phydev->supported &= supported;
693 phydev->advertising = phydev->supported;
695 fm_eth->phydev = phydev;
703 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
705 struct eth_device *dev;
706 struct fm_eth *fm_eth;
707 int i, num = info->num;
710 /* alloc eth device */
711 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
714 memset(dev, 0, sizeof(struct eth_device));
716 /* alloc the FMan ethernet private struct */
717 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
720 memset(fm_eth, 0, sizeof(struct fm_eth));
722 /* save off some things we need from the info struct */
723 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
725 fm_eth->type = info->type;
727 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
728 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
730 /* set the ethernet max receive length */
731 fm_eth->max_rx_len = MAX_RXBUF_LEN;
733 /* init global mac structure */
734 ret = fm_eth_init_mac(fm_eth, reg);
738 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
739 if (fm_eth->type == FM_ETH_1G_E)
740 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
742 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
744 devlist[num_controllers++] = dev;
746 dev->priv = (void *)fm_eth;
747 dev->init = fm_eth_open;
748 dev->halt = fm_eth_halt;
749 dev->send = fm_eth_send;
750 dev->recv = fm_eth_recv;
752 fm_eth->bus = info->bus;
753 fm_eth->phyaddr = info->phy_addr;
754 fm_eth->enet_if = info->enet_if;
756 /* startup the FM im */
757 ret = fm_eth_startup(fm_eth);
763 /* clear the ethernet address */
764 for (i = 0; i < 6; i++)
765 dev->enetaddr[i] = 0;