2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/fsl_dtsec.h>
17 #include <asm/fsl_tgec.h>
18 #include <fsl_memac.h>
22 static struct eth_device *devlist[NUM_FM_PORTS];
23 static int num_controllers;
25 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
27 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
30 #define TBIANA_SGMII_ACK 0x4001
32 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
33 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
35 /* Configure the TBI for SGMII operation */
36 static void dtsec_configure_serdes(struct fm_eth *priv)
38 #ifdef CONFIG_SYS_FMAN_V3
41 bus.priv = priv->mac->phyregs;
42 bool sgmii_2500 = (priv->enet_if ==
43 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
45 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
46 value = PHY_SGMII_IF_MODE_SGMII;
48 value |= PHY_SGMII_IF_MODE_AN;
50 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
52 /* Dev ability according to SGMII specification */
53 value = PHY_SGMII_DEV_ABILITY_SGMII;
54 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
56 /* Adjust link timer for SGMII -
57 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
58 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
59 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
62 value = PHY_SGMII_CR_DEF_VAL;
64 value |= PHY_SGMII_CR_RESET_AN;
65 memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
67 struct dtsec *regs = priv->mac->base;
68 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
71 * Access TBI PHY registers at given TSEC register offset as
72 * opposed to the register offset used for external PHY accesses
74 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
76 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
78 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
79 TBI_CR, TBICR_SETTINGS);
83 static void dtsec_init_phy(struct eth_device *dev)
85 struct fm_eth *fm_eth = dev->priv;
86 #ifndef CONFIG_SYS_FMAN_V3
87 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
89 /* Assign a Physical address to the TBI */
90 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
93 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
94 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
95 dtsec_configure_serdes(fm_eth);
98 static int tgec_is_fibre(struct eth_device *dev)
100 struct fm_eth *fm = dev->priv;
103 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
105 return hwconfig_arg_cmp(phyopt, "xfi");
109 static u16 muram_readw(u16 *addr)
111 u32 base = (u32)addr & ~0x3;
112 u32 val32 = in_be32((u32 *)base);
116 byte_pos = (u32)addr & 0x3;
118 ret = (u16)(val32 & 0x0000ffff);
120 ret = (u16)((val32 & 0xffff0000) >> 16);
125 static void muram_writew(u16 *addr, u16 val)
127 u32 base = (u32)addr & ~0x3;
128 u32 org32 = in_be32((u32 *)base);
132 byte_pos = (u32)addr & 0x3;
134 val32 = (org32 & 0xffff0000) | val;
136 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
138 out_be32((u32 *)base, val32);
141 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
143 int timeout = 1000000;
145 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
147 /* wait until the rx port is not busy */
148 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
152 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
154 /* set BMI to independent mode, Rx port disable */
155 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
156 /* clear FOF in IM case */
157 out_be32(&rx_port->fmbm_rim, 0);
158 /* Rx frame next engine -RISC */
159 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
160 /* Rx command attribute - no order, MR[3] = 1 */
161 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
162 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
163 /* enable Rx statistic counters */
164 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
165 /* disable Rx performance counters */
166 out_be32(&rx_port->fmbm_rpc, 0);
169 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
171 int timeout = 1000000;
173 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
175 /* wait until the tx port is not busy */
176 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
180 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
182 /* set BMI to independent mode, Tx port disable */
183 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
184 /* Tx frame next engine -RISC */
185 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
186 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
187 /* Tx command attribute - no order, MR[3] = 1 */
188 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
189 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
190 /* enable Tx statistic counters */
191 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
192 /* disable Tx performance counters */
193 out_be32(&tx_port->fmbm_tpc, 0);
196 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
198 struct fm_port_global_pram *pram;
199 u32 pram_page_offset;
200 void *rx_bd_ring_base;
202 struct fm_port_bd *rxbd;
203 struct fm_port_qd *rxqd;
204 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
207 /* alloc global parameter ram at MURAM */
208 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
209 FM_PRAM_SIZE, FM_PRAM_ALIGN);
210 fm_eth->rx_pram = pram;
212 /* parameter page offset to MURAM */
213 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
215 /* enable global mode- snooping data buffers and BDs */
216 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
218 /* init the Rx queue descriptor pionter */
219 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
221 /* set the max receive buffer length, power of 2 */
222 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
224 /* alloc Rx buffer descriptors from main memory */
225 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
227 if (!rx_bd_ring_base)
229 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
232 /* alloc Rx buffer from main memory */
233 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
236 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
238 /* save them to fm_eth */
239 fm_eth->rx_bd_ring = rx_bd_ring_base;
240 fm_eth->cur_rxbd = rx_bd_ring_base;
241 fm_eth->rx_buf = rx_buf_pool;
243 /* init Rx BDs ring */
244 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
245 for (i = 0; i < RX_BD_RING_SIZE; i++) {
246 muram_writew(&rxbd->status, RxBD_EMPTY);
247 muram_writew(&rxbd->len, 0);
248 muram_writew(&rxbd->buf_ptr_hi, 0);
249 out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool +
254 /* set the Rx queue descriptor */
256 muram_writew(&rxqd->gen, 0);
257 muram_writew(&rxqd->bd_ring_base_hi, 0);
258 out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
259 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
261 muram_writew(&rxqd->offset_in, 0);
262 muram_writew(&rxqd->offset_out, 0);
264 /* set IM parameter ram pointer to Rx Frame Queue ID */
265 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
270 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
272 struct fm_port_global_pram *pram;
273 u32 pram_page_offset;
274 void *tx_bd_ring_base;
275 struct fm_port_bd *txbd;
276 struct fm_port_qd *txqd;
277 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
280 /* alloc global parameter ram at MURAM */
281 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
282 FM_PRAM_SIZE, FM_PRAM_ALIGN);
283 fm_eth->tx_pram = pram;
285 /* parameter page offset to MURAM */
286 pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
288 /* enable global mode- snooping data buffers and BDs */
289 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
291 /* init the Tx queue descriptor pionter */
292 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
294 /* alloc Tx buffer descriptors from main memory */
295 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
297 if (!tx_bd_ring_base)
299 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
301 /* save it to fm_eth */
302 fm_eth->tx_bd_ring = tx_bd_ring_base;
303 fm_eth->cur_txbd = tx_bd_ring_base;
305 /* init Tx BDs ring */
306 txbd = (struct fm_port_bd *)tx_bd_ring_base;
307 for (i = 0; i < TX_BD_RING_SIZE; i++) {
308 muram_writew(&txbd->status, TxBD_LAST);
309 muram_writew(&txbd->len, 0);
310 muram_writew(&txbd->buf_ptr_hi, 0);
311 out_be32(&txbd->buf_ptr_lo, 0);
315 /* set the Tx queue decriptor */
317 muram_writew(&txqd->bd_ring_base_hi, 0);
318 out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base);
319 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
321 muram_writew(&txqd->offset_in, 0);
322 muram_writew(&txqd->offset_out, 0);
324 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
325 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
330 static int fm_eth_init(struct fm_eth *fm_eth)
333 if (!fm_eth_rx_port_parameter_init(fm_eth))
336 if (!fm_eth_tx_port_parameter_init(fm_eth))
342 static int fm_eth_startup(struct fm_eth *fm_eth)
344 struct fsl_enet_mac *mac;
347 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
348 if (!fm_eth_init(fm_eth))
350 /* setup the MAC controller */
353 /* For some reason we need to set SPEED_100 */
354 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
355 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
357 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
359 /* init bmi rx port, IM mode and disable */
360 bmi_rx_port_init(fm_eth->rx_port);
361 /* init bmi tx port, IM mode and disable */
362 bmi_tx_port_init(fm_eth->tx_port);
367 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
369 struct fm_port_global_pram *pram;
371 pram = fm_eth->tx_pram;
372 /* graceful stop transmission of frames */
373 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
377 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
379 struct fm_port_global_pram *pram;
381 pram = fm_eth->tx_pram;
382 /* re-enable transmission of frames */
383 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
387 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
389 struct fm_eth *fm_eth;
390 struct fsl_enet_mac *mac;
395 fm_eth = (struct fm_eth *)dev->priv;
398 /* setup the MAC address */
399 if (dev->enetaddr[0] & 0x01) {
400 printf("%s: MacAddress is multcast address\n", __func__);
403 mac->set_mac_addr(mac, dev->enetaddr);
405 /* enable bmi Rx port */
406 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
407 /* enable MAC rx/tx port */
408 mac->enable_mac(mac);
409 /* enable bmi Tx port */
410 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
411 /* re-enable transmission of frame */
412 fmc_tx_port_graceful_stop_disable(fm_eth);
415 if (fm_eth->phydev) {
416 ret = phy_startup(fm_eth->phydev);
418 printf("%s: Could not initialize\n",
419 fm_eth->phydev->dev->name);
426 fm_eth->phydev->speed = SPEED_1000;
427 fm_eth->phydev->link = 1;
428 fm_eth->phydev->duplex = DUPLEX_FULL;
431 /* set the MAC-PHY mode */
432 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
434 if (!fm_eth->phydev->link)
435 printf("%s: No link.\n", fm_eth->phydev->dev->name);
437 return fm_eth->phydev->link ? 0 : -1;
440 static void fm_eth_halt(struct eth_device *dev)
442 struct fm_eth *fm_eth;
443 struct fsl_enet_mac *mac;
445 fm_eth = (struct fm_eth *)dev->priv;
448 /* graceful stop the transmission of frames */
449 fmc_tx_port_graceful_stop_enable(fm_eth);
450 /* disable bmi Tx port */
451 bmi_tx_port_disable(fm_eth->tx_port);
452 /* disable MAC rx/tx port */
453 mac->disable_mac(mac);
454 /* disable bmi Rx port */
455 bmi_rx_port_disable(fm_eth->rx_port);
458 phy_shutdown(fm_eth->phydev);
461 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
463 struct fm_eth *fm_eth;
464 struct fm_port_global_pram *pram;
465 struct fm_port_bd *txbd, *txbd_base;
469 fm_eth = (struct fm_eth *)dev->priv;
470 pram = fm_eth->tx_pram;
471 txbd = fm_eth->cur_txbd;
473 /* find one empty TxBD */
474 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
477 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
478 dev->name, muram_readw(&txbd->status));
483 muram_writew(&txbd->buf_ptr_hi, 0);
484 out_be32(&txbd->buf_ptr_lo, (u32)buf);
485 muram_writew(&txbd->len, len);
487 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
490 /* update TxQD, let RISC to send the packet */
491 offset_in = muram_readw(&pram->txqd.offset_in);
492 offset_in += sizeof(struct fm_port_bd);
493 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
495 muram_writew(&pram->txqd.offset_in, offset_in);
498 /* wait for buffer to be transmitted */
499 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
502 printf("%s: Tx error, txbd->status = 0x%x\n",
503 dev->name, muram_readw(&txbd->status));
508 /* advance the TxBD */
510 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
511 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
513 /* update current txbd */
514 fm_eth->cur_txbd = (void *)txbd;
519 static int fm_eth_recv(struct eth_device *dev)
521 struct fm_eth *fm_eth;
522 struct fm_port_global_pram *pram;
523 struct fm_port_bd *rxbd, *rxbd_base;
529 fm_eth = (struct fm_eth *)dev->priv;
530 pram = fm_eth->rx_pram;
531 rxbd = fm_eth->cur_rxbd;
532 status = muram_readw(&rxbd->status);
534 while (!(status & RxBD_EMPTY)) {
535 if (!(status & RxBD_ERROR)) {
536 data = (u8 *)in_be32(&rxbd->buf_ptr_lo);
537 len = muram_readw(&rxbd->len);
538 net_process_received_packet(data, len);
540 printf("%s: Rx error\n", dev->name);
544 /* clear the RxBDs */
545 muram_writew(&rxbd->status, RxBD_EMPTY);
546 muram_writew(&rxbd->len, 0);
551 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
552 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
554 /* read next status */
555 status = muram_readw(&rxbd->status);
558 offset_out = muram_readw(&pram->rxqd.offset_out);
559 offset_out += sizeof(struct fm_port_bd);
560 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
562 muram_writew(&pram->rxqd.offset_out, offset_out);
565 fm_eth->cur_rxbd = (void *)rxbd;
570 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
572 struct fsl_enet_mac *mac;
574 void *base, *phyregs = NULL;
578 #ifdef CONFIG_SYS_FMAN_V3
579 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
580 if (fm_eth->type == FM_ETH_10G_E) {
581 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
582 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
583 * 10GEC1 uses mEMAC1 on T1024.
584 * so it needs to change the num.
586 if (fm_eth->num >= 2)
592 base = ®->memac[num].fm_memac;
593 phyregs = ®->memac[num].fm_memac_mdio;
595 /* Get the mac registers base address */
596 if (fm_eth->type == FM_ETH_1G_E) {
597 base = ®->mac_1g[num].fm_dtesc;
598 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
600 base = ®->mac_10g[num].fm_10gec;
601 phyregs = ®->mac_10g[num].fm_10gec_mdio;
605 /* alloc mac controller */
606 mac = malloc(sizeof(struct fsl_enet_mac));
609 memset(mac, 0, sizeof(struct fsl_enet_mac));
611 /* save the mac to fm_eth struct */
614 #ifdef CONFIG_SYS_FMAN_V3
615 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
617 if (fm_eth->type == FM_ETH_1G_E)
618 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
620 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
626 static int init_phy(struct eth_device *dev)
628 struct fm_eth *fm_eth = dev->priv;
629 struct phy_device *phydev = NULL;
633 if (fm_eth->type == FM_ETH_1G_E)
637 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
640 printf("Failed to connect\n");
647 if (fm_eth->type == FM_ETH_1G_E) {
648 supported = (SUPPORTED_10baseT_Half |
649 SUPPORTED_10baseT_Full |
650 SUPPORTED_100baseT_Half |
651 SUPPORTED_100baseT_Full |
652 SUPPORTED_1000baseT_Full);
654 supported = SUPPORTED_10000baseT_Full;
656 if (tgec_is_fibre(dev))
657 phydev->port = PORT_FIBRE;
660 phydev->supported &= supported;
661 phydev->advertising = phydev->supported;
663 fm_eth->phydev = phydev;
671 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
673 struct eth_device *dev;
674 struct fm_eth *fm_eth;
675 int i, num = info->num;
677 /* alloc eth device */
678 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
681 memset(dev, 0, sizeof(struct eth_device));
683 /* alloc the FMan ethernet private struct */
684 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
687 memset(fm_eth, 0, sizeof(struct fm_eth));
689 /* save off some things we need from the info struct */
690 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
692 fm_eth->type = info->type;
694 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
695 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
697 /* set the ethernet max receive length */
698 fm_eth->max_rx_len = MAX_RXBUF_LEN;
700 /* init global mac structure */
701 if (!fm_eth_init_mac(fm_eth, reg))
704 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
705 if (fm_eth->type == FM_ETH_1G_E)
706 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
708 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
710 devlist[num_controllers++] = dev;
712 dev->priv = (void *)fm_eth;
713 dev->init = fm_eth_open;
714 dev->halt = fm_eth_halt;
715 dev->send = fm_eth_send;
716 dev->recv = fm_eth_recv;
718 fm_eth->bus = info->bus;
719 fm_eth->phyaddr = info->phy_addr;
720 fm_eth->enet_if = info->enet_if;
722 /* startup the FM im */
723 if (!fm_eth_startup(fm_eth))
728 /* clear the ethernet address */
729 for (i = 0; i < 6; i++)
730 dev->enetaddr[i] = 0;