1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
5 * Dave Liu <daveliu@freescale.com>
12 #include <dm/ofnode.h>
13 #include <linux/compat.h>
14 #include <phy_interface.h>
23 #include <fsl_dtsec.h>
25 #include <fsl_memac.h>
30 static struct eth_device *devlist[NUM_FM_PORTS];
31 static int num_controllers;
34 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
36 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
39 #define TBIANA_SGMII_ACK 0x4001
41 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
42 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
44 /* Configure the TBI for SGMII operation */
45 static void dtsec_configure_serdes(struct fm_eth *priv)
47 #ifdef CONFIG_SYS_FMAN_V3
50 bool sgmii_2500 = (priv->enet_if ==
51 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
55 bus.priv = priv->mac->phyregs;
57 bus.priv = priv->pcs_mdio;
59 bus.read = memac_mdio_read;
60 bus.write = memac_mdio_write;
61 bus.reset = memac_mdio_reset;
64 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
66 value = PHY_SGMII_CR_PHY_RESET |
67 PHY_SGMII_IF_SPEED_GIGABIT |
68 PHY_SGMII_IF_MODE_SGMII;
70 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
72 for (j = 0; j <= 3; j++)
73 debug("dump PCS reg %#x: %#x\n", j,
74 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
76 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
78 /* Dev ability according to SGMII specification */
79 value = PHY_SGMII_DEV_ABILITY_SGMII;
80 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
83 /* Adjust link timer for 2.5G SGMII,
84 * 1.6 ms in units of 3.2 ns:
85 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
87 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
88 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
90 /* Adjust link timer for SGMII,
91 * 1.6 ms in units of 8 ns:
92 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
94 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
95 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
99 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
100 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
102 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
107 struct dtsec *regs = priv->mac->base;
108 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
111 * Access TBI PHY registers at given TSEC register offset as
112 * opposed to the register offset used for external PHY accesses
114 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
116 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
118 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
119 TBI_CR, TBICR_SETTINGS);
123 static void dtsec_init_phy(struct fm_eth *fm_eth)
125 #ifndef CONFIG_SYS_FMAN_V3
126 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
128 /* Assign a Physical address to the TBI */
129 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
132 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
133 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
134 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
135 dtsec_configure_serdes(fm_eth);
138 #ifndef CONFIG_DM_ETH
140 static int tgec_is_fibre(struct fm_eth *fm)
144 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
146 return hwconfig_arg_cmp(phyopt, "xfi");
149 #endif /* CONFIG_DM_ETH */
152 static u16 muram_readw(u16 *addr)
154 ulong base = (ulong)addr & ~0x3UL;
155 u32 val32 = in_be32((void *)base);
159 byte_pos = (ulong)addr & 0x3UL;
161 ret = (u16)(val32 & 0x0000ffff);
163 ret = (u16)((val32 & 0xffff0000) >> 16);
168 static void muram_writew(u16 *addr, u16 val)
170 ulong base = (ulong)addr & ~0x3UL;
171 u32 org32 = in_be32((void *)base);
175 byte_pos = (ulong)addr & 0x3UL;
177 val32 = (org32 & 0xffff0000) | val;
179 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
181 out_be32((void *)base, val32);
184 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
186 int timeout = 1000000;
188 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
190 /* wait until the rx port is not busy */
191 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
194 printf("%s - timeout\n", __func__);
197 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
199 /* set BMI to independent mode, Rx port disable */
200 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
201 /* clear FOF in IM case */
202 out_be32(&rx_port->fmbm_rim, 0);
203 /* Rx frame next engine -RISC */
204 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
205 /* Rx command attribute - no order, MR[3] = 1 */
206 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
207 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
208 /* enable Rx statistic counters */
209 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
210 /* disable Rx performance counters */
211 out_be32(&rx_port->fmbm_rpc, 0);
214 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
216 int timeout = 1000000;
218 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
220 /* wait until the tx port is not busy */
221 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
224 printf("%s - timeout\n", __func__);
227 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
229 /* set BMI to independent mode, Tx port disable */
230 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
231 /* Tx frame next engine -RISC */
232 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
233 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
234 /* Tx command attribute - no order, MR[3] = 1 */
235 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
236 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
237 /* enable Tx statistic counters */
238 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
239 /* disable Tx performance counters */
240 out_be32(&tx_port->fmbm_tpc, 0);
243 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
245 struct fm_port_global_pram *pram;
246 u32 pram_page_offset;
247 void *rx_bd_ring_base;
249 u32 bd_ring_base_lo, bd_ring_base_hi;
251 struct fm_port_bd *rxbd;
252 struct fm_port_qd *rxqd;
253 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
256 /* alloc global parameter ram at MURAM */
257 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
258 FM_PRAM_SIZE, FM_PRAM_ALIGN);
260 printf("%s: No muram for Rx global parameter\n", __func__);
264 fm_eth->rx_pram = pram;
266 /* parameter page offset to MURAM */
267 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
269 /* enable global mode- snooping data buffers and BDs */
270 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
272 /* init the Rx queue descriptor pionter */
273 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
275 /* set the max receive buffer length, power of 2 */
276 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
278 /* alloc Rx buffer descriptors from main memory */
279 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
281 if (!rx_bd_ring_base)
284 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
287 /* alloc Rx buffer from main memory */
288 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
292 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
293 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
295 /* save them to fm_eth */
296 fm_eth->rx_bd_ring = rx_bd_ring_base;
297 fm_eth->cur_rxbd = rx_bd_ring_base;
298 fm_eth->rx_buf = rx_buf_pool;
300 /* init Rx BDs ring */
301 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
302 for (i = 0; i < RX_BD_RING_SIZE; i++) {
303 muram_writew(&rxbd->status, RxBD_EMPTY);
304 muram_writew(&rxbd->len, 0);
305 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
307 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
309 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
310 out_be32(&rxbd->buf_ptr_lo, buf_lo);
314 /* set the Rx queue descriptor */
316 muram_writew(&rxqd->gen, 0);
317 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
318 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
319 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
320 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
321 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
323 muram_writew(&rxqd->offset_in, 0);
324 muram_writew(&rxqd->offset_out, 0);
326 /* set IM parameter ram pointer to Rx Frame Queue ID */
327 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
332 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
334 struct fm_port_global_pram *pram;
335 u32 pram_page_offset;
336 void *tx_bd_ring_base;
337 u32 bd_ring_base_lo, bd_ring_base_hi;
338 struct fm_port_bd *txbd;
339 struct fm_port_qd *txqd;
340 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
343 /* alloc global parameter ram at MURAM */
344 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
345 FM_PRAM_SIZE, FM_PRAM_ALIGN);
347 printf("%s: No muram for Tx global parameter\n", __func__);
350 fm_eth->tx_pram = pram;
352 /* parameter page offset to MURAM */
353 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
355 /* enable global mode- snooping data buffers and BDs */
356 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
358 /* init the Tx queue descriptor pionter */
359 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
361 /* alloc Tx buffer descriptors from main memory */
362 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
364 if (!tx_bd_ring_base)
367 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
369 /* save it to fm_eth */
370 fm_eth->tx_bd_ring = tx_bd_ring_base;
371 fm_eth->cur_txbd = tx_bd_ring_base;
373 /* init Tx BDs ring */
374 txbd = (struct fm_port_bd *)tx_bd_ring_base;
375 for (i = 0; i < TX_BD_RING_SIZE; i++) {
376 muram_writew(&txbd->status, TxBD_LAST);
377 muram_writew(&txbd->len, 0);
378 muram_writew(&txbd->buf_ptr_hi, 0);
379 out_be32(&txbd->buf_ptr_lo, 0);
383 /* set the Tx queue decriptor */
385 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
386 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
387 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
388 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
389 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
391 muram_writew(&txqd->offset_in, 0);
392 muram_writew(&txqd->offset_out, 0);
394 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
395 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
400 static int fm_eth_init(struct fm_eth *fm_eth)
404 ret = fm_eth_rx_port_parameter_init(fm_eth);
408 ret = fm_eth_tx_port_parameter_init(fm_eth);
415 static int fm_eth_startup(struct fm_eth *fm_eth)
417 struct fsl_enet_mac *mac;
422 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
423 ret = fm_eth_init(fm_eth);
426 /* setup the MAC controller */
429 /* For some reason we need to set SPEED_100 */
430 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
431 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
432 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
434 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
436 /* init bmi rx port, IM mode and disable */
437 bmi_rx_port_init(fm_eth->rx_port);
438 /* init bmi tx port, IM mode and disable */
439 bmi_tx_port_init(fm_eth->tx_port);
444 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
446 struct fm_port_global_pram *pram;
448 pram = fm_eth->tx_pram;
449 /* graceful stop transmission of frames */
450 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
454 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
456 struct fm_port_global_pram *pram;
458 pram = fm_eth->tx_pram;
459 /* re-enable transmission of frames */
460 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
464 #ifndef CONFIG_DM_ETH
465 static int fm_eth_open(struct eth_device *dev, bd_t *bd)
467 static int fm_eth_open(struct udevice *dev)
470 #ifndef CONFIG_DM_ETH
471 struct fm_eth *fm_eth = dev->priv;
473 struct eth_pdata *pdata = dev_get_platdata(dev);
474 struct fm_eth *fm_eth = dev_get_priv(dev);
476 unsigned char *enetaddr;
477 struct fsl_enet_mac *mac;
484 #ifndef CONFIG_DM_ETH
485 enetaddr = &dev->enetaddr[0];
487 enetaddr = pdata->enetaddr;
490 /* setup the MAC address */
491 if (enetaddr[0] & 0x01) {
492 printf("%s: MacAddress is multicast address\n", __func__);
494 enetaddr[5] = fm_eth->num;
496 mac->set_mac_addr(mac, enetaddr);
498 /* enable bmi Rx port */
499 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
500 /* enable MAC rx/tx port */
501 mac->enable_mac(mac);
502 /* enable bmi Tx port */
503 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
504 /* re-enable transmission of frame */
505 fmc_tx_port_graceful_stop_disable(fm_eth);
508 if (fm_eth->phydev) {
509 ret = phy_startup(fm_eth->phydev);
511 #ifndef CONFIG_DM_ETH
512 printf("%s: Could not initialize\n",
513 fm_eth->phydev->dev->name);
515 printf("%s: Could not initialize\n", dev->name);
523 fm_eth->phydev->speed = SPEED_1000;
524 fm_eth->phydev->link = 1;
525 fm_eth->phydev->duplex = DUPLEX_FULL;
528 /* set the MAC-PHY mode */
529 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
530 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
531 fm_eth->phydev->speed, fm_eth->phydev->link);
533 if (!fm_eth->phydev->link)
534 printf("%s: No link.\n", fm_eth->phydev->dev->name);
536 return fm_eth->phydev->link ? 0 : -1;
539 #ifndef CONFIG_DM_ETH
540 static void fm_eth_halt(struct eth_device *dev)
542 static void fm_eth_halt(struct udevice *dev)
545 struct fm_eth *fm_eth;
546 struct fsl_enet_mac *mac;
548 fm_eth = (struct fm_eth *)dev->priv;
551 /* graceful stop the transmission of frames */
552 fmc_tx_port_graceful_stop_enable(fm_eth);
553 /* disable bmi Tx port */
554 bmi_tx_port_disable(fm_eth->tx_port);
555 /* disable MAC rx/tx port */
556 mac->disable_mac(mac);
557 /* disable bmi Rx port */
558 bmi_rx_port_disable(fm_eth->rx_port);
562 phy_shutdown(fm_eth->phydev);
566 #ifndef CONFIG_DM_ETH
567 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
569 static int fm_eth_send(struct udevice *dev, void *buf, int len)
572 struct fm_eth *fm_eth;
573 struct fm_port_global_pram *pram;
574 struct fm_port_bd *txbd, *txbd_base;
578 fm_eth = (struct fm_eth *)dev->priv;
579 pram = fm_eth->tx_pram;
580 txbd = fm_eth->cur_txbd;
582 /* find one empty TxBD */
583 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
586 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
587 dev->name, muram_readw(&txbd->status));
592 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
593 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
594 muram_writew(&txbd->len, len);
596 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
599 /* update TxQD, let RISC to send the packet */
600 offset_in = muram_readw(&pram->txqd.offset_in);
601 offset_in += sizeof(struct fm_port_bd);
602 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
604 muram_writew(&pram->txqd.offset_in, offset_in);
607 /* wait for buffer to be transmitted */
608 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
611 printf("%s: Tx error, txbd->status = 0x%x\n",
612 dev->name, muram_readw(&txbd->status));
617 /* advance the TxBD */
619 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
620 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
622 /* update current txbd */
623 fm_eth->cur_txbd = (void *)txbd;
628 static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
629 struct fm_port_bd *rxbd)
631 struct fm_port_global_pram *pram;
632 struct fm_port_bd *rxbd_base;
635 pram = fm_eth->rx_pram;
637 /* clear the RxBDs */
638 muram_writew(&rxbd->status, RxBD_EMPTY);
639 muram_writew(&rxbd->len, 0);
644 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
645 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
649 offset_out = muram_readw(&pram->rxqd.offset_out);
650 offset_out += sizeof(struct fm_port_bd);
651 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
653 muram_writew(&pram->rxqd.offset_out, offset_out);
659 #ifndef CONFIG_DM_ETH
660 static int fm_eth_recv(struct eth_device *dev)
662 static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
665 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
666 struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
672 status = muram_readw(&rxbd->status);
674 while (!(status & RxBD_EMPTY)) {
675 if (!(status & RxBD_ERROR)) {
676 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
677 buf_lo = in_be32(&rxbd->buf_ptr_lo);
678 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
679 len = muram_readw(&rxbd->len);
680 #ifndef CONFIG_DM_ETH
681 net_process_received_packet(data, len);
687 printf("%s: Rx error\n", dev->name);
691 /* free current bd, advance to next one */
692 rxbd = fm_eth_free_one(fm_eth, rxbd);
694 /* read next status */
695 status = muram_readw(&rxbd->status);
697 fm_eth->cur_rxbd = (void *)rxbd;
703 static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
705 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
707 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
711 #endif /* CONFIG_DM_ETH */
713 #ifndef CONFIG_DM_ETH
714 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
716 struct fsl_enet_mac *mac;
718 void *base, *phyregs = NULL;
722 #ifdef CONFIG_SYS_FMAN_V3
723 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
724 if (fm_eth->type == FM_ETH_10G_E) {
725 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
726 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
727 * 10GEC1 uses mEMAC1 on T1024.
728 * so it needs to change the num.
730 if (fm_eth->num >= 2)
736 base = ®->memac[num].fm_memac;
737 phyregs = ®->memac[num].fm_memac_mdio;
739 /* Get the mac registers base address */
740 if (fm_eth->type == FM_ETH_1G_E) {
741 base = ®->mac_1g[num].fm_dtesc;
742 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
744 base = ®->mac_10g[num].fm_10gec;
745 phyregs = ®->mac_10g[num].fm_10gec_mdio;
749 /* alloc mac controller */
750 mac = malloc(sizeof(struct fsl_enet_mac));
753 memset(mac, 0, sizeof(struct fsl_enet_mac));
755 /* save the mac to fm_eth struct */
758 #ifdef CONFIG_SYS_FMAN_V3
759 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
761 if (fm_eth->type == FM_ETH_1G_E)
762 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
764 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
769 #else /* CONFIG_DM_ETH */
770 static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
772 #ifndef CONFIG_SYS_FMAN_V3
776 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
780 #ifndef CONFIG_SYS_FMAN_V3
781 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
782 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
785 switch (fm_eth->mac_type) {
786 #ifdef CONFIG_SYS_FMAN_V3
788 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
792 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
795 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
802 #endif /* CONFIG_DM_ETH */
804 static int init_phy(struct fm_eth *fm_eth)
807 u32 supported = PHY_GBIT_FEATURES;
808 #ifndef CONFIG_DM_ETH
809 struct phy_device *phydev = NULL;
812 if (fm_eth->type == FM_ETH_10G_E)
813 supported = PHY_10G_FEATURES;
814 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
815 supported |= SUPPORTED_2500baseX_Full;
818 if (fm_eth->type == FM_ETH_1G_E)
819 dtsec_init_phy(fm_eth);
823 #ifdef CONFIG_DM_MDIO
824 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
828 fm_eth->phydev->advertising &= supported;
829 fm_eth->phydev->supported &= supported;
831 phy_config(fm_eth->phydev);
833 #else /* CONFIG_DM_ETH */
836 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
839 printf("Failed to connect\n");
846 if (fm_eth->type == FM_ETH_1G_E) {
847 supported = (SUPPORTED_10baseT_Half |
848 SUPPORTED_10baseT_Full |
849 SUPPORTED_100baseT_Half |
850 SUPPORTED_100baseT_Full |
851 SUPPORTED_1000baseT_Full);
853 supported = SUPPORTED_10000baseT_Full;
855 if (tgec_is_fibre(fm_eth))
856 phydev->port = PORT_FIBRE;
859 phydev->supported &= supported;
860 phydev->advertising = phydev->supported;
862 fm_eth->phydev = phydev;
866 #endif /* CONFIG_DM_ETH */
870 #ifndef CONFIG_DM_ETH
871 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
873 struct eth_device *dev;
874 struct fm_eth *fm_eth;
875 int i, num = info->num;
878 /* alloc eth device */
879 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
882 memset(dev, 0, sizeof(struct eth_device));
884 /* alloc the FMan ethernet private struct */
885 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
888 memset(fm_eth, 0, sizeof(struct fm_eth));
890 /* save off some things we need from the info struct */
891 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
893 fm_eth->type = info->type;
895 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
896 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
898 /* set the ethernet max receive length */
899 fm_eth->max_rx_len = MAX_RXBUF_LEN;
901 /* init global mac structure */
902 ret = fm_eth_init_mac(fm_eth, reg);
906 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
907 if (fm_eth->type == FM_ETH_1G_E)
908 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
910 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
912 devlist[num_controllers++] = dev;
914 dev->priv = (void *)fm_eth;
915 dev->init = fm_eth_open;
916 dev->halt = fm_eth_halt;
917 dev->send = fm_eth_send;
918 dev->recv = fm_eth_recv;
920 fm_eth->bus = info->bus;
921 fm_eth->phyaddr = info->phy_addr;
922 fm_eth->enet_if = info->enet_if;
924 /* startup the FM im */
925 ret = fm_eth_startup(fm_eth);
931 /* clear the ethernet address */
932 for (i = 0; i < 6; i++)
933 dev->enetaddr[i] = 0;
938 #else /* CONFIG_DM_ETH */
940 phy_interface_t fman_read_sys_if(struct udevice *dev)
944 if_str = ofnode_read_string(dev->node, "phy-connection-type");
945 debug("MAC system interface mode %s\n", if_str);
947 return phy_get_interface_by_name(if_str);
951 static int fm_eth_bind(struct udevice *dev)
956 if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
957 printf("FMan node property cell-index missing\n");
961 if (dev && dev_read_u32(dev, "cell-index", &num)) {
962 printf("FMan MAC node property cell-index missing\n");
966 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
967 device_set_name(dev, mac_name);
969 debug("%s - binding %s\n", __func__, mac_name);
974 static struct udevice *fm_get_internal_mdio(struct udevice *dev)
976 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
977 struct udevice *mdiodev;
979 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
981 !ofnode_valid(phandle.node)) {
982 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
984 !ofnode_valid(phandle.node)) {
985 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
991 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
992 ofnode_get_parent(phandle.node),
994 printf("can't find MDIO bus for node %s\n",
995 ofnode_get_name(ofnode_get_parent(phandle.node)));
998 debug("Found internal MDIO bus %p\n", mdiodev);
1003 static int fm_eth_probe(struct udevice *dev)
1005 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
1006 struct ofnode_phandle_args args;
1010 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1011 (dev) ? dev->name : "-");
1014 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1019 fm_eth->fm_index = fman_id(dev->parent);
1020 reg = (void *)(uintptr_t)dev_read_addr(dev);
1021 fm_eth->mac_type = dev_get_driver_data(dev);
1022 #ifdef CONFIG_PHYLIB
1023 fm_eth->enet_if = fman_read_sys_if(dev);
1025 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1026 printf("%s: warning - unable to determine interface type\n", __func__);
1028 switch (fm_eth->mac_type) {
1029 #ifndef CONFIG_SYS_FMAN_V3
1031 fm_eth->type = FM_ETH_10G_E;
1036 /* default to 1G, 10G is indicated by port property in dts */
1038 fm_eth->type = FM_ETH_1G_E;
1042 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1043 printf("FMan MAC node property cell-index missing\n");
1047 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1049 goto ports_ref_failure;
1050 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1052 goto ports_ref_failure;
1053 fm_eth->rx_port = fman_port(dev->parent, index);
1055 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1056 fm_eth->type = FM_ETH_10G_E;
1058 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1060 goto ports_ref_failure;
1061 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1063 goto ports_ref_failure;
1064 fm_eth->tx_port = fman_port(dev->parent, index);
1066 /* set the ethernet max receive length */
1067 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1069 switch (fm_eth->enet_if) {
1070 case PHY_INTERFACE_MODE_QSGMII:
1071 /* all PCS blocks are accessed on one controller */
1072 if (fm_eth->num != 0)
1074 case PHY_INTERFACE_MODE_SGMII:
1075 case PHY_INTERFACE_MODE_SGMII_2500:
1076 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1082 /* init global mac structure */
1083 ret = fm_eth_init_mac(fm_eth, reg);
1087 /* startup the FM im */
1088 ret = fm_eth_startup(fm_eth);
1091 ret = init_phy(fm_eth);
1096 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1100 static int fm_eth_remove(struct udevice *dev)
1105 static const struct eth_ops fm_eth_ops = {
1106 .start = fm_eth_open,
1107 .send = fm_eth_send,
1108 .recv = fm_eth_recv,
1109 .free_pkt = fm_eth_free_pkt,
1110 .stop = fm_eth_halt,
1113 static const struct udevice_id fm_eth_ids[] = {
1114 #ifdef CONFIG_SYS_FMAN_V3
1115 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1117 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1118 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1123 U_BOOT_DRIVER(eth_fman) = {
1126 .of_match = fm_eth_ids,
1127 .bind = fm_eth_bind,
1128 .probe = fm_eth_probe,
1129 .remove = fm_eth_remove,
1131 .priv_auto_alloc_size = sizeof(struct fm_eth),
1132 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1133 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1135 #endif /* CONFIG_DM_ETH */