2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
41 #ifndef CONFIG_FEC_XCV_TYPE
42 #define CONFIG_FEC_XCV_TYPE MII100
46 * The i.MX28 operates with packets in big endian. We need to swap them before
47 * sending and after receiving.
50 #define CONFIG_FEC_MXC_SWAP_PACKET
56 uint8_t data[1500]; /**< actual data */
57 int length; /**< actual length */
58 int used; /**< buffer in use or not */
59 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
62 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
63 static void swap_packet(uint32_t *packet, int length)
67 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
68 packet[i] = __swab32(packet[i]);
73 * The i.MX28 has two ethernet interfaces, but they are not equal.
74 * Only the first one can access the MDIO bus.
77 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
79 return (struct ethernet_regs *)MXS_ENET0_BASE;
82 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
89 * MII-interface related functions
91 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
94 struct eth_device *edev = eth_get_dev_by_name(dev);
95 struct fec_priv *fec = (struct fec_priv *)edev->priv;
96 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
98 uint32_t reg; /* convenient holder for the PHY register */
99 uint32_t phy; /* convenient holder for the PHY */
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
106 writel(FEC_IEVENT_MII, ð->ievent);
107 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
111 phy | reg, ð->mii_data);
114 * wait for the related interrupt
116 start = get_timer(0);
117 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
118 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
119 printf("Read MDIO failed...\n");
125 * clear mii interrupt bit
127 writel(FEC_IEVENT_MII, ð->ievent);
130 * it's now safe to read the PHY's register
132 *retVal = readl(ð->mii_data);
133 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
138 static void fec_mii_setspeed(struct fec_priv *fec)
141 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
142 * and do not drop the Preamble.
144 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
145 &fec->eth->mii_speed);
146 debug("fec_init: mii_speed %08x\n",
147 readl(&fec->eth->mii_speed));
149 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
152 struct eth_device *edev = eth_get_dev_by_name(dev);
153 struct fec_priv *fec = (struct fec_priv *)edev->priv;
154 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
156 uint32_t reg; /* convenient holder for the PHY register */
157 uint32_t phy; /* convenient holder for the PHY */
160 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
161 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
163 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
164 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
167 * wait for the MII interrupt
169 start = get_timer(0);
170 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
171 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
172 printf("Write MDIO failed...\n");
178 * clear MII interrupt bit
180 writel(FEC_IEVENT_MII, ð->ievent);
181 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
187 static int miiphy_restart_aneg(struct eth_device *dev)
189 struct fec_priv *fec = (struct fec_priv *)dev->priv;
193 * Wake up from sleep if necessary
194 * Reset PHY, then delay 300ns
197 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
199 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
204 * Set the auto-negotiation advertisement register bits
206 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
207 LPA_100FULL | LPA_100HALF | LPA_10FULL |
208 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
209 miiphy_write(dev->name, fec->phy_id, MII_BMCR,
210 BMCR_ANENABLE | BMCR_ANRESTART);
212 if (fec->mii_postcall)
213 ret = fec->mii_postcall(fec->phy_id);
218 static int miiphy_wait_aneg(struct eth_device *dev)
222 struct fec_priv *fec = (struct fec_priv *)dev->priv;
225 * Wait for AN completion
227 start = get_timer(0);
229 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
230 printf("%s: Autonegotiation timeout\n", dev->name);
234 if (miiphy_read(dev->name, fec->phy_id,
235 MII_BMSR, &status)) {
236 printf("%s: Autonegotiation failed. status: 0x%04x\n",
240 } while (!(status & BMSR_LSTATUS));
244 static int fec_rx_task_enable(struct fec_priv *fec)
246 writel(1 << 24, &fec->eth->r_des_active);
250 static int fec_rx_task_disable(struct fec_priv *fec)
255 static int fec_tx_task_enable(struct fec_priv *fec)
257 writel(1 << 24, &fec->eth->x_des_active);
261 static int fec_tx_task_disable(struct fec_priv *fec)
267 * Initialize receive task's buffer descriptors
268 * @param[in] fec all we know about the device yet
269 * @param[in] count receive buffer count to be allocated
270 * @param[in] size size of each receive buffer
271 * @return 0 on success
273 * For this task we need additional memory for the data buffers. And each
274 * data buffer requires some alignment. Thy must be aligned to a specific
275 * boundary each (DB_DATA_ALIGNMENT).
277 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
282 /* reserve data memory and consider alignment */
283 if (fec->rdb_ptr == NULL)
284 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
285 p = (uint32_t)fec->rdb_ptr;
287 puts("fec_mxc: not enough malloc memory\n");
290 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
291 p += DB_DATA_ALIGNMENT-1;
292 p &= ~(DB_DATA_ALIGNMENT-1);
294 for (ix = 0; ix < count; ix++) {
295 writel(p, &fec->rbd_base[ix].data_pointer);
297 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
298 writew(0, &fec->rbd_base[ix].data_length);
301 * mark the last RBD to close the ring
303 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
310 * Initialize transmit task's buffer descriptors
311 * @param[in] fec all we know about the device yet
313 * Transmit buffers are created externally. We only have to init the BDs here.\n
314 * Note: There is a race condition in the hardware. When only one BD is in
315 * use it must be marked with the WRAP bit to use it for every transmitt.
316 * This bit in combination with the READY bit results into double transmit
317 * of each data buffer. It seems the state machine checks READY earlier then
318 * resetting it after the first transfer.
319 * Using two BDs solves this issue.
321 static void fec_tbd_init(struct fec_priv *fec)
323 writew(0x0000, &fec->tbd_base[0].status);
324 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
329 * Mark the given read buffer descriptor as free
330 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
331 * @param[in] pRbd buffer descriptor to mark free again
333 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
336 * Reset buffer descriptor as empty
339 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
341 writew(FEC_RBD_EMPTY, &pRbd->status);
345 writew(0, &pRbd->data_length);
348 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
351 imx_get_mac_from_fuse(dev_id, mac);
352 return !is_valid_ether_addr(mac);
355 static int fec_set_hwaddr(struct eth_device *dev)
357 uchar *mac = dev->enetaddr;
358 struct fec_priv *fec = (struct fec_priv *)dev->priv;
360 writel(0, &fec->eth->iaddr1);
361 writel(0, &fec->eth->iaddr2);
362 writel(0, &fec->eth->gaddr1);
363 writel(0, &fec->eth->gaddr2);
366 * Set physical address
368 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
370 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
376 * Start the FEC engine
377 * @param[in] dev Our device to handle
379 static int fec_open(struct eth_device *edev)
381 struct fec_priv *fec = (struct fec_priv *)edev->priv;
383 debug("fec_open: fec_open(dev)\n");
384 /* full-duplex, heartbeat disabled */
385 writel(1 << 2, &fec->eth->x_cntrl);
388 #if defined(CONFIG_MX6Q)
389 /* Enable ENET HW endian SWAP */
390 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
392 /* Enable ENET store and forward mode */
393 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
397 * Enable FEC-Lite controller
399 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
401 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
404 * setup the MII gasket for RMII mode
407 /* disable the gasket */
408 writew(0, &fec->eth->miigsk_enr);
410 /* wait for the gasket to be disabled */
411 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
414 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
415 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
417 /* re-enable the gasket */
418 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
420 /* wait until MII gasket is ready */
422 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
423 if (--max_loops <= 0) {
424 printf("WAIT for MII Gasket ready timed out\n");
430 miiphy_wait_aneg(edev);
431 miiphy_speed(edev->name, fec->phy_id);
432 miiphy_duplex(edev->name, fec->phy_id);
435 * Enable SmartDMA receive task
437 fec_rx_task_enable(fec);
443 static int fec_init(struct eth_device *dev, bd_t* bd)
446 struct fec_priv *fec = (struct fec_priv *)dev->priv;
447 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
451 /* Initialize MAC address */
455 * reserve memory for both buffer descriptor chains at once
456 * Datasheet forces the startaddress of each chain is 16 byte
459 if (fec->base_ptr == NULL)
460 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
461 sizeof(struct fec_bd) + DB_ALIGNMENT);
462 base = (uint32_t)fec->base_ptr;
464 puts("fec_mxc: not enough malloc memory\n");
467 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
468 sizeof(struct fec_bd) + DB_ALIGNMENT);
469 base += (DB_ALIGNMENT-1);
470 base &= ~(DB_ALIGNMENT-1);
472 fec->rbd_base = (struct fec_bd *)base;
474 base += FEC_RBD_NUM * sizeof(struct fec_bd);
476 fec->tbd_base = (struct fec_bd *)base;
479 * Set interrupt mask register
481 writel(0x00000000, &fec->eth->imask);
484 * Clear FEC-Lite interrupt event register(IEVENT)
486 writel(0xffffffff, &fec->eth->ievent);
490 * Set FEC-Lite receive control register(R_CNTRL):
493 /* Start with frame length = 1518, common for all modes. */
494 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
495 if (fec->xcv_type == SEVENWIRE)
496 rcntrl |= FEC_RCNTRL_FCE;
497 else if (fec->xcv_type == RGMII)
498 rcntrl |= FEC_RCNTRL_RGMII;
499 else if (fec->xcv_type == RMII)
500 rcntrl |= FEC_RCNTRL_RMII;
502 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
504 writel(rcntrl, &fec->eth->r_cntrl);
506 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
507 fec_mii_setspeed(fec);
510 * Set Opcode/Pause Duration Register
512 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
513 writel(0x2, &fec->eth->x_wmrk);
515 * Set multicast address filter
517 writel(0x00000000, &fec->eth->gaddr1);
518 writel(0x00000000, &fec->eth->gaddr2);
522 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
525 /* FIFO receive start register */
526 writel(0x520, &fec->eth->r_fstart);
528 /* size and address of each buffer */
529 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
530 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
531 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
534 * Initialize RxBD/TxBD rings
536 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
538 fec->base_ptr = NULL;
544 if (fec->xcv_type != SEVENWIRE)
545 miiphy_restart_aneg(dev);
552 * Halt the FEC engine
553 * @param[in] dev Our device to handle
555 static void fec_halt(struct eth_device *dev)
557 struct fec_priv *fec = (struct fec_priv *)dev->priv;
558 int counter = 0xffff;
561 * issue graceful stop command to the FEC transmitter if necessary
563 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
566 debug("eth_halt: wait for stop regs\n");
568 * wait for graceful stop to register
570 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
574 * Disable SmartDMA tasks
576 fec_tx_task_disable(fec);
577 fec_rx_task_disable(fec);
580 * Disable the Ethernet Controller
581 * Note: this will also reset the BD index counter!
583 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
587 debug("eth_halt: done\n");
592 * @param[in] dev Our ethernet device to handle
593 * @param[in] packet Pointer to the data to be transmitted
594 * @param[in] length Data count in bytes
595 * @return 0 on success
597 static int fec_send(struct eth_device *dev, volatile void* packet, int length)
602 * This routine transmits one frame. This routine only accepts
603 * 6-byte Ethernet addresses.
605 struct fec_priv *fec = (struct fec_priv *)dev->priv;
608 * Check for valid length of data.
610 if ((length > 1500) || (length <= 0)) {
611 printf("Payload (%d) too large\n", length);
616 * Setup the transmit buffer
617 * Note: We are always using the first buffer for transmission,
618 * the second will be empty and only used to stop the DMA engine
620 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
621 swap_packet((uint32_t *)packet, length);
623 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
624 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
626 * update BD's status now
628 * - is always the last in a chain (means no chain)
629 * - should transmitt the CRC
630 * - might be the last BD in the list, so the address counter should
631 * wrap (-> keep the WRAP flag)
633 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
634 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
635 writew(status, &fec->tbd_base[fec->tbd_index].status);
638 * Enable SmartDMA transmit task
640 fec_tx_task_enable(fec);
643 * wait until frame is sent .
645 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
648 debug("fec_send: status 0x%x index %d\n",
649 readw(&fec->tbd_base[fec->tbd_index].status),
651 /* for next transmission use the other buffer */
661 * Pull one frame from the card
662 * @param[in] dev Our ethernet device to handle
663 * @return Length of packet read
665 static int fec_recv(struct eth_device *dev)
667 struct fec_priv *fec = (struct fec_priv *)dev->priv;
668 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
669 unsigned long ievent;
670 int frame_length, len = 0;
673 uchar buff[FEC_MAX_PKT_SIZE];
676 * Check if any critical events have happened
678 ievent = readl(&fec->eth->ievent);
679 writel(ievent, &fec->eth->ievent);
680 debug("fec_recv: ievent 0x%lx\n", ievent);
681 if (ievent & FEC_IEVENT_BABR) {
683 fec_init(dev, fec->bd);
684 printf("some error: 0x%08lx\n", ievent);
687 if (ievent & FEC_IEVENT_HBERR) {
688 /* Heartbeat error */
689 writel(0x00000001 | readl(&fec->eth->x_cntrl),
692 if (ievent & FEC_IEVENT_GRA) {
693 /* Graceful stop complete */
694 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
696 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
698 fec_init(dev, fec->bd);
703 * ensure reading the right buffer status
705 bd_status = readw(&rbd->status);
706 debug("fec_recv: status 0x%x\n", bd_status);
708 if (!(bd_status & FEC_RBD_EMPTY)) {
709 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
710 ((readw(&rbd->data_length) - 4) > 14)) {
712 * Get buffer address and size
714 frame = (struct nbuf *)readl(&rbd->data_pointer);
715 frame_length = readw(&rbd->data_length) - 4;
717 * Fill the buffer and pass it to upper layers
719 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
720 swap_packet((uint32_t *)frame->data, frame_length);
722 memcpy(buff, frame->data, frame_length);
723 NetReceive(buff, frame_length);
726 if (bd_status & FEC_RBD_ERR)
727 printf("error frame: 0x%08lx 0x%08x\n",
728 (ulong)rbd->data_pointer,
732 * free the current buffer, restart the engine
733 * and move forward to the next buffer
735 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
736 fec_rx_task_enable(fec);
737 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
739 debug("fec_recv: stop\n");
744 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
746 struct eth_device *edev;
747 struct fec_priv *fec;
748 unsigned char ethaddr[6];
752 /* create and fill edev struct */
753 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
755 puts("fec_mxc: not enough malloc memory for eth_device\n");
760 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
762 puts("fec_mxc: not enough malloc memory for fec_priv\n");
767 memset(edev, 0, sizeof(*edev));
768 memset(fec, 0, sizeof(*fec));
771 edev->init = fec_init;
772 edev->send = fec_send;
773 edev->recv = fec_recv;
774 edev->halt = fec_halt;
775 edev->write_hwaddr = fec_set_hwaddr;
777 fec->eth = (struct ethernet_regs *)base_addr;
780 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
783 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
784 start = get_timer(0);
785 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
786 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
787 printf("FEC MXC: Timeout reseting chip\n");
794 * Set interrupt mask register
796 writel(0x00000000, &fec->eth->imask);
799 * Clear FEC-Lite interrupt event register(IEVENT)
801 writel(0xffffffff, &fec->eth->ievent);
804 * Set FEC-Lite receive control register(R_CNTRL):
807 * Frame length=1518; MII mode;
809 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
810 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
811 fec_mii_setspeed(fec);
814 sprintf(edev->name, "FEC");
817 sprintf(edev->name, "FEC%i", dev_id);
818 fec->dev_id = dev_id;
820 fec->phy_id = phy_id;
822 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
826 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
827 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
828 memcpy(edev->enetaddr, ethaddr, 6);
841 #ifndef CONFIG_FEC_MXC_MULTI
842 int fecmxc_initialize(bd_t *bd)
846 debug("eth_init: fec_probe(bd)\n");
847 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
853 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
857 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
858 lout = fec_probe(bd, dev_id, phy_id, addr);
863 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
865 struct fec_priv *fec = (struct fec_priv *)dev->priv;
866 fec->mii_postcall = cb;