1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
26 #include <linux/errno.h>
27 #include <linux/compiler.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/mach-imx/sys_proto.h>
32 #include <asm-generic/gpio.h>
33 #include <dm/device_compat.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 * Timeout the transfer after 5 mS. This is usually a bit more, since
43 * the code in the tightloops this timeout is used in adds some overhead.
45 #define FEC_XFER_TIMEOUT 5000
48 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
49 * 64-byte alignment in the DMA RX FEC buffer.
50 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
51 * satisfies the alignment on other SoCs (32-bytes)
53 #define FEC_DMA_RX_MINALIGN 64
56 #error "CONFIG_MII has to be defined!"
60 * The i.MX28 operates with packets in big endian. We need to swap them before
61 * sending and after receiving.
64 #define CFG_FEC_MXC_SWAP_PACKET
67 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
69 /* Check various alignment issues at compile time */
70 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
71 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
74 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
75 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
76 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
81 #ifdef CFG_FEC_MXC_SWAP_PACKET
82 static void swap_packet(uint32_t *packet, int length)
86 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
87 packet[i] = __swab32(packet[i]);
91 /* MII-interface related functions */
92 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
95 uint32_t reg; /* convenient holder for the PHY register */
96 uint32_t phy; /* convenient holder for the PHY */
101 * reading from any PHY's register is done by properly
102 * programming the FEC's MII data register.
104 writel(FEC_IEVENT_MII, ð->ievent);
105 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
106 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
108 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
109 phy | reg, ð->mii_data);
111 /* wait for the related interrupt */
112 start = get_timer(0);
113 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
114 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
115 printf("Read MDIO failed...\n");
120 /* clear mii interrupt bit */
121 writel(FEC_IEVENT_MII, ð->ievent);
123 /* it's now safe to read the PHY's register */
124 val = (unsigned short)readl(ð->mii_data);
125 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
130 #ifndef imx_get_fecclk
131 u32 __weak imx_get_fecclk(void)
137 static int fec_get_clk_rate(void *udev, int idx)
139 struct fec_priv *fec;
143 if (IS_ENABLED(CONFIG_IMX8) ||
144 CONFIG_IS_ENABLED(CLK_CCF)) {
147 ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
149 debug("Can't get FEC udev: %d\n", ret);
154 fec = dev_get_priv(dev);
156 return fec->clk_rate;
160 return imx_get_fecclk();
164 static void fec_mii_setspeed(struct ethernet_regs *eth)
167 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
168 * and do not drop the Preamble.
170 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
171 * MII_SPEED) register that defines the MDIO output hold time. Earlier
172 * versions are RAZ there, so just ignore the difference and write the
174 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
175 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
177 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
178 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
179 * holdtime cannot result in a value greater than 3.
186 ret = fec_get_clk_rate(NULL, 0);
188 printf("Can't find FEC0 clk rate: %d\n", ret);
192 speed = DIV_ROUND_UP(pclk, 5000000);
193 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
195 #ifdef FEC_QUIRK_ENET_MAC
198 writel(speed << 1 | hold << 8, ð->mii_speed);
199 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
202 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
203 uint8_t regaddr, uint16_t data)
205 uint32_t reg; /* convenient holder for the PHY register */
206 uint32_t phy; /* convenient holder for the PHY */
209 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
210 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
212 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
213 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
215 /* wait for the MII interrupt */
216 start = get_timer(0);
217 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
218 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
219 printf("Write MDIO failed...\n");
224 /* clear MII interrupt bit */
225 writel(FEC_IEVENT_MII, ð->ievent);
226 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
232 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
235 return fec_mdio_read(bus->priv, phyaddr, regaddr);
238 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
239 int regaddr, u16 data)
241 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
244 #ifndef CONFIG_PHYLIB
245 static int miiphy_restart_aneg(struct eth_device *dev)
248 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
249 struct fec_priv *fec = (struct fec_priv *)dev->priv;
250 struct ethernet_regs *eth = fec->bus->priv;
253 * Wake up from sleep if necessary
254 * Reset PHY, then delay 300ns
256 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
259 /* Set the auto-negotiation advertisement register bits */
260 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
261 LPA_100FULL | LPA_100HALF | LPA_10FULL |
262 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
263 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
264 BMCR_ANENABLE | BMCR_ANRESTART);
266 if (fec->mii_postcall)
267 ret = fec->mii_postcall(fec->phy_id);
273 static int miiphy_wait_aneg(struct eth_device *dev)
277 struct fec_priv *fec = (struct fec_priv *)dev->priv;
278 struct ethernet_regs *eth = fec->bus->priv;
280 /* Wait for AN completion */
281 start = get_timer(0);
283 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
284 printf("%s: Autonegotiation timeout\n", dev->name);
288 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
290 printf("%s: Autonegotiation failed. status: %d\n",
294 } while (!(status & BMSR_LSTATUS));
300 static int fec_rx_task_enable(struct fec_priv *fec)
302 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
306 static int fec_rx_task_disable(struct fec_priv *fec)
311 static int fec_tx_task_enable(struct fec_priv *fec)
313 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
317 static int fec_tx_task_disable(struct fec_priv *fec)
323 * Initialize receive task's buffer descriptors
324 * @param[in] fec all we know about the device yet
325 * @param[in] count receive buffer count to be allocated
326 * @param[in] dsize desired size of each receive buffer
327 * Return: 0 on success
329 * Init all RX descriptors to default values.
331 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
338 * Reload the RX descriptors with default values and wipe
341 size = roundup(dsize, ARCH_DMA_MINALIGN);
342 for (i = 0; i < count; i++) {
343 data = fec->rbd_base[i].data_pointer;
344 memset((void *)data, 0, dsize);
345 flush_dcache_range(data, data + size);
347 fec->rbd_base[i].status = FEC_RBD_EMPTY;
348 fec->rbd_base[i].data_length = 0;
351 /* Mark the last RBD to close the ring. */
352 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
355 flush_dcache_range((ulong)fec->rbd_base,
356 (ulong)fec->rbd_base + size);
360 * Initialize transmit task's buffer descriptors
361 * @param[in] fec all we know about the device yet
363 * Transmit buffers are created externally. We only have to init the BDs here.\n
364 * Note: There is a race condition in the hardware. When only one BD is in
365 * use it must be marked with the WRAP bit to use it for every transmitt.
366 * This bit in combination with the READY bit results into double transmit
367 * of each data buffer. It seems the state machine checks READY earlier then
368 * resetting it after the first transfer.
369 * Using two BDs solves this issue.
371 static void fec_tbd_init(struct fec_priv *fec)
373 ulong addr = (ulong)fec->tbd_base;
374 unsigned size = roundup(2 * sizeof(struct fec_bd),
377 memset(fec->tbd_base, 0, size);
378 fec->tbd_base[0].status = 0;
379 fec->tbd_base[1].status = FEC_TBD_WRAP;
381 flush_dcache_range(addr, addr + size);
385 * Mark the given read buffer descriptor as free
386 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
387 * @param[in] prbd buffer descriptor to mark free again
389 static void fec_rbd_clean(int last, struct fec_bd *prbd)
391 unsigned short flags = FEC_RBD_EMPTY;
393 flags |= FEC_RBD_WRAP;
394 writew(flags, &prbd->status);
395 writew(0, &prbd->data_length);
398 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
400 imx_get_mac_from_fuse(dev_id, mac);
401 return !is_valid_ethaddr(mac);
404 static int fecmxc_set_hwaddr(struct udevice *dev)
406 struct fec_priv *fec = dev_get_priv(dev);
407 struct eth_pdata *pdata = dev_get_plat(dev);
408 uchar *mac = pdata->enetaddr;
410 writel(0, &fec->eth->iaddr1);
411 writel(0, &fec->eth->iaddr2);
412 writel(0, &fec->eth->gaddr1);
413 writel(0, &fec->eth->gaddr2);
415 /* Set physical address */
416 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
418 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
423 /* Do initial configuration of the FEC registers */
424 static void fec_reg_setup(struct fec_priv *fec)
428 /* Set interrupt mask register */
429 writel(0x00000000, &fec->eth->imask);
431 /* Clear FEC-Lite interrupt event register(IEVENT) */
432 writel(0xffffffff, &fec->eth->ievent);
434 /* Set FEC-Lite receive control register(R_CNTRL): */
436 /* Start with frame length = 1518, common for all modes. */
437 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
438 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
439 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
440 if (fec->xcv_type == RGMII)
441 rcntrl |= FEC_RCNTRL_RGMII;
442 else if (fec->xcv_type == RMII)
443 rcntrl |= FEC_RCNTRL_RMII;
448 writel(rcntrl, &fec->eth->r_cntrl);
452 * Start the FEC engine
453 * @param[in] dev Our device to handle
455 static int fec_open(struct udevice *dev)
457 struct fec_priv *fec = dev_get_priv(dev);
462 debug("fec_open: fec_open(dev)\n");
463 /* full-duplex, heartbeat disabled */
464 writel(1 << 2, &fec->eth->x_cntrl);
467 /* Invalidate all descriptors */
468 for (i = 0; i < FEC_RBD_NUM - 1; i++)
469 fec_rbd_clean(0, &fec->rbd_base[i]);
470 fec_rbd_clean(1, &fec->rbd_base[i]);
472 /* Flush the descriptors into RAM */
473 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
475 addr = (ulong)fec->rbd_base;
476 flush_dcache_range(addr, addr + size);
478 #ifdef FEC_QUIRK_ENET_MAC
479 /* Enable ENET HW endian SWAP */
480 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
482 /* Enable ENET store and forward mode */
483 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
486 /* Enable FEC-Lite controller */
487 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
490 #ifdef FEC_ENET_ENABLE_TXC_DELAY
491 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
495 #ifdef FEC_ENET_ENABLE_RXC_DELAY
496 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
500 #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
503 /* setup the MII gasket for RMII mode */
504 /* disable the gasket */
505 writew(0, &fec->eth->miigsk_enr);
507 /* wait for the gasket to be disabled */
508 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
511 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
512 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
514 /* re-enable the gasket */
515 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
517 /* wait until MII gasket is ready */
519 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
520 if (--max_loops <= 0) {
521 printf("WAIT for MII Gasket ready timed out\n");
529 /* Start up the PHY */
530 int ret = phy_startup(fec->phydev);
533 printf("Could not initialize PHY %s\n",
534 fec->phydev->dev->name);
537 speed = fec->phydev->speed;
540 miiphy_wait_aneg(edev);
541 speed = miiphy_speed(edev->name, fec->phy_id);
542 miiphy_duplex(edev->name, fec->phy_id);
545 #ifdef FEC_QUIRK_ENET_MAC
547 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
548 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
549 if (speed == _1000BASET)
550 ecr |= FEC_ECNTRL_SPEED;
551 else if (speed != _100BASET)
552 rcr |= FEC_RCNTRL_RMII_10T;
553 writel(ecr, &fec->eth->ecntrl);
554 writel(rcr, &fec->eth->r_cntrl);
557 debug("%s:Speed=%i\n", __func__, speed);
559 /* Enable SmartDMA receive task */
560 fec_rx_task_enable(fec);
566 static int fecmxc_init(struct udevice *dev)
568 struct fec_priv *fec = dev_get_priv(dev);
569 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
573 /* Initialize MAC address */
574 fecmxc_set_hwaddr(dev);
576 /* Setup transmit descriptors, there are two in total. */
579 /* Setup receive descriptors. */
580 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
584 if (fec->xcv_type != SEVENWIRE)
585 fec_mii_setspeed(fec->bus->priv);
587 /* Set Opcode/Pause Duration Register */
588 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
589 writel(0x2, &fec->eth->x_wmrk);
591 /* Set multicast address filter */
592 writel(0x00000000, &fec->eth->gaddr1);
593 writel(0x00000000, &fec->eth->gaddr2);
595 /* Do not access reserved register */
596 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
599 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
602 /* FIFO receive start register */
603 writel(0x520, &fec->eth->r_fstart);
606 /* size and address of each buffer */
607 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
609 addr = (ulong)fec->tbd_base;
610 writel((uint32_t)addr, &fec->eth->etdsr);
612 addr = (ulong)fec->rbd_base;
613 writel((uint32_t)addr, &fec->eth->erdsr);
615 #ifndef CONFIG_PHYLIB
616 if (fec->xcv_type != SEVENWIRE)
617 miiphy_restart_aneg(dev);
624 * Halt the FEC engine
625 * @param[in] dev Our device to handle
627 static void fecmxc_halt(struct udevice *dev)
629 struct fec_priv *fec = dev_get_priv(dev);
630 int counter = 0xffff;
632 /* issue graceful stop command to the FEC transmitter if necessary */
633 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
636 debug("eth_halt: wait for stop regs\n");
637 /* wait for graceful stop to register */
638 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
641 /* Disable SmartDMA tasks */
642 fec_tx_task_disable(fec);
643 fec_rx_task_disable(fec);
646 * Disable the Ethernet Controller
647 * Note: this will also reset the BD index counter!
649 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
653 debug("eth_halt: done\n");
658 * @param[in] dev Our ethernet device to handle
659 * @param[in] packet Pointer to the data to be transmitted
660 * @param[in] length Data count in bytes
661 * Return: 0 on success
663 static int fecmxc_send(struct udevice *dev, void *packet, int length)
668 int timeout = FEC_XFER_TIMEOUT;
672 * This routine transmits one frame. This routine only accepts
673 * 6-byte Ethernet addresses.
675 struct fec_priv *fec = dev_get_priv(dev);
678 * Check for valid length of data.
680 if ((length > 1500) || (length <= 0)) {
681 printf("Payload (%d) too large\n", length);
686 * Setup the transmit buffer. We are always using the first buffer for
687 * transmission, the second will be empty and only used to stop the DMA
688 * engine. We also flush the packet to RAM here to avoid cache trouble.
690 #ifdef CFG_FEC_MXC_SWAP_PACKET
691 swap_packet((uint32_t *)packet, length);
694 addr = (ulong)packet;
695 end = roundup(addr + length, ARCH_DMA_MINALIGN);
696 addr &= ~(ARCH_DMA_MINALIGN - 1);
697 flush_dcache_range(addr, end);
699 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
700 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
703 * update BD's status now
705 * - is always the last in a chain (means no chain)
706 * - should transmitt the CRC
707 * - might be the last BD in the list, so the address counter should
708 * wrap (-> keep the WRAP flag)
710 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
711 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
712 writew(status, &fec->tbd_base[fec->tbd_index].status);
715 * Flush data cache. This code flushes both TX descriptors to RAM.
716 * After this code, the descriptors will be safely in RAM and we
719 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
720 addr = (ulong)fec->tbd_base;
721 flush_dcache_range(addr, addr + size);
724 * Below we read the DMA descriptor's last four bytes back from the
725 * DRAM. This is important in order to make sure that all WRITE
726 * operations on the bus that were triggered by previous cache FLUSH
729 * Otherwise, on MX28, it is possible to observe a corruption of the
730 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
731 * for the bus structure of MX28. The scenario is as follows:
733 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
734 * to DRAM due to flush_dcache_range()
735 * 2) ARM core writes the FEC registers via AHB_ARB2
736 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
738 * Note that 2) does sometimes finish before 1) due to reordering of
739 * WRITE accesses on the AHB bus, therefore triggering 3) before the
740 * DMA descriptor is fully written into DRAM. This results in occasional
741 * corruption of the DMA descriptor.
743 readl(addr + size - 4);
745 /* Enable SmartDMA transmit task */
746 fec_tx_task_enable(fec);
749 * Wait until frame is sent. On each turn of the wait cycle, we must
750 * invalidate data cache to see what's really in RAM. Also, we need
754 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
764 * The TDAR bit is cleared when the descriptors are all out from TX
765 * but on mx6solox we noticed that the READY bit is still not cleared
767 * These are two distinct signals, and in IC simulation, we found that
768 * TDAR always gets cleared prior than the READY bit of last BD becomes
770 * In mx6solox, we use a later version of FEC IP. It looks like that
771 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
774 * Fix this by polling the READY bit of BD after the TDAR polling,
775 * which covers the mx6solox case and does not harm the other SoCs.
777 timeout = FEC_XFER_TIMEOUT;
779 invalidate_dcache_range(addr, addr + size);
780 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
789 debug("fec_send: status 0x%x index %d ret %i\n",
790 readw(&fec->tbd_base[fec->tbd_index].status),
791 fec->tbd_index, ret);
792 /* for next transmission use the other buffer */
802 * Pull one frame from the card
803 * @param[in] dev Our ethernet device to handle
804 * Return: Length of packet read
806 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
808 struct fec_priv *fec = dev_get_priv(dev);
809 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
810 unsigned long ievent;
811 int frame_length, len = 0;
813 ulong addr, size, end;
816 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
818 printf("%s: error allocating packetp\n", __func__);
822 /* Check if any critical events have happened */
823 ievent = readl(&fec->eth->ievent);
824 writel(ievent, &fec->eth->ievent);
825 debug("fec_recv: ievent 0x%lx\n", ievent);
826 if (ievent & FEC_IEVENT_BABR) {
829 printf("some error: 0x%08lx\n", ievent);
832 if (ievent & FEC_IEVENT_HBERR) {
833 /* Heartbeat error */
834 writel(0x00000001 | readl(&fec->eth->x_cntrl),
837 if (ievent & FEC_IEVENT_GRA) {
838 /* Graceful stop complete */
839 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
841 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
848 * Read the buffer status. Before the status can be read, the data cache
849 * must be invalidated, because the data in RAM might have been changed
850 * by DMA. The descriptors are properly aligned to cachelines so there's
851 * no need to worry they'd overlap.
853 * WARNING: By invalidating the descriptor here, we also invalidate
854 * the descriptors surrounding this one. Therefore we can NOT change the
855 * contents of this descriptor nor the surrounding ones. The problem is
856 * that in order to mark the descriptor as processed, we need to change
857 * the descriptor. The solution is to mark the whole cache line when all
858 * descriptors in the cache line are processed.
861 addr &= ~(ARCH_DMA_MINALIGN - 1);
862 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
863 invalidate_dcache_range(addr, addr + size);
865 bd_status = readw(&rbd->status);
866 debug("fec_recv: status 0x%x\n", bd_status);
868 if (!(bd_status & FEC_RBD_EMPTY)) {
869 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
870 ((readw(&rbd->data_length) - 4) > 14)) {
871 /* Get buffer address and size */
872 addr = readl(&rbd->data_pointer);
873 frame_length = readw(&rbd->data_length) - 4;
874 /* Invalidate data cache over the buffer */
875 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
876 addr &= ~(ARCH_DMA_MINALIGN - 1);
877 invalidate_dcache_range(addr, end);
879 /* Fill the buffer and pass it to upper layers */
880 #ifdef CFG_FEC_MXC_SWAP_PACKET
881 swap_packet((uint32_t *)addr, frame_length);
884 memcpy(*packetp, (char *)addr, frame_length);
887 if (bd_status & FEC_RBD_ERR)
888 debug("error frame: 0x%08lx 0x%08x\n",
893 * Free the current buffer, restart the engine and move forward
894 * to the next buffer. Here we check if the whole cacheline of
895 * descriptors was already processed and if so, we mark it free
898 size = RXDESC_PER_CACHELINE - 1;
899 if ((fec->rbd_index & size) == size) {
900 i = fec->rbd_index - size;
901 addr = (ulong)&fec->rbd_base[i];
902 for (; i <= fec->rbd_index ; i++) {
903 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
906 flush_dcache_range(addr,
907 addr + ARCH_DMA_MINALIGN);
910 fec_rx_task_enable(fec);
911 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
913 debug("fec_recv: stop\n");
918 static void fec_set_dev_name(char *dest, int dev_id)
920 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
923 static int fec_alloc_descs(struct fec_priv *fec)
930 /* Allocate TX descriptors. */
931 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
932 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
936 /* Allocate RX descriptors. */
937 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
938 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
942 memset(fec->rbd_base, 0, size);
944 /* Allocate RX buffers. */
946 /* Maximum RX buffer size. */
947 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
948 for (i = 0; i < FEC_RBD_NUM; i++) {
949 data = memalign(FEC_DMA_RX_MINALIGN, size);
951 printf("%s: error allocating rxbuf %d\n", __func__, i);
955 memset(data, 0, size);
958 fec->rbd_base[i].data_pointer = (uint32_t)addr;
959 fec->rbd_base[i].status = FEC_RBD_EMPTY;
960 fec->rbd_base[i].data_length = 0;
961 /* Flush the buffer to memory. */
962 flush_dcache_range(addr, addr + size);
965 /* Mark the last RBD to close the ring. */
966 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
974 for (; i >= 0; i--) {
975 addr = fec->rbd_base[i].data_pointer;
985 static void fec_free_descs(struct fec_priv *fec)
990 for (i = 0; i < FEC_RBD_NUM; i++) {
991 addr = fec->rbd_base[i].data_pointer;
998 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1000 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1001 struct mii_dev *bus;
1006 printf("mdio_alloc failed\n");
1009 bus->read = fec_phy_read;
1010 bus->write = fec_phy_write;
1012 fec_set_dev_name(bus->name, dev_id);
1014 ret = mdio_register(bus);
1016 printf("mdio_register failed\n");
1020 fec_mii_setspeed(eth);
1024 #ifdef CONFIG_DM_MDIO
1025 struct dm_fec_mdio_priv {
1026 struct ethernet_regs *regs;
1029 static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
1031 struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
1033 return fec_mdio_read(priv->regs, addr, reg);
1036 static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 data)
1038 struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
1040 return fec_mdio_write(priv->regs, addr, reg, data);
1043 static const struct mdio_ops dm_fec_mdio_ops = {
1044 .read = dm_fec_mdio_read,
1045 .write = dm_fec_mdio_write,
1048 static int dm_fec_mdio_probe(struct udevice *dev)
1050 struct dm_fec_mdio_priv *priv = dev_get_priv(dev);
1052 priv->regs = (struct ethernet_regs *)ofnode_get_addr(dev_ofnode(dev->parent));
1057 U_BOOT_DRIVER(fec_mdio) = {
1060 .probe = dm_fec_mdio_probe,
1061 .ops = &dm_fec_mdio_ops,
1062 .priv_auto = sizeof(struct dm_fec_mdio_priv),
1065 static int dm_fec_bind_mdio(struct udevice *dev)
1067 struct udevice *mdiodev;
1072 /* for a UCLASS_MDIO driver we need to bind and probe manually
1073 * for an internal MDIO bus that has no dt compatible of its own
1075 ofnode_for_each_subnode(mdio, dev_ofnode(dev)) {
1076 name = ofnode_get_name(mdio);
1078 if (strcmp(name, "mdio"))
1081 ret = device_bind_driver_to_node(dev, "fec_mdio",
1082 name, mdio, &mdiodev);
1084 printf("%s bind %s failed: %d\n", __func__, name, ret);
1088 /* need to probe it as there is no compatible to do so */
1089 ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev);
1092 printf("%s probe %s failed: %d\n", __func__, name, ret);
1099 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1101 struct fec_priv *priv = dev_get_priv(dev);
1102 struct eth_pdata *pdata = dev_get_plat(dev);
1104 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1107 static int fecmxc_set_promisc(struct udevice *dev, bool enable)
1109 struct fec_priv *priv = dev_get_priv(dev);
1111 priv->promisc = enable;
1116 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1124 static const struct eth_ops fecmxc_ops = {
1125 .start = fecmxc_init,
1126 .send = fecmxc_send,
1127 .recv = fecmxc_recv,
1128 .free_pkt = fecmxc_free_pkt,
1129 .stop = fecmxc_halt,
1130 .write_hwaddr = fecmxc_set_hwaddr,
1131 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1132 .set_promisc = fecmxc_set_promisc,
1135 static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
1137 struct ofnode_phandle_args phandle_args;
1140 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1143 priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
1145 if (ofnode_valid(priv->phy_of_node))
1147 debug("Failed to find phy-handle (err = %d)\n", ret);
1151 if (!ofnode_is_enabled(phandle_args.node))
1154 priv->phy_of_node = phandle_args.node;
1155 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1160 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1162 struct phy_device *phydev = NULL;
1165 addr = device_get_phy_addr(priv, dev);
1166 #ifdef CFG_FEC_MXC_PHYADDR
1167 addr = CFG_FEC_MXC_PHYADDR;
1170 if (IS_ENABLED(CONFIG_DM_MDIO))
1171 phydev = dm_eth_phy_connect(dev);
1173 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1177 priv->phydev = phydev;
1178 priv->phydev->node = priv->phy_of_node;
1184 #if CONFIG_IS_ENABLED(DM_GPIO)
1185 /* FEC GPIO reset */
1186 static void fec_gpio_reset(struct fec_priv *priv)
1188 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1189 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1190 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1191 mdelay(priv->reset_delay);
1192 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1193 if (priv->reset_post_delay)
1194 mdelay(priv->reset_post_delay);
1199 static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
1204 if (!CONFIG_IS_ENABLED(CLK_CCF))
1207 if (interface == PHY_INTERFACE_MODE_MII)
1209 else if (interface == PHY_INTERFACE_MODE_RMII)
1211 else if (interface == PHY_INTERFACE_MODE_RGMII ||
1212 interface == PHY_INTERFACE_MODE_RGMII_ID ||
1213 interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1214 interface == PHY_INTERFACE_MODE_RGMII_TXID)
1219 ret = clk_set_rate(clk_ref, freq);
1226 static int fecmxc_probe(struct udevice *dev)
1228 bool dm_mii_bus = true;
1229 struct eth_pdata *pdata = dev_get_plat(dev);
1230 struct fec_priv *priv = dev_get_priv(dev);
1231 struct mii_dev *bus = NULL;
1235 ret = board_interface_eth_init(dev, pdata->phy_interface);
1239 if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) {
1240 if (enet_fused((ulong)priv->eth)) {
1241 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1246 if (IS_ENABLED(CONFIG_IMX8)) {
1247 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1249 debug("Can't get FEC ipg clk: %d\n", ret);
1252 ret = clk_enable(&priv->ipg_clk);
1254 debug("Can't enable FEC ipg clk: %d\n", ret);
1258 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1259 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1260 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1262 debug("Can't get FEC ipg clk: %d\n", ret);
1265 ret = clk_enable(&priv->ipg_clk);
1269 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1271 debug("Can't get FEC ahb clk: %d\n", ret);
1274 ret = clk_enable(&priv->ahb_clk);
1278 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1280 ret = clk_enable(&priv->clk_enet_out);
1285 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1287 ret = fecmxc_set_ref_clk(&priv->clk_ref,
1288 pdata->phy_interface);
1292 ret = clk_enable(&priv->clk_ref);
1297 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1299 ret = clk_enable(&priv->clk_ptp);
1304 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1307 ret = fec_alloc_descs(priv);
1311 #ifdef CONFIG_DM_REGULATOR
1312 if (priv->phy_supply) {
1313 ret = regulator_set_enable(priv->phy_supply, true);
1315 printf("%s: Error enabling phy supply\n", dev->name);
1321 #if CONFIG_IS_ENABLED(DM_GPIO)
1322 fec_gpio_reset(priv);
1325 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1326 &priv->eth->ecntrl);
1327 start = get_timer(0);
1328 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1329 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1330 printf("FEC MXC: Timeout resetting chip\n");
1336 fec_reg_setup(priv);
1338 priv->dev_id = dev_seq(dev);
1340 #ifdef CONFIG_DM_MDIO
1341 ret = dm_fec_bind_mdio(dev);
1342 if (ret && ret != -ENODEV)
1346 #ifdef CONFIG_DM_ETH_PHY
1347 bus = eth_phy_get_mdio_bus(dev);
1352 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1353 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
1356 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
1364 #ifdef CONFIG_DM_ETH_PHY
1365 eth_phy_set_mdio_bus(dev, bus);
1369 priv->interface = pdata->phy_interface;
1370 switch (priv->interface) {
1371 case PHY_INTERFACE_MODE_MII:
1372 priv->xcv_type = MII100;
1374 case PHY_INTERFACE_MODE_RMII:
1375 priv->xcv_type = RMII;
1377 case PHY_INTERFACE_MODE_RGMII:
1378 case PHY_INTERFACE_MODE_RGMII_ID:
1379 case PHY_INTERFACE_MODE_RGMII_RXID:
1380 case PHY_INTERFACE_MODE_RGMII_TXID:
1381 priv->xcv_type = RGMII;
1384 priv->xcv_type = MII100;
1385 printf("Unsupported interface type %d defaulting to MII100\n",
1390 ret = fec_phy_init(priv, dev);
1398 mdio_unregister(bus);
1403 fec_free_descs(priv);
1407 static int fecmxc_remove(struct udevice *dev)
1409 struct fec_priv *priv = dev_get_priv(dev);
1412 fec_free_descs(priv);
1413 mdio_unregister(priv->bus);
1414 mdio_free(priv->bus);
1416 #ifdef CONFIG_DM_REGULATOR
1417 if (priv->phy_supply)
1418 regulator_set_enable(priv->phy_supply, false);
1424 static int fecmxc_of_to_plat(struct udevice *dev)
1427 struct eth_pdata *pdata = dev_get_plat(dev);
1428 struct fec_priv *priv = dev_get_priv(dev);
1430 pdata->iobase = dev_read_addr(dev);
1431 priv->eth = (struct ethernet_regs *)pdata->iobase;
1433 pdata->phy_interface = dev_read_phy_mode(dev);
1434 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1437 #ifdef CONFIG_DM_REGULATOR
1438 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1441 #if CONFIG_IS_ENABLED(DM_GPIO)
1442 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1443 &priv->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1445 return 0; /* property is optional, don't return error! */
1447 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1448 if (priv->reset_delay > 1000) {
1449 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1450 /* property value wrong, use default value */
1451 priv->reset_delay = 1;
1454 priv->reset_post_delay = dev_read_u32_default(dev,
1455 "phy-reset-post-delay",
1457 if (priv->reset_post_delay > 1000) {
1458 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1459 /* property value wrong, use default value */
1460 priv->reset_post_delay = 0;
1467 static const struct udevice_id fecmxc_ids[] = {
1468 { .compatible = "fsl,imx28-fec" },
1469 { .compatible = "fsl,imx6q-fec" },
1470 { .compatible = "fsl,imx6sl-fec" },
1471 { .compatible = "fsl,imx6sx-fec" },
1472 { .compatible = "fsl,imx6ul-fec" },
1473 { .compatible = "fsl,imx53-fec" },
1474 { .compatible = "fsl,imx7d-fec" },
1475 { .compatible = "fsl,mvf600-fec" },
1476 { .compatible = "fsl,imx93-fec" },
1480 U_BOOT_DRIVER(fecmxc_gem) = {
1483 .of_match = fecmxc_ids,
1484 .of_to_plat = fecmxc_of_to_plat,
1485 .probe = fecmxc_probe,
1486 .remove = fecmxc_remove,
1488 .priv_auto = sizeof(struct fec_priv),
1489 .plat_auto = sizeof(struct eth_pdata),