1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
20 #include <asm/cache.h>
21 #include <linux/delay.h>
22 #include <power/regulator.h>
25 #include <linux/errno.h>
26 #include <linux/compiler.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/imx-regs.h>
30 #include <asm/mach-imx/sys_proto.h>
31 #include <asm-generic/gpio.h>
36 DECLARE_GLOBAL_DATA_PTR;
39 * Timeout the transfer after 5 mS. This is usually a bit more, since
40 * the code in the tightloops this timeout is used in adds some overhead.
42 #define FEC_XFER_TIMEOUT 5000
45 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
46 * 64-byte alignment in the DMA RX FEC buffer.
47 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
48 * satisfies the alignment on other SoCs (32-bytes)
50 #define FEC_DMA_RX_MINALIGN 64
53 #error "CONFIG_MII has to be defined!"
56 #ifndef CONFIG_FEC_XCV_TYPE
57 #define CONFIG_FEC_XCV_TYPE MII100
61 * The i.MX28 operates with packets in big endian. We need to swap them before
62 * sending and after receiving.
65 #define CONFIG_FEC_MXC_SWAP_PACKET
68 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
70 /* Check various alignment issues at compile time */
71 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
72 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
75 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
76 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
77 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
82 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
83 static void swap_packet(uint32_t *packet, int length)
87 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
88 packet[i] = __swab32(packet[i]);
92 /* MII-interface related functions */
93 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
96 uint32_t reg; /* convenient holder for the PHY register */
97 uint32_t phy; /* convenient holder for the PHY */
102 * reading from any PHY's register is done by properly
103 * programming the FEC's MII data register.
105 writel(FEC_IEVENT_MII, ð->ievent);
106 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
107 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
109 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
110 phy | reg, ð->mii_data);
112 /* wait for the related interrupt */
113 start = get_timer(0);
114 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
115 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
116 printf("Read MDIO failed...\n");
121 /* clear mii interrupt bit */
122 writel(FEC_IEVENT_MII, ð->ievent);
124 /* it's now safe to read the PHY's register */
125 val = (unsigned short)readl(ð->mii_data);
126 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
131 #ifndef imx_get_fecclk
132 u32 __weak imx_get_fecclk(void)
138 static int fec_get_clk_rate(void *udev, int idx)
140 struct fec_priv *fec;
144 if (IS_ENABLED(CONFIG_IMX8) ||
145 CONFIG_IS_ENABLED(CLK_CCF)) {
148 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
150 debug("Can't get FEC udev: %d\n", ret);
155 fec = dev_get_priv(dev);
157 return fec->clk_rate;
161 return imx_get_fecclk();
165 static void fec_mii_setspeed(struct ethernet_regs *eth)
168 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
169 * and do not drop the Preamble.
171 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
172 * MII_SPEED) register that defines the MDIO output hold time. Earlier
173 * versions are RAZ there, so just ignore the difference and write the
175 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
176 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
178 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
179 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
180 * holdtime cannot result in a value greater than 3.
187 ret = fec_get_clk_rate(NULL, 0);
189 printf("Can't find FEC0 clk rate: %d\n", ret);
193 speed = DIV_ROUND_UP(pclk, 5000000);
194 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
196 #ifdef FEC_QUIRK_ENET_MAC
199 writel(speed << 1 | hold << 8, ð->mii_speed);
200 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
203 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
204 uint8_t regaddr, uint16_t data)
206 uint32_t reg; /* convenient holder for the PHY register */
207 uint32_t phy; /* convenient holder for the PHY */
210 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
211 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
213 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
214 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
216 /* wait for the MII interrupt */
217 start = get_timer(0);
218 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
219 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
220 printf("Write MDIO failed...\n");
225 /* clear MII interrupt bit */
226 writel(FEC_IEVENT_MII, ð->ievent);
227 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
233 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
236 return fec_mdio_read(bus->priv, phyaddr, regaddr);
239 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
240 int regaddr, u16 data)
242 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
245 #ifndef CONFIG_PHYLIB
246 static int miiphy_restart_aneg(struct eth_device *dev)
249 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
250 struct fec_priv *fec = (struct fec_priv *)dev->priv;
251 struct ethernet_regs *eth = fec->bus->priv;
254 * Wake up from sleep if necessary
255 * Reset PHY, then delay 300ns
258 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
260 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
263 /* Set the auto-negotiation advertisement register bits */
264 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
265 LPA_100FULL | LPA_100HALF | LPA_10FULL |
266 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
267 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
268 BMCR_ANENABLE | BMCR_ANRESTART);
270 if (fec->mii_postcall)
271 ret = fec->mii_postcall(fec->phy_id);
277 #ifndef CONFIG_FEC_FIXED_SPEED
278 static int miiphy_wait_aneg(struct eth_device *dev)
282 struct fec_priv *fec = (struct fec_priv *)dev->priv;
283 struct ethernet_regs *eth = fec->bus->priv;
285 /* Wait for AN completion */
286 start = get_timer(0);
288 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
289 printf("%s: Autonegotiation timeout\n", dev->name);
293 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
295 printf("%s: Autonegotiation failed. status: %d\n",
299 } while (!(status & BMSR_LSTATUS));
303 #endif /* CONFIG_FEC_FIXED_SPEED */
306 static int fec_rx_task_enable(struct fec_priv *fec)
308 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
312 static int fec_rx_task_disable(struct fec_priv *fec)
317 static int fec_tx_task_enable(struct fec_priv *fec)
319 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
323 static int fec_tx_task_disable(struct fec_priv *fec)
329 * Initialize receive task's buffer descriptors
330 * @param[in] fec all we know about the device yet
331 * @param[in] count receive buffer count to be allocated
332 * @param[in] dsize desired size of each receive buffer
333 * @return 0 on success
335 * Init all RX descriptors to default values.
337 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
344 * Reload the RX descriptors with default values and wipe
347 size = roundup(dsize, ARCH_DMA_MINALIGN);
348 for (i = 0; i < count; i++) {
349 data = fec->rbd_base[i].data_pointer;
350 memset((void *)data, 0, dsize);
351 flush_dcache_range(data, data + size);
353 fec->rbd_base[i].status = FEC_RBD_EMPTY;
354 fec->rbd_base[i].data_length = 0;
357 /* Mark the last RBD to close the ring. */
358 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
361 flush_dcache_range((ulong)fec->rbd_base,
362 (ulong)fec->rbd_base + size);
366 * Initialize transmit task's buffer descriptors
367 * @param[in] fec all we know about the device yet
369 * Transmit buffers are created externally. We only have to init the BDs here.\n
370 * Note: There is a race condition in the hardware. When only one BD is in
371 * use it must be marked with the WRAP bit to use it for every transmitt.
372 * This bit in combination with the READY bit results into double transmit
373 * of each data buffer. It seems the state machine checks READY earlier then
374 * resetting it after the first transfer.
375 * Using two BDs solves this issue.
377 static void fec_tbd_init(struct fec_priv *fec)
379 ulong addr = (ulong)fec->tbd_base;
380 unsigned size = roundup(2 * sizeof(struct fec_bd),
383 memset(fec->tbd_base, 0, size);
384 fec->tbd_base[0].status = 0;
385 fec->tbd_base[1].status = FEC_TBD_WRAP;
387 flush_dcache_range(addr, addr + size);
391 * Mark the given read buffer descriptor as free
392 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
393 * @param[in] prbd buffer descriptor to mark free again
395 static void fec_rbd_clean(int last, struct fec_bd *prbd)
397 unsigned short flags = FEC_RBD_EMPTY;
399 flags |= FEC_RBD_WRAP;
400 writew(flags, &prbd->status);
401 writew(0, &prbd->data_length);
404 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
406 imx_get_mac_from_fuse(dev_id, mac);
407 return !is_valid_ethaddr(mac);
411 static int fecmxc_set_hwaddr(struct udevice *dev)
413 static int fec_set_hwaddr(struct eth_device *dev)
417 struct fec_priv *fec = dev_get_priv(dev);
418 struct eth_pdata *pdata = dev_get_plat(dev);
419 uchar *mac = pdata->enetaddr;
421 uchar *mac = dev->enetaddr;
422 struct fec_priv *fec = (struct fec_priv *)dev->priv;
425 writel(0, &fec->eth->iaddr1);
426 writel(0, &fec->eth->iaddr2);
427 writel(0, &fec->eth->gaddr1);
428 writel(0, &fec->eth->gaddr2);
430 /* Set physical address */
431 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
433 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
438 /* Do initial configuration of the FEC registers */
439 static void fec_reg_setup(struct fec_priv *fec)
443 /* Set interrupt mask register */
444 writel(0x00000000, &fec->eth->imask);
446 /* Clear FEC-Lite interrupt event register(IEVENT) */
447 writel(0xffffffff, &fec->eth->ievent);
449 /* Set FEC-Lite receive control register(R_CNTRL): */
451 /* Start with frame length = 1518, common for all modes. */
452 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
453 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
454 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
455 if (fec->xcv_type == RGMII)
456 rcntrl |= FEC_RCNTRL_RGMII;
457 else if (fec->xcv_type == RMII)
458 rcntrl |= FEC_RCNTRL_RMII;
460 writel(rcntrl, &fec->eth->r_cntrl);
464 * Start the FEC engine
465 * @param[in] dev Our device to handle
468 static int fec_open(struct udevice *dev)
470 static int fec_open(struct eth_device *edev)
474 struct fec_priv *fec = dev_get_priv(dev);
476 struct fec_priv *fec = (struct fec_priv *)edev->priv;
482 debug("fec_open: fec_open(dev)\n");
483 /* full-duplex, heartbeat disabled */
484 writel(1 << 2, &fec->eth->x_cntrl);
487 /* Invalidate all descriptors */
488 for (i = 0; i < FEC_RBD_NUM - 1; i++)
489 fec_rbd_clean(0, &fec->rbd_base[i]);
490 fec_rbd_clean(1, &fec->rbd_base[i]);
492 /* Flush the descriptors into RAM */
493 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
495 addr = (ulong)fec->rbd_base;
496 flush_dcache_range(addr, addr + size);
498 #ifdef FEC_QUIRK_ENET_MAC
499 /* Enable ENET HW endian SWAP */
500 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
502 /* Enable ENET store and forward mode */
503 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
506 /* Enable FEC-Lite controller */
507 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
510 #ifdef FEC_ENET_ENABLE_TXC_DELAY
511 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
515 #ifdef FEC_ENET_ENABLE_RXC_DELAY
516 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
520 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
523 /* setup the MII gasket for RMII mode */
524 /* disable the gasket */
525 writew(0, &fec->eth->miigsk_enr);
527 /* wait for the gasket to be disabled */
528 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
531 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
532 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
534 /* re-enable the gasket */
535 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
537 /* wait until MII gasket is ready */
539 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
540 if (--max_loops <= 0) {
541 printf("WAIT for MII Gasket ready timed out\n");
549 /* Start up the PHY */
550 int ret = phy_startup(fec->phydev);
553 printf("Could not initialize PHY %s\n",
554 fec->phydev->dev->name);
557 speed = fec->phydev->speed;
559 #elif CONFIG_FEC_FIXED_SPEED
560 speed = CONFIG_FEC_FIXED_SPEED;
562 miiphy_wait_aneg(edev);
563 speed = miiphy_speed(edev->name, fec->phy_id);
564 miiphy_duplex(edev->name, fec->phy_id);
567 #ifdef FEC_QUIRK_ENET_MAC
569 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
570 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
571 if (speed == _1000BASET)
572 ecr |= FEC_ECNTRL_SPEED;
573 else if (speed != _100BASET)
574 rcr |= FEC_RCNTRL_RMII_10T;
575 writel(ecr, &fec->eth->ecntrl);
576 writel(rcr, &fec->eth->r_cntrl);
579 debug("%s:Speed=%i\n", __func__, speed);
581 /* Enable SmartDMA receive task */
582 fec_rx_task_enable(fec);
589 static int fecmxc_init(struct udevice *dev)
591 static int fec_init(struct eth_device *dev, struct bd_info *bd)
595 struct fec_priv *fec = dev_get_priv(dev);
597 struct fec_priv *fec = (struct fec_priv *)dev->priv;
599 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
603 /* Initialize MAC address */
605 fecmxc_set_hwaddr(dev);
610 /* Setup transmit descriptors, there are two in total. */
613 /* Setup receive descriptors. */
614 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
618 if (fec->xcv_type != SEVENWIRE)
619 fec_mii_setspeed(fec->bus->priv);
621 /* Set Opcode/Pause Duration Register */
622 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
623 writel(0x2, &fec->eth->x_wmrk);
625 /* Set multicast address filter */
626 writel(0x00000000, &fec->eth->gaddr1);
627 writel(0x00000000, &fec->eth->gaddr2);
629 /* Do not access reserved register */
630 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
632 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
635 /* FIFO receive start register */
636 writel(0x520, &fec->eth->r_fstart);
639 /* size and address of each buffer */
640 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
642 addr = (ulong)fec->tbd_base;
643 writel((uint32_t)addr, &fec->eth->etdsr);
645 addr = (ulong)fec->rbd_base;
646 writel((uint32_t)addr, &fec->eth->erdsr);
648 #ifndef CONFIG_PHYLIB
649 if (fec->xcv_type != SEVENWIRE)
650 miiphy_restart_aneg(dev);
657 * Halt the FEC engine
658 * @param[in] dev Our device to handle
661 static void fecmxc_halt(struct udevice *dev)
663 static void fec_halt(struct eth_device *dev)
667 struct fec_priv *fec = dev_get_priv(dev);
669 struct fec_priv *fec = (struct fec_priv *)dev->priv;
671 int counter = 0xffff;
673 /* issue graceful stop command to the FEC transmitter if necessary */
674 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
677 debug("eth_halt: wait for stop regs\n");
678 /* wait for graceful stop to register */
679 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
682 /* Disable SmartDMA tasks */
683 fec_tx_task_disable(fec);
684 fec_rx_task_disable(fec);
687 * Disable the Ethernet Controller
688 * Note: this will also reset the BD index counter!
690 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
694 debug("eth_halt: done\n");
699 * @param[in] dev Our ethernet device to handle
700 * @param[in] packet Pointer to the data to be transmitted
701 * @param[in] length Data count in bytes
702 * @return 0 on success
705 static int fecmxc_send(struct udevice *dev, void *packet, int length)
707 static int fec_send(struct eth_device *dev, void *packet, int length)
713 int timeout = FEC_XFER_TIMEOUT;
717 * This routine transmits one frame. This routine only accepts
718 * 6-byte Ethernet addresses.
721 struct fec_priv *fec = dev_get_priv(dev);
723 struct fec_priv *fec = (struct fec_priv *)dev->priv;
727 * Check for valid length of data.
729 if ((length > 1500) || (length <= 0)) {
730 printf("Payload (%d) too large\n", length);
735 * Setup the transmit buffer. We are always using the first buffer for
736 * transmission, the second will be empty and only used to stop the DMA
737 * engine. We also flush the packet to RAM here to avoid cache trouble.
739 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
740 swap_packet((uint32_t *)packet, length);
743 addr = (ulong)packet;
744 end = roundup(addr + length, ARCH_DMA_MINALIGN);
745 addr &= ~(ARCH_DMA_MINALIGN - 1);
746 flush_dcache_range(addr, end);
748 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
749 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
752 * update BD's status now
754 * - is always the last in a chain (means no chain)
755 * - should transmitt the CRC
756 * - might be the last BD in the list, so the address counter should
757 * wrap (-> keep the WRAP flag)
759 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
760 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
761 writew(status, &fec->tbd_base[fec->tbd_index].status);
764 * Flush data cache. This code flushes both TX descriptors to RAM.
765 * After this code, the descriptors will be safely in RAM and we
768 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
769 addr = (ulong)fec->tbd_base;
770 flush_dcache_range(addr, addr + size);
773 * Below we read the DMA descriptor's last four bytes back from the
774 * DRAM. This is important in order to make sure that all WRITE
775 * operations on the bus that were triggered by previous cache FLUSH
778 * Otherwise, on MX28, it is possible to observe a corruption of the
779 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
780 * for the bus structure of MX28. The scenario is as follows:
782 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
783 * to DRAM due to flush_dcache_range()
784 * 2) ARM core writes the FEC registers via AHB_ARB2
785 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
787 * Note that 2) does sometimes finish before 1) due to reordering of
788 * WRITE accesses on the AHB bus, therefore triggering 3) before the
789 * DMA descriptor is fully written into DRAM. This results in occasional
790 * corruption of the DMA descriptor.
792 readl(addr + size - 4);
794 /* Enable SmartDMA transmit task */
795 fec_tx_task_enable(fec);
798 * Wait until frame is sent. On each turn of the wait cycle, we must
799 * invalidate data cache to see what's really in RAM. Also, we need
803 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
813 * The TDAR bit is cleared when the descriptors are all out from TX
814 * but on mx6solox we noticed that the READY bit is still not cleared
816 * These are two distinct signals, and in IC simulation, we found that
817 * TDAR always gets cleared prior than the READY bit of last BD becomes
819 * In mx6solox, we use a later version of FEC IP. It looks like that
820 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
823 * Fix this by polling the READY bit of BD after the TDAR polling,
824 * which covers the mx6solox case and does not harm the other SoCs.
826 timeout = FEC_XFER_TIMEOUT;
828 invalidate_dcache_range(addr, addr + size);
829 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
838 debug("fec_send: status 0x%x index %d ret %i\n",
839 readw(&fec->tbd_base[fec->tbd_index].status),
840 fec->tbd_index, ret);
841 /* for next transmission use the other buffer */
851 * Pull one frame from the card
852 * @param[in] dev Our ethernet device to handle
853 * @return Length of packet read
856 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
858 static int fec_recv(struct eth_device *dev)
862 struct fec_priv *fec = dev_get_priv(dev);
864 struct fec_priv *fec = (struct fec_priv *)dev->priv;
866 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
867 unsigned long ievent;
868 int frame_length, len = 0;
870 ulong addr, size, end;
874 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
876 printf("%s: error allocating packetp\n", __func__);
880 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
883 /* Check if any critical events have happened */
884 ievent = readl(&fec->eth->ievent);
885 writel(ievent, &fec->eth->ievent);
886 debug("fec_recv: ievent 0x%lx\n", ievent);
887 if (ievent & FEC_IEVENT_BABR) {
893 fec_init(dev, fec->bd);
895 printf("some error: 0x%08lx\n", ievent);
898 if (ievent & FEC_IEVENT_HBERR) {
899 /* Heartbeat error */
900 writel(0x00000001 | readl(&fec->eth->x_cntrl),
903 if (ievent & FEC_IEVENT_GRA) {
904 /* Graceful stop complete */
905 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
911 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
916 fec_init(dev, fec->bd);
922 * Read the buffer status. Before the status can be read, the data cache
923 * must be invalidated, because the data in RAM might have been changed
924 * by DMA. The descriptors are properly aligned to cachelines so there's
925 * no need to worry they'd overlap.
927 * WARNING: By invalidating the descriptor here, we also invalidate
928 * the descriptors surrounding this one. Therefore we can NOT change the
929 * contents of this descriptor nor the surrounding ones. The problem is
930 * that in order to mark the descriptor as processed, we need to change
931 * the descriptor. The solution is to mark the whole cache line when all
932 * descriptors in the cache line are processed.
935 addr &= ~(ARCH_DMA_MINALIGN - 1);
936 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
937 invalidate_dcache_range(addr, addr + size);
939 bd_status = readw(&rbd->status);
940 debug("fec_recv: status 0x%x\n", bd_status);
942 if (!(bd_status & FEC_RBD_EMPTY)) {
943 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
944 ((readw(&rbd->data_length) - 4) > 14)) {
945 /* Get buffer address and size */
946 addr = readl(&rbd->data_pointer);
947 frame_length = readw(&rbd->data_length) - 4;
948 /* Invalidate data cache over the buffer */
949 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
950 addr &= ~(ARCH_DMA_MINALIGN - 1);
951 invalidate_dcache_range(addr, end);
953 /* Fill the buffer and pass it to upper layers */
954 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
955 swap_packet((uint32_t *)addr, frame_length);
959 memcpy(*packetp, (char *)addr, frame_length);
961 memcpy(buff, (char *)addr, frame_length);
962 net_process_received_packet(buff, frame_length);
966 if (bd_status & FEC_RBD_ERR)
967 debug("error frame: 0x%08lx 0x%08x\n",
972 * Free the current buffer, restart the engine and move forward
973 * to the next buffer. Here we check if the whole cacheline of
974 * descriptors was already processed and if so, we mark it free
977 size = RXDESC_PER_CACHELINE - 1;
978 if ((fec->rbd_index & size) == size) {
979 i = fec->rbd_index - size;
980 addr = (ulong)&fec->rbd_base[i];
981 for (; i <= fec->rbd_index ; i++) {
982 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
985 flush_dcache_range(addr,
986 addr + ARCH_DMA_MINALIGN);
989 fec_rx_task_enable(fec);
990 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
992 debug("fec_recv: stop\n");
997 static void fec_set_dev_name(char *dest, int dev_id)
999 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1002 static int fec_alloc_descs(struct fec_priv *fec)
1009 /* Allocate TX descriptors. */
1010 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1011 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1015 /* Allocate RX descriptors. */
1016 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1017 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1021 memset(fec->rbd_base, 0, size);
1023 /* Allocate RX buffers. */
1025 /* Maximum RX buffer size. */
1026 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1027 for (i = 0; i < FEC_RBD_NUM; i++) {
1028 data = memalign(FEC_DMA_RX_MINALIGN, size);
1030 printf("%s: error allocating rxbuf %d\n", __func__, i);
1034 memset(data, 0, size);
1037 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1038 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1039 fec->rbd_base[i].data_length = 0;
1040 /* Flush the buffer to memory. */
1041 flush_dcache_range(addr, addr + size);
1044 /* Mark the last RBD to close the ring. */
1045 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1053 for (; i >= 0; i--) {
1054 addr = fec->rbd_base[i].data_pointer;
1057 free(fec->rbd_base);
1059 free(fec->tbd_base);
1064 static void fec_free_descs(struct fec_priv *fec)
1069 for (i = 0; i < FEC_RBD_NUM; i++) {
1070 addr = fec->rbd_base[i].data_pointer;
1073 free(fec->rbd_base);
1074 free(fec->tbd_base);
1077 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1079 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1080 struct mii_dev *bus;
1085 printf("mdio_alloc failed\n");
1088 bus->read = fec_phy_read;
1089 bus->write = fec_phy_write;
1091 fec_set_dev_name(bus->name, dev_id);
1093 ret = mdio_register(bus);
1095 printf("mdio_register failed\n");
1099 fec_mii_setspeed(eth);
1103 #ifndef CONFIG_DM_ETH
1104 #ifdef CONFIG_PHYLIB
1105 int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1106 struct mii_dev *bus, struct phy_device *phydev)
1108 static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1109 struct mii_dev *bus, int phy_id)
1112 struct eth_device *edev;
1113 struct fec_priv *fec;
1114 unsigned char ethaddr[6];
1119 /* create and fill edev struct */
1120 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1122 puts("fec_mxc: not enough malloc memory for eth_device\n");
1127 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1129 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1134 memset(edev, 0, sizeof(*edev));
1135 memset(fec, 0, sizeof(*fec));
1137 ret = fec_alloc_descs(fec);
1142 edev->init = fec_init;
1143 edev->send = fec_send;
1144 edev->recv = fec_recv;
1145 edev->halt = fec_halt;
1146 edev->write_hwaddr = fec_set_hwaddr;
1148 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1151 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1154 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1155 start = get_timer(0);
1156 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1157 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1158 printf("FEC MXC: Timeout resetting chip\n");
1165 fec_set_dev_name(edev->name, dev_id);
1166 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1168 fec_mii_setspeed(bus->priv);
1169 #ifdef CONFIG_PHYLIB
1170 fec->phydev = phydev;
1171 phy_connect_dev(phydev, edev);
1175 fec->phy_id = phy_id;
1178 /* only support one eth device, the index number pointed by dev_id */
1179 edev->index = fec->dev_id;
1181 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1182 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1183 memcpy(edev->enetaddr, ethaddr, 6);
1185 sprintf(mac, "eth%daddr", fec->dev_id);
1187 strcpy(mac, "ethaddr");
1189 eth_env_set_enetaddr(mac, ethaddr);
1193 fec_free_descs(fec);
1202 int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
1206 struct mii_dev *bus = NULL;
1207 #ifdef CONFIG_PHYLIB
1208 struct phy_device *phydev = NULL;
1212 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1213 if (enet_fused((ulong)addr)) {
1214 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1219 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1221 * The i.MX28 has two ethernet interfaces, but they are not equal.
1222 * Only the first one can access the MDIO bus.
1224 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1228 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1229 bus = fec_get_miibus(base_mii, dev_id);
1232 #ifdef CONFIG_PHYLIB
1233 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1235 mdio_unregister(bus);
1239 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1241 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1244 #ifdef CONFIG_PHYLIB
1247 mdio_unregister(bus);
1253 #ifdef CONFIG_FEC_MXC_PHYADDR
1254 int fecmxc_initialize(struct bd_info *bd)
1256 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1261 #ifndef CONFIG_PHYLIB
1262 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1264 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1265 fec->mii_postcall = cb;
1272 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1274 struct fec_priv *priv = dev_get_priv(dev);
1275 struct eth_pdata *pdata = dev_get_plat(dev);
1277 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1280 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1288 static const struct eth_ops fecmxc_ops = {
1289 .start = fecmxc_init,
1290 .send = fecmxc_send,
1291 .recv = fecmxc_recv,
1292 .free_pkt = fecmxc_free_pkt,
1293 .stop = fecmxc_halt,
1294 .write_hwaddr = fecmxc_set_hwaddr,
1295 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1298 static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
1300 struct ofnode_phandle_args phandle_args;
1303 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1305 debug("Failed to find phy-handle");
1309 priv->phy_of_node = phandle_args.node;
1311 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1316 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1318 struct phy_device *phydev;
1321 addr = device_get_phy_addr(priv, dev);
1322 #ifdef CONFIG_FEC_MXC_PHYADDR
1323 addr = CONFIG_FEC_MXC_PHYADDR;
1326 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1330 priv->phydev = phydev;
1331 priv->phydev->node = priv->phy_of_node;
1337 #if CONFIG_IS_ENABLED(DM_GPIO)
1338 /* FEC GPIO reset */
1339 static void fec_gpio_reset(struct fec_priv *priv)
1341 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1342 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1343 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1344 mdelay(priv->reset_delay);
1345 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1346 if (priv->reset_post_delay)
1347 mdelay(priv->reset_post_delay);
1352 static int fecmxc_probe(struct udevice *dev)
1354 struct eth_pdata *pdata = dev_get_plat(dev);
1355 struct fec_priv *priv = dev_get_priv(dev);
1356 struct mii_dev *bus = NULL;
1360 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1361 if (enet_fused((ulong)priv->eth)) {
1362 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1367 if (IS_ENABLED(CONFIG_IMX8)) {
1368 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1370 debug("Can't get FEC ipg clk: %d\n", ret);
1373 ret = clk_enable(&priv->ipg_clk);
1375 debug("Can't enable FEC ipg clk: %d\n", ret);
1379 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1380 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1381 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1383 debug("Can't get FEC ipg clk: %d\n", ret);
1386 ret = clk_enable(&priv->ipg_clk);
1390 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1392 debug("Can't get FEC ahb clk: %d\n", ret);
1395 ret = clk_enable(&priv->ahb_clk);
1399 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1401 ret = clk_enable(&priv->clk_enet_out);
1406 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1408 ret = clk_enable(&priv->clk_ref);
1413 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1415 ret = clk_enable(&priv->clk_ptp);
1420 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1423 ret = fec_alloc_descs(priv);
1427 #ifdef CONFIG_DM_REGULATOR
1428 if (priv->phy_supply) {
1429 ret = regulator_set_enable(priv->phy_supply, true);
1431 printf("%s: Error enabling phy supply\n", dev->name);
1437 #if CONFIG_IS_ENABLED(DM_GPIO)
1438 fec_gpio_reset(priv);
1441 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1442 &priv->eth->ecntrl);
1443 start = get_timer(0);
1444 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1445 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1446 printf("FEC MXC: Timeout reseting chip\n");
1452 fec_reg_setup(priv);
1454 priv->dev_id = dev->seq;
1456 #ifdef CONFIG_DM_ETH_PHY
1457 bus = eth_phy_get_mdio_bus(dev);
1461 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1462 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1464 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1472 #ifdef CONFIG_DM_ETH_PHY
1473 eth_phy_set_mdio_bus(dev, bus);
1477 priv->interface = pdata->phy_interface;
1478 switch (priv->interface) {
1479 case PHY_INTERFACE_MODE_MII:
1480 priv->xcv_type = MII100;
1482 case PHY_INTERFACE_MODE_RMII:
1483 priv->xcv_type = RMII;
1485 case PHY_INTERFACE_MODE_RGMII:
1486 case PHY_INTERFACE_MODE_RGMII_ID:
1487 case PHY_INTERFACE_MODE_RGMII_RXID:
1488 case PHY_INTERFACE_MODE_RGMII_TXID:
1489 priv->xcv_type = RGMII;
1492 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1493 printf("Unsupported interface type %d defaulting to %d\n",
1494 priv->interface, priv->xcv_type);
1498 ret = fec_phy_init(priv, dev);
1505 mdio_unregister(bus);
1509 fec_free_descs(priv);
1513 static int fecmxc_remove(struct udevice *dev)
1515 struct fec_priv *priv = dev_get_priv(dev);
1518 fec_free_descs(priv);
1519 mdio_unregister(priv->bus);
1520 mdio_free(priv->bus);
1522 #ifdef CONFIG_DM_REGULATOR
1523 if (priv->phy_supply)
1524 regulator_set_enable(priv->phy_supply, false);
1530 static int fecmxc_of_to_plat(struct udevice *dev)
1533 struct eth_pdata *pdata = dev_get_plat(dev);
1534 struct fec_priv *priv = dev_get_priv(dev);
1535 const char *phy_mode;
1537 pdata->iobase = dev_read_addr(dev);
1538 priv->eth = (struct ethernet_regs *)pdata->iobase;
1540 pdata->phy_interface = -1;
1541 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1544 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1545 if (pdata->phy_interface == -1) {
1546 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1550 #ifdef CONFIG_DM_REGULATOR
1551 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1554 #if CONFIG_IS_ENABLED(DM_GPIO)
1555 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1556 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1558 return 0; /* property is optional, don't return error! */
1560 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1561 if (priv->reset_delay > 1000) {
1562 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1563 /* property value wrong, use default value */
1564 priv->reset_delay = 1;
1567 priv->reset_post_delay = dev_read_u32_default(dev,
1568 "phy-reset-post-delay",
1570 if (priv->reset_post_delay > 1000) {
1571 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1572 /* property value wrong, use default value */
1573 priv->reset_post_delay = 0;
1580 static const struct udevice_id fecmxc_ids[] = {
1581 { .compatible = "fsl,imx28-fec" },
1582 { .compatible = "fsl,imx6q-fec" },
1583 { .compatible = "fsl,imx6sl-fec" },
1584 { .compatible = "fsl,imx6sx-fec" },
1585 { .compatible = "fsl,imx6ul-fec" },
1586 { .compatible = "fsl,imx53-fec" },
1587 { .compatible = "fsl,imx7d-fec" },
1588 { .compatible = "fsl,mvf600-fec" },
1592 U_BOOT_DRIVER(fecmxc_gem) = {
1595 .of_match = fecmxc_ids,
1596 .of_to_plat = fecmxc_of_to_plat,
1597 .probe = fecmxc_probe,
1598 .remove = fecmxc_remove,
1600 .priv_auto = sizeof(struct fec_priv),
1601 .plat_auto = sizeof(struct eth_pdata),