1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
13 #include <environment.h>
19 #include <power/regulator.h>
22 #include <linux/errno.h>
23 #include <linux/compiler.h>
25 #include <asm/arch/clock.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/mach-imx/sys_proto.h>
28 #include <asm-generic/gpio.h>
32 DECLARE_GLOBAL_DATA_PTR;
35 * Timeout the transfer after 5 mS. This is usually a bit more, since
36 * the code in the tightloops this timeout is used in adds some overhead.
38 #define FEC_XFER_TIMEOUT 5000
41 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
42 * 64-byte alignment in the DMA RX FEC buffer.
43 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
44 * satisfies the alignment on other SoCs (32-bytes)
46 #define FEC_DMA_RX_MINALIGN 64
49 #error "CONFIG_MII has to be defined!"
52 #ifndef CONFIG_FEC_XCV_TYPE
53 #define CONFIG_FEC_XCV_TYPE MII100
57 * The i.MX28 operates with packets in big endian. We need to swap them before
58 * sending and after receiving.
61 #define CONFIG_FEC_MXC_SWAP_PACKET
64 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
66 /* Check various alignment issues at compile time */
67 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
68 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
71 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
72 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
73 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
78 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
79 static void swap_packet(uint32_t *packet, int length)
83 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
84 packet[i] = __swab32(packet[i]);
88 /* MII-interface related functions */
89 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
92 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
101 writel(FEC_IEVENT_MII, ð->ievent);
102 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
106 phy | reg, ð->mii_data);
108 /* wait for the related interrupt */
109 start = get_timer(0);
110 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
117 /* clear mii interrupt bit */
118 writel(FEC_IEVENT_MII, ð->ievent);
120 /* it's now safe to read the PHY's register */
121 val = (unsigned short)readl(ð->mii_data);
122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
127 static int fec_get_clk_rate(void *udev, int idx)
129 #if IS_ENABLED(CONFIG_IMX8)
130 struct fec_priv *fec;
136 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
138 debug("Can't get FEC udev: %d\n", ret);
143 fec = dev_get_priv(dev);
145 return fec->clk_rate;
149 return imx_get_fecclk();
153 static void fec_mii_setspeed(struct ethernet_regs *eth)
156 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
157 * and do not drop the Preamble.
159 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
160 * MII_SPEED) register that defines the MDIO output hold time. Earlier
161 * versions are RAZ there, so just ignore the difference and write the
163 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
164 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
166 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
167 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
168 * holdtime cannot result in a value greater than 3.
175 ret = fec_get_clk_rate(NULL, 0);
177 printf("Can't find FEC0 clk rate: %d\n", ret);
181 speed = DIV_ROUND_UP(pclk, 5000000);
182 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
184 #ifdef FEC_QUIRK_ENET_MAC
187 writel(speed << 1 | hold << 8, ð->mii_speed);
188 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
191 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
192 uint8_t regaddr, uint16_t data)
194 uint32_t reg; /* convenient holder for the PHY register */
195 uint32_t phy; /* convenient holder for the PHY */
198 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
199 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
201 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
202 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
204 /* wait for the MII interrupt */
205 start = get_timer(0);
206 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
207 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
208 printf("Write MDIO failed...\n");
213 /* clear MII interrupt bit */
214 writel(FEC_IEVENT_MII, ð->ievent);
215 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
221 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
224 return fec_mdio_read(bus->priv, phyaddr, regaddr);
227 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
228 int regaddr, u16 data)
230 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
233 #ifndef CONFIG_PHYLIB
234 static int miiphy_restart_aneg(struct eth_device *dev)
237 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
238 struct fec_priv *fec = (struct fec_priv *)dev->priv;
239 struct ethernet_regs *eth = fec->bus->priv;
242 * Wake up from sleep if necessary
243 * Reset PHY, then delay 300ns
246 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
248 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
251 /* Set the auto-negotiation advertisement register bits */
252 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
253 LPA_100FULL | LPA_100HALF | LPA_10FULL |
254 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
255 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
256 BMCR_ANENABLE | BMCR_ANRESTART);
258 if (fec->mii_postcall)
259 ret = fec->mii_postcall(fec->phy_id);
265 #ifndef CONFIG_FEC_FIXED_SPEED
266 static int miiphy_wait_aneg(struct eth_device *dev)
270 struct fec_priv *fec = (struct fec_priv *)dev->priv;
271 struct ethernet_regs *eth = fec->bus->priv;
273 /* Wait for AN completion */
274 start = get_timer(0);
276 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
277 printf("%s: Autonegotiation timeout\n", dev->name);
281 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
283 printf("%s: Autonegotiation failed. status: %d\n",
287 } while (!(status & BMSR_LSTATUS));
291 #endif /* CONFIG_FEC_FIXED_SPEED */
294 static int fec_rx_task_enable(struct fec_priv *fec)
296 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
300 static int fec_rx_task_disable(struct fec_priv *fec)
305 static int fec_tx_task_enable(struct fec_priv *fec)
307 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
311 static int fec_tx_task_disable(struct fec_priv *fec)
317 * Initialize receive task's buffer descriptors
318 * @param[in] fec all we know about the device yet
319 * @param[in] count receive buffer count to be allocated
320 * @param[in] dsize desired size of each receive buffer
321 * @return 0 on success
323 * Init all RX descriptors to default values.
325 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
332 * Reload the RX descriptors with default values and wipe
335 size = roundup(dsize, ARCH_DMA_MINALIGN);
336 for (i = 0; i < count; i++) {
337 data = fec->rbd_base[i].data_pointer;
338 memset((void *)data, 0, dsize);
339 flush_dcache_range(data, data + size);
341 fec->rbd_base[i].status = FEC_RBD_EMPTY;
342 fec->rbd_base[i].data_length = 0;
345 /* Mark the last RBD to close the ring. */
346 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
349 flush_dcache_range((ulong)fec->rbd_base,
350 (ulong)fec->rbd_base + size);
354 * Initialize transmit task's buffer descriptors
355 * @param[in] fec all we know about the device yet
357 * Transmit buffers are created externally. We only have to init the BDs here.\n
358 * Note: There is a race condition in the hardware. When only one BD is in
359 * use it must be marked with the WRAP bit to use it for every transmitt.
360 * This bit in combination with the READY bit results into double transmit
361 * of each data buffer. It seems the state machine checks READY earlier then
362 * resetting it after the first transfer.
363 * Using two BDs solves this issue.
365 static void fec_tbd_init(struct fec_priv *fec)
367 ulong addr = (ulong)fec->tbd_base;
368 unsigned size = roundup(2 * sizeof(struct fec_bd),
371 memset(fec->tbd_base, 0, size);
372 fec->tbd_base[0].status = 0;
373 fec->tbd_base[1].status = FEC_TBD_WRAP;
375 flush_dcache_range(addr, addr + size);
379 * Mark the given read buffer descriptor as free
380 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
381 * @param[in] prbd buffer descriptor to mark free again
383 static void fec_rbd_clean(int last, struct fec_bd *prbd)
385 unsigned short flags = FEC_RBD_EMPTY;
387 flags |= FEC_RBD_WRAP;
388 writew(flags, &prbd->status);
389 writew(0, &prbd->data_length);
392 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
394 imx_get_mac_from_fuse(dev_id, mac);
395 return !is_valid_ethaddr(mac);
399 static int fecmxc_set_hwaddr(struct udevice *dev)
401 static int fec_set_hwaddr(struct eth_device *dev)
405 struct fec_priv *fec = dev_get_priv(dev);
406 struct eth_pdata *pdata = dev_get_platdata(dev);
407 uchar *mac = pdata->enetaddr;
409 uchar *mac = dev->enetaddr;
410 struct fec_priv *fec = (struct fec_priv *)dev->priv;
413 writel(0, &fec->eth->iaddr1);
414 writel(0, &fec->eth->iaddr2);
415 writel(0, &fec->eth->gaddr1);
416 writel(0, &fec->eth->gaddr2);
418 /* Set physical address */
419 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
421 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
426 /* Do initial configuration of the FEC registers */
427 static void fec_reg_setup(struct fec_priv *fec)
431 /* Set interrupt mask register */
432 writel(0x00000000, &fec->eth->imask);
434 /* Clear FEC-Lite interrupt event register(IEVENT) */
435 writel(0xffffffff, &fec->eth->ievent);
437 /* Set FEC-Lite receive control register(R_CNTRL): */
439 /* Start with frame length = 1518, common for all modes. */
440 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
441 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
442 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
443 if (fec->xcv_type == RGMII)
444 rcntrl |= FEC_RCNTRL_RGMII;
445 else if (fec->xcv_type == RMII)
446 rcntrl |= FEC_RCNTRL_RMII;
448 writel(rcntrl, &fec->eth->r_cntrl);
452 * Start the FEC engine
453 * @param[in] dev Our device to handle
456 static int fec_open(struct udevice *dev)
458 static int fec_open(struct eth_device *edev)
462 struct fec_priv *fec = dev_get_priv(dev);
464 struct fec_priv *fec = (struct fec_priv *)edev->priv;
470 debug("fec_open: fec_open(dev)\n");
471 /* full-duplex, heartbeat disabled */
472 writel(1 << 2, &fec->eth->x_cntrl);
475 /* Invalidate all descriptors */
476 for (i = 0; i < FEC_RBD_NUM - 1; i++)
477 fec_rbd_clean(0, &fec->rbd_base[i]);
478 fec_rbd_clean(1, &fec->rbd_base[i]);
480 /* Flush the descriptors into RAM */
481 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
483 addr = (ulong)fec->rbd_base;
484 flush_dcache_range(addr, addr + size);
486 #ifdef FEC_QUIRK_ENET_MAC
487 /* Enable ENET HW endian SWAP */
488 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
490 /* Enable ENET store and forward mode */
491 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
494 /* Enable FEC-Lite controller */
495 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
498 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
501 /* setup the MII gasket for RMII mode */
502 /* disable the gasket */
503 writew(0, &fec->eth->miigsk_enr);
505 /* wait for the gasket to be disabled */
506 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
509 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
510 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
512 /* re-enable the gasket */
513 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
515 /* wait until MII gasket is ready */
517 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
518 if (--max_loops <= 0) {
519 printf("WAIT for MII Gasket ready timed out\n");
527 /* Start up the PHY */
528 int ret = phy_startup(fec->phydev);
531 printf("Could not initialize PHY %s\n",
532 fec->phydev->dev->name);
535 speed = fec->phydev->speed;
537 #elif CONFIG_FEC_FIXED_SPEED
538 speed = CONFIG_FEC_FIXED_SPEED;
540 miiphy_wait_aneg(edev);
541 speed = miiphy_speed(edev->name, fec->phy_id);
542 miiphy_duplex(edev->name, fec->phy_id);
545 #ifdef FEC_QUIRK_ENET_MAC
547 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
548 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
549 if (speed == _1000BASET)
550 ecr |= FEC_ECNTRL_SPEED;
551 else if (speed != _100BASET)
552 rcr |= FEC_RCNTRL_RMII_10T;
553 writel(ecr, &fec->eth->ecntrl);
554 writel(rcr, &fec->eth->r_cntrl);
557 debug("%s:Speed=%i\n", __func__, speed);
559 /* Enable SmartDMA receive task */
560 fec_rx_task_enable(fec);
567 static int fecmxc_init(struct udevice *dev)
569 static int fec_init(struct eth_device *dev, bd_t *bd)
573 struct fec_priv *fec = dev_get_priv(dev);
575 struct fec_priv *fec = (struct fec_priv *)dev->priv;
577 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
581 /* Initialize MAC address */
583 fecmxc_set_hwaddr(dev);
588 /* Setup transmit descriptors, there are two in total. */
591 /* Setup receive descriptors. */
592 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
596 if (fec->xcv_type != SEVENWIRE)
597 fec_mii_setspeed(fec->bus->priv);
599 /* Set Opcode/Pause Duration Register */
600 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
601 writel(0x2, &fec->eth->x_wmrk);
603 /* Set multicast address filter */
604 writel(0x00000000, &fec->eth->gaddr1);
605 writel(0x00000000, &fec->eth->gaddr2);
607 /* Do not access reserved register */
608 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
610 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
613 /* FIFO receive start register */
614 writel(0x520, &fec->eth->r_fstart);
617 /* size and address of each buffer */
618 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
620 addr = (ulong)fec->tbd_base;
621 writel((uint32_t)addr, &fec->eth->etdsr);
623 addr = (ulong)fec->rbd_base;
624 writel((uint32_t)addr, &fec->eth->erdsr);
626 #ifndef CONFIG_PHYLIB
627 if (fec->xcv_type != SEVENWIRE)
628 miiphy_restart_aneg(dev);
635 * Halt the FEC engine
636 * @param[in] dev Our device to handle
639 static void fecmxc_halt(struct udevice *dev)
641 static void fec_halt(struct eth_device *dev)
645 struct fec_priv *fec = dev_get_priv(dev);
647 struct fec_priv *fec = (struct fec_priv *)dev->priv;
649 int counter = 0xffff;
651 /* issue graceful stop command to the FEC transmitter if necessary */
652 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
655 debug("eth_halt: wait for stop regs\n");
656 /* wait for graceful stop to register */
657 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
660 /* Disable SmartDMA tasks */
661 fec_tx_task_disable(fec);
662 fec_rx_task_disable(fec);
665 * Disable the Ethernet Controller
666 * Note: this will also reset the BD index counter!
668 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
672 debug("eth_halt: done\n");
677 * @param[in] dev Our ethernet device to handle
678 * @param[in] packet Pointer to the data to be transmitted
679 * @param[in] length Data count in bytes
680 * @return 0 on success
683 static int fecmxc_send(struct udevice *dev, void *packet, int length)
685 static int fec_send(struct eth_device *dev, void *packet, int length)
691 int timeout = FEC_XFER_TIMEOUT;
695 * This routine transmits one frame. This routine only accepts
696 * 6-byte Ethernet addresses.
699 struct fec_priv *fec = dev_get_priv(dev);
701 struct fec_priv *fec = (struct fec_priv *)dev->priv;
705 * Check for valid length of data.
707 if ((length > 1500) || (length <= 0)) {
708 printf("Payload (%d) too large\n", length);
713 * Setup the transmit buffer. We are always using the first buffer for
714 * transmission, the second will be empty and only used to stop the DMA
715 * engine. We also flush the packet to RAM here to avoid cache trouble.
717 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
718 swap_packet((uint32_t *)packet, length);
721 addr = (ulong)packet;
722 end = roundup(addr + length, ARCH_DMA_MINALIGN);
723 addr &= ~(ARCH_DMA_MINALIGN - 1);
724 flush_dcache_range(addr, end);
726 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
727 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
730 * update BD's status now
732 * - is always the last in a chain (means no chain)
733 * - should transmitt the CRC
734 * - might be the last BD in the list, so the address counter should
735 * wrap (-> keep the WRAP flag)
737 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
738 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
739 writew(status, &fec->tbd_base[fec->tbd_index].status);
742 * Flush data cache. This code flushes both TX descriptors to RAM.
743 * After this code, the descriptors will be safely in RAM and we
746 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
747 addr = (ulong)fec->tbd_base;
748 flush_dcache_range(addr, addr + size);
751 * Below we read the DMA descriptor's last four bytes back from the
752 * DRAM. This is important in order to make sure that all WRITE
753 * operations on the bus that were triggered by previous cache FLUSH
756 * Otherwise, on MX28, it is possible to observe a corruption of the
757 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
758 * for the bus structure of MX28. The scenario is as follows:
760 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
761 * to DRAM due to flush_dcache_range()
762 * 2) ARM core writes the FEC registers via AHB_ARB2
763 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
765 * Note that 2) does sometimes finish before 1) due to reordering of
766 * WRITE accesses on the AHB bus, therefore triggering 3) before the
767 * DMA descriptor is fully written into DRAM. This results in occasional
768 * corruption of the DMA descriptor.
770 readl(addr + size - 4);
772 /* Enable SmartDMA transmit task */
773 fec_tx_task_enable(fec);
776 * Wait until frame is sent. On each turn of the wait cycle, we must
777 * invalidate data cache to see what's really in RAM. Also, we need
781 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
791 * The TDAR bit is cleared when the descriptors are all out from TX
792 * but on mx6solox we noticed that the READY bit is still not cleared
794 * These are two distinct signals, and in IC simulation, we found that
795 * TDAR always gets cleared prior than the READY bit of last BD becomes
797 * In mx6solox, we use a later version of FEC IP. It looks like that
798 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
801 * Fix this by polling the READY bit of BD after the TDAR polling,
802 * which covers the mx6solox case and does not harm the other SoCs.
804 timeout = FEC_XFER_TIMEOUT;
806 invalidate_dcache_range(addr, addr + size);
807 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
816 debug("fec_send: status 0x%x index %d ret %i\n",
817 readw(&fec->tbd_base[fec->tbd_index].status),
818 fec->tbd_index, ret);
819 /* for next transmission use the other buffer */
829 * Pull one frame from the card
830 * @param[in] dev Our ethernet device to handle
831 * @return Length of packet read
834 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
836 static int fec_recv(struct eth_device *dev)
840 struct fec_priv *fec = dev_get_priv(dev);
842 struct fec_priv *fec = (struct fec_priv *)dev->priv;
844 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
845 unsigned long ievent;
846 int frame_length, len = 0;
848 ulong addr, size, end;
852 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
854 printf("%s: error allocating packetp\n", __func__);
858 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
861 /* Check if any critical events have happened */
862 ievent = readl(&fec->eth->ievent);
863 writel(ievent, &fec->eth->ievent);
864 debug("fec_recv: ievent 0x%lx\n", ievent);
865 if (ievent & FEC_IEVENT_BABR) {
871 fec_init(dev, fec->bd);
873 printf("some error: 0x%08lx\n", ievent);
876 if (ievent & FEC_IEVENT_HBERR) {
877 /* Heartbeat error */
878 writel(0x00000001 | readl(&fec->eth->x_cntrl),
881 if (ievent & FEC_IEVENT_GRA) {
882 /* Graceful stop complete */
883 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
889 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
894 fec_init(dev, fec->bd);
900 * Read the buffer status. Before the status can be read, the data cache
901 * must be invalidated, because the data in RAM might have been changed
902 * by DMA. The descriptors are properly aligned to cachelines so there's
903 * no need to worry they'd overlap.
905 * WARNING: By invalidating the descriptor here, we also invalidate
906 * the descriptors surrounding this one. Therefore we can NOT change the
907 * contents of this descriptor nor the surrounding ones. The problem is
908 * that in order to mark the descriptor as processed, we need to change
909 * the descriptor. The solution is to mark the whole cache line when all
910 * descriptors in the cache line are processed.
913 addr &= ~(ARCH_DMA_MINALIGN - 1);
914 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
915 invalidate_dcache_range(addr, addr + size);
917 bd_status = readw(&rbd->status);
918 debug("fec_recv: status 0x%x\n", bd_status);
920 if (!(bd_status & FEC_RBD_EMPTY)) {
921 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
922 ((readw(&rbd->data_length) - 4) > 14)) {
923 /* Get buffer address and size */
924 addr = readl(&rbd->data_pointer);
925 frame_length = readw(&rbd->data_length) - 4;
926 /* Invalidate data cache over the buffer */
927 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
928 addr &= ~(ARCH_DMA_MINALIGN - 1);
929 invalidate_dcache_range(addr, end);
931 /* Fill the buffer and pass it to upper layers */
932 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
933 swap_packet((uint32_t *)addr, frame_length);
937 memcpy(*packetp, (char *)addr, frame_length);
939 memcpy(buff, (char *)addr, frame_length);
940 net_process_received_packet(buff, frame_length);
944 if (bd_status & FEC_RBD_ERR)
945 debug("error frame: 0x%08lx 0x%08x\n",
950 * Free the current buffer, restart the engine and move forward
951 * to the next buffer. Here we check if the whole cacheline of
952 * descriptors was already processed and if so, we mark it free
955 size = RXDESC_PER_CACHELINE - 1;
956 if ((fec->rbd_index & size) == size) {
957 i = fec->rbd_index - size;
958 addr = (ulong)&fec->rbd_base[i];
959 for (; i <= fec->rbd_index ; i++) {
960 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
963 flush_dcache_range(addr,
964 addr + ARCH_DMA_MINALIGN);
967 fec_rx_task_enable(fec);
968 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
970 debug("fec_recv: stop\n");
975 static void fec_set_dev_name(char *dest, int dev_id)
977 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
980 static int fec_alloc_descs(struct fec_priv *fec)
987 /* Allocate TX descriptors. */
988 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
989 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
993 /* Allocate RX descriptors. */
994 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
995 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
999 memset(fec->rbd_base, 0, size);
1001 /* Allocate RX buffers. */
1003 /* Maximum RX buffer size. */
1004 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1005 for (i = 0; i < FEC_RBD_NUM; i++) {
1006 data = memalign(FEC_DMA_RX_MINALIGN, size);
1008 printf("%s: error allocating rxbuf %d\n", __func__, i);
1012 memset(data, 0, size);
1015 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1016 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1017 fec->rbd_base[i].data_length = 0;
1018 /* Flush the buffer to memory. */
1019 flush_dcache_range(addr, addr + size);
1022 /* Mark the last RBD to close the ring. */
1023 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1031 for (; i >= 0; i--) {
1032 addr = fec->rbd_base[i].data_pointer;
1035 free(fec->rbd_base);
1037 free(fec->tbd_base);
1042 static void fec_free_descs(struct fec_priv *fec)
1047 for (i = 0; i < FEC_RBD_NUM; i++) {
1048 addr = fec->rbd_base[i].data_pointer;
1051 free(fec->rbd_base);
1052 free(fec->tbd_base);
1055 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1057 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1058 struct mii_dev *bus;
1063 printf("mdio_alloc failed\n");
1066 bus->read = fec_phy_read;
1067 bus->write = fec_phy_write;
1069 fec_set_dev_name(bus->name, dev_id);
1071 ret = mdio_register(bus);
1073 printf("mdio_register failed\n");
1077 fec_mii_setspeed(eth);
1081 #ifndef CONFIG_DM_ETH
1082 #ifdef CONFIG_PHYLIB
1083 int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1084 struct mii_dev *bus, struct phy_device *phydev)
1086 static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1087 struct mii_dev *bus, int phy_id)
1090 struct eth_device *edev;
1091 struct fec_priv *fec;
1092 unsigned char ethaddr[6];
1097 /* create and fill edev struct */
1098 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1100 puts("fec_mxc: not enough malloc memory for eth_device\n");
1105 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1107 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1112 memset(edev, 0, sizeof(*edev));
1113 memset(fec, 0, sizeof(*fec));
1115 ret = fec_alloc_descs(fec);
1120 edev->init = fec_init;
1121 edev->send = fec_send;
1122 edev->recv = fec_recv;
1123 edev->halt = fec_halt;
1124 edev->write_hwaddr = fec_set_hwaddr;
1126 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1129 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1132 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1133 start = get_timer(0);
1134 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1135 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1136 printf("FEC MXC: Timeout resetting chip\n");
1143 fec_set_dev_name(edev->name, dev_id);
1144 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1146 fec_mii_setspeed(bus->priv);
1147 #ifdef CONFIG_PHYLIB
1148 fec->phydev = phydev;
1149 phy_connect_dev(phydev, edev);
1153 fec->phy_id = phy_id;
1156 /* only support one eth device, the index number pointed by dev_id */
1157 edev->index = fec->dev_id;
1159 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1160 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1161 memcpy(edev->enetaddr, ethaddr, 6);
1163 sprintf(mac, "eth%daddr", fec->dev_id);
1165 strcpy(mac, "ethaddr");
1167 eth_env_set_enetaddr(mac, ethaddr);
1171 fec_free_descs(fec);
1180 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1183 struct mii_dev *bus = NULL;
1184 #ifdef CONFIG_PHYLIB
1185 struct phy_device *phydev = NULL;
1189 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1191 * The i.MX28 has two ethernet interfaces, but they are not equal.
1192 * Only the first one can access the MDIO bus.
1194 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1198 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1199 bus = fec_get_miibus(base_mii, dev_id);
1202 #ifdef CONFIG_PHYLIB
1203 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1205 mdio_unregister(bus);
1209 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1211 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1214 #ifdef CONFIG_PHYLIB
1217 mdio_unregister(bus);
1223 #ifdef CONFIG_FEC_MXC_PHYADDR
1224 int fecmxc_initialize(bd_t *bd)
1226 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1231 #ifndef CONFIG_PHYLIB
1232 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1234 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1235 fec->mii_postcall = cb;
1242 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1244 struct fec_priv *priv = dev_get_priv(dev);
1245 struct eth_pdata *pdata = dev_get_platdata(dev);
1247 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1250 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1258 static const struct eth_ops fecmxc_ops = {
1259 .start = fecmxc_init,
1260 .send = fecmxc_send,
1261 .recv = fecmxc_recv,
1262 .free_pkt = fecmxc_free_pkt,
1263 .stop = fecmxc_halt,
1264 .write_hwaddr = fecmxc_set_hwaddr,
1265 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1268 static int device_get_phy_addr(struct udevice *dev)
1270 struct ofnode_phandle_args phandle_args;
1273 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1275 debug("Failed to find phy-handle");
1279 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1284 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1286 struct phy_device *phydev;
1289 addr = device_get_phy_addr(dev);
1290 #ifdef CONFIG_FEC_MXC_PHYADDR
1291 addr = CONFIG_FEC_MXC_PHYADDR;
1294 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1298 priv->phydev = phydev;
1304 #ifdef CONFIG_DM_GPIO
1305 /* FEC GPIO reset */
1306 static void fec_gpio_reset(struct fec_priv *priv)
1308 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1309 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1310 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1311 mdelay(priv->reset_delay);
1312 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1313 if (priv->reset_post_delay)
1314 mdelay(priv->reset_post_delay);
1319 static int fecmxc_probe(struct udevice *dev)
1321 struct eth_pdata *pdata = dev_get_platdata(dev);
1322 struct fec_priv *priv = dev_get_priv(dev);
1323 struct mii_dev *bus = NULL;
1327 if (IS_ENABLED(CONFIG_IMX8)) {
1328 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1330 debug("Can't get FEC ipg clk: %d\n", ret);
1333 ret = clk_enable(&priv->ipg_clk);
1335 debug("Can't enable FEC ipg clk: %d\n", ret);
1339 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1342 ret = fec_alloc_descs(priv);
1346 #ifdef CONFIG_DM_REGULATOR
1347 if (priv->phy_supply) {
1348 ret = regulator_set_enable(priv->phy_supply, true);
1350 printf("%s: Error enabling phy supply\n", dev->name);
1356 #ifdef CONFIG_DM_GPIO
1357 fec_gpio_reset(priv);
1360 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1361 &priv->eth->ecntrl);
1362 start = get_timer(0);
1363 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1364 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1365 printf("FEC MXC: Timeout reseting chip\n");
1371 fec_reg_setup(priv);
1373 priv->dev_id = dev->seq;
1374 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1375 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1377 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
1385 priv->interface = pdata->phy_interface;
1386 switch (priv->interface) {
1387 case PHY_INTERFACE_MODE_MII:
1388 priv->xcv_type = MII100;
1390 case PHY_INTERFACE_MODE_RMII:
1391 priv->xcv_type = RMII;
1393 case PHY_INTERFACE_MODE_RGMII:
1394 case PHY_INTERFACE_MODE_RGMII_ID:
1395 case PHY_INTERFACE_MODE_RGMII_RXID:
1396 case PHY_INTERFACE_MODE_RGMII_TXID:
1397 priv->xcv_type = RGMII;
1400 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1401 printf("Unsupported interface type %d defaulting to %d\n",
1402 priv->interface, priv->xcv_type);
1406 ret = fec_phy_init(priv, dev);
1413 mdio_unregister(bus);
1417 fec_free_descs(priv);
1421 static int fecmxc_remove(struct udevice *dev)
1423 struct fec_priv *priv = dev_get_priv(dev);
1426 fec_free_descs(priv);
1427 mdio_unregister(priv->bus);
1428 mdio_free(priv->bus);
1430 #ifdef CONFIG_DM_REGULATOR
1431 if (priv->phy_supply)
1432 regulator_set_enable(priv->phy_supply, false);
1438 static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1441 struct eth_pdata *pdata = dev_get_platdata(dev);
1442 struct fec_priv *priv = dev_get_priv(dev);
1443 const char *phy_mode;
1445 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1446 priv->eth = (struct ethernet_regs *)pdata->iobase;
1448 pdata->phy_interface = -1;
1449 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1452 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1453 if (pdata->phy_interface == -1) {
1454 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1458 #ifdef CONFIG_DM_REGULATOR
1459 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1462 #ifdef CONFIG_DM_GPIO
1463 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1464 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1466 return 0; /* property is optional, don't return error! */
1468 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1469 if (priv->reset_delay > 1000) {
1470 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1471 /* property value wrong, use default value */
1472 priv->reset_delay = 1;
1475 priv->reset_post_delay = dev_read_u32_default(dev,
1476 "phy-reset-post-delay",
1478 if (priv->reset_post_delay > 1000) {
1479 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1480 /* property value wrong, use default value */
1481 priv->reset_post_delay = 0;
1488 static const struct udevice_id fecmxc_ids[] = {
1489 { .compatible = "fsl,imx28-fec" },
1490 { .compatible = "fsl,imx6q-fec" },
1491 { .compatible = "fsl,imx6sl-fec" },
1492 { .compatible = "fsl,imx6sx-fec" },
1493 { .compatible = "fsl,imx6ul-fec" },
1494 { .compatible = "fsl,imx53-fec" },
1495 { .compatible = "fsl,imx7d-fec" },
1496 { .compatible = "fsl,mvf600-fec" },
1500 U_BOOT_DRIVER(fecmxc_gem) = {
1503 .of_match = fecmxc_ids,
1504 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1505 .probe = fecmxc_probe,
1506 .remove = fecmxc_remove,
1508 .priv_auto_alloc_size = sizeof(struct fec_priv),
1509 .platdata_auto_alloc_size = sizeof(struct eth_pdata),