2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
44 uint8_t data[1500]; /**< actual data */
45 int length; /**< actual length */
46 int used; /**< buffer in use or not */
47 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
50 struct fec_priv gfec = {
51 .eth = (struct ethernet_regs *)IMX_FEC_BASE,
63 * MII-interface related functions
65 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
68 struct eth_device *edev = eth_get_dev_by_name(dev);
69 struct fec_priv *fec = (struct fec_priv *)edev->priv;
71 uint32_t reg; /* convenient holder for the PHY register */
72 uint32_t phy; /* convenient holder for the PHY */
76 * reading from any PHY's register is done by properly
77 * programming the FEC's MII data register.
79 writel(FEC_IEVENT_MII, &fec->eth->ievent);
80 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
81 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
83 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
84 phy | reg, &fec->eth->mii_data);
87 * wait for the related interrupt
90 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
91 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
92 printf("Read MDIO failed...\n");
98 * clear mii interrupt bit
100 writel(FEC_IEVENT_MII, &fec->eth->ievent);
103 * it's now safe to read the PHY's register
105 *retVal = readl(&fec->eth->mii_data);
106 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
111 static void fec_mii_setspeed(struct fec_priv *fec)
114 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
115 * and do not drop the Preamble.
117 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
118 &fec->eth->mii_speed);
119 debug("fec_init: mii_speed %#lx\n",
120 readl(&fec->eth->mii_speed));
122 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
125 struct eth_device *edev = eth_get_dev_by_name(dev);
126 struct fec_priv *fec = (struct fec_priv *)edev->priv;
128 uint32_t reg; /* convenient holder for the PHY register */
129 uint32_t phy; /* convenient holder for the PHY */
132 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
133 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
135 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
136 FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
139 * wait for the MII interrupt
141 start = get_timer(0);
142 while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
143 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
144 printf("Write MDIO failed...\n");
150 * clear MII interrupt bit
152 writel(FEC_IEVENT_MII, &fec->eth->ievent);
153 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
159 static int miiphy_restart_aneg(struct eth_device *dev)
162 * Wake up from sleep if necessary
163 * Reset PHY, then delay 300ns
166 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_DCOUNTER, 0x00FF);
168 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
173 * Set the auto-negotiation advertisement register bits
175 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_ADVERTISE,
176 LPA_100FULL | LPA_100HALF | LPA_10FULL |
177 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
178 miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, MII_BMCR,
179 BMCR_ANENABLE | BMCR_ANRESTART);
184 static int miiphy_wait_aneg(struct eth_device *dev)
190 * Wait for AN completion
192 start = get_timer(0);
194 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
195 printf("%s: Autonegotiation timeout\n", dev->name);
199 if (miiphy_read(dev->name, CONFIG_FEC_MXC_PHYADDR,
200 MII_BMSR, &status)) {
201 printf("%s: Autonegotiation failed. status: 0x%04x\n",
205 } while (!(status & BMSR_LSTATUS));
209 static int fec_rx_task_enable(struct fec_priv *fec)
211 writel(1 << 24, &fec->eth->r_des_active);
215 static int fec_rx_task_disable(struct fec_priv *fec)
220 static int fec_tx_task_enable(struct fec_priv *fec)
222 writel(1 << 24, &fec->eth->x_des_active);
226 static int fec_tx_task_disable(struct fec_priv *fec)
232 * Initialize receive task's buffer descriptors
233 * @param[in] fec all we know about the device yet
234 * @param[in] count receive buffer count to be allocated
235 * @param[in] size size of each receive buffer
236 * @return 0 on success
238 * For this task we need additional memory for the data buffers. And each
239 * data buffer requires some alignment. Thy must be aligned to a specific
240 * boundary each (DB_DATA_ALIGNMENT).
242 static int fec_rbd_init(struct fec_priv *fec, int count, int size)
247 /* reserve data memory and consider alignment */
248 if (fec->rdb_ptr == NULL)
249 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
250 p = (uint32_t)fec->rdb_ptr;
252 puts("fec_mxc: not enough malloc memory\n");
255 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
256 p += DB_DATA_ALIGNMENT-1;
257 p &= ~(DB_DATA_ALIGNMENT-1);
259 for (ix = 0; ix < count; ix++) {
260 writel(p, &fec->rbd_base[ix].data_pointer);
262 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
263 writew(0, &fec->rbd_base[ix].data_length);
266 * mark the last RBD to close the ring
268 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
275 * Initialize transmit task's buffer descriptors
276 * @param[in] fec all we know about the device yet
278 * Transmit buffers are created externally. We only have to init the BDs here.\n
279 * Note: There is a race condition in the hardware. When only one BD is in
280 * use it must be marked with the WRAP bit to use it for every transmitt.
281 * This bit in combination with the READY bit results into double transmit
282 * of each data buffer. It seems the state machine checks READY earlier then
283 * resetting it after the first transfer.
284 * Using two BDs solves this issue.
286 static void fec_tbd_init(struct fec_priv *fec)
288 writew(0x0000, &fec->tbd_base[0].status);
289 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
294 * Mark the given read buffer descriptor as free
295 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
296 * @param[in] pRbd buffer descriptor to mark free again
298 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
301 * Reset buffer descriptor as empty
304 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
306 writew(FEC_RBD_EMPTY, &pRbd->status);
310 writew(0, &pRbd->data_length);
313 static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
315 imx_get_mac_from_fuse(mac);
316 return !is_valid_ether_addr(mac);
319 static int fec_set_hwaddr(struct eth_device *dev)
321 uchar *mac = dev->enetaddr;
322 struct fec_priv *fec = (struct fec_priv *)dev->priv;
324 writel(0, &fec->eth->iaddr1);
325 writel(0, &fec->eth->iaddr2);
326 writel(0, &fec->eth->gaddr1);
327 writel(0, &fec->eth->gaddr2);
330 * Set physical address
332 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
334 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
340 * Start the FEC engine
341 * @param[in] dev Our device to handle
343 static int fec_open(struct eth_device *edev)
345 struct fec_priv *fec = (struct fec_priv *)edev->priv;
347 debug("fec_open: fec_open(dev)\n");
348 /* full-duplex, heartbeat disabled */
349 writel(1 << 2, &fec->eth->x_cntrl);
353 * Enable FEC-Lite controller
355 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
357 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
360 * setup the MII gasket for RMII mode
363 /* disable the gasket */
364 writew(0, &fec->eth->miigsk_enr);
366 /* wait for the gasket to be disabled */
367 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
370 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
371 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
373 /* re-enable the gasket */
374 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
376 /* wait until MII gasket is ready */
378 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
379 if (--max_loops <= 0) {
380 printf("WAIT for MII Gasket ready timed out\n");
386 miiphy_wait_aneg(edev);
387 miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
388 miiphy_duplex(edev->name, CONFIG_FEC_MXC_PHYADDR);
391 * Enable SmartDMA receive task
393 fec_rx_task_enable(fec);
399 static int fec_init(struct eth_device *dev, bd_t* bd)
402 struct fec_priv *fec = (struct fec_priv *)dev->priv;
405 /* Initialize MAC address */
409 * reserve memory for both buffer descriptor chains at once
410 * Datasheet forces the startaddress of each chain is 16 byte
413 if (fec->base_ptr == NULL)
414 fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
415 sizeof(struct fec_bd) + DB_ALIGNMENT);
416 base = (uint32_t)fec->base_ptr;
418 puts("fec_mxc: not enough malloc memory\n");
421 memset((void *)base, 0, (2 + FEC_RBD_NUM) *
422 sizeof(struct fec_bd) + DB_ALIGNMENT);
423 base += (DB_ALIGNMENT-1);
424 base &= ~(DB_ALIGNMENT-1);
426 fec->rbd_base = (struct fec_bd *)base;
428 base += FEC_RBD_NUM * sizeof(struct fec_bd);
430 fec->tbd_base = (struct fec_bd *)base;
433 * Set interrupt mask register
435 writel(0x00000000, &fec->eth->imask);
438 * Clear FEC-Lite interrupt event register(IEVENT)
440 writel(0xffffffff, &fec->eth->ievent);
444 * Set FEC-Lite receive control register(R_CNTRL):
447 /* Start with frame length = 1518, common for all modes. */
448 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
449 if (fec->xcv_type == SEVENWIRE)
450 rcntrl |= FEC_RCNTRL_FCE;
452 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
454 writel(rcntrl, &fec->eth->r_cntrl);
456 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
457 fec_mii_setspeed(fec);
460 * Set Opcode/Pause Duration Register
462 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
463 writel(0x2, &fec->eth->x_wmrk);
465 * Set multicast address filter
467 writel(0x00000000, &fec->eth->gaddr1);
468 writel(0x00000000, &fec->eth->gaddr2);
472 long *mib_ptr = (long *)(IMX_FEC_BASE + 0x200);
473 while (mib_ptr <= (long *)(IMX_FEC_BASE + 0x2FC))
476 /* FIFO receive start register */
477 writel(0x520, &fec->eth->r_fstart);
479 /* size and address of each buffer */
480 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
481 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
482 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
485 * Initialize RxBD/TxBD rings
487 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
489 fec->base_ptr = NULL;
495 if (fec->xcv_type != SEVENWIRE)
496 miiphy_restart_aneg(dev);
503 * Halt the FEC engine
504 * @param[in] dev Our device to handle
506 static void fec_halt(struct eth_device *dev)
508 struct fec_priv *fec = &gfec;
509 int counter = 0xffff;
512 * issue graceful stop command to the FEC transmitter if necessary
514 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
517 debug("eth_halt: wait for stop regs\n");
519 * wait for graceful stop to register
521 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
525 * Disable SmartDMA tasks
527 fec_tx_task_disable(fec);
528 fec_rx_task_disable(fec);
531 * Disable the Ethernet Controller
532 * Note: this will also reset the BD index counter!
534 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
538 debug("eth_halt: done\n");
543 * @param[in] dev Our ethernet device to handle
544 * @param[in] packet Pointer to the data to be transmitted
545 * @param[in] length Data count in bytes
546 * @return 0 on success
548 static int fec_send(struct eth_device *dev, volatile void* packet, int length)
553 * This routine transmits one frame. This routine only accepts
554 * 6-byte Ethernet addresses.
556 struct fec_priv *fec = (struct fec_priv *)dev->priv;
559 * Check for valid length of data.
561 if ((length > 1500) || (length <= 0)) {
562 printf("Payload (%d) too large\n", length);
567 * Setup the transmit buffer
568 * Note: We are always using the first buffer for transmission,
569 * the second will be empty and only used to stop the DMA engine
571 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
572 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
574 * update BD's status now
576 * - is always the last in a chain (means no chain)
577 * - should transmitt the CRC
578 * - might be the last BD in the list, so the address counter should
579 * wrap (-> keep the WRAP flag)
581 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
582 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
583 writew(status, &fec->tbd_base[fec->tbd_index].status);
586 * Enable SmartDMA transmit task
588 fec_tx_task_enable(fec);
591 * wait until frame is sent .
593 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
596 debug("fec_send: status 0x%x index %d\n",
597 readw(&fec->tbd_base[fec->tbd_index].status),
599 /* for next transmission use the other buffer */
609 * Pull one frame from the card
610 * @param[in] dev Our ethernet device to handle
611 * @return Length of packet read
613 static int fec_recv(struct eth_device *dev)
615 struct fec_priv *fec = (struct fec_priv *)dev->priv;
616 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
617 unsigned long ievent;
618 int frame_length, len = 0;
621 uchar buff[FEC_MAX_PKT_SIZE];
624 * Check if any critical events have happened
626 ievent = readl(&fec->eth->ievent);
627 writel(ievent, &fec->eth->ievent);
628 debug("fec_recv: ievent 0x%x\n", ievent);
629 if (ievent & FEC_IEVENT_BABR) {
631 fec_init(dev, fec->bd);
632 printf("some error: 0x%08lx\n", ievent);
635 if (ievent & FEC_IEVENT_HBERR) {
636 /* Heartbeat error */
637 writel(0x00000001 | readl(&fec->eth->x_cntrl),
640 if (ievent & FEC_IEVENT_GRA) {
641 /* Graceful stop complete */
642 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
644 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
646 fec_init(dev, fec->bd);
651 * ensure reading the right buffer status
653 bd_status = readw(&rbd->status);
654 debug("fec_recv: status 0x%x\n", bd_status);
656 if (!(bd_status & FEC_RBD_EMPTY)) {
657 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
658 ((readw(&rbd->data_length) - 4) > 14)) {
660 * Get buffer address and size
662 frame = (struct nbuf *)readl(&rbd->data_pointer);
663 frame_length = readw(&rbd->data_length) - 4;
665 * Fill the buffer and pass it to upper layers
667 memcpy(buff, frame->data, frame_length);
668 NetReceive(buff, frame_length);
671 if (bd_status & FEC_RBD_ERR)
672 printf("error frame: 0x%08lx 0x%08x\n",
673 (ulong)rbd->data_pointer,
677 * free the current buffer, restart the engine
678 * and move forward to the next buffer
680 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
681 fec_rx_task_enable(fec);
682 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
684 debug("fec_recv: stop\n");
689 static int fec_probe(bd_t *bd)
691 struct eth_device *edev;
692 struct fec_priv *fec = &gfec;
693 unsigned char ethaddr[6];
695 /* create and fill edev struct */
696 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
698 puts("fec_mxc: not enough malloc memory\n");
701 memset(edev, 0, sizeof(*edev));
703 edev->init = fec_init;
704 edev->send = fec_send;
705 edev->recv = fec_recv;
706 edev->halt = fec_halt;
707 edev->write_hwaddr = fec_set_hwaddr;
709 fec->eth = (struct ethernet_regs *)IMX_FEC_BASE;
712 fec->xcv_type = MII100;
715 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
716 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET)
720 * Set interrupt mask register
722 writel(0x00000000, &fec->eth->imask);
725 * Clear FEC-Lite interrupt event register(IEVENT)
727 writel(0xffffffff, &fec->eth->ievent);
730 * Set FEC-Lite receive control register(R_CNTRL):
733 * Frame length=1518; MII mode;
735 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
736 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
737 fec_mii_setspeed(fec);
739 sprintf(edev->name, "FEC");
741 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
745 if (fec_get_hwaddr(edev, ethaddr) == 0) {
746 printf("got MAC address from fuse: %pM\n", ethaddr);
747 memcpy(edev->enetaddr, ethaddr, 6);
753 int fecmxc_initialize(bd_t *bd)
757 debug("eth_init: fec_probe(bd)\n");
758 lout = fec_probe(bd);