1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
26 #include <linux/errno.h>
27 #include <linux/compiler.h>
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/mach-imx/sys_proto.h>
32 #include <asm-generic/gpio.h>
37 DECLARE_GLOBAL_DATA_PTR;
40 * Timeout the transfer after 5 mS. This is usually a bit more, since
41 * the code in the tightloops this timeout is used in adds some overhead.
43 #define FEC_XFER_TIMEOUT 5000
46 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
47 * 64-byte alignment in the DMA RX FEC buffer.
48 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
49 * satisfies the alignment on other SoCs (32-bytes)
51 #define FEC_DMA_RX_MINALIGN 64
54 #error "CONFIG_MII has to be defined!"
58 * The i.MX28 operates with packets in big endian. We need to swap them before
59 * sending and after receiving.
62 #define CONFIG_FEC_MXC_SWAP_PACKET
65 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
67 /* Check various alignment issues at compile time */
68 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
69 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
72 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
73 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
74 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
79 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
80 static void swap_packet(uint32_t *packet, int length)
84 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
85 packet[i] = __swab32(packet[i]);
89 /* MII-interface related functions */
90 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
93 uint32_t reg; /* convenient holder for the PHY register */
94 uint32_t phy; /* convenient holder for the PHY */
99 * reading from any PHY's register is done by properly
100 * programming the FEC's MII data register.
102 writel(FEC_IEVENT_MII, ð->ievent);
103 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
104 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
106 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
107 phy | reg, ð->mii_data);
109 /* wait for the related interrupt */
110 start = get_timer(0);
111 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
112 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
113 printf("Read MDIO failed...\n");
118 /* clear mii interrupt bit */
119 writel(FEC_IEVENT_MII, ð->ievent);
121 /* it's now safe to read the PHY's register */
122 val = (unsigned short)readl(ð->mii_data);
123 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
128 #ifndef imx_get_fecclk
129 u32 __weak imx_get_fecclk(void)
135 static int fec_get_clk_rate(void *udev, int idx)
137 struct fec_priv *fec;
141 if (IS_ENABLED(CONFIG_IMX8) ||
142 CONFIG_IS_ENABLED(CLK_CCF)) {
145 ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
147 debug("Can't get FEC udev: %d\n", ret);
152 fec = dev_get_priv(dev);
154 return fec->clk_rate;
158 return imx_get_fecclk();
162 static void fec_mii_setspeed(struct ethernet_regs *eth)
165 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
166 * and do not drop the Preamble.
168 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
169 * MII_SPEED) register that defines the MDIO output hold time. Earlier
170 * versions are RAZ there, so just ignore the difference and write the
172 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
173 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
175 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
176 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
177 * holdtime cannot result in a value greater than 3.
184 ret = fec_get_clk_rate(NULL, 0);
186 printf("Can't find FEC0 clk rate: %d\n", ret);
190 speed = DIV_ROUND_UP(pclk, 5000000);
191 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
193 #ifdef FEC_QUIRK_ENET_MAC
196 writel(speed << 1 | hold << 8, ð->mii_speed);
197 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
200 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
201 uint8_t regaddr, uint16_t data)
203 uint32_t reg; /* convenient holder for the PHY register */
204 uint32_t phy; /* convenient holder for the PHY */
207 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
208 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
210 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
211 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
213 /* wait for the MII interrupt */
214 start = get_timer(0);
215 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
216 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
217 printf("Write MDIO failed...\n");
222 /* clear MII interrupt bit */
223 writel(FEC_IEVENT_MII, ð->ievent);
224 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
230 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
233 return fec_mdio_read(bus->priv, phyaddr, regaddr);
236 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
237 int regaddr, u16 data)
239 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
242 #ifndef CONFIG_PHYLIB
243 static int miiphy_restart_aneg(struct eth_device *dev)
246 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
247 struct fec_priv *fec = (struct fec_priv *)dev->priv;
248 struct ethernet_regs *eth = fec->bus->priv;
251 * Wake up from sleep if necessary
252 * Reset PHY, then delay 300ns
255 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
257 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
260 /* Set the auto-negotiation advertisement register bits */
261 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
262 LPA_100FULL | LPA_100HALF | LPA_10FULL |
263 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
264 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
265 BMCR_ANENABLE | BMCR_ANRESTART);
267 if (fec->mii_postcall)
268 ret = fec->mii_postcall(fec->phy_id);
274 #ifndef CONFIG_FEC_FIXED_SPEED
275 static int miiphy_wait_aneg(struct eth_device *dev)
279 struct fec_priv *fec = (struct fec_priv *)dev->priv;
280 struct ethernet_regs *eth = fec->bus->priv;
282 /* Wait for AN completion */
283 start = get_timer(0);
285 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
286 printf("%s: Autonegotiation timeout\n", dev->name);
290 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
292 printf("%s: Autonegotiation failed. status: %d\n",
296 } while (!(status & BMSR_LSTATUS));
300 #endif /* CONFIG_FEC_FIXED_SPEED */
303 static int fec_rx_task_enable(struct fec_priv *fec)
305 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
309 static int fec_rx_task_disable(struct fec_priv *fec)
314 static int fec_tx_task_enable(struct fec_priv *fec)
316 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
320 static int fec_tx_task_disable(struct fec_priv *fec)
326 * Initialize receive task's buffer descriptors
327 * @param[in] fec all we know about the device yet
328 * @param[in] count receive buffer count to be allocated
329 * @param[in] dsize desired size of each receive buffer
330 * Return: 0 on success
332 * Init all RX descriptors to default values.
334 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
341 * Reload the RX descriptors with default values and wipe
344 size = roundup(dsize, ARCH_DMA_MINALIGN);
345 for (i = 0; i < count; i++) {
346 data = fec->rbd_base[i].data_pointer;
347 memset((void *)data, 0, dsize);
348 flush_dcache_range(data, data + size);
350 fec->rbd_base[i].status = FEC_RBD_EMPTY;
351 fec->rbd_base[i].data_length = 0;
354 /* Mark the last RBD to close the ring. */
355 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
358 flush_dcache_range((ulong)fec->rbd_base,
359 (ulong)fec->rbd_base + size);
363 * Initialize transmit task's buffer descriptors
364 * @param[in] fec all we know about the device yet
366 * Transmit buffers are created externally. We only have to init the BDs here.\n
367 * Note: There is a race condition in the hardware. When only one BD is in
368 * use it must be marked with the WRAP bit to use it for every transmitt.
369 * This bit in combination with the READY bit results into double transmit
370 * of each data buffer. It seems the state machine checks READY earlier then
371 * resetting it after the first transfer.
372 * Using two BDs solves this issue.
374 static void fec_tbd_init(struct fec_priv *fec)
376 ulong addr = (ulong)fec->tbd_base;
377 unsigned size = roundup(2 * sizeof(struct fec_bd),
380 memset(fec->tbd_base, 0, size);
381 fec->tbd_base[0].status = 0;
382 fec->tbd_base[1].status = FEC_TBD_WRAP;
384 flush_dcache_range(addr, addr + size);
388 * Mark the given read buffer descriptor as free
389 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
390 * @param[in] prbd buffer descriptor to mark free again
392 static void fec_rbd_clean(int last, struct fec_bd *prbd)
394 unsigned short flags = FEC_RBD_EMPTY;
396 flags |= FEC_RBD_WRAP;
397 writew(flags, &prbd->status);
398 writew(0, &prbd->data_length);
401 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
403 imx_get_mac_from_fuse(dev_id, mac);
404 return !is_valid_ethaddr(mac);
407 static int fecmxc_set_hwaddr(struct udevice *dev)
409 struct fec_priv *fec = dev_get_priv(dev);
410 struct eth_pdata *pdata = dev_get_plat(dev);
411 uchar *mac = pdata->enetaddr;
413 writel(0, &fec->eth->iaddr1);
414 writel(0, &fec->eth->iaddr2);
415 writel(0, &fec->eth->gaddr1);
416 writel(0, &fec->eth->gaddr2);
418 /* Set physical address */
419 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
421 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
426 /* Do initial configuration of the FEC registers */
427 static void fec_reg_setup(struct fec_priv *fec)
431 /* Set interrupt mask register */
432 writel(0x00000000, &fec->eth->imask);
434 /* Clear FEC-Lite interrupt event register(IEVENT) */
435 writel(0xffffffff, &fec->eth->ievent);
437 /* Set FEC-Lite receive control register(R_CNTRL): */
439 /* Start with frame length = 1518, common for all modes. */
440 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
441 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
442 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
443 if (fec->xcv_type == RGMII)
444 rcntrl |= FEC_RCNTRL_RGMII;
445 else if (fec->xcv_type == RMII)
446 rcntrl |= FEC_RCNTRL_RMII;
451 writel(rcntrl, &fec->eth->r_cntrl);
455 * Start the FEC engine
456 * @param[in] dev Our device to handle
458 static int fec_open(struct udevice *dev)
460 struct fec_priv *fec = dev_get_priv(dev);
465 debug("fec_open: fec_open(dev)\n");
466 /* full-duplex, heartbeat disabled */
467 writel(1 << 2, &fec->eth->x_cntrl);
470 /* Invalidate all descriptors */
471 for (i = 0; i < FEC_RBD_NUM - 1; i++)
472 fec_rbd_clean(0, &fec->rbd_base[i]);
473 fec_rbd_clean(1, &fec->rbd_base[i]);
475 /* Flush the descriptors into RAM */
476 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
478 addr = (ulong)fec->rbd_base;
479 flush_dcache_range(addr, addr + size);
481 #ifdef FEC_QUIRK_ENET_MAC
482 /* Enable ENET HW endian SWAP */
483 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
485 /* Enable ENET store and forward mode */
486 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
489 /* Enable FEC-Lite controller */
490 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
493 #ifdef FEC_ENET_ENABLE_TXC_DELAY
494 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
498 #ifdef FEC_ENET_ENABLE_RXC_DELAY
499 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
503 #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
506 /* setup the MII gasket for RMII mode */
507 /* disable the gasket */
508 writew(0, &fec->eth->miigsk_enr);
510 /* wait for the gasket to be disabled */
511 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
514 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
515 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
517 /* re-enable the gasket */
518 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
520 /* wait until MII gasket is ready */
522 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
523 if (--max_loops <= 0) {
524 printf("WAIT for MII Gasket ready timed out\n");
532 /* Start up the PHY */
533 int ret = phy_startup(fec->phydev);
536 printf("Could not initialize PHY %s\n",
537 fec->phydev->dev->name);
540 speed = fec->phydev->speed;
542 #elif CONFIG_FEC_FIXED_SPEED
543 speed = CONFIG_FEC_FIXED_SPEED;
545 miiphy_wait_aneg(edev);
546 speed = miiphy_speed(edev->name, fec->phy_id);
547 miiphy_duplex(edev->name, fec->phy_id);
550 #ifdef FEC_QUIRK_ENET_MAC
552 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
553 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
554 if (speed == _1000BASET)
555 ecr |= FEC_ECNTRL_SPEED;
556 else if (speed != _100BASET)
557 rcr |= FEC_RCNTRL_RMII_10T;
558 writel(ecr, &fec->eth->ecntrl);
559 writel(rcr, &fec->eth->r_cntrl);
562 debug("%s:Speed=%i\n", __func__, speed);
564 /* Enable SmartDMA receive task */
565 fec_rx_task_enable(fec);
571 static int fecmxc_init(struct udevice *dev)
573 struct fec_priv *fec = dev_get_priv(dev);
574 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
578 /* Initialize MAC address */
579 fecmxc_set_hwaddr(dev);
581 /* Setup transmit descriptors, there are two in total. */
584 /* Setup receive descriptors. */
585 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
589 if (fec->xcv_type != SEVENWIRE)
590 fec_mii_setspeed(fec->bus->priv);
592 /* Set Opcode/Pause Duration Register */
593 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
594 writel(0x2, &fec->eth->x_wmrk);
596 /* Set multicast address filter */
597 writel(0x00000000, &fec->eth->gaddr1);
598 writel(0x00000000, &fec->eth->gaddr2);
600 /* Do not access reserved register */
601 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
604 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
607 /* FIFO receive start register */
608 writel(0x520, &fec->eth->r_fstart);
611 /* size and address of each buffer */
612 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
614 addr = (ulong)fec->tbd_base;
615 writel((uint32_t)addr, &fec->eth->etdsr);
617 addr = (ulong)fec->rbd_base;
618 writel((uint32_t)addr, &fec->eth->erdsr);
620 #ifndef CONFIG_PHYLIB
621 if (fec->xcv_type != SEVENWIRE)
622 miiphy_restart_aneg(dev);
629 * Halt the FEC engine
630 * @param[in] dev Our device to handle
632 static void fecmxc_halt(struct udevice *dev)
634 struct fec_priv *fec = dev_get_priv(dev);
635 int counter = 0xffff;
637 /* issue graceful stop command to the FEC transmitter if necessary */
638 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
641 debug("eth_halt: wait for stop regs\n");
642 /* wait for graceful stop to register */
643 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
646 /* Disable SmartDMA tasks */
647 fec_tx_task_disable(fec);
648 fec_rx_task_disable(fec);
651 * Disable the Ethernet Controller
652 * Note: this will also reset the BD index counter!
654 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
658 debug("eth_halt: done\n");
663 * @param[in] dev Our ethernet device to handle
664 * @param[in] packet Pointer to the data to be transmitted
665 * @param[in] length Data count in bytes
666 * Return: 0 on success
668 static int fecmxc_send(struct udevice *dev, void *packet, int length)
673 int timeout = FEC_XFER_TIMEOUT;
677 * This routine transmits one frame. This routine only accepts
678 * 6-byte Ethernet addresses.
680 struct fec_priv *fec = dev_get_priv(dev);
683 * Check for valid length of data.
685 if ((length > 1500) || (length <= 0)) {
686 printf("Payload (%d) too large\n", length);
691 * Setup the transmit buffer. We are always using the first buffer for
692 * transmission, the second will be empty and only used to stop the DMA
693 * engine. We also flush the packet to RAM here to avoid cache trouble.
695 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
696 swap_packet((uint32_t *)packet, length);
699 addr = (ulong)packet;
700 end = roundup(addr + length, ARCH_DMA_MINALIGN);
701 addr &= ~(ARCH_DMA_MINALIGN - 1);
702 flush_dcache_range(addr, end);
704 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
705 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
708 * update BD's status now
710 * - is always the last in a chain (means no chain)
711 * - should transmitt the CRC
712 * - might be the last BD in the list, so the address counter should
713 * wrap (-> keep the WRAP flag)
715 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
716 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
717 writew(status, &fec->tbd_base[fec->tbd_index].status);
720 * Flush data cache. This code flushes both TX descriptors to RAM.
721 * After this code, the descriptors will be safely in RAM and we
724 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
725 addr = (ulong)fec->tbd_base;
726 flush_dcache_range(addr, addr + size);
729 * Below we read the DMA descriptor's last four bytes back from the
730 * DRAM. This is important in order to make sure that all WRITE
731 * operations on the bus that were triggered by previous cache FLUSH
734 * Otherwise, on MX28, it is possible to observe a corruption of the
735 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
736 * for the bus structure of MX28. The scenario is as follows:
738 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
739 * to DRAM due to flush_dcache_range()
740 * 2) ARM core writes the FEC registers via AHB_ARB2
741 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
743 * Note that 2) does sometimes finish before 1) due to reordering of
744 * WRITE accesses on the AHB bus, therefore triggering 3) before the
745 * DMA descriptor is fully written into DRAM. This results in occasional
746 * corruption of the DMA descriptor.
748 readl(addr + size - 4);
750 /* Enable SmartDMA transmit task */
751 fec_tx_task_enable(fec);
754 * Wait until frame is sent. On each turn of the wait cycle, we must
755 * invalidate data cache to see what's really in RAM. Also, we need
759 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
769 * The TDAR bit is cleared when the descriptors are all out from TX
770 * but on mx6solox we noticed that the READY bit is still not cleared
772 * These are two distinct signals, and in IC simulation, we found that
773 * TDAR always gets cleared prior than the READY bit of last BD becomes
775 * In mx6solox, we use a later version of FEC IP. It looks like that
776 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
779 * Fix this by polling the READY bit of BD after the TDAR polling,
780 * which covers the mx6solox case and does not harm the other SoCs.
782 timeout = FEC_XFER_TIMEOUT;
784 invalidate_dcache_range(addr, addr + size);
785 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
794 debug("fec_send: status 0x%x index %d ret %i\n",
795 readw(&fec->tbd_base[fec->tbd_index].status),
796 fec->tbd_index, ret);
797 /* for next transmission use the other buffer */
807 * Pull one frame from the card
808 * @param[in] dev Our ethernet device to handle
809 * Return: Length of packet read
811 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
813 struct fec_priv *fec = dev_get_priv(dev);
814 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
815 unsigned long ievent;
816 int frame_length, len = 0;
818 ulong addr, size, end;
821 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
823 printf("%s: error allocating packetp\n", __func__);
827 /* Check if any critical events have happened */
828 ievent = readl(&fec->eth->ievent);
829 writel(ievent, &fec->eth->ievent);
830 debug("fec_recv: ievent 0x%lx\n", ievent);
831 if (ievent & FEC_IEVENT_BABR) {
834 printf("some error: 0x%08lx\n", ievent);
837 if (ievent & FEC_IEVENT_HBERR) {
838 /* Heartbeat error */
839 writel(0x00000001 | readl(&fec->eth->x_cntrl),
842 if (ievent & FEC_IEVENT_GRA) {
843 /* Graceful stop complete */
844 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
846 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
853 * Read the buffer status. Before the status can be read, the data cache
854 * must be invalidated, because the data in RAM might have been changed
855 * by DMA. The descriptors are properly aligned to cachelines so there's
856 * no need to worry they'd overlap.
858 * WARNING: By invalidating the descriptor here, we also invalidate
859 * the descriptors surrounding this one. Therefore we can NOT change the
860 * contents of this descriptor nor the surrounding ones. The problem is
861 * that in order to mark the descriptor as processed, we need to change
862 * the descriptor. The solution is to mark the whole cache line when all
863 * descriptors in the cache line are processed.
866 addr &= ~(ARCH_DMA_MINALIGN - 1);
867 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
868 invalidate_dcache_range(addr, addr + size);
870 bd_status = readw(&rbd->status);
871 debug("fec_recv: status 0x%x\n", bd_status);
873 if (!(bd_status & FEC_RBD_EMPTY)) {
874 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
875 ((readw(&rbd->data_length) - 4) > 14)) {
876 /* Get buffer address and size */
877 addr = readl(&rbd->data_pointer);
878 frame_length = readw(&rbd->data_length) - 4;
879 /* Invalidate data cache over the buffer */
880 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
881 addr &= ~(ARCH_DMA_MINALIGN - 1);
882 invalidate_dcache_range(addr, end);
884 /* Fill the buffer and pass it to upper layers */
885 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
886 swap_packet((uint32_t *)addr, frame_length);
889 memcpy(*packetp, (char *)addr, frame_length);
892 if (bd_status & FEC_RBD_ERR)
893 debug("error frame: 0x%08lx 0x%08x\n",
898 * Free the current buffer, restart the engine and move forward
899 * to the next buffer. Here we check if the whole cacheline of
900 * descriptors was already processed and if so, we mark it free
903 size = RXDESC_PER_CACHELINE - 1;
904 if ((fec->rbd_index & size) == size) {
905 i = fec->rbd_index - size;
906 addr = (ulong)&fec->rbd_base[i];
907 for (; i <= fec->rbd_index ; i++) {
908 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
911 flush_dcache_range(addr,
912 addr + ARCH_DMA_MINALIGN);
915 fec_rx_task_enable(fec);
916 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
918 debug("fec_recv: stop\n");
923 static void fec_set_dev_name(char *dest, int dev_id)
925 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
928 static int fec_alloc_descs(struct fec_priv *fec)
935 /* Allocate TX descriptors. */
936 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
937 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
941 /* Allocate RX descriptors. */
942 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
943 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
947 memset(fec->rbd_base, 0, size);
949 /* Allocate RX buffers. */
951 /* Maximum RX buffer size. */
952 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
953 for (i = 0; i < FEC_RBD_NUM; i++) {
954 data = memalign(FEC_DMA_RX_MINALIGN, size);
956 printf("%s: error allocating rxbuf %d\n", __func__, i);
960 memset(data, 0, size);
963 fec->rbd_base[i].data_pointer = (uint32_t)addr;
964 fec->rbd_base[i].status = FEC_RBD_EMPTY;
965 fec->rbd_base[i].data_length = 0;
966 /* Flush the buffer to memory. */
967 flush_dcache_range(addr, addr + size);
970 /* Mark the last RBD to close the ring. */
971 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
979 for (; i >= 0; i--) {
980 addr = fec->rbd_base[i].data_pointer;
990 static void fec_free_descs(struct fec_priv *fec)
995 for (i = 0; i < FEC_RBD_NUM; i++) {
996 addr = fec->rbd_base[i].data_pointer;
1000 free(fec->tbd_base);
1003 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1005 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1006 struct mii_dev *bus;
1011 printf("mdio_alloc failed\n");
1014 bus->read = fec_phy_read;
1015 bus->write = fec_phy_write;
1017 fec_set_dev_name(bus->name, dev_id);
1019 ret = mdio_register(bus);
1021 printf("mdio_register failed\n");
1025 fec_mii_setspeed(eth);
1029 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1031 struct fec_priv *priv = dev_get_priv(dev);
1032 struct eth_pdata *pdata = dev_get_plat(dev);
1034 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1037 static int fecmxc_set_promisc(struct udevice *dev, bool enable)
1039 struct fec_priv *priv = dev_get_priv(dev);
1041 priv->promisc = enable;
1046 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1054 static const struct eth_ops fecmxc_ops = {
1055 .start = fecmxc_init,
1056 .send = fecmxc_send,
1057 .recv = fecmxc_recv,
1058 .free_pkt = fecmxc_free_pkt,
1059 .stop = fecmxc_halt,
1060 .write_hwaddr = fecmxc_set_hwaddr,
1061 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1062 .set_promisc = fecmxc_set_promisc,
1065 static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
1067 struct ofnode_phandle_args phandle_args;
1070 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1073 priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
1075 if (ofnode_valid(priv->phy_of_node))
1077 debug("Failed to find phy-handle (err = %d)\n", ret);
1081 if (!ofnode_is_available(phandle_args.node))
1084 priv->phy_of_node = phandle_args.node;
1085 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1090 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1092 struct phy_device *phydev;
1095 addr = device_get_phy_addr(priv, dev);
1096 #ifdef CONFIG_FEC_MXC_PHYADDR
1097 addr = CONFIG_FEC_MXC_PHYADDR;
1100 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1104 priv->phydev = phydev;
1105 priv->phydev->node = priv->phy_of_node;
1111 #if CONFIG_IS_ENABLED(DM_GPIO)
1112 /* FEC GPIO reset */
1113 static void fec_gpio_reset(struct fec_priv *priv)
1115 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1116 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1117 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1118 mdelay(priv->reset_delay);
1119 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1120 if (priv->reset_post_delay)
1121 mdelay(priv->reset_post_delay);
1126 static int fecmxc_probe(struct udevice *dev)
1128 bool dm_mii_bus = true;
1129 struct eth_pdata *pdata = dev_get_plat(dev);
1130 struct fec_priv *priv = dev_get_priv(dev);
1131 struct mii_dev *bus = NULL;
1135 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1136 if (enet_fused((ulong)priv->eth)) {
1137 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1142 if (IS_ENABLED(CONFIG_IMX8)) {
1143 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1145 debug("Can't get FEC ipg clk: %d\n", ret);
1148 ret = clk_enable(&priv->ipg_clk);
1150 debug("Can't enable FEC ipg clk: %d\n", ret);
1154 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1155 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1156 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1158 debug("Can't get FEC ipg clk: %d\n", ret);
1161 ret = clk_enable(&priv->ipg_clk);
1165 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1167 debug("Can't get FEC ahb clk: %d\n", ret);
1170 ret = clk_enable(&priv->ahb_clk);
1174 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1176 ret = clk_enable(&priv->clk_enet_out);
1181 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1183 ret = clk_enable(&priv->clk_ref);
1188 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1190 ret = clk_enable(&priv->clk_ptp);
1195 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1198 ret = fec_alloc_descs(priv);
1202 #ifdef CONFIG_DM_REGULATOR
1203 if (priv->phy_supply) {
1204 ret = regulator_set_enable(priv->phy_supply, true);
1206 printf("%s: Error enabling phy supply\n", dev->name);
1212 #if CONFIG_IS_ENABLED(DM_GPIO)
1213 fec_gpio_reset(priv);
1216 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1217 &priv->eth->ecntrl);
1218 start = get_timer(0);
1219 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1220 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1221 printf("FEC MXC: Timeout resetting chip\n");
1227 fec_reg_setup(priv);
1229 priv->dev_id = dev_seq(dev);
1231 #ifdef CONFIG_DM_ETH_PHY
1232 bus = eth_phy_get_mdio_bus(dev);
1237 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1238 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
1241 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
1249 #ifdef CONFIG_DM_ETH_PHY
1250 eth_phy_set_mdio_bus(dev, bus);
1254 priv->interface = pdata->phy_interface;
1255 switch (priv->interface) {
1256 case PHY_INTERFACE_MODE_MII:
1257 priv->xcv_type = MII100;
1259 case PHY_INTERFACE_MODE_RMII:
1260 priv->xcv_type = RMII;
1262 case PHY_INTERFACE_MODE_RGMII:
1263 case PHY_INTERFACE_MODE_RGMII_ID:
1264 case PHY_INTERFACE_MODE_RGMII_RXID:
1265 case PHY_INTERFACE_MODE_RGMII_TXID:
1266 priv->xcv_type = RGMII;
1269 priv->xcv_type = MII100;
1270 printf("Unsupported interface type %d defaulting to MII100\n",
1275 ret = fec_phy_init(priv, dev);
1283 mdio_unregister(bus);
1288 fec_free_descs(priv);
1292 static int fecmxc_remove(struct udevice *dev)
1294 struct fec_priv *priv = dev_get_priv(dev);
1297 fec_free_descs(priv);
1298 mdio_unregister(priv->bus);
1299 mdio_free(priv->bus);
1301 #ifdef CONFIG_DM_REGULATOR
1302 if (priv->phy_supply)
1303 regulator_set_enable(priv->phy_supply, false);
1309 static int fecmxc_of_to_plat(struct udevice *dev)
1312 struct eth_pdata *pdata = dev_get_plat(dev);
1313 struct fec_priv *priv = dev_get_priv(dev);
1315 pdata->iobase = dev_read_addr(dev);
1316 priv->eth = (struct ethernet_regs *)pdata->iobase;
1318 pdata->phy_interface = dev_read_phy_mode(dev);
1319 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
1322 #ifdef CONFIG_DM_REGULATOR
1323 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1326 #if CONFIG_IS_ENABLED(DM_GPIO)
1327 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1328 &priv->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1330 return 0; /* property is optional, don't return error! */
1332 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1333 if (priv->reset_delay > 1000) {
1334 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1335 /* property value wrong, use default value */
1336 priv->reset_delay = 1;
1339 priv->reset_post_delay = dev_read_u32_default(dev,
1340 "phy-reset-post-delay",
1342 if (priv->reset_post_delay > 1000) {
1343 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1344 /* property value wrong, use default value */
1345 priv->reset_post_delay = 0;
1352 static const struct udevice_id fecmxc_ids[] = {
1353 { .compatible = "fsl,imx28-fec" },
1354 { .compatible = "fsl,imx6q-fec" },
1355 { .compatible = "fsl,imx6sl-fec" },
1356 { .compatible = "fsl,imx6sx-fec" },
1357 { .compatible = "fsl,imx6ul-fec" },
1358 { .compatible = "fsl,imx53-fec" },
1359 { .compatible = "fsl,imx7d-fec" },
1360 { .compatible = "fsl,mvf600-fec" },
1361 { .compatible = "fsl,imx93-fec" },
1365 U_BOOT_DRIVER(fecmxc_gem) = {
1368 .of_match = fecmxc_ids,
1369 .of_to_plat = fecmxc_of_to_plat,
1370 .probe = fecmxc_probe,
1371 .remove = fecmxc_remove,
1373 .priv_auto = sizeof(struct fec_priv),
1374 .plat_auto = sizeof(struct eth_pdata),