2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
4 * (C) Copyright 2008 Armadeus Systems nc
5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/imx-regs.h>
33 #include <asm/errno.h>
35 DECLARE_GLOBAL_DATA_PTR;
38 #error "CONFIG_MII has to be defined!"
41 #ifndef CONFIG_FEC_XCV_TYPE
42 #define CONFIG_FEC_XCV_TYPE MII100
46 * The i.MX28 operates with packets in big endian. We need to swap them before
47 * sending and after receiving.
50 #define CONFIG_FEC_MXC_SWAP_PACKET
53 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
55 /* Check various alignment issues at compile time */
56 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
57 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
60 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
61 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
62 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
68 uint8_t data[1500]; /**< actual data */
69 int length; /**< actual length */
70 int used; /**< buffer in use or not */
71 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
74 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
75 static void swap_packet(uint32_t *packet, int length)
79 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
80 packet[i] = __swab32(packet[i]);
85 * MII-interface related functions
87 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
90 uint32_t reg; /* convenient holder for the PHY register */
91 uint32_t phy; /* convenient holder for the PHY */
96 * reading from any PHY's register is done by properly
97 * programming the FEC's MII data register.
99 writel(FEC_IEVENT_MII, ð->ievent);
100 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
101 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
103 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
104 phy | reg, ð->mii_data);
107 * wait for the related interrupt
109 start = get_timer(0);
110 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
118 * clear mii interrupt bit
120 writel(FEC_IEVENT_MII, ð->ievent);
123 * it's now safe to read the PHY's register
125 val = (unsigned short)readl(ð->mii_data);
126 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
131 static void fec_mii_setspeed(struct fec_priv *fec)
134 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
135 * and do not drop the Preamble.
137 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
138 &fec->eth->mii_speed);
139 debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
142 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
143 uint8_t regAddr, uint16_t data)
145 uint32_t reg; /* convenient holder for the PHY register */
146 uint32_t phy; /* convenient holder for the PHY */
149 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
150 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
152 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
153 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
156 * wait for the MII interrupt
158 start = get_timer(0);
159 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
160 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
161 printf("Write MDIO failed...\n");
167 * clear MII interrupt bit
169 writel(FEC_IEVENT_MII, ð->ievent);
170 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr,
176 int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr)
178 return fec_mdio_read(bus->priv, phyAddr, regAddr);
181 int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
184 return fec_mdio_write(bus->priv, phyAddr, regAddr, data);
187 #ifndef CONFIG_PHYLIB
188 static int miiphy_restart_aneg(struct eth_device *dev)
191 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
192 struct fec_priv *fec = (struct fec_priv *)dev->priv;
193 struct ethernet_regs *eth = fec->bus->priv;
196 * Wake up from sleep if necessary
197 * Reset PHY, then delay 300ns
200 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
202 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
206 * Set the auto-negotiation advertisement register bits
208 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
209 LPA_100FULL | LPA_100HALF | LPA_10FULL |
210 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
211 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
212 BMCR_ANENABLE | BMCR_ANRESTART);
214 if (fec->mii_postcall)
215 ret = fec->mii_postcall(fec->phy_id);
221 static int miiphy_wait_aneg(struct eth_device *dev)
225 struct fec_priv *fec = (struct fec_priv *)dev->priv;
226 struct ethernet_regs *eth = fec->bus->priv;
229 * Wait for AN completion
231 start = get_timer(0);
233 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
234 printf("%s: Autonegotiation timeout\n", dev->name);
238 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
240 printf("%s: Autonegotiation failed. status: %d\n",
244 } while (!(status & BMSR_LSTATUS));
250 static int fec_rx_task_enable(struct fec_priv *fec)
252 writel(1 << 24, &fec->eth->r_des_active);
256 static int fec_rx_task_disable(struct fec_priv *fec)
261 static int fec_tx_task_enable(struct fec_priv *fec)
263 writel(1 << 24, &fec->eth->x_des_active);
267 static int fec_tx_task_disable(struct fec_priv *fec)
273 * Initialize receive task's buffer descriptors
274 * @param[in] fec all we know about the device yet
275 * @param[in] count receive buffer count to be allocated
276 * @param[in] dsize desired size of each receive buffer
277 * @return 0 on success
279 * For this task we need additional memory for the data buffers. And each
280 * data buffer requires some alignment. Thy must be aligned to a specific
283 static int fec_rbd_init(struct fec_priv *fec, int count, int dsize)
289 * Allocate memory for the buffers. This allocation respects the
292 size = roundup(dsize, ARCH_DMA_MINALIGN);
293 for (i = 0; i < count; i++) {
294 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
296 uint8_t *data = memalign(ARCH_DMA_MINALIGN,
299 printf("%s: error allocating rxbuf %d\n",
303 writel((uint32_t)data, &fec->rbd_base[i].data_pointer);
304 } /* needs allocation */
305 writew(FEC_RBD_EMPTY, &fec->rbd_base[i].status);
306 writew(0, &fec->rbd_base[i].data_length);
309 /* Mark the last RBD to close the ring. */
310 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[i - 1].status);
316 for (; i >= 0; i--) {
317 uint32_t data_ptr = readl(&fec->rbd_base[i].data_pointer);
318 free((void *)data_ptr);
325 * Initialize transmit task's buffer descriptors
326 * @param[in] fec all we know about the device yet
328 * Transmit buffers are created externally. We only have to init the BDs here.\n
329 * Note: There is a race condition in the hardware. When only one BD is in
330 * use it must be marked with the WRAP bit to use it for every transmitt.
331 * This bit in combination with the READY bit results into double transmit
332 * of each data buffer. It seems the state machine checks READY earlier then
333 * resetting it after the first transfer.
334 * Using two BDs solves this issue.
336 static void fec_tbd_init(struct fec_priv *fec)
338 unsigned addr = (unsigned)fec->tbd_base;
339 unsigned size = roundup(2 * sizeof(struct fec_bd),
341 writew(0x0000, &fec->tbd_base[0].status);
342 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
344 flush_dcache_range(addr, addr+size);
348 * Mark the given read buffer descriptor as free
349 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
350 * @param[in] pRbd buffer descriptor to mark free again
352 static void fec_rbd_clean(int last, struct fec_bd *pRbd)
354 unsigned short flags = FEC_RBD_EMPTY;
356 flags |= FEC_RBD_WRAP;
357 writew(flags, &pRbd->status);
358 writew(0, &pRbd->data_length);
361 static int fec_get_hwaddr(struct eth_device *dev, int dev_id,
364 imx_get_mac_from_fuse(dev_id, mac);
365 return !is_valid_ether_addr(mac);
368 static int fec_set_hwaddr(struct eth_device *dev)
370 uchar *mac = dev->enetaddr;
371 struct fec_priv *fec = (struct fec_priv *)dev->priv;
373 writel(0, &fec->eth->iaddr1);
374 writel(0, &fec->eth->iaddr2);
375 writel(0, &fec->eth->gaddr1);
376 writel(0, &fec->eth->gaddr2);
379 * Set physical address
381 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
383 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
388 static void fec_eth_phy_config(struct eth_device *dev)
391 struct fec_priv *fec = (struct fec_priv *)dev->priv;
392 struct phy_device *phydev;
394 phydev = phy_connect(fec->bus, fec->phy_id, dev,
395 PHY_INTERFACE_MODE_RGMII);
397 fec->phydev = phydev;
404 * Do initial configuration of the FEC registers
406 static void fec_reg_setup(struct fec_priv *fec)
411 * Set interrupt mask register
413 writel(0x00000000, &fec->eth->imask);
416 * Clear FEC-Lite interrupt event register(IEVENT)
418 writel(0xffffffff, &fec->eth->ievent);
422 * Set FEC-Lite receive control register(R_CNTRL):
425 /* Start with frame length = 1518, common for all modes. */
426 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
427 if (fec->xcv_type == SEVENWIRE)
428 rcntrl |= FEC_RCNTRL_FCE;
429 else if (fec->xcv_type == RGMII)
430 rcntrl |= FEC_RCNTRL_RGMII;
431 else if (fec->xcv_type == RMII)
432 rcntrl |= FEC_RCNTRL_RMII;
434 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
436 writel(rcntrl, &fec->eth->r_cntrl);
440 * Start the FEC engine
441 * @param[in] dev Our device to handle
443 static int fec_open(struct eth_device *edev)
445 struct fec_priv *fec = (struct fec_priv *)edev->priv;
450 debug("fec_open: fec_open(dev)\n");
451 /* full-duplex, heartbeat disabled */
452 writel(1 << 2, &fec->eth->x_cntrl);
455 /* Invalidate all descriptors */
456 for (i = 0; i < FEC_RBD_NUM - 1; i++)
457 fec_rbd_clean(0, &fec->rbd_base[i]);
458 fec_rbd_clean(1, &fec->rbd_base[i]);
460 /* Flush the descriptors into RAM */
461 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
463 addr = (uint32_t)fec->rbd_base;
464 flush_dcache_range(addr, addr + size);
466 #ifdef FEC_QUIRK_ENET_MAC
467 /* Enable ENET HW endian SWAP */
468 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
470 /* Enable ENET store and forward mode */
471 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
475 * Enable FEC-Lite controller
477 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
479 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
482 * setup the MII gasket for RMII mode
485 /* disable the gasket */
486 writew(0, &fec->eth->miigsk_enr);
488 /* wait for the gasket to be disabled */
489 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
492 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
493 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
495 /* re-enable the gasket */
496 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
498 /* wait until MII gasket is ready */
500 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
501 if (--max_loops <= 0) {
502 printf("WAIT for MII Gasket ready timed out\n");
510 fec_eth_phy_config(edev);
512 /* Start up the PHY */
513 int ret = phy_startup(fec->phydev);
516 printf("Could not initialize PHY %s\n",
517 fec->phydev->dev->name);
520 speed = fec->phydev->speed;
525 miiphy_wait_aneg(edev);
526 speed = miiphy_speed(edev->name, fec->phy_id);
527 miiphy_duplex(edev->name, fec->phy_id);
530 #ifdef FEC_QUIRK_ENET_MAC
532 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
533 u32 rcr = (readl(&fec->eth->r_cntrl) &
534 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
535 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
536 if (speed == _1000BASET)
537 ecr |= FEC_ECNTRL_SPEED;
538 else if (speed != _100BASET)
539 rcr |= FEC_RCNTRL_RMII_10T;
540 writel(ecr, &fec->eth->ecntrl);
541 writel(rcr, &fec->eth->r_cntrl);
544 debug("%s:Speed=%i\n", __func__, speed);
547 * Enable SmartDMA receive task
549 fec_rx_task_enable(fec);
555 static int fec_init(struct eth_device *dev, bd_t* bd)
557 struct fec_priv *fec = (struct fec_priv *)dev->priv;
558 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
562 /* Initialize MAC address */
566 * Allocate transmit descriptors, there are two in total. This
567 * allocation respects cache alignment.
569 if (!fec->tbd_base) {
570 size = roundup(2 * sizeof(struct fec_bd),
572 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
573 if (!fec->tbd_base) {
577 memset(fec->tbd_base, 0, size);
579 flush_dcache_range((unsigned)fec->tbd_base, size);
583 * Allocate receive descriptors. This allocation respects cache
586 if (!fec->rbd_base) {
587 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
589 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
590 if (!fec->rbd_base) {
594 memset(fec->rbd_base, 0, size);
596 * Initialize RxBD ring
598 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
602 flush_dcache_range((unsigned)fec->rbd_base,
603 (unsigned)fec->rbd_base + size);
608 if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
609 fec_mii_setspeed(fec);
612 * Set Opcode/Pause Duration Register
614 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
615 writel(0x2, &fec->eth->x_wmrk);
617 * Set multicast address filter
619 writel(0x00000000, &fec->eth->gaddr1);
620 writel(0x00000000, &fec->eth->gaddr2);
624 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
627 /* FIFO receive start register */
628 writel(0x520, &fec->eth->r_fstart);
630 /* size and address of each buffer */
631 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
632 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
633 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
635 #ifndef CONFIG_PHYLIB
636 if (fec->xcv_type != SEVENWIRE)
637 miiphy_restart_aneg(dev);
651 * Halt the FEC engine
652 * @param[in] dev Our device to handle
654 static void fec_halt(struct eth_device *dev)
656 struct fec_priv *fec = (struct fec_priv *)dev->priv;
657 int counter = 0xffff;
660 * issue graceful stop command to the FEC transmitter if necessary
662 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
665 debug("eth_halt: wait for stop regs\n");
667 * wait for graceful stop to register
669 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
673 * Disable SmartDMA tasks
675 fec_tx_task_disable(fec);
676 fec_rx_task_disable(fec);
679 * Disable the Ethernet Controller
680 * Note: this will also reset the BD index counter!
682 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
686 debug("eth_halt: done\n");
691 * @param[in] dev Our ethernet device to handle
692 * @param[in] packet Pointer to the data to be transmitted
693 * @param[in] length Data count in bytes
694 * @return 0 on success
696 static int fec_send(struct eth_device *dev, void *packet, int length)
703 * This routine transmits one frame. This routine only accepts
704 * 6-byte Ethernet addresses.
706 struct fec_priv *fec = (struct fec_priv *)dev->priv;
709 * Check for valid length of data.
711 if ((length > 1500) || (length <= 0)) {
712 printf("Payload (%d) too large\n", length);
717 * Setup the transmit buffer. We are always using the first buffer for
718 * transmission, the second will be empty and only used to stop the DMA
719 * engine. We also flush the packet to RAM here to avoid cache trouble.
721 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
722 swap_packet((uint32_t *)packet, length);
725 addr = (uint32_t)packet;
726 size = roundup(length, ARCH_DMA_MINALIGN);
727 flush_dcache_range(addr, addr + size);
729 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
730 writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer);
733 * update BD's status now
735 * - is always the last in a chain (means no chain)
736 * - should transmitt the CRC
737 * - might be the last BD in the list, so the address counter should
738 * wrap (-> keep the WRAP flag)
740 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
741 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
742 writew(status, &fec->tbd_base[fec->tbd_index].status);
745 * Flush data cache. This code flushes both TX descriptors to RAM.
746 * After this code, the descriptors will be safely in RAM and we
749 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
750 addr = (uint32_t)fec->tbd_base;
751 flush_dcache_range(addr, addr + size);
754 * Enable SmartDMA transmit task
756 fec_tx_task_enable(fec);
759 * Wait until frame is sent. On each turn of the wait cycle, we must
760 * invalidate data cache to see what's really in RAM. Also, we need
763 invalidate_dcache_range(addr, addr + size);
764 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
766 invalidate_dcache_range(addr, addr + size);
769 debug("fec_send: status 0x%x index %d\n",
770 readw(&fec->tbd_base[fec->tbd_index].status),
772 /* for next transmission use the other buffer */
782 * Pull one frame from the card
783 * @param[in] dev Our ethernet device to handle
784 * @return Length of packet read
786 static int fec_recv(struct eth_device *dev)
788 struct fec_priv *fec = (struct fec_priv *)dev->priv;
789 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
790 unsigned long ievent;
791 int frame_length, len = 0;
796 uchar buff[FEC_MAX_PKT_SIZE];
799 * Check if any critical events have happened
801 ievent = readl(&fec->eth->ievent);
802 writel(ievent, &fec->eth->ievent);
803 debug("fec_recv: ievent 0x%lx\n", ievent);
804 if (ievent & FEC_IEVENT_BABR) {
806 fec_init(dev, fec->bd);
807 printf("some error: 0x%08lx\n", ievent);
810 if (ievent & FEC_IEVENT_HBERR) {
811 /* Heartbeat error */
812 writel(0x00000001 | readl(&fec->eth->x_cntrl),
815 if (ievent & FEC_IEVENT_GRA) {
816 /* Graceful stop complete */
817 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
819 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
821 fec_init(dev, fec->bd);
826 * Read the buffer status. Before the status can be read, the data cache
827 * must be invalidated, because the data in RAM might have been changed
828 * by DMA. The descriptors are properly aligned to cachelines so there's
829 * no need to worry they'd overlap.
831 * WARNING: By invalidating the descriptor here, we also invalidate
832 * the descriptors surrounding this one. Therefore we can NOT change the
833 * contents of this descriptor nor the surrounding ones. The problem is
834 * that in order to mark the descriptor as processed, we need to change
835 * the descriptor. The solution is to mark the whole cache line when all
836 * descriptors in the cache line are processed.
838 addr = (uint32_t)rbd;
839 addr &= ~(ARCH_DMA_MINALIGN - 1);
840 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
841 invalidate_dcache_range(addr, addr + size);
843 bd_status = readw(&rbd->status);
844 debug("fec_recv: status 0x%x\n", bd_status);
846 if (!(bd_status & FEC_RBD_EMPTY)) {
847 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
848 ((readw(&rbd->data_length) - 4) > 14)) {
850 * Get buffer address and size
852 frame = (struct nbuf *)readl(&rbd->data_pointer);
853 frame_length = readw(&rbd->data_length) - 4;
855 * Invalidate data cache over the buffer
857 addr = (uint32_t)frame;
858 size = roundup(frame_length, ARCH_DMA_MINALIGN);
859 invalidate_dcache_range(addr, addr + size);
862 * Fill the buffer and pass it to upper layers
864 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
865 swap_packet((uint32_t *)frame->data, frame_length);
867 memcpy(buff, frame->data, frame_length);
868 NetReceive(buff, frame_length);
871 if (bd_status & FEC_RBD_ERR)
872 printf("error frame: 0x%08lx 0x%08x\n",
873 (ulong)rbd->data_pointer,
878 * Free the current buffer, restart the engine and move forward
879 * to the next buffer. Here we check if the whole cacheline of
880 * descriptors was already processed and if so, we mark it free
883 size = RXDESC_PER_CACHELINE - 1;
884 if ((fec->rbd_index & size) == size) {
885 i = fec->rbd_index - size;
886 addr = (uint32_t)&fec->rbd_base[i];
887 for (; i <= fec->rbd_index ; i++) {
888 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
891 flush_dcache_range(addr,
892 addr + ARCH_DMA_MINALIGN);
895 fec_rx_task_enable(fec);
896 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
898 debug("fec_recv: stop\n");
903 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
905 struct eth_device *edev;
906 struct fec_priv *fec;
908 unsigned char ethaddr[6];
912 /* create and fill edev struct */
913 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
915 puts("fec_mxc: not enough malloc memory for eth_device\n");
920 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
922 puts("fec_mxc: not enough malloc memory for fec_priv\n");
927 memset(edev, 0, sizeof(*edev));
928 memset(fec, 0, sizeof(*fec));
931 edev->init = fec_init;
932 edev->send = fec_send;
933 edev->recv = fec_recv;
934 edev->halt = fec_halt;
935 edev->write_hwaddr = fec_set_hwaddr;
937 fec->eth = (struct ethernet_regs *)base_addr;
940 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
943 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
944 start = get_timer(0);
945 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
946 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
947 printf("FEC MXC: Timeout reseting chip\n");
954 fec_mii_setspeed(fec);
957 sprintf(edev->name, "FEC");
960 sprintf(edev->name, "FEC%i", dev_id);
961 fec->dev_id = dev_id;
963 fec->phy_id = phy_id;
967 printf("mdio_alloc failed\n");
971 bus->read = fec_phy_read;
972 bus->write = fec_phy_write;
973 sprintf(bus->name, edev->name);
976 * The i.MX28 has two ethernet interfaces, but they are not equal.
977 * Only the first one can access the MDIO bus.
979 bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
981 bus->priv = fec->eth;
983 ret = mdio_register(bus);
985 printf("mdio_register failed\n");
993 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
994 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
995 memcpy(edev->enetaddr, ethaddr, 6);
998 fec_eth_phy_config(edev);
1009 #ifndef CONFIG_FEC_MXC_MULTI
1010 int fecmxc_initialize(bd_t *bd)
1014 debug("eth_init: fec_probe(bd)\n");
1015 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
1021 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1025 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1026 lout = fec_probe(bd, dev_id, phy_id, addr);
1031 #ifndef CONFIG_PHYLIB
1032 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1034 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1035 fec->mii_postcall = cb;