2 * Opencore 10/100 ethernet mac driver
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 * Thierry Reding <thierry.reding@avionic-design.de>
7 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
20 #include <asm/cache.h>
22 /* register offsets */
24 #define INT_SOURCE 0x04
29 #define PACKETLEN 0x18
31 #define TX_BD_NUM 0x20
32 #define CTRLMODER 0x24
34 #define MIICOMMAND 0x2c
35 #define MIIADDRESS 0x30
36 #define MIITX_DATA 0x34
37 #define MIIRX_DATA 0x38
38 #define MIISTATUS 0x3c
39 #define MAC_ADDR0 0x40
40 #define MAC_ADDR1 0x44
41 #define ETH_HASH0 0x48
42 #define ETH_HASH1 0x4c
43 #define ETH_TXCTRL 0x50
46 #define MODER_RXEN (1 << 0) /* receive enable */
47 #define MODER_TXEN (1 << 1) /* transmit enable */
48 #define MODER_NOPRE (1 << 2) /* no preamble */
49 #define MODER_BRO (1 << 3) /* broadcast address */
50 #define MODER_IAM (1 << 4) /* individual address mode */
51 #define MODER_PRO (1 << 5) /* promiscuous mode */
52 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
53 #define MODER_LOOP (1 << 7) /* loopback */
54 #define MODER_NBO (1 << 8) /* no back-off */
55 #define MODER_EDE (1 << 9) /* excess defer enable */
56 #define MODER_FULLD (1 << 10) /* full duplex */
57 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
58 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
59 #define MODER_CRC (1 << 13) /* CRC enable */
60 #define MODER_HUGE (1 << 14) /* huge packets enable */
61 #define MODER_PAD (1 << 15) /* padding enabled */
62 #define MODER_RSM (1 << 16) /* receive small packets */
64 /* interrupt source and mask registers */
65 #define INT_MASK_TXF (1 << 0) /* transmit frame */
66 #define INT_MASK_TXE (1 << 1) /* transmit error */
67 #define INT_MASK_RXF (1 << 2) /* receive frame */
68 #define INT_MASK_RXE (1 << 3) /* receive error */
69 #define INT_MASK_BUSY (1 << 4)
70 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
71 #define INT_MASK_RXC (1 << 6) /* receive control frame */
73 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
74 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
76 #define INT_MASK_ALL ( \
77 INT_MASK_TXF | INT_MASK_TXE | \
78 INT_MASK_RXF | INT_MASK_RXE | \
79 INT_MASK_TXC | INT_MASK_RXC | \
83 /* packet length register */
84 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
85 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
86 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
89 /* transmit buffer number register */
90 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
92 /* control module mode register */
93 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
94 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
95 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
97 /* MII mode register */
98 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
99 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
101 /* MII command register */
102 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
103 #define MIICOMMAND_READ (1 << 1) /* read status */
104 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
106 /* MII address register */
107 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
108 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
109 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
110 MIIADDRESS_RGAD(reg))
112 /* MII transmit data register */
113 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
115 /* MII receive data register */
116 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
118 /* MII status register */
119 #define MIISTATUS_LINKFAIL (1 << 0)
120 #define MIISTATUS_BUSY (1 << 1)
121 #define MIISTATUS_INVALID (1 << 2)
123 /* TX buffer descriptor */
124 #define TX_BD_CS (1 << 0) /* carrier sense lost */
125 #define TX_BD_DF (1 << 1) /* defer indication */
126 #define TX_BD_LC (1 << 2) /* late collision */
127 #define TX_BD_RL (1 << 3) /* retransmission limit */
128 #define TX_BD_RETRY_MASK (0x00f0)
129 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
130 #define TX_BD_UR (1 << 8) /* transmitter underrun */
131 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
132 #define TX_BD_PAD (1 << 12) /* pad enable */
133 #define TX_BD_WRAP (1 << 13)
134 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
135 #define TX_BD_READY (1 << 15) /* TX buffer ready */
136 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
137 #define TX_BD_LEN_MASK (0xffff << 16)
139 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
140 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
142 /* RX buffer descriptor */
143 #define RX_BD_LC (1 << 0) /* late collision */
144 #define RX_BD_CRC (1 << 1) /* RX CRC error */
145 #define RX_BD_SF (1 << 2) /* short frame */
146 #define RX_BD_TL (1 << 3) /* too long */
147 #define RX_BD_DN (1 << 4) /* dribble nibble */
148 #define RX_BD_IS (1 << 5) /* invalid symbol */
149 #define RX_BD_OR (1 << 6) /* receiver overrun */
150 #define RX_BD_MISS (1 << 7)
151 #define RX_BD_CF (1 << 8) /* control frame */
152 #define RX_BD_WRAP (1 << 13)
153 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
154 #define RX_BD_EMPTY (1 << 15)
155 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
157 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
158 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
160 #define ETHOC_BUFSIZ 1536
161 #define ETHOC_ZLEN 64
162 #define ETHOC_BD_BASE 0x400
163 #define ETHOC_TIMEOUT (HZ / 2)
164 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
167 * struct ethoc - driver-private device structure
168 * @num_tx: number of send buffers
169 * @cur_tx: last send buffer written
170 * @dty_tx: last buffer actually sent
171 * @num_rx: number of receive buffers
172 * @cur_rx: current receive buffer
183 * struct ethoc_bd - buffer descriptor
184 * @stat: buffer statistics
185 * @addr: physical memory address
192 static inline u32 ethoc_read(struct eth_device *dev, loff_t offset)
194 return readl(dev->iobase + offset);
197 static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data)
199 writel(data, dev->iobase + offset);
202 static inline void ethoc_read_bd(struct eth_device *dev, int index,
205 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
206 bd->stat = ethoc_read(dev, offset + 0);
207 bd->addr = ethoc_read(dev, offset + 4);
210 static inline void ethoc_write_bd(struct eth_device *dev, int index,
211 const struct ethoc_bd *bd)
213 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
214 ethoc_write(dev, offset + 0, bd->stat);
215 ethoc_write(dev, offset + 4, bd->addr);
218 static inline void ethoc_set_mac_address(struct eth_device *dev)
220 u8 *mac = dev->enetaddr;
222 ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
223 (mac[4] << 8) | (mac[5] << 0));
224 ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
227 static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
229 ethoc_write(dev, INT_SOURCE, mask);
232 static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
234 u32 mode = ethoc_read(dev, MODER);
235 mode |= MODER_RXEN | MODER_TXEN;
236 ethoc_write(dev, MODER, mode);
239 static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
241 u32 mode = ethoc_read(dev, MODER);
242 mode &= ~(MODER_RXEN | MODER_TXEN);
243 ethoc_write(dev, MODER, mode);
246 static int ethoc_init_ring(struct eth_device *dev)
248 struct ethoc *priv = (struct ethoc *)dev->priv;
256 /* setup transmission buffers */
257 bd.stat = TX_BD_IRQ | TX_BD_CRC;
259 for (i = 0; i < priv->num_tx; i++) {
260 if (i == priv->num_tx - 1)
261 bd.stat |= TX_BD_WRAP;
263 ethoc_write_bd(dev, i, &bd);
266 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
268 for (i = 0; i < priv->num_rx; i++) {
269 bd.addr = (u32)NetRxPackets[i];
270 if (i == priv->num_rx - 1)
271 bd.stat |= RX_BD_WRAP;
273 flush_dcache(bd.addr, PKTSIZE_ALIGN);
274 ethoc_write_bd(dev, priv->num_tx + i, &bd);
280 static int ethoc_reset(struct eth_device *dev)
284 /* TODO: reset controller? */
286 ethoc_disable_rx_and_tx(dev);
288 /* TODO: setup registers */
290 /* enable FCS generation and automatic padding */
291 mode = ethoc_read(dev, MODER);
292 mode |= MODER_CRC | MODER_PAD;
293 ethoc_write(dev, MODER, mode);
295 /* set full-duplex mode */
296 mode = ethoc_read(dev, MODER);
298 ethoc_write(dev, MODER, mode);
299 ethoc_write(dev, IPGT, 0x15);
301 ethoc_ack_irq(dev, INT_MASK_ALL);
302 ethoc_enable_rx_and_tx(dev);
306 static int ethoc_init(struct eth_device *dev, bd_t * bd)
308 struct ethoc *priv = (struct ethoc *)dev->priv;
311 ethoc_set_mac_address(dev);
314 priv->num_rx = PKTBUFSRX;
315 ethoc_write(dev, TX_BD_NUM, priv->num_tx);
316 ethoc_init_ring(dev);
322 static int ethoc_update_rx_stats(struct ethoc_bd *bd)
326 if (bd->stat & RX_BD_TL) {
327 debug("ETHOC: " "RX: frame too long\n");
331 if (bd->stat & RX_BD_SF) {
332 debug("ETHOC: " "RX: frame too short\n");
336 if (bd->stat & RX_BD_DN)
337 debug("ETHOC: " "RX: dribble nibble\n");
339 if (bd->stat & RX_BD_CRC) {
340 debug("ETHOC: " "RX: wrong CRC\n");
344 if (bd->stat & RX_BD_OR) {
345 debug("ETHOC: " "RX: overrun\n");
349 if (bd->stat & RX_BD_LC) {
350 debug("ETHOC: " "RX: late collision\n");
357 static int ethoc_rx(struct eth_device *dev, int limit)
359 struct ethoc *priv = (struct ethoc *)dev->priv;
362 for (count = 0; count < limit; ++count) {
366 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
367 ethoc_read_bd(dev, entry, &bd);
368 if (bd.stat & RX_BD_EMPTY)
371 debug("%s(): RX buffer %d, %x received\n",
372 __func__, priv->cur_rx, bd.stat);
373 if (ethoc_update_rx_stats(&bd) == 0) {
374 int size = bd.stat >> 16;
375 size -= 4; /* strip the CRC */
376 NetReceive((void *)bd.addr, size);
379 /* clear the buffer descriptor so it can be reused */
380 flush_dcache(bd.addr, PKTSIZE_ALIGN);
381 bd.stat &= ~RX_BD_STATS;
382 bd.stat |= RX_BD_EMPTY;
383 ethoc_write_bd(dev, entry, &bd);
390 static int ethoc_update_tx_stats(struct ethoc_bd *bd)
392 if (bd->stat & TX_BD_LC)
393 debug("ETHOC: " "TX: late collision\n");
395 if (bd->stat & TX_BD_RL)
396 debug("ETHOC: " "TX: retransmit limit\n");
398 if (bd->stat & TX_BD_UR)
399 debug("ETHOC: " "TX: underrun\n");
401 if (bd->stat & TX_BD_CS)
402 debug("ETHOC: " "TX: carrier sense lost\n");
407 static void ethoc_tx(struct eth_device *dev)
409 struct ethoc *priv = (struct ethoc *)dev->priv;
410 u32 entry = priv->dty_tx % priv->num_tx;
413 ethoc_read_bd(dev, entry, &bd);
414 if ((bd.stat & TX_BD_READY) == 0)
415 (void)ethoc_update_tx_stats(&bd);
418 static int ethoc_send(struct eth_device *dev, volatile void *packet, int length)
420 struct ethoc *priv = (struct ethoc *)dev->priv;
426 entry = priv->cur_tx % priv->num_tx;
427 ethoc_read_bd(dev, entry, &bd);
428 if (unlikely(length < ETHOC_ZLEN))
429 bd.stat |= TX_BD_PAD;
431 bd.stat &= ~TX_BD_PAD;
432 bd.addr = (u32)packet;
434 flush_dcache(bd.addr, length);
435 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
436 bd.stat |= TX_BD_LEN(length);
437 ethoc_write_bd(dev, entry, &bd);
440 bd.stat |= TX_BD_READY;
441 ethoc_write_bd(dev, entry, &bd);
443 /* wait for transfer to succeed */
444 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
446 pending = ethoc_read(dev, INT_SOURCE);
447 ethoc_ack_irq(dev, pending & ~INT_MASK_RX);
448 if (pending & INT_MASK_BUSY)
449 debug("%s(): packet dropped\n", __func__);
451 if (pending & INT_MASK_TX) {
455 if (get_timer(0) >= tmo) {
456 debug("%s(): timed out\n", __func__);
461 debug("%s(): packet sent\n", __func__);
465 static void ethoc_halt(struct eth_device *dev)
467 ethoc_disable_rx_and_tx(dev);
470 static int ethoc_recv(struct eth_device *dev)
474 pending = ethoc_read(dev, INT_SOURCE);
475 ethoc_ack_irq(dev, pending);
476 if (pending & INT_MASK_BUSY)
477 debug("%s(): packet dropped\n", __func__);
478 if (pending & INT_MASK_RX) {
479 debug("%s(): rx irq\n", __func__);
480 ethoc_rx(dev, PKTBUFSRX);
486 int ethoc_initialize(u8 dev_num, int base_addr)
489 struct eth_device *dev;
491 priv = malloc(sizeof(*priv));
494 dev = malloc(sizeof(*dev));
500 memset(dev, 0, sizeof(*dev));
502 dev->iobase = base_addr;
503 dev->init = ethoc_init;
504 dev->halt = ethoc_halt;
505 dev->send = ethoc_send;
506 dev->recv = ethoc_recv;
507 sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);