1 // SPDX-License-Identifier: GPL-2.0
3 * SGMI module initialisation
5 * Copyright (C) 2014 Texas Instruments Incorporated
6 * Authors: Sandeep Nair <sandeep_n@ti.com>
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
14 #define SGMII_SRESET_RESET BIT(0)
15 #define SGMII_SRESET_RTRESET BIT(1)
17 #define SGMII_REG_STATUS_LOCK BIT(4)
18 #define SGMII_REG_STATUS_LINK BIT(0)
19 #define SGMII_REG_STATUS_AUTONEG BIT(2)
20 #define SGMII_REG_CONTROL_AUTONEG BIT(0)
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100)
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x)))
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004)
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010)
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014)
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018)
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val)
33 writel(val, base + reg);
36 static u32 sgmii_read_reg(void __iomem *base, int reg)
38 return readl(base + reg);
41 static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val)
43 writel((readl(base + reg) | val), base + reg);
47 int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
50 sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port),
53 while ((sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) &
54 SGMII_SRESET_RESET) != 0x0)
61 bool netcp_sgmii_rtreset(void __iomem *sgmii_ofs, int port, bool set)
66 /* Initiate a soft reset */
67 reg = sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port));
68 oldval = (reg & SGMII_SRESET_RTRESET) != 0x0;
70 reg |= SGMII_SRESET_RTRESET;
72 reg &= ~SGMII_SRESET_RTRESET;
73 sgmii_write_reg(sgmii_ofs, SGMII_SRESET_REG(port), reg);
79 int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
81 u32 status = 0, link = 0;
83 status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
84 if ((status & SGMII_REG_STATUS_LINK) != 0)
89 int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface)
91 unsigned int i, status, mask;
96 case SGMII_LINK_MAC_MAC_AUTONEG:
97 mr_adv_ability = 0x9801;
101 case SGMII_LINK_MAC_PHY:
102 case SGMII_LINK_MAC_PHY_NO_MDIO:
107 case SGMII_LINK_MAC_MAC_FORCED:
108 mr_adv_ability = 0x9801;
112 case SGMII_LINK_MAC_FIBER:
113 mr_adv_ability = 0x20;
118 WARN_ONCE(1, "Invalid sgmii interface: %d\n", interface);
122 sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), 0);
124 /* Wait for the SerDes pll to lock */
125 for (i = 0; i < 1000; i++) {
126 usleep_range(1000, 2000);
127 status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
128 if ((status & SGMII_REG_STATUS_LOCK) != 0)
132 if ((status & SGMII_REG_STATUS_LOCK) == 0)
133 pr_err("serdes PLL not locked\n");
135 sgmii_write_reg(sgmii_ofs, SGMII_MRADV_REG(port), mr_adv_ability);
136 sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control);
138 mask = SGMII_REG_STATUS_LINK;
139 if (control & SGMII_REG_CONTROL_AUTONEG)
140 mask |= SGMII_REG_STATUS_AUTONEG;
142 for (i = 0; i < 1000; i++) {
143 usleep_range(200, 500);
144 status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
145 if ((status & mask) == mask)