1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
5 * Copyright (C) 2012 Texas Instruments
8 #include <linux/bitmap.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
17 #include <linux/stat.h>
18 #include <linux/sysfs.h>
19 #include <linux/etherdevice.h>
23 #define BITMASK(bits) (BIT(bits) - 1)
25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask))
26 #define ALE_VERSION_MINOR(rev) (rev & 0xff)
27 #define ALE_VERSION_1R3 0x0103
28 #define ALE_VERSION_1R4 0x0104
31 #define ALE_IDVER 0x00
32 #define ALE_STATUS 0x04
33 #define ALE_CONTROL 0x08
34 #define ALE_PRESCALE 0x10
35 #define ALE_UNKNOWNVLAN 0x18
36 #define ALE_TABLE_CONTROL 0x20
37 #define ALE_TABLE 0x34
38 #define ALE_PORTCTL 0x40
40 /* ALE NetCP NU switch specific Registers */
41 #define ALE_UNKNOWNVLAN_MEMBER 0x90
42 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94
43 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98
44 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C
45 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg)))
47 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134
49 #define ALE_TABLE_WRITE BIT(31)
51 #define ALE_TYPE_FREE 0
52 #define ALE_TYPE_ADDR 1
53 #define ALE_TYPE_VLAN 2
54 #define ALE_TYPE_VLAN_ADDR 3
56 #define ALE_UCAST_PERSISTANT 0
57 #define ALE_UCAST_UNTOUCHED 1
58 #define ALE_UCAST_OUI 2
59 #define ALE_UCAST_TOUCHED 3
61 #define ALE_TABLE_SIZE_MULTIPLIER 1024
62 #define ALE_STATUS_SIZE_MASK 0x1f
63 #define ALE_TABLE_SIZE_DEFAULT 64
65 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
71 idx = 2 - idx; /* flip */
72 return (ale_entry[idx] >> start) & BITMASK(bits);
75 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
80 value &= BITMASK(bits);
83 idx = 2 - idx; /* flip */
84 ale_entry[idx] &= ~(BITMASK(bits) << start);
85 ale_entry[idx] |= (value << start);
88 #define DEFINE_ALE_FIELD(name, start, bits) \
89 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
91 return cpsw_ale_get_field(ale_entry, start, bits); \
93 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
95 cpsw_ale_set_field(ale_entry, start, bits, value); \
98 #define DEFINE_ALE_FIELD1(name, start) \
99 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \
101 return cpsw_ale_get_field(ale_entry, start, bits); \
103 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \
106 cpsw_ale_set_field(ale_entry, start, bits, value); \
109 DEFINE_ALE_FIELD(entry_type, 60, 2)
110 DEFINE_ALE_FIELD(vlan_id, 48, 12)
111 DEFINE_ALE_FIELD(mcast_state, 62, 2)
112 DEFINE_ALE_FIELD1(port_mask, 66)
113 DEFINE_ALE_FIELD(super, 65, 1)
114 DEFINE_ALE_FIELD(ucast_type, 62, 2)
115 DEFINE_ALE_FIELD1(port_num, 66)
116 DEFINE_ALE_FIELD(blocked, 65, 1)
117 DEFINE_ALE_FIELD(secure, 64, 1)
118 DEFINE_ALE_FIELD1(vlan_untag_force, 24)
119 DEFINE_ALE_FIELD1(vlan_reg_mcast, 16)
120 DEFINE_ALE_FIELD1(vlan_unreg_mcast, 8)
121 DEFINE_ALE_FIELD1(vlan_member_list, 0)
122 DEFINE_ALE_FIELD(mcast, 40, 1)
123 /* ALE NetCP nu switch specific */
124 DEFINE_ALE_FIELD(vlan_unreg_mcast_idx, 20, 3)
125 DEFINE_ALE_FIELD(vlan_reg_mcast_idx, 44, 3)
127 #define NU_VLAN_UNREG_MCAST_IDX 1
129 /* The MAC address field in the ALE entry cannot be macroized as above */
130 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
134 for (i = 0; i < 6; i++)
135 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
138 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
142 for (i = 0; i < 6; i++)
143 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
146 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
150 WARN_ON(idx > ale->params.ale_entries);
152 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
154 for (i = 0; i < ALE_ENTRY_WORDS; i++)
155 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
161 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
165 WARN_ON(idx > ale->params.ale_entries);
167 for (i = 0; i < ALE_ENTRY_WORDS; i++)
168 writel_relaxed(ale_entry[i], ale->params.ale_regs +
171 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
177 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
179 u32 ale_entry[ALE_ENTRY_WORDS];
182 for (idx = 0; idx < ale->params.ale_entries; idx++) {
185 cpsw_ale_read(ale, idx, ale_entry);
186 type = cpsw_ale_get_entry_type(ale_entry);
187 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
189 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
191 cpsw_ale_get_addr(ale_entry, entry_addr);
192 if (ether_addr_equal(entry_addr, addr))
198 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
200 u32 ale_entry[ALE_ENTRY_WORDS];
203 for (idx = 0; idx < ale->params.ale_entries; idx++) {
204 cpsw_ale_read(ale, idx, ale_entry);
205 type = cpsw_ale_get_entry_type(ale_entry);
206 if (type != ALE_TYPE_VLAN)
208 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
214 static int cpsw_ale_match_free(struct cpsw_ale *ale)
216 u32 ale_entry[ALE_ENTRY_WORDS];
219 for (idx = 0; idx < ale->params.ale_entries; idx++) {
220 cpsw_ale_read(ale, idx, ale_entry);
221 type = cpsw_ale_get_entry_type(ale_entry);
222 if (type == ALE_TYPE_FREE)
228 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
230 u32 ale_entry[ALE_ENTRY_WORDS];
233 for (idx = 0; idx < ale->params.ale_entries; idx++) {
234 cpsw_ale_read(ale, idx, ale_entry);
235 type = cpsw_ale_get_entry_type(ale_entry);
236 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
238 if (cpsw_ale_get_mcast(ale_entry))
240 type = cpsw_ale_get_ucast_type(ale_entry);
241 if (type != ALE_UCAST_PERSISTANT &&
242 type != ALE_UCAST_OUI)
248 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
253 mask = cpsw_ale_get_port_mask(ale_entry,
254 ale->port_mask_bits);
255 if ((mask & port_mask) == 0)
256 return; /* ports dont intersect, not interested */
259 /* free if only remaining port is host port */
261 cpsw_ale_set_port_mask(ale_entry, mask,
262 ale->port_mask_bits);
264 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
267 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
269 u32 ale_entry[ALE_ENTRY_WORDS];
272 for (idx = 0; idx < ale->params.ale_entries; idx++) {
273 cpsw_ale_read(ale, idx, ale_entry);
274 ret = cpsw_ale_get_entry_type(ale_entry);
275 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
278 /* if vid passed is -1 then remove all multicast entry from
279 * the table irrespective of vlan id, if a valid vlan id is
280 * passed then remove only multicast added to that vlan id.
281 * if vlan id doesn't match then move on to next entry.
283 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
286 if (cpsw_ale_get_mcast(ale_entry)) {
289 if (cpsw_ale_get_super(ale_entry))
292 cpsw_ale_get_addr(ale_entry, addr);
293 if (!is_broadcast_ether_addr(addr))
294 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
297 cpsw_ale_write(ale, idx, ale_entry);
302 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
305 if (flags & ALE_VLAN) {
306 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
307 cpsw_ale_set_vlan_id(ale_entry, vid);
309 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
313 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
316 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
319 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
321 cpsw_ale_set_addr(ale_entry, addr);
322 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
323 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
324 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
325 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
327 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
329 idx = cpsw_ale_match_free(ale);
331 idx = cpsw_ale_find_ageable(ale);
335 cpsw_ale_write(ale, idx, ale_entry);
339 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
342 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
345 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
349 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
350 cpsw_ale_write(ale, idx, ale_entry);
354 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
355 int flags, u16 vid, int mcast_state)
357 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
360 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
362 cpsw_ale_read(ale, idx, ale_entry);
364 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
366 cpsw_ale_set_addr(ale_entry, addr);
367 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
368 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
370 mask = cpsw_ale_get_port_mask(ale_entry,
371 ale->port_mask_bits);
373 cpsw_ale_set_port_mask(ale_entry, port_mask,
374 ale->port_mask_bits);
377 idx = cpsw_ale_match_free(ale);
379 idx = cpsw_ale_find_ageable(ale);
383 cpsw_ale_write(ale, idx, ale_entry);
387 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
390 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
391 int mcast_members = 0;
394 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
398 cpsw_ale_read(ale, idx, ale_entry);
401 mcast_members = cpsw_ale_get_port_mask(ale_entry,
402 ale->port_mask_bits);
403 mcast_members &= ~port_mask;
407 cpsw_ale_set_port_mask(ale_entry, mcast_members,
408 ale->port_mask_bits);
410 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
412 cpsw_ale_write(ale, idx, ale_entry);
416 /* ALE NetCP NU switch specific vlan functions */
417 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
418 int reg_mcast, int unreg_mcast)
422 /* Set VLAN registered multicast flood mask */
423 idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry);
424 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
426 /* Set VLAN unregistered multicast flood mask */
427 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry);
428 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
431 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
432 u16 vid, int untag_mask)
434 cpsw_ale_set_vlan_untag_force(ale_entry,
435 untag_mask, ale->vlan_field_bits);
436 if (untag_mask & ALE_PORT_HOST)
437 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
439 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
442 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
443 int reg_mcast, int unreg_mcast)
445 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
448 idx = cpsw_ale_match_vlan(ale, vid);
450 cpsw_ale_read(ale, idx, ale_entry);
452 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
453 cpsw_ale_set_vlan_id(ale_entry, vid);
454 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
456 if (!ale->params.nu_switch_ale) {
457 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
458 ale->vlan_field_bits);
459 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
460 ale->vlan_field_bits);
462 cpsw_ale_set_vlan_unreg_mcast_idx(ale_entry,
463 NU_VLAN_UNREG_MCAST_IDX);
464 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
466 cpsw_ale_set_vlan_member_list(ale_entry, port_mask,
467 ale->vlan_field_bits);
470 idx = cpsw_ale_match_free(ale);
472 idx = cpsw_ale_find_ageable(ale);
476 cpsw_ale_write(ale, idx, ale_entry);
480 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry,
481 u16 vid, int port_mask)
483 int reg_mcast, unreg_mcast;
486 members = cpsw_ale_get_vlan_member_list(ale_entry,
487 ale->vlan_field_bits);
488 members &= ~port_mask;
490 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
494 untag = cpsw_ale_get_vlan_untag_force(ale_entry,
495 ale->vlan_field_bits);
496 reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry,
497 ale->vlan_field_bits);
498 unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry,
499 ale->vlan_field_bits);
501 reg_mcast &= members;
502 unreg_mcast &= members;
504 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
506 if (!ale->params.nu_switch_ale) {
507 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
508 ale->vlan_field_bits);
509 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
510 ale->vlan_field_bits);
512 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
515 cpsw_ale_set_vlan_member_list(ale_entry, members,
516 ale->vlan_field_bits);
519 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
521 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
524 idx = cpsw_ale_match_vlan(ale, vid);
528 cpsw_ale_read(ale, idx, ale_entry);
531 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask);
533 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
534 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
537 cpsw_ale_write(ale, idx, ale_entry);
542 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
543 int untag_mask, int reg_mask, int unreg_mask)
545 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
546 int reg_mcast_members, unreg_mcast_members;
547 int vlan_members, untag_members;
550 idx = cpsw_ale_match_vlan(ale, vid);
552 cpsw_ale_read(ale, idx, ale_entry);
554 vlan_members = cpsw_ale_get_vlan_member_list(ale_entry,
555 ale->vlan_field_bits);
556 reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry,
557 ale->vlan_field_bits);
558 unreg_mcast_members =
559 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
560 ale->vlan_field_bits);
561 untag_members = cpsw_ale_get_vlan_untag_force(ale_entry,
562 ale->vlan_field_bits);
564 vlan_members |= port_mask;
565 untag_members = (untag_members & ~port_mask) | untag_mask;
566 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
567 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
569 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
570 reg_mcast_members, unreg_mcast_members);
572 dev_err(ale->params.dev, "Unable to add vlan\n");
575 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
581 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
584 u32 ale_entry[ALE_ENTRY_WORDS];
585 int unreg_members = 0;
588 for (idx = 0; idx < ale->params.ale_entries; idx++) {
589 cpsw_ale_read(ale, idx, ale_entry);
590 type = cpsw_ale_get_entry_type(ale_entry);
591 if (type != ALE_TYPE_VLAN)
595 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
596 ale->vlan_field_bits);
598 unreg_members |= unreg_mcast_mask;
600 unreg_members &= ~unreg_mcast_mask;
601 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members,
602 ale->vlan_field_bits);
603 cpsw_ale_write(ale, idx, ale_entry);
607 static void cpsw_ale_vlan_set_unreg_mcast(struct cpsw_ale *ale, u32 *ale_entry,
613 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
614 ale->vlan_field_bits);
616 unreg_mcast |= ALE_PORT_HOST;
618 unreg_mcast &= ~ALE_PORT_HOST;
619 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
620 ale->vlan_field_bits);
624 cpsw_ale_vlan_set_unreg_mcast_idx(struct cpsw_ale *ale, u32 *ale_entry,
630 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry);
632 unreg_mcast = readl(ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
635 unreg_mcast |= ALE_PORT_HOST;
637 unreg_mcast &= ~ALE_PORT_HOST;
639 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
642 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
644 u32 ale_entry[ALE_ENTRY_WORDS];
647 for (idx = 0; idx < ale->params.ale_entries; idx++) {
650 cpsw_ale_read(ale, idx, ale_entry);
651 type = cpsw_ale_get_entry_type(ale_entry);
652 if (type != ALE_TYPE_VLAN)
655 cpsw_ale_get_vlan_member_list(ale_entry,
656 ale->vlan_field_bits);
658 if (port != -1 && !(vlan_members & BIT(port)))
661 if (!ale->params.nu_switch_ale)
662 cpsw_ale_vlan_set_unreg_mcast(ale, ale_entry, allmulti);
664 cpsw_ale_vlan_set_unreg_mcast_idx(ale, ale_entry,
667 cpsw_ale_write(ale, idx, ale_entry);
671 struct ale_control_info {
673 int offset, port_offset;
674 int shift, port_shift;
678 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
681 .offset = ALE_CONTROL,
689 .offset = ALE_CONTROL,
697 .offset = ALE_CONTROL,
703 [ALE_P0_UNI_FLOOD] = {
704 .name = "port0_unicast_flood",
705 .offset = ALE_CONTROL,
711 [ALE_VLAN_NOLEARN] = {
712 .name = "vlan_nolearn",
713 .offset = ALE_CONTROL,
719 [ALE_NO_PORT_VLAN] = {
720 .name = "no_port_vlan",
721 .offset = ALE_CONTROL,
729 .offset = ALE_CONTROL,
737 .offset = ALE_CONTROL,
743 [ALE_RATE_LIMIT_TX] = {
744 .name = "rate_limit_tx",
745 .offset = ALE_CONTROL,
752 .name = "vlan_aware",
753 .offset = ALE_CONTROL,
759 [ALE_AUTH_ENABLE] = {
760 .name = "auth_enable",
761 .offset = ALE_CONTROL,
768 .name = "rate_limit",
769 .offset = ALE_CONTROL,
776 .name = "port_state",
777 .offset = ALE_PORTCTL,
783 [ALE_PORT_DROP_UNTAGGED] = {
784 .name = "drop_untagged",
785 .offset = ALE_PORTCTL,
791 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
792 .name = "drop_unknown",
793 .offset = ALE_PORTCTL,
799 [ALE_PORT_NOLEARN] = {
801 .offset = ALE_PORTCTL,
807 [ALE_PORT_NO_SA_UPDATE] = {
808 .name = "no_source_update",
809 .offset = ALE_PORTCTL,
815 [ALE_PORT_MACONLY] = {
816 .name = "mac_only_port_mode",
817 .offset = ALE_PORTCTL,
823 [ALE_PORT_MACONLY_CAF] = {
824 .name = "mac_only_port_caf",
825 .offset = ALE_PORTCTL,
831 [ALE_PORT_MCAST_LIMIT] = {
832 .name = "mcast_limit",
833 .offset = ALE_PORTCTL,
839 [ALE_PORT_BCAST_LIMIT] = {
840 .name = "bcast_limit",
841 .offset = ALE_PORTCTL,
847 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
848 .name = "unknown_vlan_member",
849 .offset = ALE_UNKNOWNVLAN,
855 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
856 .name = "unknown_mcast_flood",
857 .offset = ALE_UNKNOWNVLAN,
863 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
864 .name = "unknown_reg_flood",
865 .offset = ALE_UNKNOWNVLAN,
871 [ALE_PORT_UNTAGGED_EGRESS] = {
872 .name = "untagged_egress",
873 .offset = ALE_UNKNOWNVLAN,
879 [ALE_DEFAULT_THREAD_ID] = {
880 .name = "default_thread_id",
881 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
887 [ALE_DEFAULT_THREAD_ENABLE] = {
888 .name = "default_thread_id_enable",
889 .offset = AM65_CPSW_ALE_THREAD_DEF_REG,
897 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
900 const struct ale_control_info *info;
904 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
907 info = &ale_controls[control];
908 if (info->port_offset == 0 && info->port_shift == 0)
909 port = 0; /* global, port is a dont care */
911 if (port < 0 || port >= ale->params.ale_ports)
914 mask = BITMASK(info->bits);
918 offset = info->offset + (port * info->port_offset);
919 shift = info->shift + (port * info->port_shift);
921 tmp = readl_relaxed(ale->params.ale_regs + offset);
922 tmp = (tmp & ~(mask << shift)) | (value << shift);
923 writel_relaxed(tmp, ale->params.ale_regs + offset);
928 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
930 const struct ale_control_info *info;
934 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
937 info = &ale_controls[control];
938 if (info->port_offset == 0 && info->port_shift == 0)
939 port = 0; /* global, port is a dont care */
941 if (port < 0 || port >= ale->params.ale_ports)
944 offset = info->offset + (port * info->port_offset);
945 shift = info->shift + (port * info->port_shift);
947 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
948 return tmp & BITMASK(info->bits);
951 static void cpsw_ale_timer(struct timer_list *t)
953 struct cpsw_ale *ale = from_timer(ale, t, timer);
955 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
958 ale->timer.expires = jiffies + ale->ageout;
959 add_timer(&ale->timer);
963 void cpsw_ale_start(struct cpsw_ale *ale)
965 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
966 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
968 timer_setup(&ale->timer, cpsw_ale_timer, 0);
970 ale->timer.expires = jiffies + ale->ageout;
971 add_timer(&ale->timer);
975 void cpsw_ale_stop(struct cpsw_ale *ale)
977 del_timer_sync(&ale->timer);
978 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
979 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
982 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
984 struct cpsw_ale *ale;
985 u32 rev, ale_entries;
987 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
989 return ERR_PTR(-ENOMEM);
991 ale->p0_untag_vid_mask =
992 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID),
993 sizeof(unsigned long),
995 if (!ale->p0_untag_vid_mask)
996 return ERR_PTR(-ENOMEM);
998 ale->params = *params;
999 ale->ageout = ale->params.ale_ageout * HZ;
1001 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER);
1002 if (!ale->params.major_ver_mask)
1003 ale->params.major_ver_mask = 0xff;
1005 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) |
1006 ALE_VERSION_MINOR(rev);
1007 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
1008 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask),
1009 ALE_VERSION_MINOR(rev));
1011 if (!ale->params.ale_entries) {
1013 readl_relaxed(ale->params.ale_regs + ALE_STATUS) &
1014 ALE_STATUS_SIZE_MASK;
1015 /* ALE available on newer NetCP switches has introduced
1016 * a register, ALE_STATUS, to indicate the size of ALE
1017 * table which shows the size as a multiple of 1024 entries.
1018 * For these, params.ale_entries will be set to zero. So
1019 * read the register and update the value of ale_entries.
1020 * ALE table on NetCP lite, is much smaller and is indicated
1021 * by a value of zero in ALE_STATUS. So use a default value
1022 * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected
1023 * to set the value of ale_entries for all other versions
1027 ale_entries = ALE_TABLE_SIZE_DEFAULT;
1029 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
1030 ale->params.ale_entries = ale_entries;
1032 dev_info(ale->params.dev,
1033 "ALE Table size %ld\n", ale->params.ale_entries);
1035 /* set default bits for existing h/w */
1036 ale->port_mask_bits = ale->params.ale_ports;
1037 ale->port_num_bits = order_base_2(ale->params.ale_ports);
1038 ale->vlan_field_bits = ale->params.ale_ports;
1040 /* Set defaults override for ALE on NetCP NU switch and for version
1043 if (ale->params.nu_switch_ale) {
1044 /* Separate registers for unknown vlan configuration.
1045 * Also there are N bits, where N is number of ale
1046 * ports and shift value should be 0
1048 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
1049 ale->params.ale_ports;
1050 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
1051 ALE_UNKNOWNVLAN_MEMBER;
1052 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
1053 ale->params.ale_ports;
1054 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
1055 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
1056 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
1057 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
1058 ale->params.ale_ports;
1059 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
1060 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
1061 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
1062 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
1063 ale->params.ale_ports;
1064 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
1065 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
1066 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
1069 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1073 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1077 for (i = 0; i < ale->params.ale_entries; i++) {
1078 cpsw_ale_read(ale, i, data);
1079 data += ALE_ENTRY_WORDS;