drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(priv)                          \
 144                 ((priv->data.dual_emac) ? priv->emac_port :     \
 145                 priv->data.active_slave)
 146
 147 static int debug_level;
 148 module_param(debug_level, int, 0);
 149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 150
 151 static int ale_ageout = 10;
 152 module_param(ale_ageout, int, 0);
 153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 154
 155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 156 module_param(rx_packet_max, int, 0);
 157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 158
 159 struct cpsw_wr_regs {
 160         u32     id_ver;
 161         u32     soft_reset;
 162         u32     control;
 163         u32     int_control;
 164         u32     rx_thresh_en;
 165         u32     rx_en;
 166         u32     tx_en;
 167         u32     misc_en;
 168         u32     mem_allign1[8];
 169         u32     rx_thresh_stat;
 170         u32     rx_stat;
 171         u32     tx_stat;
 172         u32     misc_stat;
 173         u32     mem_allign2[8];
 174         u32     rx_imax;
 175         u32     tx_imax;
 176
 177 };
 178
 179 struct cpsw_ss_regs {
 180         u32     id_ver;
 181         u32     control;
 182         u32     soft_reset;
 183         u32     stat_port_en;
 184         u32     ptype;
 185         u32     soft_idle;
 186         u32     thru_rate;
 187         u32     gap_thresh;
 188         u32     tx_start_wds;
 189         u32     flow_control;
 190         u32     vlan_ltype;
 191         u32     ts_ltype;
 192         u32     dlr_ltype;
 193 };
 194
 195 /* CPSW_PORT_V1 */
 196 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 197 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 198 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 199 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 200 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 201 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 202 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 203 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 204
 205 /* CPSW_PORT_V2 */
 206 #define CPSW2_CONTROL       0x00 /* Control Register */
 207 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 208 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 210 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 211 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 213
 214 /* CPSW_PORT_V1 and V2 */
 215 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 216 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 217 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 218
 219 /* CPSW_PORT_V2 only */
 220 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 221 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 222 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 228
 229 /* Bit definitions for the CPSW2_CONTROL register */
 230 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 231 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 232 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 233 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 234 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 235 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 236 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 237 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 238 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 239 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 240 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 241 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 242 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 243 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 244 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 245 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 246 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 247
 248 #define CTRL_V2_TS_BITS \
 249         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 250          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 251
 252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 253 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 254 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 255
 256
 257 #define CTRL_V3_TS_BITS \
 258         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 259          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 260          TS_LTYPE1_EN)
 261
 262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 263 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 264 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 265
 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 267 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 268 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 269 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 270 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 271
 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 274
 275 /* Bit definitions for the CPSW1_TS_CTL register */
 276 #define CPSW_V1_TS_RX_EN                BIT(0)
 277 #define CPSW_V1_TS_TX_EN                BIT(4)
 278 #define CPSW_V1_MSG_TYPE_OFS            16
 279
 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 282
 283 struct cpsw_host_regs {
 284         u32     max_blks;
 285         u32     blk_cnt;
 286         u32     tx_in_ctl;
 287         u32     port_vlan;
 288         u32     tx_pri_map;
 289         u32     cpdma_tx_pri_map;
 290         u32     cpdma_rx_chan_map;
 291 };
 292
 293 struct cpsw_sliver_regs {
 294         u32     id_ver;
 295         u32     mac_control;
 296         u32     mac_status;
 297         u32     soft_reset;
 298         u32     rx_maxlen;
 299         u32     __reserved_0;
 300         u32     rx_pause;
 301         u32     tx_pause;
 302         u32     __reserved_1;
 303         u32     rx_pri_map;
 304 };
 305
 306 struct cpsw_hw_stats {
 307         u32     rxgoodframes;
 308         u32     rxbroadcastframes;
 309         u32     rxmulticastframes;
 310         u32     rxpauseframes;
 311         u32     rxcrcerrors;
 312         u32     rxaligncodeerrors;
 313         u32     rxoversizedframes;
 314         u32     rxjabberframes;
 315         u32     rxundersizedframes;
 316         u32     rxfragments;
 317         u32     __pad_0[2];
 318         u32     rxoctets;
 319         u32     txgoodframes;
 320         u32     txbroadcastframes;
 321         u32     txmulticastframes;
 322         u32     txpauseframes;
 323         u32     txdeferredframes;
 324         u32     txcollisionframes;
 325         u32     txsinglecollframes;
 326         u32     txmultcollframes;
 327         u32     txexcessivecollisions;
 328         u32     txlatecollisions;
 329         u32     txunderrun;
 330         u32     txcarriersenseerrors;
 331         u32     txoctets;
 332         u32     octetframes64;
 333         u32     octetframes65t127;
 334         u32     octetframes128t255;
 335         u32     octetframes256t511;
 336         u32     octetframes512t1023;
 337         u32     octetframes1024tup;
 338         u32     netoctets;
 339         u32     rxsofoverruns;
 340         u32     rxmofoverruns;
 341         u32     rxdmaoverruns;
 342 };
 343
 344 struct cpsw_slave {
 345         void __iomem                    *regs;
 346         struct cpsw_sliver_regs __iomem *sliver;
 347         int                             slave_num;
 348         u32                             mac_control;
 349         struct cpsw_slave_data          *data;
 350         struct phy_device               *phy;
 351         struct net_device               *ndev;
 352         u32                             port_vlan;
 353         u32                             open_stat;
 354 };
 355
 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 357 {
 358         return __raw_readl(slave->regs + offset);
 359 }
 360
 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 362 {
 363         __raw_writel(val, slave->regs + offset);
 364 }
 365
 366 struct cpsw_priv {
 367         struct platform_device          *pdev;
 368         struct net_device               *ndev;
 369         struct napi_struct              napi_rx;
 370         struct napi_struct              napi_tx;
 371         struct device                   *dev;
 372         struct cpsw_platform_data       data;
 373         struct cpsw_ss_regs __iomem     *regs;
 374         struct cpsw_wr_regs __iomem     *wr_regs;
 375         u8 __iomem                      *hw_stats;
 376         struct cpsw_host_regs __iomem   *host_port_regs;
 377         u32                             msg_enable;
 378         u32                             version;
 379         u32                             coal_intvl;
 380         u32                             bus_freq_mhz;
 381         int                             rx_packet_max;
 382         struct clk                      *clk;
 383         u8                              mac_addr[ETH_ALEN];
 384         struct cpsw_slave               *slaves;
 385         struct cpdma_ctlr               *dma;
 386         struct cpdma_chan               *txch, *rxch;
 387         struct cpsw_ale                 *ale;
 388         bool                            rx_pause;
 389         bool                            tx_pause;
 390         bool                            quirk_irq;
 391         bool                            rx_irq_disabled;
 392         bool                            tx_irq_disabled;
 393         /* snapshot of IRQ numbers */
 394         u32 irqs_table[4];
 395         u32 num_irqs;
 396         struct cpts *cpts;
 397         u32 emac_port;
 398 };
 399
 400 struct cpsw_stats {
 401         char stat_string[ETH_GSTRING_LEN];
 402         int type;
 403         int sizeof_stat;
 404         int stat_offset;
 405 };
 406
 407 enum {
 408         CPSW_STATS,
 409         CPDMA_RX_STATS,
 410         CPDMA_TX_STATS,
 411 };
 412
 413 #define CPSW_STAT(m)            CPSW_STATS,                             \
 414                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 415                                 offsetof(struct cpsw_hw_stats, m)
 416 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 417                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 418                                 offsetof(struct cpdma_chan_stats, m)
 419 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 420                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 421                                 offsetof(struct cpdma_chan_stats, m)
 422
 423 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 424         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 425         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 426         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 427         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 428         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 429         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 430         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 431         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 432         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 433         { "Rx Fragments", CPSW_STAT(rxfragments) },
 434         { "Rx Octets", CPSW_STAT(rxoctets) },
 435         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 436         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 437         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 438         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 439         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 440         { "Collisions", CPSW_STAT(txcollisionframes) },
 441         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 442         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 443         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 444         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 445         { "Tx Underrun", CPSW_STAT(txunderrun) },
 446         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 447         { "Tx Octets", CPSW_STAT(txoctets) },
 448         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 449         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 450         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 451         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 452         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 453         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 454         { "Net Octets", CPSW_STAT(netoctets) },
 455         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 456         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 457         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 458         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 459         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 460         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 461         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 462         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 463         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 464         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 465         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 466         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 467         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 468         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 469         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 470         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 471         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 472         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 473         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 474         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 475         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 476         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 477         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 478         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 479         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 480         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 481         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 482         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 483         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 484 };
 485
 486 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 487
 488 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 489 #define for_each_slave(priv, func, arg...)                              \
 490         do {                                                            \
 491                 struct cpsw_slave *slave;                               \
 492                 int n;                                                  \
 493                 if (priv->data.dual_emac)                               \
 494                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 495                 else                                                    \
 496                         for (n = (priv)->data.slaves,                   \
 497                                         slave = (priv)->slaves;         \
 498                                         n; n--)                         \
 499                                 (func)(slave++, ##arg);                 \
 500         } while (0)
 501 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 502         ((__slave_no__ < priv->data.slaves) ?                           \
 503                 priv->slaves[__slave_no__].ndev : NULL)
 504 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 505         (((__slave_no__ < priv->data.slaves) &&                         \
 506                 (priv->slaves[__slave_no__].ndev)) ?                    \
 507                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 508
 509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 510         do {                                                            \
 511                 if (!priv->data.dual_emac)                              \
 512                         break;                                          \
 513                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 514                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 515                         priv = netdev_priv(ndev);                       \
 516                         skb->dev = ndev;                                \
 517                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 518                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 519                         priv = netdev_priv(ndev);                       \
 520                         skb->dev = ndev;                                \
 521                 }                                                       \
 522         } while (0)
 523 #define cpsw_add_mcast(priv, addr)                                      \
 524         do {                                                            \
 525                 if (priv->data.dual_emac) {                             \
 526                         struct cpsw_slave *slave = priv->slaves +       \
 527                                                 priv->emac_port;        \
 528                         int slave_port = cpsw_get_slave_port(priv,      \
 529                                                 slave->slave_num);      \
 530                         cpsw_ale_add_mcast(priv->ale, addr,             \
 531                                 1 << slave_port | ALE_PORT_HOST,        \
 532                                 ALE_VLAN, slave->port_vlan, 0);         \
 533                 } else {                                                \
 534                         cpsw_ale_add_mcast(priv->ale, addr,             \
 535                                 ALE_ALL_PORTS,                          \
 536                                 0, 0, 0);                               \
 537                 }                                                       \
 538         } while (0)
 539
 540 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 541 {
 542         return slave_num + 1;
 543 }
 544
 545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 546 {
 547         struct cpsw_priv *priv = netdev_priv(ndev);
 548         struct cpsw_ale *ale = priv->ale;
 549         int i;
 550
 551         if (priv->data.dual_emac) {
 552                 bool flag = false;
 553
 554                 /* Enabling promiscuous mode for one interface will be
 555                  * common for both the interface as the interface shares
 556                  * the same hardware resource.
 557                  */
 558                 for (i = 0; i < priv->data.slaves; i++)
 559                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 560                                 flag = true;
 561
 562                 if (!enable && flag) {
 563                         enable = true;
 564                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 565                 }
 566
 567                 if (enable) {
 568                         /* Enable Bypass */
 569                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 570
 571                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 572                 } else {
 573                         /* Disable Bypass */
 574                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 575                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 576                 }
 577         } else {
 578                 if (enable) {
 579                         unsigned long timeout = jiffies + HZ;
 580
 581                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 582                         for (i = 0; i <= priv->data.slaves; i++) {
 583                                 cpsw_ale_control_set(ale, i,
 584                                                      ALE_PORT_NOLEARN, 1);
 585                                 cpsw_ale_control_set(ale, i,
 586                                                      ALE_PORT_NO_SA_UPDATE, 1);
 587                         }
 588
 589                         /* Clear All Untouched entries */
 590                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 591                         do {
 592                                 cpu_relax();
 593                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 594                                         break;
 595                         } while (time_after(timeout, jiffies));
 596                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 597
 598                         /* Clear all mcast from ALE */
 599                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 600
 601                         /* Flood All Unicast Packets to Host port */
 602                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 603                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 604                 } else {
 605                         /* Don't Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 607
 608                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 609                         for (i = 0; i <= priv->data.slaves; i++) {
 610                                 cpsw_ale_control_set(ale, i,
 611                                                      ALE_PORT_NOLEARN, 0);
 612                                 cpsw_ale_control_set(ale, i,
 613                                                      ALE_PORT_NO_SA_UPDATE, 0);
 614                         }
 615                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 616                 }
 617         }
 618 }
 619
 620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 621 {
 622         struct cpsw_priv *priv = netdev_priv(ndev);
 623         int vid;
 624
 625         if (priv->data.dual_emac)
 626                 vid = priv->slaves[priv->emac_port].port_vlan;
 627         else
 628                 vid = priv->data.default_vlan;
 629
 630         if (ndev->flags & IFF_PROMISC) {
 631                 /* Enable promiscuous mode */
 632                 cpsw_set_promiscious(ndev, true);
 633                 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
 634                 return;
 635         } else {
 636                 /* Disable promiscuous mode */
 637                 cpsw_set_promiscious(ndev, false);
 638         }
 639
 640         /* Restore allmulti on vlans if necessary */
 641         cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
 642
 643         /* Clear all mcast from ALE */
 644         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
 645
 646         if (!netdev_mc_empty(ndev)) {
 647                 struct netdev_hw_addr *ha;
 648
 649                 /* program multicast address list into ALE register */
 650                 netdev_for_each_mc_addr(ha, ndev) {
 651                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 652                 }
 653         }
 654 }
 655
 656 static void cpsw_intr_enable(struct cpsw_priv *priv)
 657 {
 658         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 659         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 660
 661         cpdma_ctlr_int_ctrl(priv->dma, true);
 662         return;
 663 }
 664
 665 static void cpsw_intr_disable(struct cpsw_priv *priv)
 666 {
 667         __raw_writel(0, &priv->wr_regs->tx_en);
 668         __raw_writel(0, &priv->wr_regs->rx_en);
 669
 670         cpdma_ctlr_int_ctrl(priv->dma, false);
 671         return;
 672 }
 673
 674 static void cpsw_tx_handler(void *token, int len, int status)
 675 {
 676         struct sk_buff          *skb = token;
 677         struct net_device       *ndev = skb->dev;
 678         struct cpsw_priv        *priv = netdev_priv(ndev);
 679
 680         /* Check whether the queue is stopped due to stalled tx dma, if the
 681          * queue is stopped then start the queue as we have free desc for tx
 682          */
 683         if (unlikely(netif_queue_stopped(ndev)))
 684                 netif_wake_queue(ndev);
 685         cpts_tx_timestamp(priv->cpts, skb);
 686         ndev->stats.tx_packets++;
 687         ndev->stats.tx_bytes += len;
 688         dev_kfree_skb_any(skb);
 689 }
 690
 691 static void cpsw_rx_handler(void *token, int len, int status)
 692 {
 693         struct sk_buff          *skb = token;
 694         struct sk_buff          *new_skb;
 695         struct net_device       *ndev = skb->dev;
 696         struct cpsw_priv        *priv = netdev_priv(ndev);
 697         int                     ret = 0;
 698
 699         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 700
 701         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 702                 bool ndev_status = false;
 703                 struct cpsw_slave *slave = priv->slaves;
 704                 int n;
 705
 706                 if (priv->data.dual_emac) {
 707                         /* In dual emac mode check for all interfaces */
 708                         for (n = priv->data.slaves; n; n--, slave++)
 709                                 if (netif_running(slave->ndev))
 710                                         ndev_status = true;
 711                 }
 712
 713                 if (ndev_status && (status >= 0)) {
 714                         /* The packet received is for the interface which
 715                          * is already down and the other interface is up
 716                          * and running, instead of freeing which results
 717                          * in reducing of the number of rx descriptor in
 718                          * DMA engine, requeue skb back to cpdma.
 719                          */
 720                         new_skb = skb;
 721                         goto requeue;
 722                 }
 723
 724                 /* the interface is going down, skbs are purged */
 725                 dev_kfree_skb_any(skb);
 726                 return;
 727         }
 728
 729         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 730         if (new_skb) {
 731                 skb_put(skb, len);
 732                 cpts_rx_timestamp(priv->cpts, skb);
 733                 skb->protocol = eth_type_trans(skb, ndev);
 734                 netif_receive_skb(skb);
 735                 ndev->stats.rx_bytes += len;
 736                 ndev->stats.rx_packets++;
 737         } else {
 738                 ndev->stats.rx_dropped++;
 739                 new_skb = skb;
 740         }
 741
 742 requeue:
 743         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 744                         skb_tailroom(new_skb), 0);
 745         if (WARN_ON(ret < 0))
 746                 dev_kfree_skb_any(new_skb);
 747 }
 748
 749 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 750 {
 751         struct cpsw_priv *priv = dev_id;
 752
 753         writel(0, &priv->wr_regs->tx_en);
 754         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 755
 756         if (priv->quirk_irq) {
 757                 disable_irq_nosync(priv->irqs_table[1]);
 758                 priv->tx_irq_disabled = true;
 759         }
 760
 761         napi_schedule(&priv->napi_tx);
 762         return IRQ_HANDLED;
 763 }
 764
 765 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 766 {
 767         struct cpsw_priv *priv = dev_id;
 768
 769         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 770         writel(0, &priv->wr_regs->rx_en);
 771
 772         if (priv->quirk_irq) {
 773                 disable_irq_nosync(priv->irqs_table[0]);
 774                 priv->rx_irq_disabled = true;
 775         }
 776
 777         napi_schedule(&priv->napi_rx);
 778         return IRQ_HANDLED;
 779 }
 780
 781 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 782 {
 783         struct cpsw_priv        *priv = napi_to_priv(napi_tx);
 784         int                     num_tx;
 785
 786         num_tx = cpdma_chan_process(priv->txch, budget);
 787         if (num_tx < budget) {
 788                 napi_complete(napi_tx);
 789                 writel(0xff, &priv->wr_regs->tx_en);
 790                 if (priv->quirk_irq && priv->tx_irq_disabled) {
 791                         priv->tx_irq_disabled = false;
 792                         enable_irq(priv->irqs_table[1]);
 793                 }
 794         }
 795
 796         if (num_tx)
 797                 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
 798
 799         return num_tx;
 800 }
 801
 802 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 803 {
 804         struct cpsw_priv        *priv = napi_to_priv(napi_rx);
 805         int                     num_rx;
 806
 807         num_rx = cpdma_chan_process(priv->rxch, budget);
 808         if (num_rx < budget) {
 809                 napi_complete(napi_rx);
 810                 writel(0xff, &priv->wr_regs->rx_en);
 811                 if (priv->quirk_irq && priv->rx_irq_disabled) {
 812                         priv->rx_irq_disabled = false;
 813                         enable_irq(priv->irqs_table[0]);
 814                 }
 815         }
 816
 817         if (num_rx)
 818                 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
 819
 820         return num_rx;
 821 }
 822
 823 static inline void soft_reset(const char *module, void __iomem *reg)
 824 {
 825         unsigned long timeout = jiffies + HZ;
 826
 827         __raw_writel(1, reg);
 828         do {
 829                 cpu_relax();
 830         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 831
 832         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 833 }
 834
 835 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 836                          ((mac)[2] << 16) | ((mac)[3] << 24))
 837 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 838
 839 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 840                                struct cpsw_priv *priv)
 841 {
 842         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 843         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 844 }
 845
 846 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 847                               struct cpsw_priv *priv, bool *link)
 848 {
 849         struct phy_device       *phy = slave->phy;
 850         u32                     mac_control = 0;
 851         u32                     slave_port;
 852
 853         if (!phy)
 854                 return;
 855
 856         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 857
 858         if (phy->link) {
 859                 mac_control = priv->data.mac_control;
 860
 861                 /* enable forwarding */
 862                 cpsw_ale_control_set(priv->ale, slave_port,
 863                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 864
 865                 if (phy->speed == 1000)
 866                         mac_control |= BIT(7);  /* GIGABITEN    */
 867                 if (phy->duplex)
 868                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 869
 870                 /* set speed_in input in case RMII mode is used in 100Mbps */
 871                 if (phy->speed == 100)
 872                         mac_control |= BIT(15);
 873                 else if (phy->speed == 10)
 874                         mac_control |= BIT(18); /* In Band mode */
 875
 876                 if (priv->rx_pause)
 877                         mac_control |= BIT(3);
 878
 879                 if (priv->tx_pause)
 880                         mac_control |= BIT(4);
 881
 882                 *link = true;
 883         } else {
 884                 mac_control = 0;
 885                 /* disable forwarding */
 886                 cpsw_ale_control_set(priv->ale, slave_port,
 887                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 888         }
 889
 890         if (mac_control != slave->mac_control) {
 891                 phy_print_status(phy);
 892                 __raw_writel(mac_control, &slave->sliver->mac_control);
 893         }
 894
 895         slave->mac_control = mac_control;
 896 }
 897
 898 static void cpsw_adjust_link(struct net_device *ndev)
 899 {
 900         struct cpsw_priv        *priv = netdev_priv(ndev);
 901         bool                    link = false;
 902
 903         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 904
 905         if (link) {
 906                 netif_carrier_on(ndev);
 907                 if (netif_running(ndev))
 908                         netif_wake_queue(ndev);
 909         } else {
 910                 netif_carrier_off(ndev);
 911                 netif_stop_queue(ndev);
 912         }
 913 }
 914
 915 static int cpsw_get_coalesce(struct net_device *ndev,
 916                                 struct ethtool_coalesce *coal)
 917 {
 918         struct cpsw_priv *priv = netdev_priv(ndev);
 919
 920         coal->rx_coalesce_usecs = priv->coal_intvl;
 921         return 0;
 922 }
 923
 924 static int cpsw_set_coalesce(struct net_device *ndev,
 925                                 struct ethtool_coalesce *coal)
 926 {
 927         struct cpsw_priv *priv = netdev_priv(ndev);
 928         u32 int_ctrl;
 929         u32 num_interrupts = 0;
 930         u32 prescale = 0;
 931         u32 addnl_dvdr = 1;
 932         u32 coal_intvl = 0;
 933
 934         coal_intvl = coal->rx_coalesce_usecs;
 935
 936         int_ctrl =  readl(&priv->wr_regs->int_control);
 937         prescale = priv->bus_freq_mhz * 4;
 938
 939         if (!coal->rx_coalesce_usecs) {
 940                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 941                 goto update_return;
 942         }
 943
 944         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 945                 coal_intvl = CPSW_CMINTMIN_INTVL;
 946
 947         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 948                 /* Interrupt pacer works with 4us Pulse, we can
 949                  * throttle further by dilating the 4us pulse.
 950                  */
 951                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 952
 953                 if (addnl_dvdr > 1) {
 954                         prescale *= addnl_dvdr;
 955                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 956                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 957                                                 * addnl_dvdr);
 958                 } else {
 959                         addnl_dvdr = 1;
 960                         coal_intvl = CPSW_CMINTMAX_INTVL;
 961                 }
 962         }
 963
 964         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 965         writel(num_interrupts, &priv->wr_regs->rx_imax);
 966         writel(num_interrupts, &priv->wr_regs->tx_imax);
 967
 968         int_ctrl |= CPSW_INTPACEEN;
 969         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 970         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 971
 972 update_return:
 973         writel(int_ctrl, &priv->wr_regs->int_control);
 974
 975         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 976         if (priv->data.dual_emac) {
 977                 int i;
 978
 979                 for (i = 0; i < priv->data.slaves; i++) {
 980                         priv = netdev_priv(priv->slaves[i].ndev);
 981                         priv->coal_intvl = coal_intvl;
 982                 }
 983         } else {
 984                 priv->coal_intvl = coal_intvl;
 985         }
 986
 987         return 0;
 988 }
 989
 990 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 991 {
 992         switch (sset) {
 993         case ETH_SS_STATS:
 994                 return CPSW_STATS_LEN;
 995         default:
 996                 return -EOPNOTSUPP;
 997         }
 998 }
 999
1000 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1001 {
1002         u8 *p = data;
1003         int i;
1004
1005         switch (stringset) {
1006         case ETH_SS_STATS:
1007                 for (i = 0; i < CPSW_STATS_LEN; i++) {
1008                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1009                                ETH_GSTRING_LEN);
1010                         p += ETH_GSTRING_LEN;
1011                 }
1012                 break;
1013         }
1014 }
1015
1016 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1017                                     struct ethtool_stats *stats, u64 *data)
1018 {
1019         struct cpsw_priv *priv = netdev_priv(ndev);
1020         struct cpdma_chan_stats rx_stats;
1021         struct cpdma_chan_stats tx_stats;
1022         u32 val;
1023         u8 *p;
1024         int i;
1025
1026         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1027         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1028         cpdma_chan_get_stats(priv->txch, &tx_stats);
1029
1030         for (i = 0; i < CPSW_STATS_LEN; i++) {
1031                 switch (cpsw_gstrings_stats[i].type) {
1032                 case CPSW_STATS:
1033                         val = readl(priv->hw_stats +
1034                                     cpsw_gstrings_stats[i].stat_offset);
1035                         data[i] = val;
1036                         break;
1037
1038                 case CPDMA_RX_STATS:
1039                         p = (u8 *)&rx_stats +
1040                                 cpsw_gstrings_stats[i].stat_offset;
1041                         data[i] = *(u32 *)p;
1042                         break;
1043
1044                 case CPDMA_TX_STATS:
1045                         p = (u8 *)&tx_stats +
1046                                 cpsw_gstrings_stats[i].stat_offset;
1047                         data[i] = *(u32 *)p;
1048                         break;
1049                 }
1050         }
1051 }
1052
1053 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1054 {
1055         u32 i;
1056         u32 usage_count = 0;
1057
1058         if (!priv->data.dual_emac)
1059                 return 0;
1060
1061         for (i = 0; i < priv->data.slaves; i++)
1062                 if (priv->slaves[i].open_stat)
1063                         usage_count++;
1064
1065         return usage_count;
1066 }
1067
1068 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1069                         struct cpsw_priv *priv, struct sk_buff *skb)
1070 {
1071         if (!priv->data.dual_emac)
1072                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1073                                   skb->len, 0);
1074
1075         if (ndev == cpsw_get_slave_ndev(priv, 0))
1076                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1077                                   skb->len, 1);
1078         else
1079                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1080                                   skb->len, 2);
1081 }
1082
1083 static inline void cpsw_add_dual_emac_def_ale_entries(
1084                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1085                 u32 slave_port)
1086 {
1087         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1088
1089         if (priv->version == CPSW_VERSION_1)
1090                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1091         else
1092                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1093         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1094                           port_mask, port_mask, 0);
1095         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1096                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1097         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1098                 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1099 }
1100
1101 static void soft_reset_slave(struct cpsw_slave *slave)
1102 {
1103         char name[32];
1104
1105         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1106         soft_reset(name, &slave->sliver->soft_reset);
1107 }
1108
1109 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1110 {
1111         u32 slave_port;
1112
1113         soft_reset_slave(slave);
1114
1115         /* setup priority mapping */
1116         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1117
1118         switch (priv->version) {
1119         case CPSW_VERSION_1:
1120                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1121                 break;
1122         case CPSW_VERSION_2:
1123         case CPSW_VERSION_3:
1124         case CPSW_VERSION_4:
1125                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1126                 break;
1127         }
1128
1129         /* setup max packet size, and mac address */
1130         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1131         cpsw_set_slave_mac(slave, priv);
1132
1133         slave->mac_control = 0; /* no link yet */
1134
1135         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1136
1137         if (priv->data.dual_emac)
1138                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1139         else
1140                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1141                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1142
1143         if (slave->data->phy_node) {
1144                 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1145                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1146                 if (!slave->phy) {
1147                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1148                                 slave->data->phy_node->full_name,
1149                                 slave->slave_num);
1150                         return;
1151                 }
1152         } else {
1153                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1154                                  &cpsw_adjust_link, slave->data->phy_if);
1155                 if (IS_ERR(slave->phy)) {
1156                         dev_err(priv->dev,
1157                                 "phy \"%s\" not found on slave %d, err %ld\n",
1158                                 slave->data->phy_id, slave->slave_num,
1159                                 PTR_ERR(slave->phy));
1160                         slave->phy = NULL;
1161                         return;
1162                 }
1163         }
1164
1165         phy_attached_info(slave->phy);
1166
1167         phy_start(slave->phy);
1168
1169         /* Configure GMII_SEL register */
1170         cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1171 }
1172
1173 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1174 {
1175         const int vlan = priv->data.default_vlan;
1176         u32 reg;
1177         int i;
1178         int unreg_mcast_mask;
1179
1180         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1181                CPSW2_PORT_VLAN;
1182
1183         writel(vlan, &priv->host_port_regs->port_vlan);
1184
1185         for (i = 0; i < priv->data.slaves; i++)
1186                 slave_write(priv->slaves + i, vlan, reg);
1187
1188         if (priv->ndev->flags & IFF_ALLMULTI)
1189                 unreg_mcast_mask = ALE_ALL_PORTS;
1190         else
1191                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1192
1193         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1194                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1195                           unreg_mcast_mask);
1196 }
1197
1198 static void cpsw_init_host_port(struct cpsw_priv *priv)
1199 {
1200         u32 control_reg;
1201         u32 fifo_mode;
1202
1203         /* soft reset the controller and initialize ale */
1204         soft_reset("cpsw", &priv->regs->soft_reset);
1205         cpsw_ale_start(priv->ale);
1206
1207         /* switch to vlan unaware mode */
1208         cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1209                              CPSW_ALE_VLAN_AWARE);
1210         control_reg = readl(&priv->regs->control);
1211         control_reg |= CPSW_VLAN_AWARE;
1212         writel(control_reg, &priv->regs->control);
1213         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1214                      CPSW_FIFO_NORMAL_MODE;
1215         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1216
1217         /* setup host port priority mapping */
1218         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1219                      &priv->host_port_regs->cpdma_tx_pri_map);
1220         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1221
1222         cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
1223                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1224
1225         if (!priv->data.dual_emac) {
1226                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1227                                    0, 0);
1228                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1229                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1230         }
1231 }
1232
1233 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1234 {
1235         u32 slave_port;
1236
1237         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1238
1239         if (!slave->phy)
1240                 return;
1241         phy_stop(slave->phy);
1242         phy_disconnect(slave->phy);
1243         slave->phy = NULL;
1244         cpsw_ale_control_set(priv->ale, slave_port,
1245                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1246         soft_reset_slave(slave);
1247 }
1248
1249 static int cpsw_ndo_open(struct net_device *ndev)
1250 {
1251         struct cpsw_priv *priv = netdev_priv(ndev);
1252         int i, ret;
1253         u32 reg;
1254
1255         ret = pm_runtime_get_sync(&priv->pdev->dev);
1256         if (ret < 0) {
1257                 pm_runtime_put_noidle(&priv->pdev->dev);
1258                 return ret;
1259         }
1260
1261         if (!cpsw_common_res_usage_state(priv))
1262                 cpsw_intr_disable(priv);
1263         netif_carrier_off(ndev);
1264
1265         reg = priv->version;
1266
1267         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1268                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1269                  CPSW_RTL_VERSION(reg));
1270
1271         /* initialize host and slave ports */
1272         if (!cpsw_common_res_usage_state(priv))
1273                 cpsw_init_host_port(priv);
1274         for_each_slave(priv, cpsw_slave_open, priv);
1275
1276         /* Add default VLAN */
1277         if (!priv->data.dual_emac)
1278                 cpsw_add_default_vlan(priv);
1279         else
1280                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1281                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1282
1283         if (!cpsw_common_res_usage_state(priv)) {
1284                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1285                 int buf_num;
1286
1287                 /* setup tx dma to fixed prio and zero offset */
1288                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1289                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1290
1291                 /* disable priority elevation */
1292                 __raw_writel(0, &priv->regs->ptype);
1293
1294                 /* enable statistics collection only on all ports */
1295                 __raw_writel(0x7, &priv->regs->stat_port_en);
1296
1297                 /* Enable internal fifo flow control */
1298                 writel(0x7, &priv->regs->flow_control);
1299
1300                 napi_enable(&priv_sl0->napi_rx);
1301                 napi_enable(&priv_sl0->napi_tx);
1302
1303                 if (priv_sl0->tx_irq_disabled) {
1304                         priv_sl0->tx_irq_disabled = false;
1305                         enable_irq(priv->irqs_table[1]);
1306                 }
1307
1308                 if (priv_sl0->rx_irq_disabled) {
1309                         priv_sl0->rx_irq_disabled = false;
1310                         enable_irq(priv->irqs_table[0]);
1311                 }
1312
1313                 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1314                 for (i = 0; i < buf_num; i++) {
1315                         struct sk_buff *skb;
1316
1317                         ret = -ENOMEM;
1318                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1319                                         priv->rx_packet_max, GFP_KERNEL);
1320                         if (!skb)
1321                                 goto err_cleanup;
1322                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1323                                         skb_tailroom(skb), 0);
1324                         if (ret < 0) {
1325                                 kfree_skb(skb);
1326                                 goto err_cleanup;
1327                         }
1328                 }
1329                 /* continue even if we didn't manage to submit all
1330                  * receive descs
1331                  */
1332                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1333
1334                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1335                                   priv->data.cpts_clock_mult,
1336                                   priv->data.cpts_clock_shift))
1337                         dev_err(priv->dev, "error registering cpts device\n");
1338
1339         }
1340
1341         /* Enable Interrupt pacing if configured */
1342         if (priv->coal_intvl != 0) {
1343                 struct ethtool_coalesce coal;
1344
1345                 coal.rx_coalesce_usecs = priv->coal_intvl;
1346                 cpsw_set_coalesce(ndev, &coal);
1347         }
1348
1349         cpdma_ctlr_start(priv->dma);
1350         cpsw_intr_enable(priv);
1351
1352         if (priv->data.dual_emac)
1353                 priv->slaves[priv->emac_port].open_stat = true;
1354         return 0;
1355
1356 err_cleanup:
1357         cpdma_ctlr_stop(priv->dma);
1358         for_each_slave(priv, cpsw_slave_stop, priv);
1359         pm_runtime_put_sync(&priv->pdev->dev);
1360         netif_carrier_off(priv->ndev);
1361         return ret;
1362 }
1363
1364 static int cpsw_ndo_stop(struct net_device *ndev)
1365 {
1366         struct cpsw_priv *priv = netdev_priv(ndev);
1367
1368         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1369         netif_stop_queue(priv->ndev);
1370         netif_carrier_off(priv->ndev);
1371
1372         if (cpsw_common_res_usage_state(priv) <= 1) {
1373                 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1374
1375                 napi_disable(&priv_sl0->napi_rx);
1376                 napi_disable(&priv_sl0->napi_tx);
1377                 cpts_unregister(priv->cpts);
1378                 cpsw_intr_disable(priv);
1379                 cpdma_ctlr_stop(priv->dma);
1380                 cpsw_ale_stop(priv->ale);
1381         }
1382         for_each_slave(priv, cpsw_slave_stop, priv);
1383         pm_runtime_put_sync(&priv->pdev->dev);
1384         if (priv->data.dual_emac)
1385                 priv->slaves[priv->emac_port].open_stat = false;
1386         return 0;
1387 }
1388
1389 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1390                                        struct net_device *ndev)
1391 {
1392         struct cpsw_priv *priv = netdev_priv(ndev);
1393         int ret;
1394
1395         netif_trans_update(ndev);
1396
1397         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1398                 cpsw_err(priv, tx_err, "packet pad failed\n");
1399                 ndev->stats.tx_dropped++;
1400                 return NETDEV_TX_OK;
1401         }
1402
1403         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1404                                 priv->cpts->tx_enable)
1405                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1406
1407         skb_tx_timestamp(skb);
1408
1409         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1410         if (unlikely(ret != 0)) {
1411                 cpsw_err(priv, tx_err, "desc submit failed\n");
1412                 goto fail;
1413         }
1414
1415         /* If there is no more tx desc left free then we need to
1416          * tell the kernel to stop sending us tx frames.
1417          */
1418         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1419                 netif_stop_queue(ndev);
1420
1421         return NETDEV_TX_OK;
1422 fail:
1423         ndev->stats.tx_dropped++;
1424         netif_stop_queue(ndev);
1425         return NETDEV_TX_BUSY;
1426 }
1427
1428 #ifdef CONFIG_TI_CPTS
1429
1430 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1431 {
1432         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1433         u32 ts_en, seq_id;
1434
1435         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1436                 slave_write(slave, 0, CPSW1_TS_CTL);
1437                 return;
1438         }
1439
1440         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1441         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1442
1443         if (priv->cpts->tx_enable)
1444                 ts_en |= CPSW_V1_TS_TX_EN;
1445
1446         if (priv->cpts->rx_enable)
1447                 ts_en |= CPSW_V1_TS_RX_EN;
1448
1449         slave_write(slave, ts_en, CPSW1_TS_CTL);
1450         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1451 }
1452
1453 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1454 {
1455         struct cpsw_slave *slave;
1456         u32 ctrl, mtype;
1457
1458         if (priv->data.dual_emac)
1459                 slave = &priv->slaves[priv->emac_port];
1460         else
1461                 slave = &priv->slaves[priv->data.active_slave];
1462
1463         ctrl = slave_read(slave, CPSW2_CONTROL);
1464         switch (priv->version) {
1465         case CPSW_VERSION_2:
1466                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1467
1468                 if (priv->cpts->tx_enable)
1469                         ctrl |= CTRL_V2_TX_TS_BITS;
1470
1471                 if (priv->cpts->rx_enable)
1472                         ctrl |= CTRL_V2_RX_TS_BITS;
1473                 break;
1474         case CPSW_VERSION_3:
1475         default:
1476                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1477
1478                 if (priv->cpts->tx_enable)
1479                         ctrl |= CTRL_V3_TX_TS_BITS;
1480
1481                 if (priv->cpts->rx_enable)
1482                         ctrl |= CTRL_V3_RX_TS_BITS;
1483                 break;
1484         }
1485
1486         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1487
1488         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1489         slave_write(slave, ctrl, CPSW2_CONTROL);
1490         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1491 }
1492
1493 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1494 {
1495         struct cpsw_priv *priv = netdev_priv(dev);
1496         struct cpts *cpts = priv->cpts;
1497         struct hwtstamp_config cfg;
1498
1499         if (priv->version != CPSW_VERSION_1 &&
1500             priv->version != CPSW_VERSION_2 &&
1501             priv->version != CPSW_VERSION_3)
1502                 return -EOPNOTSUPP;
1503
1504         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1505                 return -EFAULT;
1506
1507         /* reserved for future extensions */
1508         if (cfg.flags)
1509                 return -EINVAL;
1510
1511         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1512                 return -ERANGE;
1513
1514         switch (cfg.rx_filter) {
1515         case HWTSTAMP_FILTER_NONE:
1516                 cpts->rx_enable = 0;
1517                 break;
1518         case HWTSTAMP_FILTER_ALL:
1519         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1520         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1521         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1522                 return -ERANGE;
1523         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1524         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1525         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1526         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1527         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1528         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1529         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1530         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1531         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1532                 cpts->rx_enable = 1;
1533                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1534                 break;
1535         default:
1536                 return -ERANGE;
1537         }
1538
1539         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1540
1541         switch (priv->version) {
1542         case CPSW_VERSION_1:
1543                 cpsw_hwtstamp_v1(priv);
1544                 break;
1545         case CPSW_VERSION_2:
1546         case CPSW_VERSION_3:
1547                 cpsw_hwtstamp_v2(priv);
1548                 break;
1549         default:
1550                 WARN_ON(1);
1551         }
1552
1553         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1554 }
1555
1556 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1557 {
1558         struct cpsw_priv *priv = netdev_priv(dev);
1559         struct cpts *cpts = priv->cpts;
1560         struct hwtstamp_config cfg;
1561
1562         if (priv->version != CPSW_VERSION_1 &&
1563             priv->version != CPSW_VERSION_2 &&
1564             priv->version != CPSW_VERSION_3)
1565                 return -EOPNOTSUPP;
1566
1567         cfg.flags = 0;
1568         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1569         cfg.rx_filter = (cpts->rx_enable ?
1570                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1571
1572         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1573 }
1574
1575 #endif /*CONFIG_TI_CPTS*/
1576
1577 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1578 {
1579         struct cpsw_priv *priv = netdev_priv(dev);
1580         int slave_no = cpsw_slave_index(priv);
1581
1582         if (!netif_running(dev))
1583                 return -EINVAL;
1584
1585         switch (cmd) {
1586 #ifdef CONFIG_TI_CPTS
1587         case SIOCSHWTSTAMP:
1588                 return cpsw_hwtstamp_set(dev, req);
1589         case SIOCGHWTSTAMP:
1590                 return cpsw_hwtstamp_get(dev, req);
1591 #endif
1592         }
1593
1594         if (!priv->slaves[slave_no].phy)
1595                 return -EOPNOTSUPP;
1596         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1597 }
1598
1599 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1600 {
1601         struct cpsw_priv *priv = netdev_priv(ndev);
1602
1603         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1604         ndev->stats.tx_errors++;
1605         cpsw_intr_disable(priv);
1606         cpdma_chan_stop(priv->txch);
1607         cpdma_chan_start(priv->txch);
1608         cpsw_intr_enable(priv);
1609 }
1610
1611 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1612 {
1613         struct cpsw_priv *priv = netdev_priv(ndev);
1614         struct sockaddr *addr = (struct sockaddr *)p;
1615         int flags = 0;
1616         u16 vid = 0;
1617         int ret;
1618
1619         if (!is_valid_ether_addr(addr->sa_data))
1620                 return -EADDRNOTAVAIL;
1621
1622         ret = pm_runtime_get_sync(&priv->pdev->dev);
1623         if (ret < 0) {
1624                 pm_runtime_put_noidle(&priv->pdev->dev);
1625                 return ret;
1626         }
1627
1628         if (priv->data.dual_emac) {
1629                 vid = priv->slaves[priv->emac_port].port_vlan;
1630                 flags = ALE_VLAN;
1631         }
1632
1633         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1634                            flags, vid);
1635         cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
1636                            flags, vid);
1637
1638         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1639         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1640         for_each_slave(priv, cpsw_set_slave_mac, priv);
1641
1642         pm_runtime_put(&priv->pdev->dev);
1643
1644         return 0;
1645 }
1646
1647 #ifdef CONFIG_NET_POLL_CONTROLLER
1648 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1649 {
1650         struct cpsw_priv *priv = netdev_priv(ndev);
1651
1652         cpsw_intr_disable(priv);
1653         cpsw_rx_interrupt(priv->irqs_table[0], priv);
1654         cpsw_tx_interrupt(priv->irqs_table[1], priv);
1655         cpsw_intr_enable(priv);
1656 }
1657 #endif
1658
1659 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1660                                 unsigned short vid)
1661 {
1662         int ret;
1663         int unreg_mcast_mask = 0;
1664         u32 port_mask;
1665
1666         if (priv->data.dual_emac) {
1667                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1668
1669                 if (priv->ndev->flags & IFF_ALLMULTI)
1670                         unreg_mcast_mask = port_mask;
1671         } else {
1672                 port_mask = ALE_ALL_PORTS;
1673
1674                 if (priv->ndev->flags & IFF_ALLMULTI)
1675                         unreg_mcast_mask = ALE_ALL_PORTS;
1676                 else
1677                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1678         }
1679
1680         ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1681                                 unreg_mcast_mask);
1682         if (ret != 0)
1683                 return ret;
1684
1685         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1686                                  HOST_PORT_NUM, ALE_VLAN, vid);
1687         if (ret != 0)
1688                 goto clean_vid;
1689
1690         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1691                                  port_mask, ALE_VLAN, vid, 0);
1692         if (ret != 0)
1693                 goto clean_vlan_ucast;
1694         return 0;
1695
1696 clean_vlan_ucast:
1697         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1698                            HOST_PORT_NUM, ALE_VLAN, vid);
1699 clean_vid:
1700         cpsw_ale_del_vlan(priv->ale, vid, 0);
1701         return ret;
1702 }
1703
1704 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1705                                     __be16 proto, u16 vid)
1706 {
1707         struct cpsw_priv *priv = netdev_priv(ndev);
1708         int ret;
1709
1710         if (vid == priv->data.default_vlan)
1711                 return 0;
1712
1713         ret = pm_runtime_get_sync(&priv->pdev->dev);
1714         if (ret < 0) {
1715                 pm_runtime_put_noidle(&priv->pdev->dev);
1716                 return ret;
1717         }
1718
1719         if (priv->data.dual_emac) {
1720                 /* In dual EMAC, reserved VLAN id should not be used for
1721                  * creating VLAN interfaces as this can break the dual
1722                  * EMAC port separation
1723                  */
1724                 int i;
1725
1726                 for (i = 0; i < priv->data.slaves; i++) {
1727                         if (vid == priv->slaves[i].port_vlan)
1728                                 return -EINVAL;
1729                 }
1730         }
1731
1732         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1733         ret = cpsw_add_vlan_ale_entry(priv, vid);
1734
1735         pm_runtime_put(&priv->pdev->dev);
1736         return ret;
1737 }
1738
1739 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1740                                      __be16 proto, u16 vid)
1741 {
1742         struct cpsw_priv *priv = netdev_priv(ndev);
1743         int ret;
1744
1745         if (vid == priv->data.default_vlan)
1746                 return 0;
1747
1748         ret = pm_runtime_get_sync(&priv->pdev->dev);
1749         if (ret < 0) {
1750                 pm_runtime_put_noidle(&priv->pdev->dev);
1751                 return ret;
1752         }
1753
1754         if (priv->data.dual_emac) {
1755                 int i;
1756
1757                 for (i = 0; i < priv->data.slaves; i++) {
1758                         if (vid == priv->slaves[i].port_vlan)
1759                                 return -EINVAL;
1760                 }
1761         }
1762
1763         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1764         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1765         if (ret != 0)
1766                 return ret;
1767
1768         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1769                                  HOST_PORT_NUM, ALE_VLAN, vid);
1770         if (ret != 0)
1771                 return ret;
1772
1773         ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1774                                  0, ALE_VLAN, vid);
1775         pm_runtime_put(&priv->pdev->dev);
1776         return ret;
1777 }
1778
1779 static const struct net_device_ops cpsw_netdev_ops = {
1780         .ndo_open               = cpsw_ndo_open,
1781         .ndo_stop               = cpsw_ndo_stop,
1782         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1783         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1784         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1785         .ndo_validate_addr      = eth_validate_addr,
1786         .ndo_change_mtu         = eth_change_mtu,
1787         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1788         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1789 #ifdef CONFIG_NET_POLL_CONTROLLER
1790         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1791 #endif
1792         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1793         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1794 };
1795
1796 static int cpsw_get_regs_len(struct net_device *ndev)
1797 {
1798         struct cpsw_priv *priv = netdev_priv(ndev);
1799
1800         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1801 }
1802
1803 static void cpsw_get_regs(struct net_device *ndev,
1804                           struct ethtool_regs *regs, void *p)
1805 {
1806         struct cpsw_priv *priv = netdev_priv(ndev);
1807         u32 *reg = p;
1808
1809         /* update CPSW IP version */
1810         regs->version = priv->version;
1811
1812         cpsw_ale_dump(priv->ale, reg);
1813 }
1814
1815 static void cpsw_get_drvinfo(struct net_device *ndev,
1816                              struct ethtool_drvinfo *info)
1817 {
1818         struct cpsw_priv *priv = netdev_priv(ndev);
1819
1820         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1821         strlcpy(info->version, "1.0", sizeof(info->version));
1822         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1823 }
1824
1825 static u32 cpsw_get_msglevel(struct net_device *ndev)
1826 {
1827         struct cpsw_priv *priv = netdev_priv(ndev);
1828         return priv->msg_enable;
1829 }
1830
1831 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1832 {
1833         struct cpsw_priv *priv = netdev_priv(ndev);
1834         priv->msg_enable = value;
1835 }
1836
1837 static int cpsw_get_ts_info(struct net_device *ndev,
1838                             struct ethtool_ts_info *info)
1839 {
1840 #ifdef CONFIG_TI_CPTS
1841         struct cpsw_priv *priv = netdev_priv(ndev);
1842
1843         info->so_timestamping =
1844                 SOF_TIMESTAMPING_TX_HARDWARE |
1845                 SOF_TIMESTAMPING_TX_SOFTWARE |
1846                 SOF_TIMESTAMPING_RX_HARDWARE |
1847                 SOF_TIMESTAMPING_RX_SOFTWARE |
1848                 SOF_TIMESTAMPING_SOFTWARE |
1849                 SOF_TIMESTAMPING_RAW_HARDWARE;
1850         info->phc_index = priv->cpts->phc_index;
1851         info->tx_types =
1852                 (1 << HWTSTAMP_TX_OFF) |
1853                 (1 << HWTSTAMP_TX_ON);
1854         info->rx_filters =
1855                 (1 << HWTSTAMP_FILTER_NONE) |
1856                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1857 #else
1858         info->so_timestamping =
1859                 SOF_TIMESTAMPING_TX_SOFTWARE |
1860                 SOF_TIMESTAMPING_RX_SOFTWARE |
1861                 SOF_TIMESTAMPING_SOFTWARE;
1862         info->phc_index = -1;
1863         info->tx_types = 0;
1864         info->rx_filters = 0;
1865 #endif
1866         return 0;
1867 }
1868
1869 static int cpsw_get_settings(struct net_device *ndev,
1870                              struct ethtool_cmd *ecmd)
1871 {
1872         struct cpsw_priv *priv = netdev_priv(ndev);
1873         int slave_no = cpsw_slave_index(priv);
1874
1875         if (priv->slaves[slave_no].phy)
1876                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1877         else
1878                 return -EOPNOTSUPP;
1879 }
1880
1881 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1882 {
1883         struct cpsw_priv *priv = netdev_priv(ndev);
1884         int slave_no = cpsw_slave_index(priv);
1885
1886         if (priv->slaves[slave_no].phy)
1887                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1888         else
1889                 return -EOPNOTSUPP;
1890 }
1891
1892 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1893 {
1894         struct cpsw_priv *priv = netdev_priv(ndev);
1895         int slave_no = cpsw_slave_index(priv);
1896
1897         wol->supported = 0;
1898         wol->wolopts = 0;
1899
1900         if (priv->slaves[slave_no].phy)
1901                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1902 }
1903
1904 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1905 {
1906         struct cpsw_priv *priv = netdev_priv(ndev);
1907         int slave_no = cpsw_slave_index(priv);
1908
1909         if (priv->slaves[slave_no].phy)
1910                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1911         else
1912                 return -EOPNOTSUPP;
1913 }
1914
1915 static void cpsw_get_pauseparam(struct net_device *ndev,
1916                                 struct ethtool_pauseparam *pause)
1917 {
1918         struct cpsw_priv *priv = netdev_priv(ndev);
1919
1920         pause->autoneg = AUTONEG_DISABLE;
1921         pause->rx_pause = priv->rx_pause ? true : false;
1922         pause->tx_pause = priv->tx_pause ? true : false;
1923 }
1924
1925 static int cpsw_set_pauseparam(struct net_device *ndev,
1926                                struct ethtool_pauseparam *pause)
1927 {
1928         struct cpsw_priv *priv = netdev_priv(ndev);
1929         bool link;
1930
1931         priv->rx_pause = pause->rx_pause ? true : false;
1932         priv->tx_pause = pause->tx_pause ? true : false;
1933
1934         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1935         return 0;
1936 }
1937
1938 static int cpsw_ethtool_op_begin(struct net_device *ndev)
1939 {
1940         struct cpsw_priv *priv = netdev_priv(ndev);
1941         int ret;
1942
1943         ret = pm_runtime_get_sync(&priv->pdev->dev);
1944         if (ret < 0) {
1945                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
1946                 pm_runtime_put_noidle(&priv->pdev->dev);
1947         }
1948
1949         return ret;
1950 }
1951
1952 static void cpsw_ethtool_op_complete(struct net_device *ndev)
1953 {
1954         struct cpsw_priv *priv = netdev_priv(ndev);
1955         int ret;
1956
1957         ret = pm_runtime_put(&priv->pdev->dev);
1958         if (ret < 0)
1959                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1960 }
1961
1962 static const struct ethtool_ops cpsw_ethtool_ops = {
1963         .get_drvinfo    = cpsw_get_drvinfo,
1964         .get_msglevel   = cpsw_get_msglevel,
1965         .set_msglevel   = cpsw_set_msglevel,
1966         .get_link       = ethtool_op_get_link,
1967         .get_ts_info    = cpsw_get_ts_info,
1968         .get_settings   = cpsw_get_settings,
1969         .set_settings   = cpsw_set_settings,
1970         .get_coalesce   = cpsw_get_coalesce,
1971         .set_coalesce   = cpsw_set_coalesce,
1972         .get_sset_count         = cpsw_get_sset_count,
1973         .get_strings            = cpsw_get_strings,
1974         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1975         .get_pauseparam         = cpsw_get_pauseparam,
1976         .set_pauseparam         = cpsw_set_pauseparam,
1977         .get_wol        = cpsw_get_wol,
1978         .set_wol        = cpsw_set_wol,
1979         .get_regs_len   = cpsw_get_regs_len,
1980         .get_regs       = cpsw_get_regs,
1981         .begin          = cpsw_ethtool_op_begin,
1982         .complete       = cpsw_ethtool_op_complete,
1983 };
1984
1985 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1986                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1987 {
1988         void __iomem            *regs = priv->regs;
1989         int                     slave_num = slave->slave_num;
1990         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1991
1992         slave->data     = data;
1993         slave->regs     = regs + slave_reg_ofs;
1994         slave->sliver   = regs + sliver_reg_ofs;
1995         slave->port_vlan = data->dual_emac_res_vlan;
1996 }
1997
1998 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1999                          struct platform_device *pdev)
2000 {
2001         struct device_node *node = pdev->dev.of_node;
2002         struct device_node *slave_node;
2003         int i = 0, ret;
2004         u32 prop;
2005
2006         if (!node)
2007                 return -EINVAL;
2008
2009         if (of_property_read_u32(node, "slaves", &prop)) {
2010                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2011                 return -EINVAL;
2012         }
2013         data->slaves = prop;
2014
2015         if (of_property_read_u32(node, "active_slave", &prop)) {
2016                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2017                 return -EINVAL;
2018         }
2019         data->active_slave = prop;
2020
2021         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2022                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2023                 return -EINVAL;
2024         }
2025         data->cpts_clock_mult = prop;
2026
2027         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2028                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2029                 return -EINVAL;
2030         }
2031         data->cpts_clock_shift = prop;
2032
2033         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2034                                         * sizeof(struct cpsw_slave_data),
2035                                         GFP_KERNEL);
2036         if (!data->slave_data)
2037                 return -ENOMEM;
2038
2039         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2040                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2041                 return -EINVAL;
2042         }
2043         data->channels = prop;
2044
2045         if (of_property_read_u32(node, "ale_entries", &prop)) {
2046                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2047                 return -EINVAL;
2048         }
2049         data->ale_entries = prop;
2050
2051         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2052                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2053                 return -EINVAL;
2054         }
2055         data->bd_ram_size = prop;
2056
2057         if (of_property_read_u32(node, "mac_control", &prop)) {
2058                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2059                 return -EINVAL;
2060         }
2061         data->mac_control = prop;
2062
2063         if (of_property_read_bool(node, "dual_emac"))
2064                 data->dual_emac = 1;
2065
2066         /*
2067          * Populate all the child nodes here...
2068          */
2069         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2070         /* We do not want to force this, as in some cases may not have child */
2071         if (ret)
2072                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2073
2074         for_each_available_child_of_node(node, slave_node) {
2075                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2076                 const void *mac_addr = NULL;
2077                 int lenp;
2078                 const __be32 *parp;
2079
2080                 /* This is no slave child node, continue */
2081                 if (strcmp(slave_node->name, "slave"))
2082                         continue;
2083
2084                 slave_data->phy_node = of_parse_phandle(slave_node,
2085                                                         "phy-handle", 0);
2086                 parp = of_get_property(slave_node, "phy_id", &lenp);
2087                 if (slave_data->phy_node) {
2088                         dev_dbg(&pdev->dev,
2089                                 "slave[%d] using phy-handle=\"%s\"\n",
2090                                 i, slave_data->phy_node->full_name);
2091                 } else if (of_phy_is_fixed_link(slave_node)) {
2092                         /* In the case of a fixed PHY, the DT node associated
2093                          * to the PHY is the Ethernet MAC DT node.
2094                          */
2095                         ret = of_phy_register_fixed_link(slave_node);
2096                         if (ret)
2097                                 return ret;
2098                         slave_data->phy_node = of_node_get(slave_node);
2099                 } else if (parp) {
2100                         u32 phyid;
2101                         struct device_node *mdio_node;
2102                         struct platform_device *mdio;
2103
2104                         if (lenp != (sizeof(__be32) * 2)) {
2105                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2106                                 goto no_phy_slave;
2107                         }
2108                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2109                         phyid = be32_to_cpup(parp+1);
2110                         mdio = of_find_device_by_node(mdio_node);
2111                         of_node_put(mdio_node);
2112                         if (!mdio) {
2113                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2114                                 return -EINVAL;
2115                         }
2116                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2117                                  PHY_ID_FMT, mdio->name, phyid);
2118                 } else {
2119                         dev_err(&pdev->dev,
2120                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2121                                 i);
2122                         goto no_phy_slave;
2123                 }
2124                 slave_data->phy_if = of_get_phy_mode(slave_node);
2125                 if (slave_data->phy_if < 0) {
2126                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2127                                 i);
2128                         return slave_data->phy_if;
2129                 }
2130
2131 no_phy_slave:
2132                 mac_addr = of_get_mac_address(slave_node);
2133                 if (mac_addr) {
2134                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2135                 } else {
2136                         ret = ti_cm_get_macid(&pdev->dev, i,
2137                                               slave_data->mac_addr);
2138                         if (ret)
2139                                 return ret;
2140                 }
2141                 if (data->dual_emac) {
2142                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2143                                                  &prop)) {
2144                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2145                                 slave_data->dual_emac_res_vlan = i+1;
2146                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2147                                         slave_data->dual_emac_res_vlan, i);
2148                         } else {
2149                                 slave_data->dual_emac_res_vlan = prop;
2150                         }
2151                 }
2152
2153                 i++;
2154                 if (i == data->slaves)
2155                         break;
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2162                                 struct cpsw_priv *priv)
2163 {
2164         struct cpsw_platform_data       *data = &priv->data;
2165         struct net_device               *ndev;
2166         struct cpsw_priv                *priv_sl2;
2167         int ret = 0, i;
2168
2169         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2170         if (!ndev) {
2171                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2172                 return -ENOMEM;
2173         }
2174
2175         priv_sl2 = netdev_priv(ndev);
2176         priv_sl2->data = *data;
2177         priv_sl2->pdev = pdev;
2178         priv_sl2->ndev = ndev;
2179         priv_sl2->dev  = &ndev->dev;
2180         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2181         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2182
2183         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2184                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2185                         ETH_ALEN);
2186                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2187         } else {
2188                 random_ether_addr(priv_sl2->mac_addr);
2189                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2190         }
2191         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2192
2193         priv_sl2->slaves = priv->slaves;
2194         priv_sl2->clk = priv->clk;
2195
2196         priv_sl2->coal_intvl = 0;
2197         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2198
2199         priv_sl2->regs = priv->regs;
2200         priv_sl2->host_port_regs = priv->host_port_regs;
2201         priv_sl2->wr_regs = priv->wr_regs;
2202         priv_sl2->hw_stats = priv->hw_stats;
2203         priv_sl2->dma = priv->dma;
2204         priv_sl2->txch = priv->txch;
2205         priv_sl2->rxch = priv->rxch;
2206         priv_sl2->ale = priv->ale;
2207         priv_sl2->emac_port = 1;
2208         priv->slaves[1].ndev = ndev;
2209         priv_sl2->cpts = priv->cpts;
2210         priv_sl2->version = priv->version;
2211
2212         for (i = 0; i < priv->num_irqs; i++) {
2213                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2214                 priv_sl2->num_irqs = priv->num_irqs;
2215         }
2216         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2217
2218         ndev->netdev_ops = &cpsw_netdev_ops;
2219         ndev->ethtool_ops = &cpsw_ethtool_ops;
2220
2221         /* register the network device */
2222         SET_NETDEV_DEV(ndev, &pdev->dev);
2223         ret = register_netdev(ndev);
2224         if (ret) {
2225                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2226                 free_netdev(ndev);
2227                 ret = -ENODEV;
2228         }
2229
2230         return ret;
2231 }
2232
2233 #define CPSW_QUIRK_IRQ          BIT(0)
2234
2235 static struct platform_device_id cpsw_devtype[] = {
2236         {
2237                 /* keep it for existing comaptibles */
2238                 .name = "cpsw",
2239                 .driver_data = CPSW_QUIRK_IRQ,
2240         }, {
2241                 .name = "am335x-cpsw",
2242                 .driver_data = CPSW_QUIRK_IRQ,
2243         }, {
2244                 .name = "am4372-cpsw",
2245                 .driver_data = 0,
2246         }, {
2247                 .name = "dra7-cpsw",
2248                 .driver_data = 0,
2249         }, {
2250                 /* sentinel */
2251         }
2252 };
2253 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2254
2255 enum ti_cpsw_type {
2256         CPSW = 0,
2257         AM335X_CPSW,
2258         AM4372_CPSW,
2259         DRA7_CPSW,
2260 };
2261
2262 static const struct of_device_id cpsw_of_mtable[] = {
2263         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2264         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2265         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2266         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2267         { /* sentinel */ },
2268 };
2269 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2270
2271 static int cpsw_probe(struct platform_device *pdev)
2272 {
2273         struct cpsw_platform_data       *data;
2274         struct net_device               *ndev;
2275         struct cpsw_priv                *priv;
2276         struct cpdma_params             dma_params;
2277         struct cpsw_ale_params          ale_params;
2278         void __iomem                    *ss_regs;
2279         struct resource                 *res, *ss_res;
2280         const struct of_device_id       *of_id;
2281         struct gpio_descs               *mode;
2282         u32 slave_offset, sliver_offset, slave_size;
2283         int ret = 0, i;
2284         int irq;
2285
2286         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2287         if (!ndev) {
2288                 dev_err(&pdev->dev, "error allocating net_device\n");
2289                 return -ENOMEM;
2290         }
2291
2292         platform_set_drvdata(pdev, ndev);
2293         priv = netdev_priv(ndev);
2294         priv->pdev = pdev;
2295         priv->ndev = ndev;
2296         priv->dev  = &ndev->dev;
2297         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2298         priv->rx_packet_max = max(rx_packet_max, 128);
2299         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2300         if (!priv->cpts) {
2301                 dev_err(&pdev->dev, "error allocating cpts\n");
2302                 ret = -ENOMEM;
2303                 goto clean_ndev_ret;
2304         }
2305
2306         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2307         if (IS_ERR(mode)) {
2308                 ret = PTR_ERR(mode);
2309                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2310                 goto clean_ndev_ret;
2311         }
2312
2313         /*
2314          * This may be required here for child devices.
2315          */
2316         pm_runtime_enable(&pdev->dev);
2317
2318         /* Select default pin state */
2319         pinctrl_pm_select_default_state(&pdev->dev);
2320
2321         if (cpsw_probe_dt(&priv->data, pdev)) {
2322                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2323                 ret = -ENODEV;
2324                 goto clean_runtime_disable_ret;
2325         }
2326         data = &priv->data;
2327
2328         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2329                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2330                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2331         } else {
2332                 eth_random_addr(priv->mac_addr);
2333                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2334         }
2335
2336         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2337
2338         priv->slaves = devm_kzalloc(&pdev->dev,
2339                                     sizeof(struct cpsw_slave) * data->slaves,
2340                                     GFP_KERNEL);
2341         if (!priv->slaves) {
2342                 ret = -ENOMEM;
2343                 goto clean_runtime_disable_ret;
2344         }
2345         for (i = 0; i < data->slaves; i++)
2346                 priv->slaves[i].slave_num = i;
2347
2348         priv->slaves[0].ndev = ndev;
2349         priv->emac_port = 0;
2350
2351         priv->clk = devm_clk_get(&pdev->dev, "fck");
2352         if (IS_ERR(priv->clk)) {
2353                 dev_err(priv->dev, "fck is not found\n");
2354                 ret = -ENODEV;
2355                 goto clean_runtime_disable_ret;
2356         }
2357         priv->coal_intvl = 0;
2358         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2359
2360         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2361         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2362         if (IS_ERR(ss_regs)) {
2363                 ret = PTR_ERR(ss_regs);
2364                 goto clean_runtime_disable_ret;
2365         }
2366         priv->regs = ss_regs;
2367
2368         /* Need to enable clocks with runtime PM api to access module
2369          * registers
2370          */
2371         ret = pm_runtime_get_sync(&pdev->dev);
2372         if (ret < 0) {
2373                 pm_runtime_put_noidle(&pdev->dev);
2374                 goto clean_runtime_disable_ret;
2375         }
2376         priv->version = readl(&priv->regs->id_ver);
2377         pm_runtime_put_sync(&pdev->dev);
2378
2379         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2380         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2381         if (IS_ERR(priv->wr_regs)) {
2382                 ret = PTR_ERR(priv->wr_regs);
2383                 goto clean_runtime_disable_ret;
2384         }
2385
2386         memset(&dma_params, 0, sizeof(dma_params));
2387         memset(&ale_params, 0, sizeof(ale_params));
2388
2389         switch (priv->version) {
2390         case CPSW_VERSION_1:
2391                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2392                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2393                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2394                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2395                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2396                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2397                 slave_offset         = CPSW1_SLAVE_OFFSET;
2398                 slave_size           = CPSW1_SLAVE_SIZE;
2399                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2400                 dma_params.desc_mem_phys = 0;
2401                 break;
2402         case CPSW_VERSION_2:
2403         case CPSW_VERSION_3:
2404         case CPSW_VERSION_4:
2405                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2406                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2407                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2408                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2409                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2410                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2411                 slave_offset         = CPSW2_SLAVE_OFFSET;
2412                 slave_size           = CPSW2_SLAVE_SIZE;
2413                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2414                 dma_params.desc_mem_phys =
2415                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2416                 break;
2417         default:
2418                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2419                 ret = -ENODEV;
2420                 goto clean_runtime_disable_ret;
2421         }
2422         for (i = 0; i < priv->data.slaves; i++) {
2423                 struct cpsw_slave *slave = &priv->slaves[i];
2424                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2425                 slave_offset  += slave_size;
2426                 sliver_offset += SLIVER_SIZE;
2427         }
2428
2429         dma_params.dev          = &pdev->dev;
2430         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2431         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2432         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2433         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2434         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2435
2436         dma_params.num_chan             = data->channels;
2437         dma_params.has_soft_reset       = true;
2438         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2439         dma_params.desc_mem_size        = data->bd_ram_size;
2440         dma_params.desc_align           = 16;
2441         dma_params.has_ext_regs         = true;
2442         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2443
2444         priv->dma = cpdma_ctlr_create(&dma_params);
2445         if (!priv->dma) {
2446                 dev_err(priv->dev, "error initializing dma\n");
2447                 ret = -ENOMEM;
2448                 goto clean_runtime_disable_ret;
2449         }
2450
2451         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2452                                        cpsw_tx_handler);
2453         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2454                                        cpsw_rx_handler);
2455
2456         if (WARN_ON(!priv->txch || !priv->rxch)) {
2457                 dev_err(priv->dev, "error initializing dma channels\n");
2458                 ret = -ENOMEM;
2459                 goto clean_dma_ret;
2460         }
2461
2462         ale_params.dev                  = &ndev->dev;
2463         ale_params.ale_ageout           = ale_ageout;
2464         ale_params.ale_entries          = data->ale_entries;
2465         ale_params.ale_ports            = data->slaves;
2466
2467         priv->ale = cpsw_ale_create(&ale_params);
2468         if (!priv->ale) {
2469                 dev_err(priv->dev, "error initializing ale engine\n");
2470                 ret = -ENODEV;
2471                 goto clean_dma_ret;
2472         }
2473
2474         ndev->irq = platform_get_irq(pdev, 1);
2475         if (ndev->irq < 0) {
2476                 dev_err(priv->dev, "error getting irq resource\n");
2477                 ret = ndev->irq;
2478                 goto clean_ale_ret;
2479         }
2480
2481         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2482         if (of_id) {
2483                 pdev->id_entry = of_id->data;
2484                 if (pdev->id_entry->driver_data)
2485                         priv->quirk_irq = true;
2486         }
2487
2488         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2489          * MISC IRQs which are always kept disabled with this driver so
2490          * we will not request them.
2491          *
2492          * If anyone wants to implement support for those, make sure to
2493          * first request and append them to irqs_table array.
2494          */
2495
2496         /* RX IRQ */
2497         irq = platform_get_irq(pdev, 1);
2498         if (irq < 0) {
2499                 ret = irq;
2500                 goto clean_ale_ret;
2501         }
2502
2503         priv->irqs_table[0] = irq;
2504         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2505                                0, dev_name(&pdev->dev), priv);
2506         if (ret < 0) {
2507                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2508                 goto clean_ale_ret;
2509         }
2510
2511         /* TX IRQ */
2512         irq = platform_get_irq(pdev, 2);
2513         if (irq < 0) {
2514                 ret = irq;
2515                 goto clean_ale_ret;
2516         }
2517
2518         priv->irqs_table[1] = irq;
2519         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2520                                0, dev_name(&pdev->dev), priv);
2521         if (ret < 0) {
2522                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2523                 goto clean_ale_ret;
2524         }
2525         priv->num_irqs = 2;
2526
2527         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2528
2529         ndev->netdev_ops = &cpsw_netdev_ops;
2530         ndev->ethtool_ops = &cpsw_ethtool_ops;
2531         netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2532         netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2533
2534         /* register the network device */
2535         SET_NETDEV_DEV(ndev, &pdev->dev);
2536         ret = register_netdev(ndev);
2537         if (ret) {
2538                 dev_err(priv->dev, "error registering net device\n");
2539                 ret = -ENODEV;
2540                 goto clean_ale_ret;
2541         }
2542
2543         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2544                     &ss_res->start, ndev->irq);
2545
2546         if (priv->data.dual_emac) {
2547                 ret = cpsw_probe_dual_emac(pdev, priv);
2548                 if (ret) {
2549                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2550                         goto clean_ale_ret;
2551                 }
2552         }
2553
2554         return 0;
2555
2556 clean_ale_ret:
2557         cpsw_ale_destroy(priv->ale);
2558 clean_dma_ret:
2559         cpdma_ctlr_destroy(priv->dma);
2560 clean_runtime_disable_ret:
2561         pm_runtime_disable(&pdev->dev);
2562 clean_ndev_ret:
2563         free_netdev(priv->ndev);
2564         return ret;
2565 }
2566
2567 static int cpsw_remove(struct platform_device *pdev)
2568 {
2569         struct net_device *ndev = platform_get_drvdata(pdev);
2570         struct cpsw_priv *priv = netdev_priv(ndev);
2571         int ret;
2572
2573         ret = pm_runtime_get_sync(&pdev->dev);
2574         if (ret < 0) {
2575                 pm_runtime_put_noidle(&pdev->dev);
2576                 return ret;
2577         }
2578
2579         if (priv->data.dual_emac)
2580                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2581         unregister_netdev(ndev);
2582
2583         cpsw_ale_destroy(priv->ale);
2584         cpdma_ctlr_destroy(priv->dma);
2585         of_platform_depopulate(&pdev->dev);
2586         pm_runtime_put_sync(&pdev->dev);
2587         pm_runtime_disable(&pdev->dev);
2588         if (priv->data.dual_emac)
2589                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2590         free_netdev(ndev);
2591         return 0;
2592 }
2593
2594 #ifdef CONFIG_PM_SLEEP
2595 static int cpsw_suspend(struct device *dev)
2596 {
2597         struct platform_device  *pdev = to_platform_device(dev);
2598         struct net_device       *ndev = platform_get_drvdata(pdev);
2599         struct cpsw_priv        *priv = netdev_priv(ndev);
2600
2601         if (priv->data.dual_emac) {
2602                 int i;
2603
2604                 for (i = 0; i < priv->data.slaves; i++) {
2605                         if (netif_running(priv->slaves[i].ndev))
2606                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2607                 }
2608         } else {
2609                 if (netif_running(ndev))
2610                         cpsw_ndo_stop(ndev);
2611         }
2612
2613         /* Select sleep pin state */
2614         pinctrl_pm_select_sleep_state(&pdev->dev);
2615
2616         return 0;
2617 }
2618
2619 static int cpsw_resume(struct device *dev)
2620 {
2621         struct platform_device  *pdev = to_platform_device(dev);
2622         struct net_device       *ndev = platform_get_drvdata(pdev);
2623         struct cpsw_priv        *priv = netdev_priv(ndev);
2624
2625         /* Select default pin state */
2626         pinctrl_pm_select_default_state(&pdev->dev);
2627
2628         if (priv->data.dual_emac) {
2629                 int i;
2630
2631                 for (i = 0; i < priv->data.slaves; i++) {
2632                         if (netif_running(priv->slaves[i].ndev))
2633                                 cpsw_ndo_open(priv->slaves[i].ndev);
2634                 }
2635         } else {
2636                 if (netif_running(ndev))
2637                         cpsw_ndo_open(ndev);
2638         }
2639         return 0;
2640 }
2641 #endif
2642
2643 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2644
2645 static struct platform_driver cpsw_driver = {
2646         .driver = {
2647                 .name    = "cpsw",
2648                 .pm      = &cpsw_pm_ops,
2649                 .of_match_table = cpsw_of_mtable,
2650         },
2651         .probe = cpsw_probe,
2652         .remove = cpsw_remove,
2653 };
2654
2655 module_platform_driver(cpsw_driver);
2656
2657 MODULE_LICENSE("GPL");
2658 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2659 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2660 MODULE_DESCRIPTION("TI CPSW Ethernet driver");