drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 149
 150 static int debug_level;
 151 module_param(debug_level, int, 0);
 152 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 153
 154 static int ale_ageout = 10;
 155 module_param(ale_ageout, int, 0);
 156 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 157
 158 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 159 module_param(rx_packet_max, int, 0);
 160 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 161
 162 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 163 module_param(descs_pool_size, int, 0444);
 164 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 165
 166 struct cpsw_wr_regs {
 167         u32     id_ver;
 168         u32     soft_reset;
 169         u32     control;
 170         u32     int_control;
 171         u32     rx_thresh_en;
 172         u32     rx_en;
 173         u32     tx_en;
 174         u32     misc_en;
 175         u32     mem_allign1[8];
 176         u32     rx_thresh_stat;
 177         u32     rx_stat;
 178         u32     tx_stat;
 179         u32     misc_stat;
 180         u32     mem_allign2[8];
 181         u32     rx_imax;
 182         u32     tx_imax;
 183
 184 };
 185
 186 struct cpsw_ss_regs {
 187         u32     id_ver;
 188         u32     control;
 189         u32     soft_reset;
 190         u32     stat_port_en;
 191         u32     ptype;
 192         u32     soft_idle;
 193         u32     thru_rate;
 194         u32     gap_thresh;
 195         u32     tx_start_wds;
 196         u32     flow_control;
 197         u32     vlan_ltype;
 198         u32     ts_ltype;
 199         u32     dlr_ltype;
 200 };
 201
 202 /* CPSW_PORT_V1 */
 203 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 204 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 205 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 206 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 207 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 208 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 209 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 210 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 211
 212 /* CPSW_PORT_V2 */
 213 #define CPSW2_CONTROL       0x00 /* Control Register */
 214 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 215 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 216 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 217 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 218 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 219 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 220
 221 /* CPSW_PORT_V1 and V2 */
 222 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 223 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 224 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 225
 226 /* CPSW_PORT_V2 only */
 227 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 235
 236 /* Bit definitions for the CPSW2_CONTROL register */
 237 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 238 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 239 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 240 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 241 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 242 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 243 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 244 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 245 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 246 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 247 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 248 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 249 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 250 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 251 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 252 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 253 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 254
 255 #define CTRL_V2_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 258
 259 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 260 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 261 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 262
 263
 264 #define CTRL_V3_TS_BITS \
 265         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 266          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 267          TS_LTYPE1_EN)
 268
 269 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 270 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 271 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 272
 273 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 274 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 275 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 276 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 277 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 278
 279 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 280 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 281
 282 /* Bit definitions for the CPSW1_TS_CTL register */
 283 #define CPSW_V1_TS_RX_EN                BIT(0)
 284 #define CPSW_V1_TS_TX_EN                BIT(4)
 285 #define CPSW_V1_MSG_TYPE_OFS            16
 286
 287 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 288 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 289
 290 #define CPSW_MAX_BLKS_TX                15
 291 #define CPSW_MAX_BLKS_TX_SHIFT          4
 292 #define CPSW_MAX_BLKS_RX                5
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364 };
 365
 366 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 367 {
 368         return __raw_readl(slave->regs + offset);
 369 }
 370
 371 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 372 {
 373         __raw_writel(val, slave->regs + offset);
 374 }
 375
 376 struct cpsw_vector {
 377         struct cpdma_chan *ch;
 378         int budget;
 379 };
 380
 381 struct cpsw_common {
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct napi_struct              napi_rx;
 385         struct napi_struct              napi_tx;
 386         struct cpsw_ss_regs __iomem     *regs;
 387         struct cpsw_wr_regs __iomem     *wr_regs;
 388         u8 __iomem                      *hw_stats;
 389         struct cpsw_host_regs __iomem   *host_port_regs;
 390         u32                             version;
 391         u32                             coal_intvl;
 392         u32                             bus_freq_mhz;
 393         int                             rx_packet_max;
 394         struct cpsw_slave               *slaves;
 395         struct cpdma_ctlr               *dma;
 396         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 397         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 398         struct cpsw_ale                 *ale;
 399         bool                            quirk_irq;
 400         bool                            rx_irq_disabled;
 401         bool                            tx_irq_disabled;
 402         u32 irqs_table[IRQ_NUM];
 403         struct cpts                     *cpts;
 404         int                             rx_ch_num, tx_ch_num;
 405         int                             speed;
 406         int                             usage_count;
 407 };
 408
 409 struct cpsw_priv {
 410         struct net_device               *ndev;
 411         struct device                   *dev;
 412         u32                             msg_enable;
 413         u8                              mac_addr[ETH_ALEN];
 414         bool                            rx_pause;
 415         bool                            tx_pause;
 416         u32 emac_port;
 417         struct cpsw_common *cpsw;
 418 };
 419
 420 struct cpsw_stats {
 421         char stat_string[ETH_GSTRING_LEN];
 422         int type;
 423         int sizeof_stat;
 424         int stat_offset;
 425 };
 426
 427 enum {
 428         CPSW_STATS,
 429         CPDMA_RX_STATS,
 430         CPDMA_TX_STATS,
 431 };
 432
 433 #define CPSW_STAT(m)            CPSW_STATS,                             \
 434                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 435                                 offsetof(struct cpsw_hw_stats, m)
 436 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 437                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 438                                 offsetof(struct cpdma_chan_stats, m)
 439 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 440                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 441                                 offsetof(struct cpdma_chan_stats, m)
 442
 443 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 444         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 445         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 446         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 447         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 448         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 449         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 450         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 451         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 452         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 453         { "Rx Fragments", CPSW_STAT(rxfragments) },
 454         { "Rx Octets", CPSW_STAT(rxoctets) },
 455         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 456         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 457         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 458         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 459         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 460         { "Collisions", CPSW_STAT(txcollisionframes) },
 461         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 462         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 463         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 464         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 465         { "Tx Underrun", CPSW_STAT(txunderrun) },
 466         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 467         { "Tx Octets", CPSW_STAT(txoctets) },
 468         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 469         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 470         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 471         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 472         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 473         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 474         { "Net Octets", CPSW_STAT(netoctets) },
 475         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 476         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 477         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 478 };
 479
 480 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 481         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 482         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 483         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 484         { "misqueued", CPDMA_RX_STAT(misqueued) },
 485         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 486         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 487         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 488         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 489         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 490         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 491         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 492         { "requeue", CPDMA_RX_STAT(requeue) },
 493         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 494 };
 495
 496 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 497 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 498
 499 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 500 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 501 #define for_each_slave(priv, func, arg...)                              \
 502         do {                                                            \
 503                 struct cpsw_slave *slave;                               \
 504                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 505                 int n;                                                  \
 506                 if (cpsw->data.dual_emac)                               \
 507                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 508                 else                                                    \
 509                         for (n = cpsw->data.slaves,                     \
 510                                         slave = cpsw->slaves;           \
 511                                         n; n--)                         \
 512                                 (func)(slave++, ##arg);                 \
 513         } while (0)
 514
 515 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 516         do {                                                            \
 517                 if (!cpsw->data.dual_emac)                              \
 518                         break;                                          \
 519                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 520                         ndev = cpsw->slaves[0].ndev;                    \
 521                         skb->dev = ndev;                                \
 522                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 523                         ndev = cpsw->slaves[1].ndev;                    \
 524                         skb->dev = ndev;                                \
 525                 }                                                       \
 526         } while (0)
 527 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 528         do {                                                            \
 529                 if (cpsw->data.dual_emac) {                             \
 530                         struct cpsw_slave *slave = cpsw->slaves +       \
 531                                                 priv->emac_port;        \
 532                         int slave_port = cpsw_get_slave_port(           \
 533                                                 slave->slave_num);      \
 534                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 535                                 1 << slave_port | ALE_PORT_HOST,        \
 536                                 ALE_VLAN, slave->port_vlan, 0);         \
 537                 } else {                                                \
 538                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 539                                 ALE_ALL_PORTS,                          \
 540                                 0, 0, 0);                               \
 541                 }                                                       \
 542         } while (0)
 543
 544 static inline int cpsw_get_slave_port(u32 slave_num)
 545 {
 546         return slave_num + 1;
 547 }
 548
 549 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 550 {
 551         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 552         struct cpsw_ale *ale = cpsw->ale;
 553         int i;
 554
 555         if (cpsw->data.dual_emac) {
 556                 bool flag = false;
 557
 558                 /* Enabling promiscuous mode for one interface will be
 559                  * common for both the interface as the interface shares
 560                  * the same hardware resource.
 561                  */
 562                 for (i = 0; i < cpsw->data.slaves; i++)
 563                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 564                                 flag = true;
 565
 566                 if (!enable && flag) {
 567                         enable = true;
 568                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 569                 }
 570
 571                 if (enable) {
 572                         /* Enable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 574
 575                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 576                 } else {
 577                         /* Disable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 579                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 580                 }
 581         } else {
 582                 if (enable) {
 583                         unsigned long timeout = jiffies + HZ;
 584
 585                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 586                         for (i = 0; i <= cpsw->data.slaves; i++) {
 587                                 cpsw_ale_control_set(ale, i,
 588                                                      ALE_PORT_NOLEARN, 1);
 589                                 cpsw_ale_control_set(ale, i,
 590                                                      ALE_PORT_NO_SA_UPDATE, 1);
 591                         }
 592
 593                         /* Clear All Untouched entries */
 594                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 595                         do {
 596                                 cpu_relax();
 597                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 598                                         break;
 599                         } while (time_after(timeout, jiffies));
 600                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 601
 602                         /* Clear all mcast from ALE */
 603                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 604
 605                         /* Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 607                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 608                 } else {
 609                         /* Don't Flood All Unicast Packets to Host port */
 610                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 611
 612                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 613                         for (i = 0; i <= cpsw->data.slaves; i++) {
 614                                 cpsw_ale_control_set(ale, i,
 615                                                      ALE_PORT_NOLEARN, 0);
 616                                 cpsw_ale_control_set(ale, i,
 617                                                      ALE_PORT_NO_SA_UPDATE, 0);
 618                         }
 619                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 620                 }
 621         }
 622 }
 623
 624 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 625 {
 626         struct cpsw_priv *priv = netdev_priv(ndev);
 627         struct cpsw_common *cpsw = priv->cpsw;
 628         int vid;
 629
 630         if (cpsw->data.dual_emac)
 631                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 632         else
 633                 vid = cpsw->data.default_vlan;
 634
 635         if (ndev->flags & IFF_PROMISC) {
 636                 /* Enable promiscuous mode */
 637                 cpsw_set_promiscious(ndev, true);
 638                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 639                 return;
 640         } else {
 641                 /* Disable promiscuous mode */
 642                 cpsw_set_promiscious(ndev, false);
 643         }
 644
 645         /* Restore allmulti on vlans if necessary */
 646         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 647
 648         /* Clear all mcast from ALE */
 649         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 650
 651         if (!netdev_mc_empty(ndev)) {
 652                 struct netdev_hw_addr *ha;
 653
 654                 /* program multicast address list into ALE register */
 655                 netdev_for_each_mc_addr(ha, ndev) {
 656                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 657                 }
 658         }
 659 }
 660
 661 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 662 {
 663         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 664         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 665
 666         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 667         return;
 668 }
 669
 670 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 671 {
 672         __raw_writel(0, &cpsw->wr_regs->tx_en);
 673         __raw_writel(0, &cpsw->wr_regs->rx_en);
 674
 675         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 676         return;
 677 }
 678
 679 static void cpsw_tx_handler(void *token, int len, int status)
 680 {
 681         struct netdev_queue     *txq;
 682         struct sk_buff          *skb = token;
 683         struct net_device       *ndev = skb->dev;
 684         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 685
 686         /* Check whether the queue is stopped due to stalled tx dma, if the
 687          * queue is stopped then start the queue as we have free desc for tx
 688          */
 689         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 690         if (unlikely(netif_tx_queue_stopped(txq)))
 691                 netif_tx_wake_queue(txq);
 692
 693         cpts_tx_timestamp(cpsw->cpts, skb);
 694         ndev->stats.tx_packets++;
 695         ndev->stats.tx_bytes += len;
 696         dev_kfree_skb_any(skb);
 697 }
 698
 699 static void cpsw_rx_handler(void *token, int len, int status)
 700 {
 701         struct cpdma_chan       *ch;
 702         struct sk_buff          *skb = token;
 703         struct sk_buff          *new_skb;
 704         struct net_device       *ndev = skb->dev;
 705         int                     ret = 0;
 706         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 707
 708         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 709
 710         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 711                 /* In dual emac mode check for all interfaces */
 712                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 713                     (status >= 0)) {
 714                         /* The packet received is for the interface which
 715                          * is already down and the other interface is up
 716                          * and running, instead of freeing which results
 717                          * in reducing of the number of rx descriptor in
 718                          * DMA engine, requeue skb back to cpdma.
 719                          */
 720                         new_skb = skb;
 721                         goto requeue;
 722                 }
 723
 724                 /* the interface is going down, skbs are purged */
 725                 dev_kfree_skb_any(skb);
 726                 return;
 727         }
 728
 729         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 730         if (new_skb) {
 731                 skb_copy_queue_mapping(new_skb, skb);
 732                 skb_put(skb, len);
 733                 cpts_rx_timestamp(cpsw->cpts, skb);
 734                 skb->protocol = eth_type_trans(skb, ndev);
 735                 netif_receive_skb(skb);
 736                 ndev->stats.rx_bytes += len;
 737                 ndev->stats.rx_packets++;
 738                 kmemleak_not_leak(new_skb);
 739         } else {
 740                 ndev->stats.rx_dropped++;
 741                 new_skb = skb;
 742         }
 743
 744 requeue:
 745         if (netif_dormant(ndev)) {
 746                 dev_kfree_skb_any(new_skb);
 747                 return;
 748         }
 749
 750         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 751         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 752                                 skb_tailroom(new_skb), 0);
 753         if (WARN_ON(ret < 0))
 754                 dev_kfree_skb_any(new_skb);
 755 }
 756
 757 static void cpsw_split_res(struct net_device *ndev)
 758 {
 759         struct cpsw_priv *priv = netdev_priv(ndev);
 760         u32 consumed_rate = 0, bigest_rate = 0;
 761         struct cpsw_common *cpsw = priv->cpsw;
 762         struct cpsw_vector *txv = cpsw->txv;
 763         int i, ch_weight, rlim_ch_num = 0;
 764         int budget, bigest_rate_ch = 0;
 765         u32 ch_rate, max_rate;
 766         int ch_budget = 0;
 767
 768         for (i = 0; i < cpsw->tx_ch_num; i++) {
 769                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 770                 if (!ch_rate)
 771                         continue;
 772
 773                 rlim_ch_num++;
 774                 consumed_rate += ch_rate;
 775         }
 776
 777         if (cpsw->tx_ch_num == rlim_ch_num) {
 778                 max_rate = consumed_rate;
 779         } else if (!rlim_ch_num) {
 780                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 781                 bigest_rate = 0;
 782                 max_rate = consumed_rate;
 783         } else {
 784                 max_rate = cpsw->speed * 1000;
 785
 786                 /* if max_rate is less then expected due to reduced link speed,
 787                  * split proportionally according next potential max speed
 788                  */
 789                 if (max_rate < consumed_rate)
 790                         max_rate *= 10;
 791
 792                 if (max_rate < consumed_rate)
 793                         max_rate *= 10;
 794
 795                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 796                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 797                             (cpsw->tx_ch_num - rlim_ch_num);
 798                 bigest_rate = (max_rate - consumed_rate) /
 799                               (cpsw->tx_ch_num - rlim_ch_num);
 800         }
 801
 802         /* split tx weight/budget */
 803         budget = CPSW_POLL_WEIGHT;
 804         for (i = 0; i < cpsw->tx_ch_num; i++) {
 805                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 806                 if (ch_rate) {
 807                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 808                         if (!txv[i].budget)
 809                                 txv[i].budget++;
 810                         if (ch_rate > bigest_rate) {
 811                                 bigest_rate_ch = i;
 812                                 bigest_rate = ch_rate;
 813                         }
 814
 815                         ch_weight = (ch_rate * 100) / max_rate;
 816                         if (!ch_weight)
 817                                 ch_weight++;
 818                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 819                 } else {
 820                         txv[i].budget = ch_budget;
 821                         if (!bigest_rate_ch)
 822                                 bigest_rate_ch = i;
 823                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 824                 }
 825
 826                 budget -= txv[i].budget;
 827         }
 828
 829         if (budget)
 830                 txv[bigest_rate_ch].budget += budget;
 831
 832         /* split rx budget */
 833         budget = CPSW_POLL_WEIGHT;
 834         ch_budget = budget / cpsw->rx_ch_num;
 835         for (i = 0; i < cpsw->rx_ch_num; i++) {
 836                 cpsw->rxv[i].budget = ch_budget;
 837                 budget -= ch_budget;
 838         }
 839
 840         if (budget)
 841                 cpsw->rxv[0].budget += budget;
 842 }
 843
 844 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 845 {
 846         struct cpsw_common *cpsw = dev_id;
 847
 848         writel(0, &cpsw->wr_regs->tx_en);
 849         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 850
 851         if (cpsw->quirk_irq) {
 852                 disable_irq_nosync(cpsw->irqs_table[1]);
 853                 cpsw->tx_irq_disabled = true;
 854         }
 855
 856         napi_schedule(&cpsw->napi_tx);
 857         return IRQ_HANDLED;
 858 }
 859
 860 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 861 {
 862         struct cpsw_common *cpsw = dev_id;
 863
 864         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 865         writel(0, &cpsw->wr_regs->rx_en);
 866
 867         if (cpsw->quirk_irq) {
 868                 disable_irq_nosync(cpsw->irqs_table[0]);
 869                 cpsw->rx_irq_disabled = true;
 870         }
 871
 872         napi_schedule(&cpsw->napi_rx);
 873         return IRQ_HANDLED;
 874 }
 875
 876 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 877 {
 878         u32                     ch_map;
 879         int                     num_tx, cur_budget, ch;
 880         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 881         struct cpsw_vector      *txv;
 882
 883         /* process every unprocessed channel */
 884         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 885         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 886                 if (!(ch_map & 0x01))
 887                         continue;
 888
 889                 txv = &cpsw->txv[ch];
 890                 if (unlikely(txv->budget > budget - num_tx))
 891                         cur_budget = budget - num_tx;
 892                 else
 893                         cur_budget = txv->budget;
 894
 895                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 896                 if (num_tx >= budget)
 897                         break;
 898         }
 899
 900         if (num_tx < budget) {
 901                 napi_complete(napi_tx);
 902                 writel(0xff, &cpsw->wr_regs->tx_en);
 903                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 904                         cpsw->tx_irq_disabled = false;
 905                         enable_irq(cpsw->irqs_table[1]);
 906                 }
 907         }
 908
 909         return num_tx;
 910 }
 911
 912 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 913 {
 914         u32                     ch_map;
 915         int                     num_rx, cur_budget, ch;
 916         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 917         struct cpsw_vector      *rxv;
 918
 919         /* process every unprocessed channel */
 920         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 921         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 922                 if (!(ch_map & 0x01))
 923                         continue;
 924
 925                 rxv = &cpsw->rxv[ch];
 926                 if (unlikely(rxv->budget > budget - num_rx))
 927                         cur_budget = budget - num_rx;
 928                 else
 929                         cur_budget = rxv->budget;
 930
 931                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 932                 if (num_rx >= budget)
 933                         break;
 934         }
 935
 936         if (num_rx < budget) {
 937                 napi_complete_done(napi_rx, num_rx);
 938                 writel(0xff, &cpsw->wr_regs->rx_en);
 939                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 940                         cpsw->rx_irq_disabled = false;
 941                         enable_irq(cpsw->irqs_table[0]);
 942                 }
 943         }
 944
 945         return num_rx;
 946 }
 947
 948 static inline void soft_reset(const char *module, void __iomem *reg)
 949 {
 950         unsigned long timeout = jiffies + HZ;
 951
 952         __raw_writel(1, reg);
 953         do {
 954                 cpu_relax();
 955         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 956
 957         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 958 }
 959
 960 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 961                          ((mac)[2] << 16) | ((mac)[3] << 24))
 962 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 963
 964 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 965                                struct cpsw_priv *priv)
 966 {
 967         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 968         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 969 }
 970
 971 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 972                               struct cpsw_priv *priv, bool *link)
 973 {
 974         struct phy_device       *phy = slave->phy;
 975         u32                     mac_control = 0;
 976         u32                     slave_port;
 977         struct cpsw_common *cpsw = priv->cpsw;
 978
 979         if (!phy)
 980                 return;
 981
 982         slave_port = cpsw_get_slave_port(slave->slave_num);
 983
 984         if (phy->link) {
 985                 mac_control = cpsw->data.mac_control;
 986
 987                 /* enable forwarding */
 988                 cpsw_ale_control_set(cpsw->ale, slave_port,
 989                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 990
 991                 if (phy->speed == 1000)
 992                         mac_control |= BIT(7);  /* GIGABITEN    */
 993                 if (phy->duplex)
 994                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 995
 996                 /* set speed_in input in case RMII mode is used in 100Mbps */
 997                 if (phy->speed == 100)
 998                         mac_control |= BIT(15);
 999                 /* in band mode only works in 10Mbps RGMII mode */
1000                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1001                         mac_control |= BIT(18); /* In Band mode */
1002
1003                 if (priv->rx_pause)
1004                         mac_control |= BIT(3);
1005
1006                 if (priv->tx_pause)
1007                         mac_control |= BIT(4);
1008
1009                 *link = true;
1010         } else {
1011                 mac_control = 0;
1012                 /* disable forwarding */
1013                 cpsw_ale_control_set(cpsw->ale, slave_port,
1014                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1015         }
1016
1017         if (mac_control != slave->mac_control) {
1018                 phy_print_status(phy);
1019                 __raw_writel(mac_control, &slave->sliver->mac_control);
1020         }
1021
1022         slave->mac_control = mac_control;
1023 }
1024
1025 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1026 {
1027         int i, speed;
1028
1029         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1030                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1031                         speed += cpsw->slaves[i].phy->speed;
1032
1033         return speed;
1034 }
1035
1036 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1037 {
1038         int i, rlim_ch_num;
1039         int speed, ch_rate;
1040
1041         /* re-split resources only in case speed was changed */
1042         speed = cpsw_get_common_speed(cpsw);
1043         if (speed == cpsw->speed || !speed)
1044                 return 0;
1045
1046         cpsw->speed = speed;
1047
1048         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1049                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1050                 if (!ch_rate)
1051                         break;
1052
1053                 rlim_ch_num++;
1054         }
1055
1056         /* cases not dependent on speed */
1057         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1058                 return 0;
1059
1060         return 1;
1061 }
1062
1063 static void cpsw_adjust_link(struct net_device *ndev)
1064 {
1065         struct cpsw_priv        *priv = netdev_priv(ndev);
1066         struct cpsw_common      *cpsw = priv->cpsw;
1067         bool                    link = false;
1068
1069         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1070
1071         if (link) {
1072                 if (cpsw_need_resplit(cpsw))
1073                         cpsw_split_res(ndev);
1074
1075                 netif_carrier_on(ndev);
1076                 if (netif_running(ndev))
1077                         netif_tx_wake_all_queues(ndev);
1078         } else {
1079                 netif_carrier_off(ndev);
1080                 netif_tx_stop_all_queues(ndev);
1081         }
1082 }
1083
1084 static int cpsw_get_coalesce(struct net_device *ndev,
1085                                 struct ethtool_coalesce *coal)
1086 {
1087         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1088
1089         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1090         return 0;
1091 }
1092
1093 static int cpsw_set_coalesce(struct net_device *ndev,
1094                                 struct ethtool_coalesce *coal)
1095 {
1096         struct cpsw_priv *priv = netdev_priv(ndev);
1097         u32 int_ctrl;
1098         u32 num_interrupts = 0;
1099         u32 prescale = 0;
1100         u32 addnl_dvdr = 1;
1101         u32 coal_intvl = 0;
1102         struct cpsw_common *cpsw = priv->cpsw;
1103
1104         coal_intvl = coal->rx_coalesce_usecs;
1105
1106         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1107         prescale = cpsw->bus_freq_mhz * 4;
1108
1109         if (!coal->rx_coalesce_usecs) {
1110                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1111                 goto update_return;
1112         }
1113
1114         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1115                 coal_intvl = CPSW_CMINTMIN_INTVL;
1116
1117         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1118                 /* Interrupt pacer works with 4us Pulse, we can
1119                  * throttle further by dilating the 4us pulse.
1120                  */
1121                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1122
1123                 if (addnl_dvdr > 1) {
1124                         prescale *= addnl_dvdr;
1125                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1126                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1127                                                 * addnl_dvdr);
1128                 } else {
1129                         addnl_dvdr = 1;
1130                         coal_intvl = CPSW_CMINTMAX_INTVL;
1131                 }
1132         }
1133
1134         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1135         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1136         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1137
1138         int_ctrl |= CPSW_INTPACEEN;
1139         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1140         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1141
1142 update_return:
1143         writel(int_ctrl, &cpsw->wr_regs->int_control);
1144
1145         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1146         cpsw->coal_intvl = coal_intvl;
1147
1148         return 0;
1149 }
1150
1151 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1152 {
1153         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1154
1155         switch (sset) {
1156         case ETH_SS_STATS:
1157                 return (CPSW_STATS_COMMON_LEN +
1158                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1159                        CPSW_STATS_CH_LEN);
1160         default:
1161                 return -EOPNOTSUPP;
1162         }
1163 }
1164
1165 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1166 {
1167         int ch_stats_len;
1168         int line;
1169         int i;
1170
1171         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1172         for (i = 0; i < ch_stats_len; i++) {
1173                 line = i % CPSW_STATS_CH_LEN;
1174                 snprintf(*p, ETH_GSTRING_LEN,
1175                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1176                          i / CPSW_STATS_CH_LEN,
1177                          cpsw_gstrings_ch_stats[line].stat_string);
1178                 *p += ETH_GSTRING_LEN;
1179         }
1180 }
1181
1182 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1183 {
1184         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1185         u8 *p = data;
1186         int i;
1187
1188         switch (stringset) {
1189         case ETH_SS_STATS:
1190                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1191                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1192                                ETH_GSTRING_LEN);
1193                         p += ETH_GSTRING_LEN;
1194                 }
1195
1196                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1197                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1198                 break;
1199         }
1200 }
1201
1202 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1203                                     struct ethtool_stats *stats, u64 *data)
1204 {
1205         u8 *p;
1206         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1207         struct cpdma_chan_stats ch_stats;
1208         int i, l, ch;
1209
1210         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1211         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1212                 data[l] = readl(cpsw->hw_stats +
1213                                 cpsw_gstrings_stats[l].stat_offset);
1214
1215         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1216                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1217                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1218                         p = (u8 *)&ch_stats +
1219                                 cpsw_gstrings_ch_stats[i].stat_offset;
1220                         data[l] = *(u32 *)p;
1221                 }
1222         }
1223
1224         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1225                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1226                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1227                         p = (u8 *)&ch_stats +
1228                                 cpsw_gstrings_ch_stats[i].stat_offset;
1229                         data[l] = *(u32 *)p;
1230                 }
1231         }
1232 }
1233
1234 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1235                                         struct sk_buff *skb,
1236                                         struct cpdma_chan *txch)
1237 {
1238         struct cpsw_common *cpsw = priv->cpsw;
1239
1240         skb_tx_timestamp(skb);
1241         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1242                                  priv->emac_port + cpsw->data.dual_emac);
1243 }
1244
1245 static inline void cpsw_add_dual_emac_def_ale_entries(
1246                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1247                 u32 slave_port)
1248 {
1249         struct cpsw_common *cpsw = priv->cpsw;
1250         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1251
1252         if (cpsw->version == CPSW_VERSION_1)
1253                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1254         else
1255                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1256         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1257                           port_mask, port_mask, 0);
1258         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1259                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1260         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1261                            HOST_PORT_NUM, ALE_VLAN |
1262                            ALE_SECURE, slave->port_vlan);
1263 }
1264
1265 static void soft_reset_slave(struct cpsw_slave *slave)
1266 {
1267         char name[32];
1268
1269         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1270         soft_reset(name, &slave->sliver->soft_reset);
1271 }
1272
1273 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1274 {
1275         u32 slave_port;
1276         struct phy_device *phy;
1277         struct cpsw_common *cpsw = priv->cpsw;
1278
1279         soft_reset_slave(slave);
1280
1281         /* setup priority mapping */
1282         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1283
1284         switch (cpsw->version) {
1285         case CPSW_VERSION_1:
1286                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1287                 /* Increase RX FIFO size to 5 for supporting fullduplex
1288                  * flow control mode
1289                  */
1290                 slave_write(slave,
1291                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1292                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1293                 break;
1294         case CPSW_VERSION_2:
1295         case CPSW_VERSION_3:
1296         case CPSW_VERSION_4:
1297                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1298                 /* Increase RX FIFO size to 5 for supporting fullduplex
1299                  * flow control mode
1300                  */
1301                 slave_write(slave,
1302                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1303                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1304                 break;
1305         }
1306
1307         /* setup max packet size, and mac address */
1308         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1309         cpsw_set_slave_mac(slave, priv);
1310
1311         slave->mac_control = 0; /* no link yet */
1312
1313         slave_port = cpsw_get_slave_port(slave->slave_num);
1314
1315         if (cpsw->data.dual_emac)
1316                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1317         else
1318                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1319                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1320
1321         if (slave->data->phy_node) {
1322                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1323                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1324                 if (!phy) {
1325                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1326                                 slave->data->phy_node,
1327                                 slave->slave_num);
1328                         return;
1329                 }
1330         } else {
1331                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1332                                  &cpsw_adjust_link, slave->data->phy_if);
1333                 if (IS_ERR(phy)) {
1334                         dev_err(priv->dev,
1335                                 "phy \"%s\" not found on slave %d, err %ld\n",
1336                                 slave->data->phy_id, slave->slave_num,
1337                                 PTR_ERR(phy));
1338                         return;
1339                 }
1340         }
1341
1342         slave->phy = phy;
1343
1344         phy_attached_info(slave->phy);
1345
1346         phy_start(slave->phy);
1347
1348         /* Configure GMII_SEL register */
1349         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1350 }
1351
1352 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1353 {
1354         struct cpsw_common *cpsw = priv->cpsw;
1355         const int vlan = cpsw->data.default_vlan;
1356         u32 reg;
1357         int i;
1358         int unreg_mcast_mask;
1359
1360         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1361                CPSW2_PORT_VLAN;
1362
1363         writel(vlan, &cpsw->host_port_regs->port_vlan);
1364
1365         for (i = 0; i < cpsw->data.slaves; i++)
1366                 slave_write(cpsw->slaves + i, vlan, reg);
1367
1368         if (priv->ndev->flags & IFF_ALLMULTI)
1369                 unreg_mcast_mask = ALE_ALL_PORTS;
1370         else
1371                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1372
1373         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1374                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1375                           unreg_mcast_mask);
1376 }
1377
1378 static void cpsw_init_host_port(struct cpsw_priv *priv)
1379 {
1380         u32 fifo_mode;
1381         u32 control_reg;
1382         struct cpsw_common *cpsw = priv->cpsw;
1383
1384         /* soft reset the controller and initialize ale */
1385         soft_reset("cpsw", &cpsw->regs->soft_reset);
1386         cpsw_ale_start(cpsw->ale);
1387
1388         /* switch to vlan unaware mode */
1389         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1390                              CPSW_ALE_VLAN_AWARE);
1391         control_reg = readl(&cpsw->regs->control);
1392         control_reg |= CPSW_VLAN_AWARE;
1393         writel(control_reg, &cpsw->regs->control);
1394         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1395                      CPSW_FIFO_NORMAL_MODE;
1396         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1397
1398         /* setup host port priority mapping */
1399         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1400                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1401         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1402
1403         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1404                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1405
1406         if (!cpsw->data.dual_emac) {
1407                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1408                                    0, 0);
1409                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1410                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1411         }
1412 }
1413
1414 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1415 {
1416         struct cpsw_common *cpsw = priv->cpsw;
1417         struct sk_buff *skb;
1418         int ch_buf_num;
1419         int ch, i, ret;
1420
1421         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1422                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1423                 for (i = 0; i < ch_buf_num; i++) {
1424                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1425                                                           cpsw->rx_packet_max,
1426                                                           GFP_KERNEL);
1427                         if (!skb) {
1428                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1429                                 return -ENOMEM;
1430                         }
1431
1432                         skb_set_queue_mapping(skb, ch);
1433                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1434                                                 skb->data, skb_tailroom(skb),
1435                                                 0);
1436                         if (ret < 0) {
1437                                 cpsw_err(priv, ifup,
1438                                          "cannot submit skb to channel %d rx, error %d\n",
1439                                          ch, ret);
1440                                 kfree_skb(skb);
1441                                 return ret;
1442                         }
1443                         kmemleak_not_leak(skb);
1444                 }
1445
1446                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1447                           ch, ch_buf_num);
1448         }
1449
1450         return 0;
1451 }
1452
1453 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1454 {
1455         u32 slave_port;
1456
1457         slave_port = cpsw_get_slave_port(slave->slave_num);
1458
1459         if (!slave->phy)
1460                 return;
1461         phy_stop(slave->phy);
1462         phy_disconnect(slave->phy);
1463         slave->phy = NULL;
1464         cpsw_ale_control_set(cpsw->ale, slave_port,
1465                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1466         soft_reset_slave(slave);
1467 }
1468
1469 static int cpsw_ndo_open(struct net_device *ndev)
1470 {
1471         struct cpsw_priv *priv = netdev_priv(ndev);
1472         struct cpsw_common *cpsw = priv->cpsw;
1473         int ret;
1474         u32 reg;
1475
1476         ret = pm_runtime_get_sync(cpsw->dev);
1477         if (ret < 0) {
1478                 pm_runtime_put_noidle(cpsw->dev);
1479                 return ret;
1480         }
1481
1482         netif_carrier_off(ndev);
1483
1484         /* Notify the stack of the actual queue counts. */
1485         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1486         if (ret) {
1487                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1488                 goto err_cleanup;
1489         }
1490
1491         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1492         if (ret) {
1493                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1494                 goto err_cleanup;
1495         }
1496
1497         reg = cpsw->version;
1498
1499         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1500                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1501                  CPSW_RTL_VERSION(reg));
1502
1503         /* Initialize host and slave ports */
1504         if (!cpsw->usage_count)
1505                 cpsw_init_host_port(priv);
1506         for_each_slave(priv, cpsw_slave_open, priv);
1507
1508         /* Add default VLAN */
1509         if (!cpsw->data.dual_emac)
1510                 cpsw_add_default_vlan(priv);
1511         else
1512                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1513                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1514
1515         /* initialize shared resources for every ndev */
1516         if (!cpsw->usage_count) {
1517                 /* disable priority elevation */
1518                 __raw_writel(0, &cpsw->regs->ptype);
1519
1520                 /* enable statistics collection only on all ports */
1521                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1522
1523                 /* Enable internal fifo flow control */
1524                 writel(0x7, &cpsw->regs->flow_control);
1525
1526                 napi_enable(&cpsw->napi_rx);
1527                 napi_enable(&cpsw->napi_tx);
1528
1529                 if (cpsw->tx_irq_disabled) {
1530                         cpsw->tx_irq_disabled = false;
1531                         enable_irq(cpsw->irqs_table[1]);
1532                 }
1533
1534                 if (cpsw->rx_irq_disabled) {
1535                         cpsw->rx_irq_disabled = false;
1536                         enable_irq(cpsw->irqs_table[0]);
1537                 }
1538
1539                 ret = cpsw_fill_rx_channels(priv);
1540                 if (ret < 0)
1541                         goto err_cleanup;
1542
1543                 if (cpts_register(cpsw->cpts))
1544                         dev_err(priv->dev, "error registering cpts device\n");
1545
1546         }
1547
1548         /* Enable Interrupt pacing if configured */
1549         if (cpsw->coal_intvl != 0) {
1550                 struct ethtool_coalesce coal;
1551
1552                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1553                 cpsw_set_coalesce(ndev, &coal);
1554         }
1555
1556         cpdma_ctlr_start(cpsw->dma);
1557         cpsw_intr_enable(cpsw);
1558         cpsw->usage_count++;
1559
1560         return 0;
1561
1562 err_cleanup:
1563         cpdma_ctlr_stop(cpsw->dma);
1564         for_each_slave(priv, cpsw_slave_stop, cpsw);
1565         pm_runtime_put_sync(cpsw->dev);
1566         netif_carrier_off(priv->ndev);
1567         return ret;
1568 }
1569
1570 static int cpsw_ndo_stop(struct net_device *ndev)
1571 {
1572         struct cpsw_priv *priv = netdev_priv(ndev);
1573         struct cpsw_common *cpsw = priv->cpsw;
1574
1575         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1576         netif_tx_stop_all_queues(priv->ndev);
1577         netif_carrier_off(priv->ndev);
1578
1579         if (cpsw->usage_count <= 1) {
1580                 napi_disable(&cpsw->napi_rx);
1581                 napi_disable(&cpsw->napi_tx);
1582                 cpts_unregister(cpsw->cpts);
1583                 cpsw_intr_disable(cpsw);
1584                 cpdma_ctlr_stop(cpsw->dma);
1585                 cpsw_ale_stop(cpsw->ale);
1586         }
1587         for_each_slave(priv, cpsw_slave_stop, cpsw);
1588
1589         if (cpsw_need_resplit(cpsw))
1590                 cpsw_split_res(ndev);
1591
1592         cpsw->usage_count--;
1593         pm_runtime_put_sync(cpsw->dev);
1594         return 0;
1595 }
1596
1597 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1598                                        struct net_device *ndev)
1599 {
1600         struct cpsw_priv *priv = netdev_priv(ndev);
1601         struct cpsw_common *cpsw = priv->cpsw;
1602         struct cpts *cpts = cpsw->cpts;
1603         struct netdev_queue *txq;
1604         struct cpdma_chan *txch;
1605         int ret, q_idx;
1606
1607         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1608                 cpsw_err(priv, tx_err, "packet pad failed\n");
1609                 ndev->stats.tx_dropped++;
1610                 return NET_XMIT_DROP;
1611         }
1612
1613         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1614             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1615                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1616
1617         q_idx = skb_get_queue_mapping(skb);
1618         if (q_idx >= cpsw->tx_ch_num)
1619                 q_idx = q_idx % cpsw->tx_ch_num;
1620
1621         txch = cpsw->txv[q_idx].ch;
1622         txq = netdev_get_tx_queue(ndev, q_idx);
1623         ret = cpsw_tx_packet_submit(priv, skb, txch);
1624         if (unlikely(ret != 0)) {
1625                 cpsw_err(priv, tx_err, "desc submit failed\n");
1626                 goto fail;
1627         }
1628
1629         /* If there is no more tx desc left free then we need to
1630          * tell the kernel to stop sending us tx frames.
1631          */
1632         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1633                 netif_tx_stop_queue(txq);
1634
1635                 /* Barrier, so that stop_queue visible to other cpus */
1636                 smp_mb__after_atomic();
1637
1638                 if (cpdma_check_free_tx_desc(txch))
1639                         netif_tx_wake_queue(txq);
1640         }
1641
1642         return NETDEV_TX_OK;
1643 fail:
1644         ndev->stats.tx_dropped++;
1645         netif_tx_stop_queue(txq);
1646
1647         /* Barrier, so that stop_queue visible to other cpus */
1648         smp_mb__after_atomic();
1649
1650         if (cpdma_check_free_tx_desc(txch))
1651                 netif_tx_wake_queue(txq);
1652
1653         return NETDEV_TX_BUSY;
1654 }
1655
1656 #if IS_ENABLED(CONFIG_TI_CPTS)
1657
1658 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1659 {
1660         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1661         u32 ts_en, seq_id;
1662
1663         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1664             !cpts_is_rx_enabled(cpsw->cpts)) {
1665                 slave_write(slave, 0, CPSW1_TS_CTL);
1666                 return;
1667         }
1668
1669         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1670         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1671
1672         if (cpts_is_tx_enabled(cpsw->cpts))
1673                 ts_en |= CPSW_V1_TS_TX_EN;
1674
1675         if (cpts_is_rx_enabled(cpsw->cpts))
1676                 ts_en |= CPSW_V1_TS_RX_EN;
1677
1678         slave_write(slave, ts_en, CPSW1_TS_CTL);
1679         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1680 }
1681
1682 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1683 {
1684         struct cpsw_slave *slave;
1685         struct cpsw_common *cpsw = priv->cpsw;
1686         u32 ctrl, mtype;
1687
1688         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1689
1690         ctrl = slave_read(slave, CPSW2_CONTROL);
1691         switch (cpsw->version) {
1692         case CPSW_VERSION_2:
1693                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1694
1695                 if (cpts_is_tx_enabled(cpsw->cpts))
1696                         ctrl |= CTRL_V2_TX_TS_BITS;
1697
1698                 if (cpts_is_rx_enabled(cpsw->cpts))
1699                         ctrl |= CTRL_V2_RX_TS_BITS;
1700                 break;
1701         case CPSW_VERSION_3:
1702         default:
1703                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1704
1705                 if (cpts_is_tx_enabled(cpsw->cpts))
1706                         ctrl |= CTRL_V3_TX_TS_BITS;
1707
1708                 if (cpts_is_rx_enabled(cpsw->cpts))
1709                         ctrl |= CTRL_V3_RX_TS_BITS;
1710                 break;
1711         }
1712
1713         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1714
1715         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1716         slave_write(slave, ctrl, CPSW2_CONTROL);
1717         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1718 }
1719
1720 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1721 {
1722         struct cpsw_priv *priv = netdev_priv(dev);
1723         struct hwtstamp_config cfg;
1724         struct cpsw_common *cpsw = priv->cpsw;
1725         struct cpts *cpts = cpsw->cpts;
1726
1727         if (cpsw->version != CPSW_VERSION_1 &&
1728             cpsw->version != CPSW_VERSION_2 &&
1729             cpsw->version != CPSW_VERSION_3)
1730                 return -EOPNOTSUPP;
1731
1732         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1733                 return -EFAULT;
1734
1735         /* reserved for future extensions */
1736         if (cfg.flags)
1737                 return -EINVAL;
1738
1739         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1740                 return -ERANGE;
1741
1742         switch (cfg.rx_filter) {
1743         case HWTSTAMP_FILTER_NONE:
1744                 cpts_rx_enable(cpts, 0);
1745                 break;
1746         case HWTSTAMP_FILTER_ALL:
1747         case HWTSTAMP_FILTER_NTP_ALL:
1748                 return -ERANGE;
1749         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1750         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1751         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1752                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1753                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1754                 break;
1755         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1756         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1757         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1758         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1759         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1760         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1761         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1762         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1763         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1764                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1765                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1766                 break;
1767         default:
1768                 return -ERANGE;
1769         }
1770
1771         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1772
1773         switch (cpsw->version) {
1774         case CPSW_VERSION_1:
1775                 cpsw_hwtstamp_v1(cpsw);
1776                 break;
1777         case CPSW_VERSION_2:
1778         case CPSW_VERSION_3:
1779                 cpsw_hwtstamp_v2(priv);
1780                 break;
1781         default:
1782                 WARN_ON(1);
1783         }
1784
1785         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1786 }
1787
1788 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1789 {
1790         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1791         struct cpts *cpts = cpsw->cpts;
1792         struct hwtstamp_config cfg;
1793
1794         if (cpsw->version != CPSW_VERSION_1 &&
1795             cpsw->version != CPSW_VERSION_2 &&
1796             cpsw->version != CPSW_VERSION_3)
1797                 return -EOPNOTSUPP;
1798
1799         cfg.flags = 0;
1800         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1801                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1802         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1803                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1804
1805         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1806 }
1807 #else
1808 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1809 {
1810         return -EOPNOTSUPP;
1811 }
1812
1813 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1814 {
1815         return -EOPNOTSUPP;
1816 }
1817 #endif /*CONFIG_TI_CPTS*/
1818
1819 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1820 {
1821         struct cpsw_priv *priv = netdev_priv(dev);
1822         struct cpsw_common *cpsw = priv->cpsw;
1823         int slave_no = cpsw_slave_index(cpsw, priv);
1824
1825         if (!netif_running(dev))
1826                 return -EINVAL;
1827
1828         switch (cmd) {
1829         case SIOCSHWTSTAMP:
1830                 return cpsw_hwtstamp_set(dev, req);
1831         case SIOCGHWTSTAMP:
1832                 return cpsw_hwtstamp_get(dev, req);
1833         }
1834
1835         if (!cpsw->slaves[slave_no].phy)
1836                 return -EOPNOTSUPP;
1837         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1838 }
1839
1840 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1841 {
1842         struct cpsw_priv *priv = netdev_priv(ndev);
1843         struct cpsw_common *cpsw = priv->cpsw;
1844         int ch;
1845
1846         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1847         ndev->stats.tx_errors++;
1848         cpsw_intr_disable(cpsw);
1849         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1850                 cpdma_chan_stop(cpsw->txv[ch].ch);
1851                 cpdma_chan_start(cpsw->txv[ch].ch);
1852         }
1853
1854         cpsw_intr_enable(cpsw);
1855         netif_trans_update(ndev);
1856         netif_tx_wake_all_queues(ndev);
1857 }
1858
1859 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1860 {
1861         struct cpsw_priv *priv = netdev_priv(ndev);
1862         struct sockaddr *addr = (struct sockaddr *)p;
1863         struct cpsw_common *cpsw = priv->cpsw;
1864         int flags = 0;
1865         u16 vid = 0;
1866         int ret;
1867
1868         if (!is_valid_ether_addr(addr->sa_data))
1869                 return -EADDRNOTAVAIL;
1870
1871         ret = pm_runtime_get_sync(cpsw->dev);
1872         if (ret < 0) {
1873                 pm_runtime_put_noidle(cpsw->dev);
1874                 return ret;
1875         }
1876
1877         if (cpsw->data.dual_emac) {
1878                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1879                 flags = ALE_VLAN;
1880         }
1881
1882         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1883                            flags, vid);
1884         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1885                            flags, vid);
1886
1887         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1888         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1889         for_each_slave(priv, cpsw_set_slave_mac, priv);
1890
1891         pm_runtime_put(cpsw->dev);
1892
1893         return 0;
1894 }
1895
1896 #ifdef CONFIG_NET_POLL_CONTROLLER
1897 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1898 {
1899         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1900
1901         cpsw_intr_disable(cpsw);
1902         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1903         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1904         cpsw_intr_enable(cpsw);
1905 }
1906 #endif
1907
1908 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1909                                 unsigned short vid)
1910 {
1911         int ret;
1912         int unreg_mcast_mask = 0;
1913         u32 port_mask;
1914         struct cpsw_common *cpsw = priv->cpsw;
1915
1916         if (cpsw->data.dual_emac) {
1917                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1918
1919                 if (priv->ndev->flags & IFF_ALLMULTI)
1920                         unreg_mcast_mask = port_mask;
1921         } else {
1922                 port_mask = ALE_ALL_PORTS;
1923
1924                 if (priv->ndev->flags & IFF_ALLMULTI)
1925                         unreg_mcast_mask = ALE_ALL_PORTS;
1926                 else
1927                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1928         }
1929
1930         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1931                                 unreg_mcast_mask);
1932         if (ret != 0)
1933                 return ret;
1934
1935         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1936                                  HOST_PORT_NUM, ALE_VLAN, vid);
1937         if (ret != 0)
1938                 goto clean_vid;
1939
1940         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1941                                  port_mask, ALE_VLAN, vid, 0);
1942         if (ret != 0)
1943                 goto clean_vlan_ucast;
1944         return 0;
1945
1946 clean_vlan_ucast:
1947         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1948                            HOST_PORT_NUM, ALE_VLAN, vid);
1949 clean_vid:
1950         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1951         return ret;
1952 }
1953
1954 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1955                                     __be16 proto, u16 vid)
1956 {
1957         struct cpsw_priv *priv = netdev_priv(ndev);
1958         struct cpsw_common *cpsw = priv->cpsw;
1959         int ret;
1960
1961         if (vid == cpsw->data.default_vlan)
1962                 return 0;
1963
1964         ret = pm_runtime_get_sync(cpsw->dev);
1965         if (ret < 0) {
1966                 pm_runtime_put_noidle(cpsw->dev);
1967                 return ret;
1968         }
1969
1970         if (cpsw->data.dual_emac) {
1971                 /* In dual EMAC, reserved VLAN id should not be used for
1972                  * creating VLAN interfaces as this can break the dual
1973                  * EMAC port separation
1974                  */
1975                 int i;
1976
1977                 for (i = 0; i < cpsw->data.slaves; i++) {
1978                         if (vid == cpsw->slaves[i].port_vlan)
1979                                 return -EINVAL;
1980                 }
1981         }
1982
1983         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1984         ret = cpsw_add_vlan_ale_entry(priv, vid);
1985
1986         pm_runtime_put(cpsw->dev);
1987         return ret;
1988 }
1989
1990 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1991                                      __be16 proto, u16 vid)
1992 {
1993         struct cpsw_priv *priv = netdev_priv(ndev);
1994         struct cpsw_common *cpsw = priv->cpsw;
1995         int ret;
1996
1997         if (vid == cpsw->data.default_vlan)
1998                 return 0;
1999
2000         ret = pm_runtime_get_sync(cpsw->dev);
2001         if (ret < 0) {
2002                 pm_runtime_put_noidle(cpsw->dev);
2003                 return ret;
2004         }
2005
2006         if (cpsw->data.dual_emac) {
2007                 int i;
2008
2009                 for (i = 0; i < cpsw->data.slaves; i++) {
2010                         if (vid == cpsw->slaves[i].port_vlan)
2011                                 return -EINVAL;
2012                 }
2013         }
2014
2015         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2016         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2017         if (ret != 0)
2018                 return ret;
2019
2020         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2021                                  HOST_PORT_NUM, ALE_VLAN, vid);
2022         if (ret != 0)
2023                 return ret;
2024
2025         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2026                                  0, ALE_VLAN, vid);
2027         pm_runtime_put(cpsw->dev);
2028         return ret;
2029 }
2030
2031 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2032 {
2033         struct cpsw_priv *priv = netdev_priv(ndev);
2034         struct cpsw_common *cpsw = priv->cpsw;
2035         struct cpsw_slave *slave;
2036         u32 min_rate;
2037         u32 ch_rate;
2038         int i, ret;
2039
2040         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2041         if (ch_rate == rate)
2042                 return 0;
2043
2044         ch_rate = rate * 1000;
2045         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2046         if ((ch_rate < min_rate && ch_rate)) {
2047                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2048                         min_rate);
2049                 return -EINVAL;
2050         }
2051
2052         if (rate > cpsw->speed) {
2053                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2054                 return -EINVAL;
2055         }
2056
2057         ret = pm_runtime_get_sync(cpsw->dev);
2058         if (ret < 0) {
2059                 pm_runtime_put_noidle(cpsw->dev);
2060                 return ret;
2061         }
2062
2063         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2064         pm_runtime_put(cpsw->dev);
2065
2066         if (ret)
2067                 return ret;
2068
2069         /* update rates for slaves tx queues */
2070         for (i = 0; i < cpsw->data.slaves; i++) {
2071                 slave = &cpsw->slaves[i];
2072                 if (!slave->ndev)
2073                         continue;
2074
2075                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2076         }
2077
2078         cpsw_split_res(ndev);
2079         return ret;
2080 }
2081
2082 static const struct net_device_ops cpsw_netdev_ops = {
2083         .ndo_open               = cpsw_ndo_open,
2084         .ndo_stop               = cpsw_ndo_stop,
2085         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2086         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2087         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2088         .ndo_validate_addr      = eth_validate_addr,
2089         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2090         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2091         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2092 #ifdef CONFIG_NET_POLL_CONTROLLER
2093         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2094 #endif
2095         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2096         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2097 };
2098
2099 static int cpsw_get_regs_len(struct net_device *ndev)
2100 {
2101         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2102
2103         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2104 }
2105
2106 static void cpsw_get_regs(struct net_device *ndev,
2107                           struct ethtool_regs *regs, void *p)
2108 {
2109         u32 *reg = p;
2110         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2111
2112         /* update CPSW IP version */
2113         regs->version = cpsw->version;
2114
2115         cpsw_ale_dump(cpsw->ale, reg);
2116 }
2117
2118 static void cpsw_get_drvinfo(struct net_device *ndev,
2119                              struct ethtool_drvinfo *info)
2120 {
2121         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2122         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2123
2124         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2125         strlcpy(info->version, "1.0", sizeof(info->version));
2126         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2127 }
2128
2129 static u32 cpsw_get_msglevel(struct net_device *ndev)
2130 {
2131         struct cpsw_priv *priv = netdev_priv(ndev);
2132         return priv->msg_enable;
2133 }
2134
2135 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2136 {
2137         struct cpsw_priv *priv = netdev_priv(ndev);
2138         priv->msg_enable = value;
2139 }
2140
2141 #if IS_ENABLED(CONFIG_TI_CPTS)
2142 static int cpsw_get_ts_info(struct net_device *ndev,
2143                             struct ethtool_ts_info *info)
2144 {
2145         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2146
2147         info->so_timestamping =
2148                 SOF_TIMESTAMPING_TX_HARDWARE |
2149                 SOF_TIMESTAMPING_TX_SOFTWARE |
2150                 SOF_TIMESTAMPING_RX_HARDWARE |
2151                 SOF_TIMESTAMPING_RX_SOFTWARE |
2152                 SOF_TIMESTAMPING_SOFTWARE |
2153                 SOF_TIMESTAMPING_RAW_HARDWARE;
2154         info->phc_index = cpsw->cpts->phc_index;
2155         info->tx_types =
2156                 (1 << HWTSTAMP_TX_OFF) |
2157                 (1 << HWTSTAMP_TX_ON);
2158         info->rx_filters =
2159                 (1 << HWTSTAMP_FILTER_NONE) |
2160                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2161                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2162         return 0;
2163 }
2164 #else
2165 static int cpsw_get_ts_info(struct net_device *ndev,
2166                             struct ethtool_ts_info *info)
2167 {
2168         info->so_timestamping =
2169                 SOF_TIMESTAMPING_TX_SOFTWARE |
2170                 SOF_TIMESTAMPING_RX_SOFTWARE |
2171                 SOF_TIMESTAMPING_SOFTWARE;
2172         info->phc_index = -1;
2173         info->tx_types = 0;
2174         info->rx_filters = 0;
2175         return 0;
2176 }
2177 #endif
2178
2179 static int cpsw_get_link_ksettings(struct net_device *ndev,
2180                                    struct ethtool_link_ksettings *ecmd)
2181 {
2182         struct cpsw_priv *priv = netdev_priv(ndev);
2183         struct cpsw_common *cpsw = priv->cpsw;
2184         int slave_no = cpsw_slave_index(cpsw, priv);
2185
2186         if (!cpsw->slaves[slave_no].phy)
2187                 return -EOPNOTSUPP;
2188
2189         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2190         return 0;
2191 }
2192
2193 static int cpsw_set_link_ksettings(struct net_device *ndev,
2194                                    const struct ethtool_link_ksettings *ecmd)
2195 {
2196         struct cpsw_priv *priv = netdev_priv(ndev);
2197         struct cpsw_common *cpsw = priv->cpsw;
2198         int slave_no = cpsw_slave_index(cpsw, priv);
2199
2200         if (cpsw->slaves[slave_no].phy)
2201                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2202                                                  ecmd);
2203         else
2204                 return -EOPNOTSUPP;
2205 }
2206
2207 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2208 {
2209         struct cpsw_priv *priv = netdev_priv(ndev);
2210         struct cpsw_common *cpsw = priv->cpsw;
2211         int slave_no = cpsw_slave_index(cpsw, priv);
2212
2213         wol->supported = 0;
2214         wol->wolopts = 0;
2215
2216         if (cpsw->slaves[slave_no].phy)
2217                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2218 }
2219
2220 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2221 {
2222         struct cpsw_priv *priv = netdev_priv(ndev);
2223         struct cpsw_common *cpsw = priv->cpsw;
2224         int slave_no = cpsw_slave_index(cpsw, priv);
2225
2226         if (cpsw->slaves[slave_no].phy)
2227                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2228         else
2229                 return -EOPNOTSUPP;
2230 }
2231
2232 static void cpsw_get_pauseparam(struct net_device *ndev,
2233                                 struct ethtool_pauseparam *pause)
2234 {
2235         struct cpsw_priv *priv = netdev_priv(ndev);
2236
2237         pause->autoneg = AUTONEG_DISABLE;
2238         pause->rx_pause = priv->rx_pause ? true : false;
2239         pause->tx_pause = priv->tx_pause ? true : false;
2240 }
2241
2242 static int cpsw_set_pauseparam(struct net_device *ndev,
2243                                struct ethtool_pauseparam *pause)
2244 {
2245         struct cpsw_priv *priv = netdev_priv(ndev);
2246         bool link;
2247
2248         priv->rx_pause = pause->rx_pause ? true : false;
2249         priv->tx_pause = pause->tx_pause ? true : false;
2250
2251         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2252         return 0;
2253 }
2254
2255 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2256 {
2257         struct cpsw_priv *priv = netdev_priv(ndev);
2258         struct cpsw_common *cpsw = priv->cpsw;
2259         int ret;
2260
2261         ret = pm_runtime_get_sync(cpsw->dev);
2262         if (ret < 0) {
2263                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2264                 pm_runtime_put_noidle(cpsw->dev);
2265         }
2266
2267         return ret;
2268 }
2269
2270 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2271 {
2272         struct cpsw_priv *priv = netdev_priv(ndev);
2273         int ret;
2274
2275         ret = pm_runtime_put(priv->cpsw->dev);
2276         if (ret < 0)
2277                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2278 }
2279
2280 static void cpsw_get_channels(struct net_device *ndev,
2281                               struct ethtool_channels *ch)
2282 {
2283         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2284
2285         ch->max_combined = 0;
2286         ch->max_rx = CPSW_MAX_QUEUES;
2287         ch->max_tx = CPSW_MAX_QUEUES;
2288         ch->max_other = 0;
2289         ch->other_count = 0;
2290         ch->rx_count = cpsw->rx_ch_num;
2291         ch->tx_count = cpsw->tx_ch_num;
2292         ch->combined_count = 0;
2293 }
2294
2295 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2296                                   struct ethtool_channels *ch)
2297 {
2298         if (ch->combined_count)
2299                 return -EINVAL;
2300
2301         /* verify we have at least one channel in each direction */
2302         if (!ch->rx_count || !ch->tx_count)
2303                 return -EINVAL;
2304
2305         if (ch->rx_count > cpsw->data.channels ||
2306             ch->tx_count > cpsw->data.channels)
2307                 return -EINVAL;
2308
2309         return 0;
2310 }
2311
2312 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2313 {
2314         int (*poll)(struct napi_struct *, int);
2315         struct cpsw_common *cpsw = priv->cpsw;
2316         void (*handler)(void *, int, int);
2317         struct netdev_queue *queue;
2318         struct cpsw_vector *vec;
2319         int ret, *ch;
2320
2321         if (rx) {
2322                 ch = &cpsw->rx_ch_num;
2323                 vec = cpsw->rxv;
2324                 handler = cpsw_rx_handler;
2325                 poll = cpsw_rx_poll;
2326         } else {
2327                 ch = &cpsw->tx_ch_num;
2328                 vec = cpsw->txv;
2329                 handler = cpsw_tx_handler;
2330                 poll = cpsw_tx_poll;
2331         }
2332
2333         while (*ch < ch_num) {
2334                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2335                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2336                 queue->tx_maxrate = 0;
2337
2338                 if (IS_ERR(vec[*ch].ch))
2339                         return PTR_ERR(vec[*ch].ch);
2340
2341                 if (!vec[*ch].ch)
2342                         return -EINVAL;
2343
2344                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2345                           (rx ? "rx" : "tx"));
2346                 (*ch)++;
2347         }
2348
2349         while (*ch > ch_num) {
2350                 (*ch)--;
2351
2352                 ret = cpdma_chan_destroy(vec[*ch].ch);
2353                 if (ret)
2354                         return ret;
2355
2356                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2357                           (rx ? "rx" : "tx"));
2358         }
2359
2360         return 0;
2361 }
2362
2363 static int cpsw_update_channels(struct cpsw_priv *priv,
2364                                 struct ethtool_channels *ch)
2365 {
2366         int ret;
2367
2368         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2369         if (ret)
2370                 return ret;
2371
2372         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2373         if (ret)
2374                 return ret;
2375
2376         return 0;
2377 }
2378
2379 static void cpsw_suspend_data_pass(struct net_device *ndev)
2380 {
2381         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2382         struct cpsw_slave *slave;
2383         int i;
2384
2385         /* Disable NAPI scheduling */
2386         cpsw_intr_disable(cpsw);
2387
2388         /* Stop all transmit queues for every network device.
2389          * Disable re-using rx descriptors with dormant_on.
2390          */
2391         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2392                 if (!(slave->ndev && netif_running(slave->ndev)))
2393                         continue;
2394
2395                 netif_tx_stop_all_queues(slave->ndev);
2396                 netif_dormant_on(slave->ndev);
2397         }
2398
2399         /* Handle rest of tx packets and stop cpdma channels */
2400         cpdma_ctlr_stop(cpsw->dma);
2401 }
2402
2403 static int cpsw_resume_data_pass(struct net_device *ndev)
2404 {
2405         struct cpsw_priv *priv = netdev_priv(ndev);
2406         struct cpsw_common *cpsw = priv->cpsw;
2407         struct cpsw_slave *slave;
2408         int i, ret;
2409
2410         /* Allow rx packets handling */
2411         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2412                 if (slave->ndev && netif_running(slave->ndev))
2413                         netif_dormant_off(slave->ndev);
2414
2415         /* After this receive is started */
2416         if (cpsw->usage_count) {
2417                 ret = cpsw_fill_rx_channels(priv);
2418                 if (ret)
2419                         return ret;
2420
2421                 cpdma_ctlr_start(cpsw->dma);
2422                 cpsw_intr_enable(cpsw);
2423         }
2424
2425         /* Resume transmit for every affected interface */
2426         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2427                 if (slave->ndev && netif_running(slave->ndev))
2428                         netif_tx_start_all_queues(slave->ndev);
2429
2430         return 0;
2431 }
2432
2433 static int cpsw_set_channels(struct net_device *ndev,
2434                              struct ethtool_channels *chs)
2435 {
2436         struct cpsw_priv *priv = netdev_priv(ndev);
2437         struct cpsw_common *cpsw = priv->cpsw;
2438         struct cpsw_slave *slave;
2439         int i, ret;
2440
2441         ret = cpsw_check_ch_settings(cpsw, chs);
2442         if (ret < 0)
2443                 return ret;
2444
2445         cpsw_suspend_data_pass(ndev);
2446         ret = cpsw_update_channels(priv, chs);
2447         if (ret)
2448                 goto err;
2449
2450         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2451                 if (!(slave->ndev && netif_running(slave->ndev)))
2452                         continue;
2453
2454                 /* Inform stack about new count of queues */
2455                 ret = netif_set_real_num_tx_queues(slave->ndev,
2456                                                    cpsw->tx_ch_num);
2457                 if (ret) {
2458                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2459                         goto err;
2460                 }
2461
2462                 ret = netif_set_real_num_rx_queues(slave->ndev,
2463                                                    cpsw->rx_ch_num);
2464                 if (ret) {
2465                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2466                         goto err;
2467                 }
2468         }
2469
2470         if (cpsw->usage_count)
2471                 cpsw_split_res(ndev);
2472
2473         ret = cpsw_resume_data_pass(ndev);
2474         if (!ret)
2475                 return 0;
2476 err:
2477         dev_err(priv->dev, "cannot update channels number, closing device\n");
2478         dev_close(ndev);
2479         return ret;
2480 }
2481
2482 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2483 {
2484         struct cpsw_priv *priv = netdev_priv(ndev);
2485         struct cpsw_common *cpsw = priv->cpsw;
2486         int slave_no = cpsw_slave_index(cpsw, priv);
2487
2488         if (cpsw->slaves[slave_no].phy)
2489                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2490         else
2491                 return -EOPNOTSUPP;
2492 }
2493
2494 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2495 {
2496         struct cpsw_priv *priv = netdev_priv(ndev);
2497         struct cpsw_common *cpsw = priv->cpsw;
2498         int slave_no = cpsw_slave_index(cpsw, priv);
2499
2500         if (cpsw->slaves[slave_no].phy)
2501                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2502         else
2503                 return -EOPNOTSUPP;
2504 }
2505
2506 static int cpsw_nway_reset(struct net_device *ndev)
2507 {
2508         struct cpsw_priv *priv = netdev_priv(ndev);
2509         struct cpsw_common *cpsw = priv->cpsw;
2510         int slave_no = cpsw_slave_index(cpsw, priv);
2511
2512         if (cpsw->slaves[slave_no].phy)
2513                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2514         else
2515                 return -EOPNOTSUPP;
2516 }
2517
2518 static void cpsw_get_ringparam(struct net_device *ndev,
2519                                struct ethtool_ringparam *ering)
2520 {
2521         struct cpsw_priv *priv = netdev_priv(ndev);
2522         struct cpsw_common *cpsw = priv->cpsw;
2523
2524         /* not supported */
2525         ering->tx_max_pending = 0;
2526         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2527         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2528         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2529 }
2530
2531 static int cpsw_set_ringparam(struct net_device *ndev,
2532                               struct ethtool_ringparam *ering)
2533 {
2534         struct cpsw_priv *priv = netdev_priv(ndev);
2535         struct cpsw_common *cpsw = priv->cpsw;
2536         int ret;
2537
2538         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2539
2540         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2541             ering->rx_pending < CPSW_MAX_QUEUES ||
2542             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2543                 return -EINVAL;
2544
2545         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2546                 return 0;
2547
2548         cpsw_suspend_data_pass(ndev);
2549
2550         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2551
2552         if (cpsw->usage_count)
2553                 cpdma_chan_split_pool(cpsw->dma);
2554
2555         ret = cpsw_resume_data_pass(ndev);
2556         if (!ret)
2557                 return 0;
2558
2559         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2560         dev_close(ndev);
2561         return ret;
2562 }
2563
2564 static const struct ethtool_ops cpsw_ethtool_ops = {
2565         .get_drvinfo    = cpsw_get_drvinfo,
2566         .get_msglevel   = cpsw_get_msglevel,
2567         .set_msglevel   = cpsw_set_msglevel,
2568         .get_link       = ethtool_op_get_link,
2569         .get_ts_info    = cpsw_get_ts_info,
2570         .get_coalesce   = cpsw_get_coalesce,
2571         .set_coalesce   = cpsw_set_coalesce,
2572         .get_sset_count         = cpsw_get_sset_count,
2573         .get_strings            = cpsw_get_strings,
2574         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2575         .get_pauseparam         = cpsw_get_pauseparam,
2576         .set_pauseparam         = cpsw_set_pauseparam,
2577         .get_wol        = cpsw_get_wol,
2578         .set_wol        = cpsw_set_wol,
2579         .get_regs_len   = cpsw_get_regs_len,
2580         .get_regs       = cpsw_get_regs,
2581         .begin          = cpsw_ethtool_op_begin,
2582         .complete       = cpsw_ethtool_op_complete,
2583         .get_channels   = cpsw_get_channels,
2584         .set_channels   = cpsw_set_channels,
2585         .get_link_ksettings     = cpsw_get_link_ksettings,
2586         .set_link_ksettings     = cpsw_set_link_ksettings,
2587         .get_eee        = cpsw_get_eee,
2588         .set_eee        = cpsw_set_eee,
2589         .nway_reset     = cpsw_nway_reset,
2590         .get_ringparam = cpsw_get_ringparam,
2591         .set_ringparam = cpsw_set_ringparam,
2592 };
2593
2594 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2595                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2596 {
2597         void __iomem            *regs = cpsw->regs;
2598         int                     slave_num = slave->slave_num;
2599         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2600
2601         slave->data     = data;
2602         slave->regs     = regs + slave_reg_ofs;
2603         slave->sliver   = regs + sliver_reg_ofs;
2604         slave->port_vlan = data->dual_emac_res_vlan;
2605 }
2606
2607 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2608                          struct platform_device *pdev)
2609 {
2610         struct device_node *node = pdev->dev.of_node;
2611         struct device_node *slave_node;
2612         int i = 0, ret;
2613         u32 prop;
2614
2615         if (!node)
2616                 return -EINVAL;
2617
2618         if (of_property_read_u32(node, "slaves", &prop)) {
2619                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2620                 return -EINVAL;
2621         }
2622         data->slaves = prop;
2623
2624         if (of_property_read_u32(node, "active_slave", &prop)) {
2625                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2626                 return -EINVAL;
2627         }
2628         data->active_slave = prop;
2629
2630         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2631                                         * sizeof(struct cpsw_slave_data),
2632                                         GFP_KERNEL);
2633         if (!data->slave_data)
2634                 return -ENOMEM;
2635
2636         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2637                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2638                 return -EINVAL;
2639         }
2640         data->channels = prop;
2641
2642         if (of_property_read_u32(node, "ale_entries", &prop)) {
2643                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2644                 return -EINVAL;
2645         }
2646         data->ale_entries = prop;
2647
2648         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2649                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2650                 return -EINVAL;
2651         }
2652         data->bd_ram_size = prop;
2653
2654         if (of_property_read_u32(node, "mac_control", &prop)) {
2655                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2656                 return -EINVAL;
2657         }
2658         data->mac_control = prop;
2659
2660         if (of_property_read_bool(node, "dual_emac"))
2661                 data->dual_emac = 1;
2662
2663         /*
2664          * Populate all the child nodes here...
2665          */
2666         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2667         /* We do not want to force this, as in some cases may not have child */
2668         if (ret)
2669                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2670
2671         for_each_available_child_of_node(node, slave_node) {
2672                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2673                 const void *mac_addr = NULL;
2674                 int lenp;
2675                 const __be32 *parp;
2676
2677                 /* This is no slave child node, continue */
2678                 if (strcmp(slave_node->name, "slave"))
2679                         continue;
2680
2681                 slave_data->phy_node = of_parse_phandle(slave_node,
2682                                                         "phy-handle", 0);
2683                 parp = of_get_property(slave_node, "phy_id", &lenp);
2684                 if (slave_data->phy_node) {
2685                         dev_dbg(&pdev->dev,
2686                                 "slave[%d] using phy-handle=\"%pOF\"\n",
2687                                 i, slave_data->phy_node);
2688                 } else if (of_phy_is_fixed_link(slave_node)) {
2689                         /* In the case of a fixed PHY, the DT node associated
2690                          * to the PHY is the Ethernet MAC DT node.
2691                          */
2692                         ret = of_phy_register_fixed_link(slave_node);
2693                         if (ret) {
2694                                 if (ret != -EPROBE_DEFER)
2695                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2696                                 return ret;
2697                         }
2698                         slave_data->phy_node = of_node_get(slave_node);
2699                 } else if (parp) {
2700                         u32 phyid;
2701                         struct device_node *mdio_node;
2702                         struct platform_device *mdio;
2703
2704                         if (lenp != (sizeof(__be32) * 2)) {
2705                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2706                                 goto no_phy_slave;
2707                         }
2708                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2709                         phyid = be32_to_cpup(parp+1);
2710                         mdio = of_find_device_by_node(mdio_node);
2711                         of_node_put(mdio_node);
2712                         if (!mdio) {
2713                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2714                                 return -EINVAL;
2715                         }
2716                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2717                                  PHY_ID_FMT, mdio->name, phyid);
2718                         put_device(&mdio->dev);
2719                 } else {
2720                         dev_err(&pdev->dev,
2721                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2722                                 i);
2723                         goto no_phy_slave;
2724                 }
2725                 slave_data->phy_if = of_get_phy_mode(slave_node);
2726                 if (slave_data->phy_if < 0) {
2727                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2728                                 i);
2729                         return slave_data->phy_if;
2730                 }
2731
2732 no_phy_slave:
2733                 mac_addr = of_get_mac_address(slave_node);
2734                 if (mac_addr) {
2735                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2736                 } else {
2737                         ret = ti_cm_get_macid(&pdev->dev, i,
2738                                               slave_data->mac_addr);
2739                         if (ret)
2740                                 return ret;
2741                 }
2742                 if (data->dual_emac) {
2743                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2744                                                  &prop)) {
2745                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2746                                 slave_data->dual_emac_res_vlan = i+1;
2747                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2748                                         slave_data->dual_emac_res_vlan, i);
2749                         } else {
2750                                 slave_data->dual_emac_res_vlan = prop;
2751                         }
2752                 }
2753
2754                 i++;
2755                 if (i == data->slaves)
2756                         break;
2757         }
2758
2759         return 0;
2760 }
2761
2762 static void cpsw_remove_dt(struct platform_device *pdev)
2763 {
2764         struct net_device *ndev = platform_get_drvdata(pdev);
2765         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2766         struct cpsw_platform_data *data = &cpsw->data;
2767         struct device_node *node = pdev->dev.of_node;
2768         struct device_node *slave_node;
2769         int i = 0;
2770
2771         for_each_available_child_of_node(node, slave_node) {
2772                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2773
2774                 if (strcmp(slave_node->name, "slave"))
2775                         continue;
2776
2777                 if (of_phy_is_fixed_link(slave_node))
2778                         of_phy_deregister_fixed_link(slave_node);
2779
2780                 of_node_put(slave_data->phy_node);
2781
2782                 i++;
2783                 if (i == data->slaves)
2784                         break;
2785         }
2786
2787         of_platform_depopulate(&pdev->dev);
2788 }
2789
2790 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2791 {
2792         struct cpsw_common              *cpsw = priv->cpsw;
2793         struct cpsw_platform_data       *data = &cpsw->data;
2794         struct net_device               *ndev;
2795         struct cpsw_priv                *priv_sl2;
2796         int ret = 0;
2797
2798         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2799         if (!ndev) {
2800                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2801                 return -ENOMEM;
2802         }
2803
2804         priv_sl2 = netdev_priv(ndev);
2805         priv_sl2->cpsw = cpsw;
2806         priv_sl2->ndev = ndev;
2807         priv_sl2->dev  = &ndev->dev;
2808         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2809
2810         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2811                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2812                         ETH_ALEN);
2813                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2814                          priv_sl2->mac_addr);
2815         } else {
2816                 random_ether_addr(priv_sl2->mac_addr);
2817                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2818                          priv_sl2->mac_addr);
2819         }
2820         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2821
2822         priv_sl2->emac_port = 1;
2823         cpsw->slaves[1].ndev = ndev;
2824         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2825
2826         ndev->netdev_ops = &cpsw_netdev_ops;
2827         ndev->ethtool_ops = &cpsw_ethtool_ops;
2828
2829         /* register the network device */
2830         SET_NETDEV_DEV(ndev, cpsw->dev);
2831         ret = register_netdev(ndev);
2832         if (ret) {
2833                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2834                 free_netdev(ndev);
2835                 ret = -ENODEV;
2836         }
2837
2838         return ret;
2839 }
2840
2841 #define CPSW_QUIRK_IRQ          BIT(0)
2842
2843 static const struct platform_device_id cpsw_devtype[] = {
2844         {
2845                 /* keep it for existing comaptibles */
2846                 .name = "cpsw",
2847                 .driver_data = CPSW_QUIRK_IRQ,
2848         }, {
2849                 .name = "am335x-cpsw",
2850                 .driver_data = CPSW_QUIRK_IRQ,
2851         }, {
2852                 .name = "am4372-cpsw",
2853                 .driver_data = 0,
2854         }, {
2855                 .name = "dra7-cpsw",
2856                 .driver_data = 0,
2857         }, {
2858                 /* sentinel */
2859         }
2860 };
2861 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2862
2863 enum ti_cpsw_type {
2864         CPSW = 0,
2865         AM335X_CPSW,
2866         AM4372_CPSW,
2867         DRA7_CPSW,
2868 };
2869
2870 static const struct of_device_id cpsw_of_mtable[] = {
2871         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2872         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2873         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2874         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2875         { /* sentinel */ },
2876 };
2877 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2878
2879 static int cpsw_probe(struct platform_device *pdev)
2880 {
2881         struct clk                      *clk;
2882         struct cpsw_platform_data       *data;
2883         struct net_device               *ndev;
2884         struct cpsw_priv                *priv;
2885         struct cpdma_params             dma_params;
2886         struct cpsw_ale_params          ale_params;
2887         void __iomem                    *ss_regs;
2888         void __iomem                    *cpts_regs;
2889         struct resource                 *res, *ss_res;
2890         const struct of_device_id       *of_id;
2891         struct gpio_descs               *mode;
2892         u32 slave_offset, sliver_offset, slave_size;
2893         struct cpsw_common              *cpsw;
2894         int ret = 0, i;
2895         int irq;
2896
2897         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2898         if (!cpsw)
2899                 return -ENOMEM;
2900
2901         cpsw->dev = &pdev->dev;
2902
2903         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2904         if (!ndev) {
2905                 dev_err(&pdev->dev, "error allocating net_device\n");
2906                 return -ENOMEM;
2907         }
2908
2909         platform_set_drvdata(pdev, ndev);
2910         priv = netdev_priv(ndev);
2911         priv->cpsw = cpsw;
2912         priv->ndev = ndev;
2913         priv->dev  = &ndev->dev;
2914         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2915         cpsw->rx_packet_max = max(rx_packet_max, 128);
2916
2917         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2918         if (IS_ERR(mode)) {
2919                 ret = PTR_ERR(mode);
2920                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2921                 goto clean_ndev_ret;
2922         }
2923
2924         /*
2925          * This may be required here for child devices.
2926          */
2927         pm_runtime_enable(&pdev->dev);
2928
2929         /* Select default pin state */
2930         pinctrl_pm_select_default_state(&pdev->dev);
2931
2932         /* Need to enable clocks with runtime PM api to access module
2933          * registers
2934          */
2935         ret = pm_runtime_get_sync(&pdev->dev);
2936         if (ret < 0) {
2937                 pm_runtime_put_noidle(&pdev->dev);
2938                 goto clean_runtime_disable_ret;
2939         }
2940
2941         ret = cpsw_probe_dt(&cpsw->data, pdev);
2942         if (ret)
2943                 goto clean_dt_ret;
2944
2945         data = &cpsw->data;
2946         cpsw->rx_ch_num = 1;
2947         cpsw->tx_ch_num = 1;
2948
2949         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2950                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2951                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2952         } else {
2953                 eth_random_addr(priv->mac_addr);
2954                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2955         }
2956
2957         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2958
2959         cpsw->slaves = devm_kzalloc(&pdev->dev,
2960                                     sizeof(struct cpsw_slave) * data->slaves,
2961                                     GFP_KERNEL);
2962         if (!cpsw->slaves) {
2963                 ret = -ENOMEM;
2964                 goto clean_dt_ret;
2965         }
2966         for (i = 0; i < data->slaves; i++)
2967                 cpsw->slaves[i].slave_num = i;
2968
2969         cpsw->slaves[0].ndev = ndev;
2970         priv->emac_port = 0;
2971
2972         clk = devm_clk_get(&pdev->dev, "fck");
2973         if (IS_ERR(clk)) {
2974                 dev_err(priv->dev, "fck is not found\n");
2975                 ret = -ENODEV;
2976                 goto clean_dt_ret;
2977         }
2978         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2979
2980         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2981         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2982         if (IS_ERR(ss_regs)) {
2983                 ret = PTR_ERR(ss_regs);
2984                 goto clean_dt_ret;
2985         }
2986         cpsw->regs = ss_regs;
2987
2988         cpsw->version = readl(&cpsw->regs->id_ver);
2989
2990         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2991         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2992         if (IS_ERR(cpsw->wr_regs)) {
2993                 ret = PTR_ERR(cpsw->wr_regs);
2994                 goto clean_dt_ret;
2995         }
2996
2997         memset(&dma_params, 0, sizeof(dma_params));
2998         memset(&ale_params, 0, sizeof(ale_params));
2999
3000         switch (cpsw->version) {
3001         case CPSW_VERSION_1:
3002                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3003                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3004                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3005                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3006                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3007                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3008                 slave_offset         = CPSW1_SLAVE_OFFSET;
3009                 slave_size           = CPSW1_SLAVE_SIZE;
3010                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3011                 dma_params.desc_mem_phys = 0;
3012                 break;
3013         case CPSW_VERSION_2:
3014         case CPSW_VERSION_3:
3015         case CPSW_VERSION_4:
3016                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3017                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3018                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3019                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3020                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3021                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3022                 slave_offset         = CPSW2_SLAVE_OFFSET;
3023                 slave_size           = CPSW2_SLAVE_SIZE;
3024                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3025                 dma_params.desc_mem_phys =
3026                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3027                 break;
3028         default:
3029                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3030                 ret = -ENODEV;
3031                 goto clean_dt_ret;
3032         }
3033         for (i = 0; i < cpsw->data.slaves; i++) {
3034                 struct cpsw_slave *slave = &cpsw->slaves[i];
3035
3036                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3037                 slave_offset  += slave_size;
3038                 sliver_offset += SLIVER_SIZE;
3039         }
3040
3041         dma_params.dev          = &pdev->dev;
3042         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3043         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3044         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3045         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3046         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3047
3048         dma_params.num_chan             = data->channels;
3049         dma_params.has_soft_reset       = true;
3050         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3051         dma_params.desc_mem_size        = data->bd_ram_size;
3052         dma_params.desc_align           = 16;
3053         dma_params.has_ext_regs         = true;
3054         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3055         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3056         dma_params.descs_pool_size      = descs_pool_size;
3057
3058         cpsw->dma = cpdma_ctlr_create(&dma_params);
3059         if (!cpsw->dma) {
3060                 dev_err(priv->dev, "error initializing dma\n");
3061                 ret = -ENOMEM;
3062                 goto clean_dt_ret;
3063         }
3064
3065         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3066         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3067         if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
3068                 dev_err(priv->dev, "error initializing dma channels\n");
3069                 ret = -ENOMEM;
3070                 goto clean_dma_ret;
3071         }
3072
3073         ale_params.dev                  = &pdev->dev;
3074         ale_params.ale_ageout           = ale_ageout;
3075         ale_params.ale_entries          = data->ale_entries;
3076         ale_params.ale_ports            = data->slaves;
3077
3078         cpsw->ale = cpsw_ale_create(&ale_params);
3079         if (!cpsw->ale) {
3080                 dev_err(priv->dev, "error initializing ale engine\n");
3081                 ret = -ENODEV;
3082                 goto clean_dma_ret;
3083         }
3084
3085         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3086         if (IS_ERR(cpsw->cpts)) {
3087                 ret = PTR_ERR(cpsw->cpts);
3088                 goto clean_ale_ret;
3089         }
3090
3091         ndev->irq = platform_get_irq(pdev, 1);
3092         if (ndev->irq < 0) {
3093                 dev_err(priv->dev, "error getting irq resource\n");
3094                 ret = ndev->irq;
3095                 goto clean_ale_ret;
3096         }
3097
3098         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3099         if (of_id) {
3100                 pdev->id_entry = of_id->data;
3101                 if (pdev->id_entry->driver_data)
3102                         cpsw->quirk_irq = true;
3103         }
3104
3105         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3106
3107         ndev->netdev_ops = &cpsw_netdev_ops;
3108         ndev->ethtool_ops = &cpsw_ethtool_ops;
3109         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3110         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3111         cpsw_split_res(ndev);
3112
3113         /* register the network device */
3114         SET_NETDEV_DEV(ndev, &pdev->dev);
3115         ret = register_netdev(ndev);
3116         if (ret) {
3117                 dev_err(priv->dev, "error registering net device\n");
3118                 ret = -ENODEV;
3119                 goto clean_ale_ret;
3120         }
3121
3122         if (cpsw->data.dual_emac) {
3123                 ret = cpsw_probe_dual_emac(priv);
3124                 if (ret) {
3125                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3126                         goto clean_unregister_netdev_ret;
3127                 }
3128         }
3129
3130         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3131          * MISC IRQs which are always kept disabled with this driver so
3132          * we will not request them.
3133          *
3134          * If anyone wants to implement support for those, make sure to
3135          * first request and append them to irqs_table array.
3136          */
3137
3138         /* RX IRQ */
3139         irq = platform_get_irq(pdev, 1);
3140         if (irq < 0) {
3141                 ret = irq;
3142                 goto clean_ale_ret;
3143         }
3144
3145         cpsw->irqs_table[0] = irq;
3146         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3147                                0, dev_name(&pdev->dev), cpsw);
3148         if (ret < 0) {
3149                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3150                 goto clean_ale_ret;
3151         }
3152
3153         /* TX IRQ */
3154         irq = platform_get_irq(pdev, 2);
3155         if (irq < 0) {
3156                 ret = irq;
3157                 goto clean_ale_ret;
3158         }
3159
3160         cpsw->irqs_table[1] = irq;
3161         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3162                                0, dev_name(&pdev->dev), cpsw);
3163         if (ret < 0) {
3164                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3165                 goto clean_ale_ret;
3166         }
3167
3168         cpsw_notice(priv, probe,
3169                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3170                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3171
3172         pm_runtime_put(&pdev->dev);
3173
3174         return 0;
3175
3176 clean_unregister_netdev_ret:
3177         unregister_netdev(ndev);
3178 clean_ale_ret:
3179         cpsw_ale_destroy(cpsw->ale);
3180 clean_dma_ret:
3181         cpdma_ctlr_destroy(cpsw->dma);
3182 clean_dt_ret:
3183         cpsw_remove_dt(pdev);
3184         pm_runtime_put_sync(&pdev->dev);
3185 clean_runtime_disable_ret:
3186         pm_runtime_disable(&pdev->dev);
3187 clean_ndev_ret:
3188         free_netdev(priv->ndev);
3189         return ret;
3190 }
3191
3192 static int cpsw_remove(struct platform_device *pdev)
3193 {
3194         struct net_device *ndev = platform_get_drvdata(pdev);
3195         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3196         int ret;
3197
3198         ret = pm_runtime_get_sync(&pdev->dev);
3199         if (ret < 0) {
3200                 pm_runtime_put_noidle(&pdev->dev);
3201                 return ret;
3202         }
3203
3204         if (cpsw->data.dual_emac)
3205                 unregister_netdev(cpsw->slaves[1].ndev);
3206         unregister_netdev(ndev);
3207
3208         cpts_release(cpsw->cpts);
3209         cpsw_ale_destroy(cpsw->ale);
3210         cpdma_ctlr_destroy(cpsw->dma);
3211         cpsw_remove_dt(pdev);
3212         pm_runtime_put_sync(&pdev->dev);
3213         pm_runtime_disable(&pdev->dev);
3214         if (cpsw->data.dual_emac)
3215                 free_netdev(cpsw->slaves[1].ndev);
3216         free_netdev(ndev);
3217         return 0;
3218 }
3219
3220 #ifdef CONFIG_PM_SLEEP
3221 static int cpsw_suspend(struct device *dev)
3222 {
3223         struct platform_device  *pdev = to_platform_device(dev);
3224         struct net_device       *ndev = platform_get_drvdata(pdev);
3225         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3226
3227         if (cpsw->data.dual_emac) {
3228                 int i;
3229
3230                 for (i = 0; i < cpsw->data.slaves; i++) {
3231                         if (netif_running(cpsw->slaves[i].ndev))
3232                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3233                 }
3234         } else {
3235                 if (netif_running(ndev))
3236                         cpsw_ndo_stop(ndev);
3237         }
3238
3239         /* Select sleep pin state */
3240         pinctrl_pm_select_sleep_state(dev);
3241
3242         return 0;
3243 }
3244
3245 static int cpsw_resume(struct device *dev)
3246 {
3247         struct platform_device  *pdev = to_platform_device(dev);
3248         struct net_device       *ndev = platform_get_drvdata(pdev);
3249         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3250
3251         /* Select default pin state */
3252         pinctrl_pm_select_default_state(dev);
3253
3254         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3255         rtnl_lock();
3256         if (cpsw->data.dual_emac) {
3257                 int i;
3258
3259                 for (i = 0; i < cpsw->data.slaves; i++) {
3260                         if (netif_running(cpsw->slaves[i].ndev))
3261                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3262                 }
3263         } else {
3264                 if (netif_running(ndev))
3265                         cpsw_ndo_open(ndev);
3266         }
3267         rtnl_unlock();
3268
3269         return 0;
3270 }
3271 #endif
3272
3273 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3274
3275 static struct platform_driver cpsw_driver = {
3276         .driver = {
3277                 .name    = "cpsw",
3278                 .pm      = &cpsw_pm_ops,
3279                 .of_match_table = cpsw_of_mtable,
3280         },
3281         .probe = cpsw_probe,
3282         .remove = cpsw_remove,
3283 };
3284
3285 module_platform_driver(cpsw_driver);
3286
3287 MODULE_LICENSE("GPL");
3288 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3289 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3290 MODULE_DESCRIPTION("TI CPSW Ethernet driver");