drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/platform_data/cpsw.h>
  38
  39 #include "cpsw_ale.h"
  40 #include "cpts.h"
  41 #include "davinci_cpdma.h"
  42
  43 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  44                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  45                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  46                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  47                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  48                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  49                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  50                          NETIF_MSG_RX_STATUS)
  51
  52 #define cpsw_info(priv, type, format, ...)              \
  53 do {                                                            \
  54         if (netif_msg_##type(priv) && net_ratelimit())          \
  55                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  56 } while (0)
  57
  58 #define cpsw_err(priv, type, format, ...)               \
  59 do {                                                            \
  60         if (netif_msg_##type(priv) && net_ratelimit())          \
  61                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  62 } while (0)
  63
  64 #define cpsw_dbg(priv, type, format, ...)               \
  65 do {                                                            \
  66         if (netif_msg_##type(priv) && net_ratelimit())          \
  67                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  68 } while (0)
  69
  70 #define cpsw_notice(priv, type, format, ...)            \
  71 do {                                                            \
  72         if (netif_msg_##type(priv) && net_ratelimit())          \
  73                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  74 } while (0)
  75
  76 #define ALE_ALL_PORTS           0x7
  77
  78 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  79 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  80 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  81
  82 #define CPSW_VERSION_1          0x19010a
  83 #define CPSW_VERSION_2          0x19010c
  84
  85 #define HOST_PORT_NUM           0
  86 #define SLIVER_SIZE             0x40
  87
  88 #define CPSW1_HOST_PORT_OFFSET  0x028
  89 #define CPSW1_SLAVE_OFFSET      0x050
  90 #define CPSW1_SLAVE_SIZE        0x040
  91 #define CPSW1_CPDMA_OFFSET      0x100
  92 #define CPSW1_STATERAM_OFFSET   0x200
  93 #define CPSW1_CPTS_OFFSET       0x500
  94 #define CPSW1_ALE_OFFSET        0x600
  95 #define CPSW1_SLIVER_OFFSET     0x700
  96
  97 #define CPSW2_HOST_PORT_OFFSET  0x108
  98 #define CPSW2_SLAVE_OFFSET      0x200
  99 #define CPSW2_SLAVE_SIZE        0x100
 100 #define CPSW2_CPDMA_OFFSET      0x800
 101 #define CPSW2_STATERAM_OFFSET   0xa00
 102 #define CPSW2_CPTS_OFFSET       0xc00
 103 #define CPSW2_ALE_OFFSET        0xd00
 104 #define CPSW2_SLIVER_OFFSET     0xd80
 105 #define CPSW2_BD_OFFSET         0x2000
 106
 107 #define CPDMA_RXTHRESH          0x0c0
 108 #define CPDMA_RXFREE            0x0e0
 109 #define CPDMA_TXHDP             0x00
 110 #define CPDMA_RXHDP             0x20
 111 #define CPDMA_TXCP              0x40
 112 #define CPDMA_RXCP              0x60
 113
 114 #define CPSW_POLL_WEIGHT        64
 115 #define CPSW_MIN_PACKET_SIZE    60
 116 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 117
 118 #define RX_PRIORITY_MAPPING     0x76543210
 119 #define TX_PRIORITY_MAPPING     0x33221100
 120 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 121
 122 #define CPSW_VLAN_AWARE         BIT(1)
 123 #define CPSW_ALE_VLAN_AWARE     1
 124
 125 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 126 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 127 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 128
 129 #define CPSW_INTPACEEN          (0x3f << 16)
 130 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 131 #define CPSW_CMINTMAX_CNT       63
 132 #define CPSW_CMINTMIN_CNT       2
 133 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 134 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 135
 136 #define cpsw_enable_irq(priv)   \
 137         do {                    \
 138                 u32 i;          \
 139                 for (i = 0; i < priv->num_irqs; i++) \
 140                         enable_irq(priv->irqs_table[i]); \
 141         } while (0);
 142 #define cpsw_disable_irq(priv)  \
 143         do {                    \
 144                 u32 i;          \
 145                 for (i = 0; i < priv->num_irqs; i++) \
 146                         disable_irq_nosync(priv->irqs_table[i]); \
 147         } while (0);
 148
 149 #define cpsw_slave_index(priv)                          \
 150                 ((priv->data.dual_emac) ? priv->emac_port :     \
 151                 priv->data.active_slave)
 152
 153 static int debug_level;
 154 module_param(debug_level, int, 0);
 155 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 156
 157 static int ale_ageout = 10;
 158 module_param(ale_ageout, int, 0);
 159 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 160
 161 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 162 module_param(rx_packet_max, int, 0);
 163 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 164
 165 struct cpsw_wr_regs {
 166         u32     id_ver;
 167         u32     soft_reset;
 168         u32     control;
 169         u32     int_control;
 170         u32     rx_thresh_en;
 171         u32     rx_en;
 172         u32     tx_en;
 173         u32     misc_en;
 174         u32     mem_allign1[8];
 175         u32     rx_thresh_stat;
 176         u32     rx_stat;
 177         u32     tx_stat;
 178         u32     misc_stat;
 179         u32     mem_allign2[8];
 180         u32     rx_imax;
 181         u32     tx_imax;
 182
 183 };
 184
 185 struct cpsw_ss_regs {
 186         u32     id_ver;
 187         u32     control;
 188         u32     soft_reset;
 189         u32     stat_port_en;
 190         u32     ptype;
 191         u32     soft_idle;
 192         u32     thru_rate;
 193         u32     gap_thresh;
 194         u32     tx_start_wds;
 195         u32     flow_control;
 196         u32     vlan_ltype;
 197         u32     ts_ltype;
 198         u32     dlr_ltype;
 199 };
 200
 201 /* CPSW_PORT_V1 */
 202 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 203 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 204 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 205 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 206 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 207 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 208 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 209 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 210
 211 /* CPSW_PORT_V2 */
 212 #define CPSW2_CONTROL       0x00 /* Control Register */
 213 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 214 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 215 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 216 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 217 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 218 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 219
 220 /* CPSW_PORT_V1 and V2 */
 221 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 222 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 223 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 224
 225 /* CPSW_PORT_V2 only */
 226 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 234
 235 /* Bit definitions for the CPSW2_CONTROL register */
 236 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 237 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 238 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 239 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 240 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 241 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 242 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 243 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 244 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 245 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 246 #define TS_BIT8             (1<<8)  /* ts_ttl_nonzero? */
 247 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 248 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 249 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 250 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 251 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 252
 253 #define CTRL_TS_BITS \
 254         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
 255          TS_ANNEX_D_EN | TS_LTYPE1_EN)
 256
 257 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
 258 #define CTRL_TX_TS_BITS  (CTRL_TS_BITS | TS_TX_EN)
 259 #define CTRL_RX_TS_BITS  (CTRL_TS_BITS | TS_RX_EN)
 260
 261 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 262 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 263 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 264 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 265 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 266
 267 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 268 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 269
 270 /* Bit definitions for the CPSW1_TS_CTL register */
 271 #define CPSW_V1_TS_RX_EN                BIT(0)
 272 #define CPSW_V1_TS_TX_EN                BIT(4)
 273 #define CPSW_V1_MSG_TYPE_OFS            16
 274
 275 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 276 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 277
 278 struct cpsw_host_regs {
 279         u32     max_blks;
 280         u32     blk_cnt;
 281         u32     tx_in_ctl;
 282         u32     port_vlan;
 283         u32     tx_pri_map;
 284         u32     cpdma_tx_pri_map;
 285         u32     cpdma_rx_chan_map;
 286 };
 287
 288 struct cpsw_sliver_regs {
 289         u32     id_ver;
 290         u32     mac_control;
 291         u32     mac_status;
 292         u32     soft_reset;
 293         u32     rx_maxlen;
 294         u32     __reserved_0;
 295         u32     rx_pause;
 296         u32     tx_pause;
 297         u32     __reserved_1;
 298         u32     rx_pri_map;
 299 };
 300
 301 struct cpsw_slave {
 302         void __iomem                    *regs;
 303         struct cpsw_sliver_regs __iomem *sliver;
 304         int                             slave_num;
 305         u32                             mac_control;
 306         struct cpsw_slave_data          *data;
 307         struct phy_device               *phy;
 308         struct net_device               *ndev;
 309         u32                             port_vlan;
 310         u32                             open_stat;
 311 };
 312
 313 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 314 {
 315         return __raw_readl(slave->regs + offset);
 316 }
 317
 318 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 319 {
 320         __raw_writel(val, slave->regs + offset);
 321 }
 322
 323 struct cpsw_priv {
 324         spinlock_t                      lock;
 325         struct platform_device          *pdev;
 326         struct net_device               *ndev;
 327         struct resource                 *cpsw_res;
 328         struct resource                 *cpsw_wr_res;
 329         struct napi_struct              napi;
 330         struct device                   *dev;
 331         struct cpsw_platform_data       data;
 332         struct cpsw_ss_regs __iomem     *regs;
 333         struct cpsw_wr_regs __iomem     *wr_regs;
 334         struct cpsw_host_regs __iomem   *host_port_regs;
 335         u32                             msg_enable;
 336         u32                             version;
 337         u32                             coal_intvl;
 338         u32                             bus_freq_mhz;
 339         struct net_device_stats         stats;
 340         int                             rx_packet_max;
 341         int                             host_port;
 342         struct clk                      *clk;
 343         u8                              mac_addr[ETH_ALEN];
 344         struct cpsw_slave               *slaves;
 345         struct cpdma_ctlr               *dma;
 346         struct cpdma_chan               *txch, *rxch;
 347         struct cpsw_ale                 *ale;
 348         /* snapshot of IRQ numbers */
 349         u32 irqs_table[4];
 350         u32 num_irqs;
 351         struct cpts *cpts;
 352         u32 emac_port;
 353 };
 354
 355 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 356 #define for_each_slave(priv, func, arg...)                              \
 357         do {                                                            \
 358                 struct cpsw_slave *slave;                               \
 359                 int n;                                                  \
 360                 if (priv->data.dual_emac)                               \
 361                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 362                 else                                                    \
 363                         for (n = (priv)->data.slaves,                   \
 364                                         slave = (priv)->slaves;         \
 365                                         n; n--)                         \
 366                                 (func)(slave++, ##arg);                 \
 367         } while (0)
 368 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 369         (priv->slaves[__slave_no__].ndev)
 370 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 371         ((priv->slaves[__slave_no__].ndev) ?                            \
 372                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 373
 374 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 375         do {                                                            \
 376                 if (!priv->data.dual_emac)                              \
 377                         break;                                          \
 378                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 379                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 380                         priv = netdev_priv(ndev);                       \
 381                         skb->dev = ndev;                                \
 382                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 383                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 384                         priv = netdev_priv(ndev);                       \
 385                         skb->dev = ndev;                                \
 386                 }                                                       \
 387         } while (0)
 388 #define cpsw_add_mcast(priv, addr)                                      \
 389         do {                                                            \
 390                 if (priv->data.dual_emac) {                             \
 391                         struct cpsw_slave *slave = priv->slaves +       \
 392                                                 priv->emac_port;        \
 393                         int slave_port = cpsw_get_slave_port(priv,      \
 394                                                 slave->slave_num);      \
 395                         cpsw_ale_add_mcast(priv->ale, addr,             \
 396                                 1 << slave_port | 1 << priv->host_port, \
 397                                 ALE_VLAN, slave->port_vlan, 0);         \
 398                 } else {                                                \
 399                         cpsw_ale_add_mcast(priv->ale, addr,             \
 400                                 ALE_ALL_PORTS << priv->host_port,       \
 401                                 0, 0, 0);                               \
 402                 }                                                       \
 403         } while (0)
 404
 405 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 406 {
 407         if (priv->host_port == 0)
 408                 return slave_num + 1;
 409         else
 410                 return slave_num;
 411 }
 412
 413 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 414 {
 415         struct cpsw_priv *priv = netdev_priv(ndev);
 416
 417         if (ndev->flags & IFF_PROMISC) {
 418                 /* Enable promiscuous mode */
 419                 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
 420                 return;
 421         }
 422
 423         /* Clear all mcast from ALE */
 424         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 425
 426         if (!netdev_mc_empty(ndev)) {
 427                 struct netdev_hw_addr *ha;
 428
 429                 /* program multicast address list into ALE register */
 430                 netdev_for_each_mc_addr(ha, ndev) {
 431                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 432                 }
 433         }
 434 }
 435
 436 static void cpsw_intr_enable(struct cpsw_priv *priv)
 437 {
 438         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 439         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 440
 441         cpdma_ctlr_int_ctrl(priv->dma, true);
 442         return;
 443 }
 444
 445 static void cpsw_intr_disable(struct cpsw_priv *priv)
 446 {
 447         __raw_writel(0, &priv->wr_regs->tx_en);
 448         __raw_writel(0, &priv->wr_regs->rx_en);
 449
 450         cpdma_ctlr_int_ctrl(priv->dma, false);
 451         return;
 452 }
 453
 454 void cpsw_tx_handler(void *token, int len, int status)
 455 {
 456         struct sk_buff          *skb = token;
 457         struct net_device       *ndev = skb->dev;
 458         struct cpsw_priv        *priv = netdev_priv(ndev);
 459
 460         /* Check whether the queue is stopped due to stalled tx dma, if the
 461          * queue is stopped then start the queue as we have free desc for tx
 462          */
 463         if (unlikely(netif_queue_stopped(ndev)))
 464                 netif_wake_queue(ndev);
 465         cpts_tx_timestamp(priv->cpts, skb);
 466         priv->stats.tx_packets++;
 467         priv->stats.tx_bytes += len;
 468         dev_kfree_skb_any(skb);
 469 }
 470
 471 void cpsw_rx_handler(void *token, int len, int status)
 472 {
 473         struct sk_buff          *skb = token;
 474         struct sk_buff          *new_skb;
 475         struct net_device       *ndev = skb->dev;
 476         struct cpsw_priv        *priv = netdev_priv(ndev);
 477         int                     ret = 0;
 478
 479         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 480
 481         if (unlikely(status < 0)) {
 482                 /* the interface is going down, skbs are purged */
 483                 dev_kfree_skb_any(skb);
 484                 return;
 485         }
 486
 487         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 488         if (new_skb) {
 489                 skb_put(skb, len);
 490                 cpts_rx_timestamp(priv->cpts, skb);
 491                 skb->protocol = eth_type_trans(skb, ndev);
 492                 netif_receive_skb(skb);
 493                 priv->stats.rx_bytes += len;
 494                 priv->stats.rx_packets++;
 495         } else {
 496                 priv->stats.rx_dropped++;
 497                 new_skb = skb;
 498         }
 499
 500         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 501                         skb_tailroom(new_skb), 0);
 502         if (WARN_ON(ret < 0))
 503                 dev_kfree_skb_any(new_skb);
 504 }
 505
 506 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 507 {
 508         struct cpsw_priv *priv = dev_id;
 509         u32 rx, tx, rx_thresh;
 510
 511         rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
 512         rx = __raw_readl(&priv->wr_regs->rx_stat);
 513         tx = __raw_readl(&priv->wr_regs->tx_stat);
 514         if (!rx_thresh && !rx && !tx)
 515                 return IRQ_NONE;
 516
 517         cpsw_intr_disable(priv);
 518         cpsw_disable_irq(priv);
 519
 520         if (netif_running(priv->ndev)) {
 521                 napi_schedule(&priv->napi);
 522                 return IRQ_HANDLED;
 523         }
 524
 525         priv = cpsw_get_slave_priv(priv, 1);
 526         if (!priv)
 527                 return IRQ_NONE;
 528
 529         if (netif_running(priv->ndev)) {
 530                 napi_schedule(&priv->napi);
 531                 return IRQ_HANDLED;
 532         }
 533         return IRQ_NONE;
 534 }
 535
 536 static int cpsw_poll(struct napi_struct *napi, int budget)
 537 {
 538         struct cpsw_priv        *priv = napi_to_priv(napi);
 539         int                     num_tx, num_rx;
 540
 541         num_tx = cpdma_chan_process(priv->txch, 128);
 542         if (num_tx)
 543                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 544
 545         num_rx = cpdma_chan_process(priv->rxch, budget);
 546         if (num_rx < budget) {
 547                 napi_complete(napi);
 548                 cpsw_intr_enable(priv);
 549                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 550                 cpsw_enable_irq(priv);
 551         }
 552
 553         if (num_rx || num_tx)
 554                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 555                          num_rx, num_tx);
 556
 557         return num_rx;
 558 }
 559
 560 static inline void soft_reset(const char *module, void __iomem *reg)
 561 {
 562         unsigned long timeout = jiffies + HZ;
 563
 564         __raw_writel(1, reg);
 565         do {
 566                 cpu_relax();
 567         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 568
 569         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 570 }
 571
 572 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 573                          ((mac)[2] << 16) | ((mac)[3] << 24))
 574 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 575
 576 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 577                                struct cpsw_priv *priv)
 578 {
 579         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 580         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 581 }
 582
 583 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 584                               struct cpsw_priv *priv, bool *link)
 585 {
 586         struct phy_device       *phy = slave->phy;
 587         u32                     mac_control = 0;
 588         u32                     slave_port;
 589
 590         if (!phy)
 591                 return;
 592
 593         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 594
 595         if (phy->link) {
 596                 mac_control = priv->data.mac_control;
 597
 598                 /* enable forwarding */
 599                 cpsw_ale_control_set(priv->ale, slave_port,
 600                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 601
 602                 if (phy->speed == 1000)
 603                         mac_control |= BIT(7);  /* GIGABITEN    */
 604                 if (phy->duplex)
 605                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 606
 607                 /* set speed_in input in case RMII mode is used in 100Mbps */
 608                 if (phy->speed == 100)
 609                         mac_control |= BIT(15);
 610
 611                 *link = true;
 612         } else {
 613                 mac_control = 0;
 614                 /* disable forwarding */
 615                 cpsw_ale_control_set(priv->ale, slave_port,
 616                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 617         }
 618
 619         if (mac_control != slave->mac_control) {
 620                 phy_print_status(phy);
 621                 __raw_writel(mac_control, &slave->sliver->mac_control);
 622         }
 623
 624         slave->mac_control = mac_control;
 625 }
 626
 627 static void cpsw_adjust_link(struct net_device *ndev)
 628 {
 629         struct cpsw_priv        *priv = netdev_priv(ndev);
 630         bool                    link = false;
 631
 632         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 633
 634         if (link) {
 635                 netif_carrier_on(ndev);
 636                 if (netif_running(ndev))
 637                         netif_wake_queue(ndev);
 638         } else {
 639                 netif_carrier_off(ndev);
 640                 netif_stop_queue(ndev);
 641         }
 642 }
 643
 644 static int cpsw_get_coalesce(struct net_device *ndev,
 645                                 struct ethtool_coalesce *coal)
 646 {
 647         struct cpsw_priv *priv = netdev_priv(ndev);
 648
 649         coal->rx_coalesce_usecs = priv->coal_intvl;
 650         return 0;
 651 }
 652
 653 static int cpsw_set_coalesce(struct net_device *ndev,
 654                                 struct ethtool_coalesce *coal)
 655 {
 656         struct cpsw_priv *priv = netdev_priv(ndev);
 657         u32 int_ctrl;
 658         u32 num_interrupts = 0;
 659         u32 prescale = 0;
 660         u32 addnl_dvdr = 1;
 661         u32 coal_intvl = 0;
 662
 663         if (!coal->rx_coalesce_usecs)
 664                 return -EINVAL;
 665
 666         coal_intvl = coal->rx_coalesce_usecs;
 667
 668         int_ctrl =  readl(&priv->wr_regs->int_control);
 669         prescale = priv->bus_freq_mhz * 4;
 670
 671         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 672                 coal_intvl = CPSW_CMINTMIN_INTVL;
 673
 674         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 675                 /* Interrupt pacer works with 4us Pulse, we can
 676                  * throttle further by dilating the 4us pulse.
 677                  */
 678                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 679
 680                 if (addnl_dvdr > 1) {
 681                         prescale *= addnl_dvdr;
 682                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 683                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 684                                                 * addnl_dvdr);
 685                 } else {
 686                         addnl_dvdr = 1;
 687                         coal_intvl = CPSW_CMINTMAX_INTVL;
 688                 }
 689         }
 690
 691         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 692         writel(num_interrupts, &priv->wr_regs->rx_imax);
 693         writel(num_interrupts, &priv->wr_regs->tx_imax);
 694
 695         int_ctrl |= CPSW_INTPACEEN;
 696         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 697         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 698         writel(int_ctrl, &priv->wr_regs->int_control);
 699
 700         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 701         if (priv->data.dual_emac) {
 702                 int i;
 703
 704                 for (i = 0; i < priv->data.slaves; i++) {
 705                         priv = netdev_priv(priv->slaves[i].ndev);
 706                         priv->coal_intvl = coal_intvl;
 707                 }
 708         } else {
 709                 priv->coal_intvl = coal_intvl;
 710         }
 711
 712         return 0;
 713 }
 714
 715 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
 716 {
 717         static char *leader = "........................................";
 718
 719         if (!val)
 720                 return 0;
 721         else
 722                 return snprintf(buf, maxlen, "%s %s %10d\n", name,
 723                                 leader + strlen(name), val);
 724 }
 725
 726 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
 727 {
 728         u32 i;
 729         u32 usage_count = 0;
 730
 731         if (!priv->data.dual_emac)
 732                 return 0;
 733
 734         for (i = 0; i < priv->data.slaves; i++)
 735                 if (priv->slaves[i].open_stat)
 736                         usage_count++;
 737
 738         return usage_count;
 739 }
 740
 741 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
 742                         struct cpsw_priv *priv, struct sk_buff *skb)
 743 {
 744         if (!priv->data.dual_emac)
 745                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 746                                   skb->len, 0);
 747
 748         if (ndev == cpsw_get_slave_ndev(priv, 0))
 749                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 750                                   skb->len, 1);
 751         else
 752                 return cpdma_chan_submit(priv->txch, skb, skb->data,
 753                                   skb->len, 2);
 754 }
 755
 756 static inline void cpsw_add_dual_emac_def_ale_entries(
 757                 struct cpsw_priv *priv, struct cpsw_slave *slave,
 758                 u32 slave_port)
 759 {
 760         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
 761
 762         if (priv->version == CPSW_VERSION_1)
 763                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
 764         else
 765                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
 766         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
 767                           port_mask, port_mask, 0);
 768         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 769                            port_mask, ALE_VLAN, slave->port_vlan, 0);
 770         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
 771                 priv->host_port, ALE_VLAN, slave->port_vlan);
 772 }
 773
 774 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
 775 {
 776         char name[32];
 777         u32 slave_port;
 778
 779         sprintf(name, "slave-%d", slave->slave_num);
 780
 781         soft_reset(name, &slave->sliver->soft_reset);
 782
 783         /* setup priority mapping */
 784         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
 785
 786         switch (priv->version) {
 787         case CPSW_VERSION_1:
 788                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
 789                 break;
 790         case CPSW_VERSION_2:
 791                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
 792                 break;
 793         }
 794
 795         /* setup max packet size, and mac address */
 796         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
 797         cpsw_set_slave_mac(slave, priv);
 798
 799         slave->mac_control = 0; /* no link yet */
 800
 801         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 802
 803         if (priv->data.dual_emac)
 804                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
 805         else
 806                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 807                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
 808
 809         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
 810                                  &cpsw_adjust_link, slave->data->phy_if);
 811         if (IS_ERR(slave->phy)) {
 812                 dev_err(priv->dev, "phy %s not found on slave %d\n",
 813                         slave->data->phy_id, slave->slave_num);
 814                 slave->phy = NULL;
 815         } else {
 816                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
 817                          slave->phy->phy_id);
 818                 phy_start(slave->phy);
 819         }
 820 }
 821
 822 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
 823 {
 824         const int vlan = priv->data.default_vlan;
 825         const int port = priv->host_port;
 826         u32 reg;
 827         int i;
 828
 829         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
 830                CPSW2_PORT_VLAN;
 831
 832         writel(vlan, &priv->host_port_regs->port_vlan);
 833
 834         for (i = 0; i < priv->data.slaves; i++)
 835                 slave_write(priv->slaves + i, vlan, reg);
 836
 837         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
 838                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
 839                           (ALE_PORT_1 | ALE_PORT_2) << port);
 840 }
 841
 842 static void cpsw_init_host_port(struct cpsw_priv *priv)
 843 {
 844         u32 control_reg;
 845         u32 fifo_mode;
 846
 847         /* soft reset the controller and initialize ale */
 848         soft_reset("cpsw", &priv->regs->soft_reset);
 849         cpsw_ale_start(priv->ale);
 850
 851         /* switch to vlan unaware mode */
 852         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
 853                              CPSW_ALE_VLAN_AWARE);
 854         control_reg = readl(&priv->regs->control);
 855         control_reg |= CPSW_VLAN_AWARE;
 856         writel(control_reg, &priv->regs->control);
 857         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
 858                      CPSW_FIFO_NORMAL_MODE;
 859         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
 860
 861         /* setup host port priority mapping */
 862         __raw_writel(CPDMA_TX_PRIORITY_MAP,
 863                      &priv->host_port_regs->cpdma_tx_pri_map);
 864         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
 865
 866         cpsw_ale_control_set(priv->ale, priv->host_port,
 867                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 868
 869         if (!priv->data.dual_emac) {
 870                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
 871                                    0, 0);
 872                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
 873                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
 874         }
 875 }
 876
 877 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
 878 {
 879         if (!slave->phy)
 880                 return;
 881         phy_stop(slave->phy);
 882         phy_disconnect(slave->phy);
 883         slave->phy = NULL;
 884 }
 885
 886 static int cpsw_ndo_open(struct net_device *ndev)
 887 {
 888         struct cpsw_priv *priv = netdev_priv(ndev);
 889         int i, ret;
 890         u32 reg;
 891
 892         if (!cpsw_common_res_usage_state(priv))
 893                 cpsw_intr_disable(priv);
 894         netif_carrier_off(ndev);
 895
 896         pm_runtime_get_sync(&priv->pdev->dev);
 897
 898         reg = priv->version;
 899
 900         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
 901                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
 902                  CPSW_RTL_VERSION(reg));
 903
 904         /* initialize host and slave ports */
 905         if (!cpsw_common_res_usage_state(priv))
 906                 cpsw_init_host_port(priv);
 907         for_each_slave(priv, cpsw_slave_open, priv);
 908
 909         /* Add default VLAN */
 910         if (!priv->data.dual_emac)
 911                 cpsw_add_default_vlan(priv);
 912
 913         if (!cpsw_common_res_usage_state(priv)) {
 914                 /* setup tx dma to fixed prio and zero offset */
 915                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
 916                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
 917
 918                 /* disable priority elevation */
 919                 __raw_writel(0, &priv->regs->ptype);
 920
 921                 /* enable statistics collection only on all ports */
 922                 __raw_writel(0x7, &priv->regs->stat_port_en);
 923
 924                 if (WARN_ON(!priv->data.rx_descs))
 925                         priv->data.rx_descs = 128;
 926
 927                 for (i = 0; i < priv->data.rx_descs; i++) {
 928                         struct sk_buff *skb;
 929
 930                         ret = -ENOMEM;
 931                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
 932                                         priv->rx_packet_max, GFP_KERNEL);
 933                         if (!skb)
 934                                 goto err_cleanup;
 935                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
 936                                         skb_tailroom(skb), 0);
 937                         if (ret < 0) {
 938                                 kfree_skb(skb);
 939                                 goto err_cleanup;
 940                         }
 941                 }
 942                 /* continue even if we didn't manage to submit all
 943                  * receive descs
 944                  */
 945                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
 946         }
 947
 948         /* Enable Interrupt pacing if configured */
 949         if (priv->coal_intvl != 0) {
 950                 struct ethtool_coalesce coal;
 951
 952                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
 953                 cpsw_set_coalesce(ndev, &coal);
 954         }
 955
 956         cpdma_ctlr_start(priv->dma);
 957         cpsw_intr_enable(priv);
 958         napi_enable(&priv->napi);
 959         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 960         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 961
 962         if (priv->data.dual_emac)
 963                 priv->slaves[priv->emac_port].open_stat = true;
 964         return 0;
 965
 966 err_cleanup:
 967         cpdma_ctlr_stop(priv->dma);
 968         for_each_slave(priv, cpsw_slave_stop, priv);
 969         pm_runtime_put_sync(&priv->pdev->dev);
 970         netif_carrier_off(priv->ndev);
 971         return ret;
 972 }
 973
 974 static int cpsw_ndo_stop(struct net_device *ndev)
 975 {
 976         struct cpsw_priv *priv = netdev_priv(ndev);
 977
 978         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
 979         netif_stop_queue(priv->ndev);
 980         napi_disable(&priv->napi);
 981         netif_carrier_off(priv->ndev);
 982
 983         if (cpsw_common_res_usage_state(priv) <= 1) {
 984                 cpsw_intr_disable(priv);
 985                 cpdma_ctlr_int_ctrl(priv->dma, false);
 986                 cpdma_ctlr_stop(priv->dma);
 987                 cpsw_ale_stop(priv->ale);
 988         }
 989         for_each_slave(priv, cpsw_slave_stop, priv);
 990         pm_runtime_put_sync(&priv->pdev->dev);
 991         if (priv->data.dual_emac)
 992                 priv->slaves[priv->emac_port].open_stat = false;
 993         return 0;
 994 }
 995
 996 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
 997                                        struct net_device *ndev)
 998 {
 999         struct cpsw_priv *priv = netdev_priv(ndev);
1000         int ret;
1001
1002         ndev->trans_start = jiffies;
1003
1004         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1005                 cpsw_err(priv, tx_err, "packet pad failed\n");
1006                 priv->stats.tx_dropped++;
1007                 return NETDEV_TX_OK;
1008         }
1009
1010         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1011                                 priv->cpts->tx_enable)
1012                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1013
1014         skb_tx_timestamp(skb);
1015
1016         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1017         if (unlikely(ret != 0)) {
1018                 cpsw_err(priv, tx_err, "desc submit failed\n");
1019                 goto fail;
1020         }
1021
1022         /* If there is no more tx desc left free then we need to
1023          * tell the kernel to stop sending us tx frames.
1024          */
1025         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1026                 netif_stop_queue(ndev);
1027
1028         return NETDEV_TX_OK;
1029 fail:
1030         priv->stats.tx_dropped++;
1031         netif_stop_queue(ndev);
1032         return NETDEV_TX_BUSY;
1033 }
1034
1035 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1036 {
1037         /*
1038          * The switch cannot operate in promiscuous mode without substantial
1039          * headache.  For promiscuous mode to work, we would need to put the
1040          * ALE in bypass mode and route all traffic to the host port.
1041          * Subsequently, the host will need to operate as a "bridge", learn,
1042          * and flood as needed.  For now, we simply complain here and
1043          * do nothing about it :-)
1044          */
1045         if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1046                 dev_err(&ndev->dev, "promiscuity ignored!\n");
1047
1048         /*
1049          * The switch cannot filter multicast traffic unless it is configured
1050          * in "VLAN Aware" mode.  Unfortunately, VLAN awareness requires a
1051          * whole bunch of additional logic that this driver does not implement
1052          * at present.
1053          */
1054         if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1055                 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1056 }
1057
1058 #ifdef CONFIG_TI_CPTS
1059
1060 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1061 {
1062         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1063         u32 ts_en, seq_id;
1064
1065         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1066                 slave_write(slave, 0, CPSW1_TS_CTL);
1067                 return;
1068         }
1069
1070         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1071         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1072
1073         if (priv->cpts->tx_enable)
1074                 ts_en |= CPSW_V1_TS_TX_EN;
1075
1076         if (priv->cpts->rx_enable)
1077                 ts_en |= CPSW_V1_TS_RX_EN;
1078
1079         slave_write(slave, ts_en, CPSW1_TS_CTL);
1080         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1081 }
1082
1083 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1084 {
1085         struct cpsw_slave *slave;
1086         u32 ctrl, mtype;
1087
1088         if (priv->data.dual_emac)
1089                 slave = &priv->slaves[priv->emac_port];
1090         else
1091                 slave = &priv->slaves[priv->data.active_slave];
1092
1093         ctrl = slave_read(slave, CPSW2_CONTROL);
1094         ctrl &= ~CTRL_ALL_TS_MASK;
1095
1096         if (priv->cpts->tx_enable)
1097                 ctrl |= CTRL_TX_TS_BITS;
1098
1099         if (priv->cpts->rx_enable)
1100                 ctrl |= CTRL_RX_TS_BITS;
1101
1102         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1103
1104         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1105         slave_write(slave, ctrl, CPSW2_CONTROL);
1106         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1107 }
1108
1109 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1110 {
1111         struct cpsw_priv *priv = netdev_priv(dev);
1112         struct cpts *cpts = priv->cpts;
1113         struct hwtstamp_config cfg;
1114
1115         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1116                 return -EFAULT;
1117
1118         /* reserved for future extensions */
1119         if (cfg.flags)
1120                 return -EINVAL;
1121
1122         switch (cfg.tx_type) {
1123         case HWTSTAMP_TX_OFF:
1124                 cpts->tx_enable = 0;
1125                 break;
1126         case HWTSTAMP_TX_ON:
1127                 cpts->tx_enable = 1;
1128                 break;
1129         default:
1130                 return -ERANGE;
1131         }
1132
1133         switch (cfg.rx_filter) {
1134         case HWTSTAMP_FILTER_NONE:
1135                 cpts->rx_enable = 0;
1136                 break;
1137         case HWTSTAMP_FILTER_ALL:
1138         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1139         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1140         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1141                 return -ERANGE;
1142         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1143         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1144         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1145         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1146         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1147         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1148         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1149         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1150         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1151                 cpts->rx_enable = 1;
1152                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1153                 break;
1154         default:
1155                 return -ERANGE;
1156         }
1157
1158         switch (priv->version) {
1159         case CPSW_VERSION_1:
1160                 cpsw_hwtstamp_v1(priv);
1161                 break;
1162         case CPSW_VERSION_2:
1163                 cpsw_hwtstamp_v2(priv);
1164                 break;
1165         default:
1166                 return -ENOTSUPP;
1167         }
1168
1169         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1170 }
1171
1172 #endif /*CONFIG_TI_CPTS*/
1173
1174 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1175 {
1176         struct cpsw_priv *priv = netdev_priv(dev);
1177         struct mii_ioctl_data *data = if_mii(req);
1178         int slave_no = cpsw_slave_index(priv);
1179
1180         if (!netif_running(dev))
1181                 return -EINVAL;
1182
1183         switch (cmd) {
1184 #ifdef CONFIG_TI_CPTS
1185         case SIOCSHWTSTAMP:
1186                 return cpsw_hwtstamp_ioctl(dev, req);
1187 #endif
1188         case SIOCGMIIPHY:
1189                 data->phy_id = priv->slaves[slave_no].phy->addr;
1190                 break;
1191         default:
1192                 return -ENOTSUPP;
1193         }
1194
1195         return 0;
1196 }
1197
1198 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1199 {
1200         struct cpsw_priv *priv = netdev_priv(ndev);
1201
1202         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1203         priv->stats.tx_errors++;
1204         cpsw_intr_disable(priv);
1205         cpdma_ctlr_int_ctrl(priv->dma, false);
1206         cpdma_chan_stop(priv->txch);
1207         cpdma_chan_start(priv->txch);
1208         cpdma_ctlr_int_ctrl(priv->dma, true);
1209         cpsw_intr_enable(priv);
1210         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1211         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1212
1213 }
1214
1215 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1216 {
1217         struct cpsw_priv *priv = netdev_priv(ndev);
1218         return &priv->stats;
1219 }
1220
1221 #ifdef CONFIG_NET_POLL_CONTROLLER
1222 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1223 {
1224         struct cpsw_priv *priv = netdev_priv(ndev);
1225
1226         cpsw_intr_disable(priv);
1227         cpdma_ctlr_int_ctrl(priv->dma, false);
1228         cpsw_interrupt(ndev->irq, priv);
1229         cpdma_ctlr_int_ctrl(priv->dma, true);
1230         cpsw_intr_enable(priv);
1231         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1232         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1233
1234 }
1235 #endif
1236
1237 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1238                                 unsigned short vid)
1239 {
1240         int ret;
1241
1242         ret = cpsw_ale_add_vlan(priv->ale, vid,
1243                                 ALE_ALL_PORTS << priv->host_port,
1244                                 0, ALE_ALL_PORTS << priv->host_port,
1245                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1246         if (ret != 0)
1247                 return ret;
1248
1249         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1250                                  priv->host_port, ALE_VLAN, vid);
1251         if (ret != 0)
1252                 goto clean_vid;
1253
1254         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1255                                  ALE_ALL_PORTS << priv->host_port,
1256                                  ALE_VLAN, vid, 0);
1257         if (ret != 0)
1258                 goto clean_vlan_ucast;
1259         return 0;
1260
1261 clean_vlan_ucast:
1262         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1263                             priv->host_port, ALE_VLAN, vid);
1264 clean_vid:
1265         cpsw_ale_del_vlan(priv->ale, vid, 0);
1266         return ret;
1267 }
1268
1269 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1270                                     __be16 proto, u16 vid)
1271 {
1272         struct cpsw_priv *priv = netdev_priv(ndev);
1273
1274         if (vid == priv->data.default_vlan)
1275                 return 0;
1276
1277         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1278         return cpsw_add_vlan_ale_entry(priv, vid);
1279 }
1280
1281 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1282                                      __be16 proto, u16 vid)
1283 {
1284         struct cpsw_priv *priv = netdev_priv(ndev);
1285         int ret;
1286
1287         if (vid == priv->data.default_vlan)
1288                 return 0;
1289
1290         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1291         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1292         if (ret != 0)
1293                 return ret;
1294
1295         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1296                                  priv->host_port, ALE_VLAN, vid);
1297         if (ret != 0)
1298                 return ret;
1299
1300         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1301                                   0, ALE_VLAN, vid);
1302 }
1303
1304 static const struct net_device_ops cpsw_netdev_ops = {
1305         .ndo_open               = cpsw_ndo_open,
1306         .ndo_stop               = cpsw_ndo_stop,
1307         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1308         .ndo_change_rx_flags    = cpsw_ndo_change_rx_flags,
1309         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1310         .ndo_validate_addr      = eth_validate_addr,
1311         .ndo_change_mtu         = eth_change_mtu,
1312         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1313         .ndo_get_stats          = cpsw_ndo_get_stats,
1314         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1315 #ifdef CONFIG_NET_POLL_CONTROLLER
1316         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1317 #endif
1318         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1319         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1320 };
1321
1322 static void cpsw_get_drvinfo(struct net_device *ndev,
1323                              struct ethtool_drvinfo *info)
1324 {
1325         struct cpsw_priv *priv = netdev_priv(ndev);
1326
1327         strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1328         strlcpy(info->version, "1.0", sizeof(info->version));
1329         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1330 }
1331
1332 static u32 cpsw_get_msglevel(struct net_device *ndev)
1333 {
1334         struct cpsw_priv *priv = netdev_priv(ndev);
1335         return priv->msg_enable;
1336 }
1337
1338 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1339 {
1340         struct cpsw_priv *priv = netdev_priv(ndev);
1341         priv->msg_enable = value;
1342 }
1343
1344 static int cpsw_get_ts_info(struct net_device *ndev,
1345                             struct ethtool_ts_info *info)
1346 {
1347 #ifdef CONFIG_TI_CPTS
1348         struct cpsw_priv *priv = netdev_priv(ndev);
1349
1350         info->so_timestamping =
1351                 SOF_TIMESTAMPING_TX_HARDWARE |
1352                 SOF_TIMESTAMPING_TX_SOFTWARE |
1353                 SOF_TIMESTAMPING_RX_HARDWARE |
1354                 SOF_TIMESTAMPING_RX_SOFTWARE |
1355                 SOF_TIMESTAMPING_SOFTWARE |
1356                 SOF_TIMESTAMPING_RAW_HARDWARE;
1357         info->phc_index = priv->cpts->phc_index;
1358         info->tx_types =
1359                 (1 << HWTSTAMP_TX_OFF) |
1360                 (1 << HWTSTAMP_TX_ON);
1361         info->rx_filters =
1362                 (1 << HWTSTAMP_FILTER_NONE) |
1363                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1364 #else
1365         info->so_timestamping =
1366                 SOF_TIMESTAMPING_TX_SOFTWARE |
1367                 SOF_TIMESTAMPING_RX_SOFTWARE |
1368                 SOF_TIMESTAMPING_SOFTWARE;
1369         info->phc_index = -1;
1370         info->tx_types = 0;
1371         info->rx_filters = 0;
1372 #endif
1373         return 0;
1374 }
1375
1376 static int cpsw_get_settings(struct net_device *ndev,
1377                              struct ethtool_cmd *ecmd)
1378 {
1379         struct cpsw_priv *priv = netdev_priv(ndev);
1380         int slave_no = cpsw_slave_index(priv);
1381
1382         if (priv->slaves[slave_no].phy)
1383                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1384         else
1385                 return -EOPNOTSUPP;
1386 }
1387
1388 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1389 {
1390         struct cpsw_priv *priv = netdev_priv(ndev);
1391         int slave_no = cpsw_slave_index(priv);
1392
1393         if (priv->slaves[slave_no].phy)
1394                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1395         else
1396                 return -EOPNOTSUPP;
1397 }
1398
1399 static const struct ethtool_ops cpsw_ethtool_ops = {
1400         .get_drvinfo    = cpsw_get_drvinfo,
1401         .get_msglevel   = cpsw_get_msglevel,
1402         .set_msglevel   = cpsw_set_msglevel,
1403         .get_link       = ethtool_op_get_link,
1404         .get_ts_info    = cpsw_get_ts_info,
1405         .get_settings   = cpsw_get_settings,
1406         .set_settings   = cpsw_set_settings,
1407         .get_coalesce   = cpsw_get_coalesce,
1408         .set_coalesce   = cpsw_set_coalesce,
1409 };
1410
1411 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1412                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1413 {
1414         void __iomem            *regs = priv->regs;
1415         int                     slave_num = slave->slave_num;
1416         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1417
1418         slave->data     = data;
1419         slave->regs     = regs + slave_reg_ofs;
1420         slave->sliver   = regs + sliver_reg_ofs;
1421         slave->port_vlan = data->dual_emac_res_vlan;
1422 }
1423
1424 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1425                          struct platform_device *pdev)
1426 {
1427         struct device_node *node = pdev->dev.of_node;
1428         struct device_node *slave_node;
1429         int i = 0, ret;
1430         u32 prop;
1431
1432         if (!node)
1433                 return -EINVAL;
1434
1435         if (of_property_read_u32(node, "slaves", &prop)) {
1436                 pr_err("Missing slaves property in the DT.\n");
1437                 return -EINVAL;
1438         }
1439         data->slaves = prop;
1440
1441         if (of_property_read_u32(node, "active_slave", &prop)) {
1442                 pr_err("Missing active_slave property in the DT.\n");
1443                 ret = -EINVAL;
1444                 goto error_ret;
1445         }
1446         data->active_slave = prop;
1447
1448         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1449                 pr_err("Missing cpts_clock_mult property in the DT.\n");
1450                 ret = -EINVAL;
1451                 goto error_ret;
1452         }
1453         data->cpts_clock_mult = prop;
1454
1455         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1456                 pr_err("Missing cpts_clock_shift property in the DT.\n");
1457                 ret = -EINVAL;
1458                 goto error_ret;
1459         }
1460         data->cpts_clock_shift = prop;
1461
1462         data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1463                                    GFP_KERNEL);
1464         if (!data->slave_data)
1465                 return -EINVAL;
1466
1467         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1468                 pr_err("Missing cpdma_channels property in the DT.\n");
1469                 ret = -EINVAL;
1470                 goto error_ret;
1471         }
1472         data->channels = prop;
1473
1474         if (of_property_read_u32(node, "ale_entries", &prop)) {
1475                 pr_err("Missing ale_entries property in the DT.\n");
1476                 ret = -EINVAL;
1477                 goto error_ret;
1478         }
1479         data->ale_entries = prop;
1480
1481         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1482                 pr_err("Missing bd_ram_size property in the DT.\n");
1483                 ret = -EINVAL;
1484                 goto error_ret;
1485         }
1486         data->bd_ram_size = prop;
1487
1488         if (of_property_read_u32(node, "rx_descs", &prop)) {
1489                 pr_err("Missing rx_descs property in the DT.\n");
1490                 ret = -EINVAL;
1491                 goto error_ret;
1492         }
1493         data->rx_descs = prop;
1494
1495         if (of_property_read_u32(node, "mac_control", &prop)) {
1496                 pr_err("Missing mac_control property in the DT.\n");
1497                 ret = -EINVAL;
1498                 goto error_ret;
1499         }
1500         data->mac_control = prop;
1501
1502         if (!of_property_read_u32(node, "dual_emac", &prop))
1503                 data->dual_emac = prop;
1504
1505         /*
1506          * Populate all the child nodes here...
1507          */
1508         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1509         /* We do not want to force this, as in some cases may not have child */
1510         if (ret)
1511                 pr_warn("Doesn't have any child node\n");
1512
1513         for_each_node_by_name(slave_node, "slave") {
1514                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1515                 const void *mac_addr = NULL;
1516                 u32 phyid;
1517                 int lenp;
1518                 const __be32 *parp;
1519                 struct device_node *mdio_node;
1520                 struct platform_device *mdio;
1521
1522                 parp = of_get_property(slave_node, "phy_id", &lenp);
1523                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1524                         pr_err("Missing slave[%d] phy_id property\n", i);
1525                         ret = -EINVAL;
1526                         goto error_ret;
1527                 }
1528                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1529                 phyid = be32_to_cpup(parp+1);
1530                 mdio = of_find_device_by_node(mdio_node);
1531                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1532                          PHY_ID_FMT, mdio->name, phyid);
1533
1534                 mac_addr = of_get_mac_address(slave_node);
1535                 if (mac_addr)
1536                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1537
1538                 if (data->dual_emac) {
1539                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1540                                                  &prop)) {
1541                                 pr_err("Missing dual_emac_res_vlan in DT.\n");
1542                                 slave_data->dual_emac_res_vlan = i+1;
1543                                 pr_err("Using %d as Reserved VLAN for %d slave\n",
1544                                        slave_data->dual_emac_res_vlan, i);
1545                         } else {
1546                                 slave_data->dual_emac_res_vlan = prop;
1547                         }
1548                 }
1549
1550                 i++;
1551         }
1552
1553         return 0;
1554
1555 error_ret:
1556         kfree(data->slave_data);
1557         return ret;
1558 }
1559
1560 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1561                                 struct cpsw_priv *priv)
1562 {
1563         struct cpsw_platform_data       *data = &priv->data;
1564         struct net_device               *ndev;
1565         struct cpsw_priv                *priv_sl2;
1566         int ret = 0, i;
1567
1568         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1569         if (!ndev) {
1570                 pr_err("cpsw: error allocating net_device\n");
1571                 return -ENOMEM;
1572         }
1573
1574         priv_sl2 = netdev_priv(ndev);
1575         spin_lock_init(&priv_sl2->lock);
1576         priv_sl2->data = *data;
1577         priv_sl2->pdev = pdev;
1578         priv_sl2->ndev = ndev;
1579         priv_sl2->dev  = &ndev->dev;
1580         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1581         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1582
1583         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1584                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1585                         ETH_ALEN);
1586                 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1587         } else {
1588                 random_ether_addr(priv_sl2->mac_addr);
1589                 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1590         }
1591         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1592
1593         priv_sl2->slaves = priv->slaves;
1594         priv_sl2->clk = priv->clk;
1595
1596         priv_sl2->coal_intvl = 0;
1597         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1598
1599         priv_sl2->cpsw_res = priv->cpsw_res;
1600         priv_sl2->regs = priv->regs;
1601         priv_sl2->host_port = priv->host_port;
1602         priv_sl2->host_port_regs = priv->host_port_regs;
1603         priv_sl2->wr_regs = priv->wr_regs;
1604         priv_sl2->dma = priv->dma;
1605         priv_sl2->txch = priv->txch;
1606         priv_sl2->rxch = priv->rxch;
1607         priv_sl2->ale = priv->ale;
1608         priv_sl2->emac_port = 1;
1609         priv->slaves[1].ndev = ndev;
1610         priv_sl2->cpts = priv->cpts;
1611         priv_sl2->version = priv->version;
1612
1613         for (i = 0; i < priv->num_irqs; i++) {
1614                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1615                 priv_sl2->num_irqs = priv->num_irqs;
1616         }
1617
1618         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1619
1620         ndev->netdev_ops = &cpsw_netdev_ops;
1621         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1622         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1623
1624         /* register the network device */
1625         SET_NETDEV_DEV(ndev, &pdev->dev);
1626         ret = register_netdev(ndev);
1627         if (ret) {
1628                 pr_err("cpsw: error registering net device\n");
1629                 free_netdev(ndev);
1630                 ret = -ENODEV;
1631         }
1632
1633         return ret;
1634 }
1635
1636 static int cpsw_probe(struct platform_device *pdev)
1637 {
1638         struct cpsw_platform_data       *data;
1639         struct net_device               *ndev;
1640         struct cpsw_priv                *priv;
1641         struct cpdma_params             dma_params;
1642         struct cpsw_ale_params          ale_params;
1643         void __iomem                    *ss_regs, *wr_regs;
1644         struct resource                 *res;
1645         u32 slave_offset, sliver_offset, slave_size;
1646         int ret = 0, i, k = 0;
1647
1648         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1649         if (!ndev) {
1650                 pr_err("error allocating net_device\n");
1651                 return -ENOMEM;
1652         }
1653
1654         platform_set_drvdata(pdev, ndev);
1655         priv = netdev_priv(ndev);
1656         spin_lock_init(&priv->lock);
1657         priv->pdev = pdev;
1658         priv->ndev = ndev;
1659         priv->dev  = &ndev->dev;
1660         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1661         priv->rx_packet_max = max(rx_packet_max, 128);
1662         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1663         if (!ndev) {
1664                 pr_err("error allocating cpts\n");
1665                 goto clean_ndev_ret;
1666         }
1667
1668         /*
1669          * This may be required here for child devices.
1670          */
1671         pm_runtime_enable(&pdev->dev);
1672
1673         if (cpsw_probe_dt(&priv->data, pdev)) {
1674                 pr_err("cpsw: platform data missing\n");
1675                 ret = -ENODEV;
1676                 goto clean_ndev_ret;
1677         }
1678         data = &priv->data;
1679
1680         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1681                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1682                 pr_info("Detected MACID = %pM", priv->mac_addr);
1683         } else {
1684                 eth_random_addr(priv->mac_addr);
1685                 pr_info("Random MACID = %pM", priv->mac_addr);
1686         }
1687
1688         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1689
1690         priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1691                                GFP_KERNEL);
1692         if (!priv->slaves) {
1693                 ret = -EBUSY;
1694                 goto clean_ndev_ret;
1695         }
1696         for (i = 0; i < data->slaves; i++)
1697                 priv->slaves[i].slave_num = i;
1698
1699         priv->slaves[0].ndev = ndev;
1700         priv->emac_port = 0;
1701
1702         priv->clk = clk_get(&pdev->dev, "fck");
1703         if (IS_ERR(priv->clk)) {
1704                 dev_err(&pdev->dev, "fck is not found\n");
1705                 ret = -ENODEV;
1706                 goto clean_slave_ret;
1707         }
1708         priv->coal_intvl = 0;
1709         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1710
1711         priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1712         if (!priv->cpsw_res) {
1713                 dev_err(priv->dev, "error getting i/o resource\n");
1714                 ret = -ENOENT;
1715                 goto clean_clk_ret;
1716         }
1717         if (!request_mem_region(priv->cpsw_res->start,
1718                                 resource_size(priv->cpsw_res), ndev->name)) {
1719                 dev_err(priv->dev, "failed request i/o region\n");
1720                 ret = -ENXIO;
1721                 goto clean_clk_ret;
1722         }
1723         ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1724         if (!ss_regs) {
1725                 dev_err(priv->dev, "unable to map i/o region\n");
1726                 goto clean_cpsw_iores_ret;
1727         }
1728         priv->regs = ss_regs;
1729         priv->version = __raw_readl(&priv->regs->id_ver);
1730         priv->host_port = HOST_PORT_NUM;
1731
1732         priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1733         if (!priv->cpsw_wr_res) {
1734                 dev_err(priv->dev, "error getting i/o resource\n");
1735                 ret = -ENOENT;
1736                 goto clean_iomap_ret;
1737         }
1738         if (!request_mem_region(priv->cpsw_wr_res->start,
1739                         resource_size(priv->cpsw_wr_res), ndev->name)) {
1740                 dev_err(priv->dev, "failed request i/o region\n");
1741                 ret = -ENXIO;
1742                 goto clean_iomap_ret;
1743         }
1744         wr_regs = ioremap(priv->cpsw_wr_res->start,
1745                                 resource_size(priv->cpsw_wr_res));
1746         if (!wr_regs) {
1747                 dev_err(priv->dev, "unable to map i/o region\n");
1748                 goto clean_cpsw_wr_iores_ret;
1749         }
1750         priv->wr_regs = wr_regs;
1751
1752         memset(&dma_params, 0, sizeof(dma_params));
1753         memset(&ale_params, 0, sizeof(ale_params));
1754
1755         switch (priv->version) {
1756         case CPSW_VERSION_1:
1757                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1758                 priv->cpts->reg       = ss_regs + CPSW1_CPTS_OFFSET;
1759                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
1760                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
1761                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
1762                 slave_offset         = CPSW1_SLAVE_OFFSET;
1763                 slave_size           = CPSW1_SLAVE_SIZE;
1764                 sliver_offset        = CPSW1_SLIVER_OFFSET;
1765                 dma_params.desc_mem_phys = 0;
1766                 break;
1767         case CPSW_VERSION_2:
1768                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1769                 priv->cpts->reg       = ss_regs + CPSW2_CPTS_OFFSET;
1770                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
1771                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
1772                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
1773                 slave_offset         = CPSW2_SLAVE_OFFSET;
1774                 slave_size           = CPSW2_SLAVE_SIZE;
1775                 sliver_offset        = CPSW2_SLIVER_OFFSET;
1776                 dma_params.desc_mem_phys =
1777                         (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1778                 break;
1779         default:
1780                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1781                 ret = -ENODEV;
1782                 goto clean_cpsw_wr_iores_ret;
1783         }
1784         for (i = 0; i < priv->data.slaves; i++) {
1785                 struct cpsw_slave *slave = &priv->slaves[i];
1786                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1787                 slave_offset  += slave_size;
1788                 sliver_offset += SLIVER_SIZE;
1789         }
1790
1791         dma_params.dev          = &pdev->dev;
1792         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
1793         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
1794         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
1795         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
1796         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
1797
1798         dma_params.num_chan             = data->channels;
1799         dma_params.has_soft_reset       = true;
1800         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
1801         dma_params.desc_mem_size        = data->bd_ram_size;
1802         dma_params.desc_align           = 16;
1803         dma_params.has_ext_regs         = true;
1804         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
1805
1806         priv->dma = cpdma_ctlr_create(&dma_params);
1807         if (!priv->dma) {
1808                 dev_err(priv->dev, "error initializing dma\n");
1809                 ret = -ENOMEM;
1810                 goto clean_wr_iomap_ret;
1811         }
1812
1813         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1814                                        cpsw_tx_handler);
1815         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1816                                        cpsw_rx_handler);
1817
1818         if (WARN_ON(!priv->txch || !priv->rxch)) {
1819                 dev_err(priv->dev, "error initializing dma channels\n");
1820                 ret = -ENOMEM;
1821                 goto clean_dma_ret;
1822         }
1823
1824         ale_params.dev                  = &ndev->dev;
1825         ale_params.ale_ageout           = ale_ageout;
1826         ale_params.ale_entries          = data->ale_entries;
1827         ale_params.ale_ports            = data->slaves;
1828
1829         priv->ale = cpsw_ale_create(&ale_params);
1830         if (!priv->ale) {
1831                 dev_err(priv->dev, "error initializing ale engine\n");
1832                 ret = -ENODEV;
1833                 goto clean_dma_ret;
1834         }
1835
1836         ndev->irq = platform_get_irq(pdev, 0);
1837         if (ndev->irq < 0) {
1838                 dev_err(priv->dev, "error getting irq resource\n");
1839                 ret = -ENOENT;
1840                 goto clean_ale_ret;
1841         }
1842
1843         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1844                 for (i = res->start; i <= res->end; i++) {
1845                         if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1846                                         dev_name(&pdev->dev), priv)) {
1847                                 dev_err(priv->dev, "error attaching irq\n");
1848                                 goto clean_ale_ret;
1849                         }
1850                         priv->irqs_table[k] = i;
1851                         priv->num_irqs = k + 1;
1852                 }
1853                 k++;
1854         }
1855
1856         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1857
1858         ndev->netdev_ops = &cpsw_netdev_ops;
1859         SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1860         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1861
1862         /* register the network device */
1863         SET_NETDEV_DEV(ndev, &pdev->dev);
1864         ret = register_netdev(ndev);
1865         if (ret) {
1866                 dev_err(priv->dev, "error registering net device\n");
1867                 ret = -ENODEV;
1868                 goto clean_irq_ret;
1869         }
1870
1871         if (cpts_register(&pdev->dev, priv->cpts,
1872                           data->cpts_clock_mult, data->cpts_clock_shift))
1873                 dev_err(priv->dev, "error registering cpts device\n");
1874
1875         cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1876                   priv->cpsw_res->start, ndev->irq);
1877
1878         if (priv->data.dual_emac) {
1879                 ret = cpsw_probe_dual_emac(pdev, priv);
1880                 if (ret) {
1881                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
1882                         goto clean_irq_ret;
1883                 }
1884         }
1885
1886         return 0;
1887
1888 clean_irq_ret:
1889         for (i = 0; i < priv->num_irqs; i++)
1890                 free_irq(priv->irqs_table[i], priv);
1891 clean_ale_ret:
1892         cpsw_ale_destroy(priv->ale);
1893 clean_dma_ret:
1894         cpdma_chan_destroy(priv->txch);
1895         cpdma_chan_destroy(priv->rxch);
1896         cpdma_ctlr_destroy(priv->dma);
1897 clean_wr_iomap_ret:
1898         iounmap(priv->wr_regs);
1899 clean_cpsw_wr_iores_ret:
1900         release_mem_region(priv->cpsw_wr_res->start,
1901                            resource_size(priv->cpsw_wr_res));
1902 clean_iomap_ret:
1903         iounmap(priv->regs);
1904 clean_cpsw_iores_ret:
1905         release_mem_region(priv->cpsw_res->start,
1906                            resource_size(priv->cpsw_res));
1907 clean_clk_ret:
1908         clk_put(priv->clk);
1909 clean_slave_ret:
1910         pm_runtime_disable(&pdev->dev);
1911         kfree(priv->slaves);
1912 clean_ndev_ret:
1913         kfree(priv->data.slave_data);
1914         free_netdev(priv->ndev);
1915         return ret;
1916 }
1917
1918 static int cpsw_remove(struct platform_device *pdev)
1919 {
1920         struct net_device *ndev = platform_get_drvdata(pdev);
1921         struct cpsw_priv *priv = netdev_priv(ndev);
1922         int i;
1923
1924         platform_set_drvdata(pdev, NULL);
1925         if (priv->data.dual_emac)
1926                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
1927         unregister_netdev(ndev);
1928
1929         cpts_unregister(priv->cpts);
1930         for (i = 0; i < priv->num_irqs; i++)
1931                 free_irq(priv->irqs_table[i], priv);
1932
1933         cpsw_ale_destroy(priv->ale);
1934         cpdma_chan_destroy(priv->txch);
1935         cpdma_chan_destroy(priv->rxch);
1936         cpdma_ctlr_destroy(priv->dma);
1937         iounmap(priv->regs);
1938         release_mem_region(priv->cpsw_res->start,
1939                            resource_size(priv->cpsw_res));
1940         iounmap(priv->wr_regs);
1941         release_mem_region(priv->cpsw_wr_res->start,
1942                            resource_size(priv->cpsw_wr_res));
1943         pm_runtime_disable(&pdev->dev);
1944         clk_put(priv->clk);
1945         kfree(priv->slaves);
1946         kfree(priv->data.slave_data);
1947         if (priv->data.dual_emac)
1948                 free_netdev(cpsw_get_slave_ndev(priv, 1));
1949         free_netdev(ndev);
1950         return 0;
1951 }
1952
1953 static int cpsw_suspend(struct device *dev)
1954 {
1955         struct platform_device  *pdev = to_platform_device(dev);
1956         struct net_device       *ndev = platform_get_drvdata(pdev);
1957
1958         if (netif_running(ndev))
1959                 cpsw_ndo_stop(ndev);
1960         pm_runtime_put_sync(&pdev->dev);
1961
1962         return 0;
1963 }
1964
1965 static int cpsw_resume(struct device *dev)
1966 {
1967         struct platform_device  *pdev = to_platform_device(dev);
1968         struct net_device       *ndev = platform_get_drvdata(pdev);
1969
1970         pm_runtime_get_sync(&pdev->dev);
1971         if (netif_running(ndev))
1972                 cpsw_ndo_open(ndev);
1973         return 0;
1974 }
1975
1976 static const struct dev_pm_ops cpsw_pm_ops = {
1977         .suspend        = cpsw_suspend,
1978         .resume         = cpsw_resume,
1979 };
1980
1981 static const struct of_device_id cpsw_of_mtable[] = {
1982         { .compatible = "ti,cpsw", },
1983         { /* sentinel */ },
1984 };
1985 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
1986
1987 static struct platform_driver cpsw_driver = {
1988         .driver = {
1989                 .name    = "cpsw",
1990                 .owner   = THIS_MODULE,
1991                 .pm      = &cpsw_pm_ops,
1992                 .of_match_table = of_match_ptr(cpsw_of_mtable),
1993         },
1994         .probe = cpsw_probe,
1995         .remove = cpsw_remove,
1996 };
1997
1998 static int __init cpsw_init(void)
1999 {
2000         return platform_driver_register(&cpsw_driver);
2001 }
2002 late_initcall(cpsw_init);
2003
2004 static void __exit cpsw_exit(void)
2005 {
2006         platform_driver_unregister(&cpsw_driver);
2007 }
2008 module_exit(cpsw_exit);
2009
2010 MODULE_LICENSE("GPL");
2011 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2012 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2013 MODULE_DESCRIPTION("TI CPSW Ethernet driver");