drivers/net/ethernet/ti/am65-cpsw-nuss.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  */
   5
   6 #ifndef AM65_CPSW_NUSS_H_
   7 #define AM65_CPSW_NUSS_H_
   8
   9 #include <linux/if_ether.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/phylink.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/soc/ti/k3-ringacc.h>
  16 #include <net/devlink.h>
  17 #include "am65-cpsw-qos.h"
  18
  19 struct am65_cpts;
  20
  21 #define HOST_PORT_NUM           0
  22
  23 #define AM65_CPSW_MAX_TX_QUEUES 8
  24 #define AM65_CPSW_MAX_RX_QUEUES 1
  25 #define AM65_CPSW_MAX_RX_FLOWS  1
  26
  27 #define AM65_CPSW_PORT_VLAN_REG_OFFSET  0x014
  28
  29 struct am65_cpsw_slave_data {
  30         bool                            mac_only;
  31         struct cpsw_sl                  *mac_sl;
  32         struct device_node              *phy_node;
  33         phy_interface_t                 phy_if;
  34         struct phy                      *ifphy;
  35         struct phy                      *serdes_phy;
  36         bool                            rx_pause;
  37         bool                            tx_pause;
  38         u8                              mac_addr[ETH_ALEN];
  39         int                             port_vlan;
  40         struct phylink                  *phylink;
  41         struct phylink_config           phylink_config;
  42 };
  43
  44 struct am65_cpsw_port {
  45         struct am65_cpsw_common         *common;
  46         struct net_device               *ndev;
  47         const char                      *name;
  48         u32                             port_id;
  49         void __iomem                    *port_base;
  50         void __iomem                    *sgmii_base;
  51         void __iomem                    *stat_base;
  52         void __iomem                    *fetch_ram_base;
  53         bool                            disabled;
  54         struct am65_cpsw_slave_data     slave;
  55         bool                            tx_ts_enabled;
  56         bool                            rx_ts_enabled;
  57         struct am65_cpsw_qos            qos;
  58         struct devlink_port             devlink_port;
  59         /* Only for suspend resume context */
  60         u32                             vid_context;
  61 };
  62
  63 struct am65_cpsw_host {
  64         struct am65_cpsw_common         *common;
  65         void __iomem                    *port_base;
  66         void __iomem                    *stat_base;
  67         /* Only for suspend resume context */
  68         u32                             vid_context;
  69 };
  70
  71 struct am65_cpsw_tx_chn {
  72         struct device *dma_dev;
  73         struct napi_struct napi_tx;
  74         struct am65_cpsw_common *common;
  75         struct k3_cppi_desc_pool *desc_pool;
  76         struct k3_udma_glue_tx_channel *tx_chn;
  77         spinlock_t lock; /* protect TX rings in multi-port mode */
  78         int irq;
  79         u32 id;
  80         u32 descs_num;
  81         char tx_chn_name[128];
  82 };
  83
  84 struct am65_cpsw_rx_chn {
  85         struct device *dev;
  86         struct device *dma_dev;
  87         struct k3_cppi_desc_pool *desc_pool;
  88         struct k3_udma_glue_rx_channel *rx_chn;
  89         u32 descs_num;
  90         int irq;
  91 };
  92
  93 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0)
  94
  95 struct am65_cpsw_pdata {
  96         u32     quirks;
  97         u64     extra_modes;
  98         enum k3_ring_mode fdqring_mode;
  99         const char      *ale_dev_id;
 100 };
 101
 102 enum cpsw_devlink_param_id {
 103         AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
 104         AM65_CPSW_DL_PARAM_SWITCH_MODE,
 105 };
 106
 107 struct am65_cpsw_devlink {
 108         struct am65_cpsw_common *common;
 109 };
 110
 111 struct am65_cpsw_common {
 112         struct device           *dev;
 113         struct device           *mdio_dev;
 114         struct am65_cpsw_pdata  pdata;
 115
 116         void __iomem            *ss_base;
 117         void __iomem            *cpsw_base;
 118
 119         u32                     port_num;
 120         struct am65_cpsw_host   host;
 121         struct am65_cpsw_port   *ports;
 122         u32                     disabled_ports_mask;
 123         struct net_device       *dma_ndev;
 124
 125         int                     usage_count; /* number of opened ports */
 126         struct cpsw_ale         *ale;
 127         int                     tx_ch_num;
 128         u32                     rx_flow_id_base;
 129
 130         struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES];
 131         struct completion       tdown_complete;
 132         atomic_t                tdown_cnt;
 133
 134         struct am65_cpsw_rx_chn rx_chns;
 135         struct napi_struct      napi_rx;
 136
 137         bool                    rx_irq_disabled;
 138
 139         u32                     nuss_ver;
 140         u32                     cpsw_ver;
 141         unsigned long           bus_freq;
 142         bool                    pf_p0_rx_ptype_rrobin;
 143         struct am65_cpts        *cpts;
 144         int                     est_enabled;
 145
 146         bool            is_emac_mode;
 147         u16                     br_members;
 148         int                     default_vlan;
 149         struct devlink *devlink;
 150         struct net_device *hw_bridge_dev;
 151         struct notifier_block am65_cpsw_netdevice_nb;
 152         unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN];
 153         /* only for suspend/resume context restore */
 154         u32                     *ale_context;
 155 };
 156
 157 struct am65_cpsw_ndev_stats {
 158         u64 tx_packets;
 159         u64 tx_bytes;
 160         u64 rx_packets;
 161         u64 rx_bytes;
 162         struct u64_stats_sync syncp;
 163 };
 164
 165 struct am65_cpsw_ndev_priv {
 166         u32                     msg_enable;
 167         struct am65_cpsw_port   *port;
 168         struct am65_cpsw_ndev_stats __percpu *stats;
 169         bool offload_fwd_mark;
 170 };
 171
 172 #define am65_ndev_to_priv(ndev) \
 173         ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev))
 174 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port)
 175 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common)
 176 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave)
 177
 178 #define am65_common_get_host(common) (&(common)->host)
 179 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1])
 180
 181 #define am65_cpsw_napi_to_common(pnapi) \
 182         container_of(pnapi, struct am65_cpsw_common, napi_rx)
 183 #define am65_cpsw_napi_to_tx_chn(pnapi) \
 184         container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx)
 185
 186 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss"
 187
 188 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1)
 189
 190 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave;
 191
 192 void am65_cpsw_nuss_adjust_link(struct net_device *ndev);
 193 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common);
 194 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common);
 195 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx);
 196
 197 bool am65_cpsw_port_dev_check(const struct net_device *dev);
 198
 199 #endif /* AM65_CPSW_NUSS_H_ */