1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac TC Handling (HW only)
7 #include <net/pkt_cls.h>
8 #include <net/tc_act/tc_gact.h>
14 static void tc_fill_all_pass_entry(struct stmmac_tc_entry *entry)
16 memset(entry, 0, sizeof(*entry));
18 entry->is_last = true;
19 entry->is_frag = false;
22 entry->val.match_data = 0x0;
23 entry->val.match_en = 0x0;
25 entry->val.dma_ch_no = 0x0;
28 static struct stmmac_tc_entry *tc_find_entry(struct stmmac_priv *priv,
29 struct tc_cls_u32_offload *cls,
32 struct stmmac_tc_entry *entry, *first = NULL, *dup = NULL;
33 u32 loc = cls->knode.handle;
36 for (i = 0; i < priv->tc_entries_max; i++) {
37 entry = &priv->tc_entries[i];
38 if (!entry->in_use && !first && free)
40 if ((entry->handle == loc) && !free && !entry->is_frag)
51 memset(&first->val, 0, sizeof(first->val));
57 static int tc_fill_actions(struct stmmac_tc_entry *entry,
58 struct stmmac_tc_entry *frag,
59 struct tc_cls_u32_offload *cls)
61 struct stmmac_tc_entry *action_entry = entry;
62 const struct tc_action *act;
63 struct tcf_exts *exts;
66 exts = cls->knode.exts;
67 if (!tcf_exts_has_actions(exts))
72 tcf_exts_for_each_action(i, act, exts) {
74 if (is_tcf_gact_ok(act)) {
75 action_entry->val.af = 1;
79 if (is_tcf_gact_shot(act)) {
80 action_entry->val.rf = 1;
91 static int tc_fill_entry(struct stmmac_priv *priv,
92 struct tc_cls_u32_offload *cls)
94 struct stmmac_tc_entry *entry, *frag = NULL;
95 struct tc_u32_sel *sel = cls->knode.sel;
96 u32 off, data, mask, real_off, rem;
97 u32 prio = cls->common.prio << 16;
100 /* Only 1 match per entry */
101 if (sel->nkeys <= 0 || sel->nkeys > 1)
104 off = sel->keys[0].off << sel->offshift;
105 data = sel->keys[0].val;
106 mask = sel->keys[0].mask;
108 switch (ntohs(cls->common.protocol)) {
118 if (off > priv->tc_off_max)
124 entry = tc_find_entry(priv, cls, true);
129 frag = tc_find_entry(priv, cls, true);
135 entry->frag_ptr = frag;
136 entry->val.match_en = (mask << (rem * 8)) &
137 GENMASK(31, rem * 8);
138 entry->val.match_data = (data << (rem * 8)) &
139 GENMASK(31, rem * 8);
140 entry->val.frame_offset = real_off;
143 frag->val.match_en = (mask >> (rem * 8)) &
144 GENMASK(rem * 8 - 1, 0);
145 frag->val.match_data = (data >> (rem * 8)) &
146 GENMASK(rem * 8 - 1, 0);
147 frag->val.frame_offset = real_off + 1;
149 frag->is_frag = true;
151 entry->frag_ptr = NULL;
152 entry->val.match_en = mask;
153 entry->val.match_data = data;
154 entry->val.frame_offset = real_off;
158 ret = tc_fill_actions(entry, frag, cls);
166 frag->in_use = false;
167 entry->in_use = false;
171 static void tc_unfill_entry(struct stmmac_priv *priv,
172 struct tc_cls_u32_offload *cls)
174 struct stmmac_tc_entry *entry;
176 entry = tc_find_entry(priv, cls, false);
180 entry->in_use = false;
181 if (entry->frag_ptr) {
182 entry = entry->frag_ptr;
183 entry->is_frag = false;
184 entry->in_use = false;
188 static int tc_config_knode(struct stmmac_priv *priv,
189 struct tc_cls_u32_offload *cls)
193 ret = tc_fill_entry(priv, cls);
197 ret = stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries,
198 priv->tc_entries_max);
205 tc_unfill_entry(priv, cls);
209 static int tc_delete_knode(struct stmmac_priv *priv,
210 struct tc_cls_u32_offload *cls)
212 /* Set entry and fragments as not used */
213 tc_unfill_entry(priv, cls);
215 return stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries,
216 priv->tc_entries_max);
219 static int tc_setup_cls_u32(struct stmmac_priv *priv,
220 struct tc_cls_u32_offload *cls)
222 switch (cls->command) {
223 case TC_CLSU32_REPLACE_KNODE:
224 tc_unfill_entry(priv, cls);
226 case TC_CLSU32_NEW_KNODE:
227 return tc_config_knode(priv, cls);
228 case TC_CLSU32_DELETE_KNODE:
229 return tc_delete_knode(priv, cls);
235 static int tc_init(struct stmmac_priv *priv)
237 struct dma_features *dma_cap = &priv->dma_cap;
241 if (dma_cap->l3l4fnum) {
242 priv->flow_entries_max = dma_cap->l3l4fnum;
243 priv->flow_entries = devm_kcalloc(priv->device,
245 sizeof(*priv->flow_entries),
247 if (!priv->flow_entries)
250 for (i = 0; i < priv->flow_entries_max; i++)
251 priv->flow_entries[i].idx = i;
253 dev_info(priv->device, "Enabled Flow TC (entries=%d)\n",
254 priv->flow_entries_max);
257 if (!priv->plat->fpe_cfg) {
258 priv->plat->fpe_cfg = devm_kzalloc(priv->device,
259 sizeof(*priv->plat->fpe_cfg),
261 if (!priv->plat->fpe_cfg)
264 memset(priv->plat->fpe_cfg, 0, sizeof(*priv->plat->fpe_cfg));
267 /* Fail silently as we can still use remaining features, e.g. CBS */
268 if (!dma_cap->frpsel)
271 switch (dma_cap->frpbs) {
273 priv->tc_off_max = 64;
276 priv->tc_off_max = 128;
279 priv->tc_off_max = 256;
285 switch (dma_cap->frpes) {
299 /* Reserve one last filter which lets all pass */
300 priv->tc_entries_max = count;
301 priv->tc_entries = devm_kcalloc(priv->device,
302 count, sizeof(*priv->tc_entries), GFP_KERNEL);
303 if (!priv->tc_entries)
306 tc_fill_all_pass_entry(&priv->tc_entries[count - 1]);
308 dev_info(priv->device, "Enabling HW TC (entries=%d, max_off=%d)\n",
309 priv->tc_entries_max, priv->tc_off_max);
314 static int tc_setup_cbs(struct stmmac_priv *priv,
315 struct tc_cbs_qopt_offload *qopt)
317 u32 tx_queues_count = priv->plat->tx_queues_to_use;
318 u32 queue = qopt->queue;
324 /* Queue 0 is not AVB capable */
325 if (queue <= 0 || queue >= tx_queues_count)
327 if (!priv->dma_cap.av)
330 /* Port Transmit Rate and Speed Divider */
331 switch (priv->speed) {
334 speed_div = 10000000;
356 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
357 if (mode_to_use == MTL_QUEUE_DCB && qopt->enable) {
358 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue, MTL_QUEUE_AVB);
362 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_AVB;
363 } else if (!qopt->enable) {
364 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue,
369 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB;
372 /* Final adjustments for HW */
373 value = div_s64(qopt->idleslope * 1024ll * ptr, speed_div);
374 priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0);
376 value = div_s64(-qopt->sendslope * 1024ll * ptr, speed_div);
377 priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0);
379 value = qopt->hicredit * 1024ll * 8;
380 priv->plat->tx_queues_cfg[queue].high_credit = value & GENMASK(31, 0);
382 value = qopt->locredit * 1024ll * 8;
383 priv->plat->tx_queues_cfg[queue].low_credit = value & GENMASK(31, 0);
385 ret = stmmac_config_cbs(priv, priv->hw,
386 priv->plat->tx_queues_cfg[queue].send_slope,
387 priv->plat->tx_queues_cfg[queue].idle_slope,
388 priv->plat->tx_queues_cfg[queue].high_credit,
389 priv->plat->tx_queues_cfg[queue].low_credit,
394 dev_info(priv->device, "CBS queue %d: send %d, idle %d, hi %d, lo %d\n",
395 queue, qopt->sendslope, qopt->idleslope,
396 qopt->hicredit, qopt->locredit);
400 static int tc_parse_flow_actions(struct stmmac_priv *priv,
401 struct flow_action *action,
402 struct stmmac_flow_entry *entry,
403 struct netlink_ext_ack *extack)
405 struct flow_action_entry *act;
408 if (!flow_action_has_entries(action))
411 if (!flow_action_basic_hw_stats_check(action, extack))
414 flow_action_for_each(i, act, action) {
416 case FLOW_ACTION_DROP:
417 entry->action |= STMMAC_FLOW_ACTION_DROP;
424 /* Nothing to do, maybe inverse filter ? */
428 static int tc_add_basic_flow(struct stmmac_priv *priv,
429 struct flow_cls_offload *cls,
430 struct stmmac_flow_entry *entry)
432 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
433 struct flow_dissector *dissector = rule->match.dissector;
434 struct flow_match_basic match;
436 /* Nothing to do here */
437 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_BASIC))
440 flow_rule_match_basic(rule, &match);
441 entry->ip_proto = match.key->ip_proto;
445 static int tc_add_ip4_flow(struct stmmac_priv *priv,
446 struct flow_cls_offload *cls,
447 struct stmmac_flow_entry *entry)
449 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
450 struct flow_dissector *dissector = rule->match.dissector;
451 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP;
452 struct flow_match_ipv4_addrs match;
456 /* Nothing to do here */
457 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_IPV4_ADDRS))
460 flow_rule_match_ipv4_addrs(rule, &match);
461 hw_match = ntohl(match.key->src) & ntohl(match.mask->src);
463 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true,
464 false, true, inv, hw_match);
469 hw_match = ntohl(match.key->dst) & ntohl(match.mask->dst);
471 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true,
472 false, false, inv, hw_match);
480 static int tc_add_ports_flow(struct stmmac_priv *priv,
481 struct flow_cls_offload *cls,
482 struct stmmac_flow_entry *entry)
484 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
485 struct flow_dissector *dissector = rule->match.dissector;
486 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP;
487 struct flow_match_ports match;
492 /* Nothing to do here */
493 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_PORTS))
496 switch (entry->ip_proto) {
507 flow_rule_match_ports(rule, &match);
509 hw_match = ntohs(match.key->src) & ntohs(match.mask->src);
511 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true,
512 is_udp, true, inv, hw_match);
517 hw_match = ntohs(match.key->dst) & ntohs(match.mask->dst);
519 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true,
520 is_udp, false, inv, hw_match);
529 static struct stmmac_flow_entry *tc_find_flow(struct stmmac_priv *priv,
530 struct flow_cls_offload *cls,
535 for (i = 0; i < priv->flow_entries_max; i++) {
536 struct stmmac_flow_entry *entry = &priv->flow_entries[i];
538 if (entry->cookie == cls->cookie)
540 if (get_free && (entry->in_use == false))
548 int (*fn)(struct stmmac_priv *priv, struct flow_cls_offload *cls,
549 struct stmmac_flow_entry *entry);
550 } tc_flow_parsers[] = {
551 { .fn = tc_add_basic_flow },
552 { .fn = tc_add_ip4_flow },
553 { .fn = tc_add_ports_flow },
556 static int tc_add_flow(struct stmmac_priv *priv,
557 struct flow_cls_offload *cls)
559 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false);
560 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
564 entry = tc_find_flow(priv, cls, true);
569 ret = tc_parse_flow_actions(priv, &rule->action, entry,
574 for (i = 0; i < ARRAY_SIZE(tc_flow_parsers); i++) {
575 ret = tc_flow_parsers[i].fn(priv, cls, entry);
577 entry->in_use = true;
583 entry->cookie = cls->cookie;
587 static int tc_del_flow(struct stmmac_priv *priv,
588 struct flow_cls_offload *cls)
590 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false);
593 if (!entry || !entry->in_use)
597 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, false,
598 false, false, false, 0);
600 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, false,
601 false, false, false, 0);
604 entry->in_use = false;
606 entry->is_l4 = false;
610 #define VLAN_PRIO_FULL_MASK (0x07)
612 static int tc_add_vlan_flow(struct stmmac_priv *priv,
613 struct flow_cls_offload *cls)
615 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
616 struct flow_dissector *dissector = rule->match.dissector;
617 int tc = tc_classid_to_hwtc(priv->dev, cls->classid);
618 struct flow_match_vlan match;
620 /* Nothing to do here */
621 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_VLAN))
625 netdev_err(priv->dev, "Invalid traffic class\n");
629 flow_rule_match_vlan(rule, &match);
631 if (match.mask->vlan_priority) {
634 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
635 netdev_err(priv->dev, "Only full mask is supported for VLAN priority");
639 prio = BIT(match.key->vlan_priority);
640 stmmac_rx_queue_prio(priv, priv->hw, prio, tc);
646 static int tc_del_vlan_flow(struct stmmac_priv *priv,
647 struct flow_cls_offload *cls)
649 struct flow_rule *rule = flow_cls_offload_flow_rule(cls);
650 struct flow_dissector *dissector = rule->match.dissector;
651 int tc = tc_classid_to_hwtc(priv->dev, cls->classid);
653 /* Nothing to do here */
654 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_VLAN))
658 netdev_err(priv->dev, "Invalid traffic class\n");
662 stmmac_rx_queue_prio(priv, priv->hw, 0, tc);
667 static int tc_add_flow_cls(struct stmmac_priv *priv,
668 struct flow_cls_offload *cls)
672 ret = tc_add_flow(priv, cls);
676 return tc_add_vlan_flow(priv, cls);
679 static int tc_del_flow_cls(struct stmmac_priv *priv,
680 struct flow_cls_offload *cls)
684 ret = tc_del_flow(priv, cls);
688 return tc_del_vlan_flow(priv, cls);
691 static int tc_setup_cls(struct stmmac_priv *priv,
692 struct flow_cls_offload *cls)
696 /* When RSS is enabled, the filtering will be bypassed */
697 if (priv->rss.enable)
700 switch (cls->command) {
701 case FLOW_CLS_REPLACE:
702 ret = tc_add_flow_cls(priv, cls);
704 case FLOW_CLS_DESTROY:
705 ret = tc_del_flow_cls(priv, cls);
714 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
715 ktime_t current_time,
718 struct timespec64 time;
720 if (ktime_after(old_base_time, current_time)) {
721 time = ktime_to_timespec64(old_base_time);
726 n = div64_s64(ktime_sub_ns(current_time, old_base_time),
728 base_time = ktime_add_ns(old_base_time,
729 (n + 1) * cycle_time);
731 time = ktime_to_timespec64(base_time);
737 static int tc_setup_taprio(struct stmmac_priv *priv,
738 struct tc_taprio_qopt_offload *qopt)
740 u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep;
741 struct plat_stmmacenet_data *plat = priv->plat;
742 struct timespec64 time, current_time, qopt_time;
743 ktime_t current_time_ns;
748 if (!priv->dma_cap.estsel)
787 if (qopt->num_entries >= dep)
789 if (!qopt->base_time)
791 if (!qopt->cycle_time)
795 plat->est = devm_kzalloc(priv->device, sizeof(*plat->est),
800 mutex_init(&priv->plat->est->lock);
802 memset(plat->est, 0, sizeof(*plat->est));
805 size = qopt->num_entries;
807 mutex_lock(&priv->plat->est->lock);
808 priv->plat->est->gcl_size = size;
809 priv->plat->est->enable = qopt->enable;
810 mutex_unlock(&priv->plat->est->lock);
812 for (i = 0; i < size; i++) {
813 s64 delta_ns = qopt->entries[i].interval;
814 u32 gates = qopt->entries[i].gate_mask;
816 if (delta_ns > GENMASK(wid, 0))
818 if (gates > GENMASK(31 - wid, 0))
821 switch (qopt->entries[i].command) {
822 case TC_TAPRIO_CMD_SET_GATES:
826 case TC_TAPRIO_CMD_SET_AND_HOLD:
830 case TC_TAPRIO_CMD_SET_AND_RELEASE:
838 priv->plat->est->gcl[i] = delta_ns | (gates << wid);
841 mutex_lock(&priv->plat->est->lock);
842 /* Adjust for real system time */
843 priv->ptp_clock_ops.gettime64(&priv->ptp_clock_ops, ¤t_time);
844 current_time_ns = timespec64_to_ktime(current_time);
845 time = stmmac_calc_tas_basetime(qopt->base_time, current_time_ns,
848 priv->plat->est->btr[0] = (u32)time.tv_nsec;
849 priv->plat->est->btr[1] = (u32)time.tv_sec;
851 qopt_time = ktime_to_timespec64(qopt->base_time);
852 priv->plat->est->btr_reserve[0] = (u32)qopt_time.tv_nsec;
853 priv->plat->est->btr_reserve[1] = (u32)qopt_time.tv_sec;
855 ctr = qopt->cycle_time;
856 priv->plat->est->ctr[0] = do_div(ctr, NSEC_PER_SEC);
857 priv->plat->est->ctr[1] = (u32)ctr;
859 if (fpe && !priv->dma_cap.fpesel) {
860 mutex_unlock(&priv->plat->est->lock);
864 /* Actual FPE register configuration will be done after FPE handshake
867 priv->plat->fpe_cfg->enable = fpe;
869 ret = stmmac_est_configure(priv, priv->ioaddr, priv->plat->est,
870 priv->plat->clk_ptp_rate);
871 mutex_unlock(&priv->plat->est->lock);
873 netdev_err(priv->dev, "failed to configure EST\n");
877 netdev_info(priv->dev, "configured EST\n");
880 stmmac_fpe_handshake(priv, true);
881 netdev_info(priv->dev, "start FPE handshake\n");
887 mutex_lock(&priv->plat->est->lock);
888 priv->plat->est->enable = false;
889 stmmac_est_configure(priv, priv->ioaddr, priv->plat->est,
890 priv->plat->clk_ptp_rate);
891 mutex_unlock(&priv->plat->est->lock);
893 priv->plat->fpe_cfg->enable = false;
894 stmmac_fpe_configure(priv, priv->ioaddr,
895 priv->plat->tx_queues_to_use,
896 priv->plat->rx_queues_to_use,
898 netdev_info(priv->dev, "disabled FPE\n");
900 stmmac_fpe_handshake(priv, false);
901 netdev_info(priv->dev, "stop FPE handshake\n");
906 static int tc_setup_etf(struct stmmac_priv *priv,
907 struct tc_etf_qopt_offload *qopt)
909 if (!priv->dma_cap.tbssel)
911 if (qopt->queue >= priv->plat->tx_queues_to_use)
913 if (!(priv->tx_queue[qopt->queue].tbs & STMMAC_TBS_AVAIL))
917 priv->tx_queue[qopt->queue].tbs |= STMMAC_TBS_EN;
919 priv->tx_queue[qopt->queue].tbs &= ~STMMAC_TBS_EN;
921 netdev_info(priv->dev, "%s ETF for Queue %d\n",
922 qopt->enable ? "enabled" : "disabled", qopt->queue);
926 const struct stmmac_tc_ops dwmac510_tc_ops = {
928 .setup_cls_u32 = tc_setup_cls_u32,
929 .setup_cbs = tc_setup_cbs,
930 .setup_cls = tc_setup_cls,
931 .setup_taprio = tc_setup_taprio,
932 .setup_etf = tc_setup_etf,