1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/prefetch.h>
33 #include <linux/pinctrl/consumer.h>
34 #ifdef CONFIG_DEBUG_FS
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif /* CONFIG_DEBUG_FS */
38 #include <linux/net_tstamp.h>
39 #include <linux/phylink.h>
40 #include <linux/udp.h>
41 #include <linux/bpf_trace.h>
42 #include <net/pkt_cls.h>
43 #include <net/xdp_sock_drv.h>
44 #include "stmmac_ptp.h"
46 #include "stmmac_xdp.h"
47 #include <linux/reset.h>
48 #include <linux/of_mdio.h>
49 #include "dwmac1000.h"
53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
56 /* Module parameters */
58 static int watchdog = TX_TIMEO;
59 module_param(watchdog, int, 0644);
60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
62 static int debug = -1;
63 module_param(debug, int, 0644);
64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
66 static int phyaddr = -1;
67 module_param(phyaddr, int, 0444);
68 MODULE_PARM_DESC(phyaddr, "Physical device address");
70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4)
71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4)
73 /* Limit to make sure XDP TX and slow path can coexist */
74 #define STMMAC_XSK_TX_BUDGET_MAX 256
75 #define STMMAC_TX_XSK_AVAIL 16
76 #define STMMAC_RX_FILL_BATCH 16
78 #define STMMAC_XDP_PASS 0
79 #define STMMAC_XDP_CONSUMED BIT(0)
80 #define STMMAC_XDP_TX BIT(1)
81 #define STMMAC_XDP_REDIRECT BIT(2)
83 static int flow_ctrl = FLOW_AUTO;
84 module_param(flow_ctrl, int, 0644);
85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
87 static int pause = PAUSE_TIME;
88 module_param(pause, int, 0644);
89 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
92 static int tc = TC_DEFAULT;
93 module_param(tc, int, 0644);
94 MODULE_PARM_DESC(tc, "DMA threshold control value");
96 #define DEFAULT_BUFSIZE 1536
97 static int buf_sz = DEFAULT_BUFSIZE;
98 module_param(buf_sz, int, 0644);
99 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
101 #define STMMAC_RX_COPYBREAK 256
103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
104 NETIF_MSG_LINK | NETIF_MSG_IFUP |
105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
107 #define STMMAC_DEFAULT_LPI_TIMER 1000
108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
109 module_param(eee_timer, int, 0644);
110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
113 /* By default the driver will use the ring mode to manage tx and rx descriptors,
114 * but allow user to force to use the chain instead of the ring
116 static unsigned int chain_mode;
117 module_param(chain_mode, int, 0444);
118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
121 /* For MSI interrupts handling */
122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
129 #ifdef CONFIG_DEBUG_FS
130 static const struct net_device_ops stmmac_netdev_ops;
131 static void stmmac_init_fs(struct net_device *dev);
132 static void stmmac_exit_fs(struct net_device *dev);
135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
142 ret = clk_prepare_enable(priv->plat->stmmac_clk);
145 ret = clk_prepare_enable(priv->plat->pclk);
147 clk_disable_unprepare(priv->plat->stmmac_clk);
150 if (priv->plat->clks_config) {
151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
153 clk_disable_unprepare(priv->plat->stmmac_clk);
154 clk_disable_unprepare(priv->plat->pclk);
159 clk_disable_unprepare(priv->plat->stmmac_clk);
160 clk_disable_unprepare(priv->plat->pclk);
161 if (priv->plat->clks_config)
162 priv->plat->clks_config(priv->plat->bsp_priv, enabled);
167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
170 * stmmac_verify_args - verify the driver parameters.
171 * Description: it checks the driver parameters and set a default in case of
174 static void stmmac_verify_args(void)
176 if (unlikely(watchdog < 0))
178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
179 buf_sz = DEFAULT_BUFSIZE;
180 if (unlikely(flow_ctrl > 1))
181 flow_ctrl = FLOW_AUTO;
182 else if (likely(flow_ctrl < 0))
183 flow_ctrl = FLOW_OFF;
184 if (unlikely((pause < 0) || (pause > 0xffff)))
187 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
197 for (queue = 0; queue < maxq; queue++) {
198 struct stmmac_channel *ch = &priv->channel[queue];
200 if (stmmac_xdp_is_enabled(priv) &&
201 test_bit(queue, priv->af_xdp_zc_qps)) {
202 napi_disable(&ch->rxtx_napi);
206 if (queue < rx_queues_cnt)
207 napi_disable(&ch->rx_napi);
208 if (queue < tx_queues_cnt)
209 napi_disable(&ch->tx_napi);
214 * stmmac_disable_all_queues - Disable all queues
215 * @priv: driver private structure
217 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
220 struct stmmac_rx_queue *rx_q;
223 /* synchronize_rcu() needed for pending XDP buffers to drain */
224 for (queue = 0; queue < rx_queues_cnt; queue++) {
225 rx_q = &priv->rx_queue[queue];
226 if (rx_q->xsk_pool) {
232 __stmmac_disable_all_queues(priv);
236 * stmmac_enable_all_queues - Enable all queues
237 * @priv: driver private structure
239 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
246 for (queue = 0; queue < maxq; queue++) {
247 struct stmmac_channel *ch = &priv->channel[queue];
249 if (stmmac_xdp_is_enabled(priv) &&
250 test_bit(queue, priv->af_xdp_zc_qps)) {
251 napi_enable(&ch->rxtx_napi);
255 if (queue < rx_queues_cnt)
256 napi_enable(&ch->rx_napi);
257 if (queue < tx_queues_cnt)
258 napi_enable(&ch->tx_napi);
262 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
264 if (!test_bit(STMMAC_DOWN, &priv->state) &&
265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
266 queue_work(priv->wq, &priv->service_task);
269 static void stmmac_global_err(struct stmmac_priv *priv)
271 netif_carrier_off(priv->dev);
272 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
273 stmmac_service_event_schedule(priv);
277 * stmmac_clk_csr_set - dynamically set the MDC clock
278 * @priv: driver private structure
279 * Description: this is to dynamically set the MDC clock according to the csr
282 * If a specific clk_csr value is passed from the platform
283 * this means that the CSR Clock Range selection cannot be
284 * changed at run-time and it is fixed (as reported in the driver
285 * documentation). Viceversa the driver will try to set the MDC
286 * clock dynamically according to the actual clock input.
288 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
292 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
294 /* Platform provided default clk_csr would be assumed valid
295 * for all other cases except for the below mentioned ones.
296 * For values higher than the IEEE 802.3 specified frequency
297 * we can not estimate the proper divider as it is not known
298 * the frequency of clk_csr_i. So we do not change the default
301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
302 if (clk_rate < CSR_F_35M)
303 priv->clk_csr = STMMAC_CSR_20_35M;
304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
305 priv->clk_csr = STMMAC_CSR_35_60M;
306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
307 priv->clk_csr = STMMAC_CSR_60_100M;
308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
309 priv->clk_csr = STMMAC_CSR_100_150M;
310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
311 priv->clk_csr = STMMAC_CSR_150_250M;
312 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
313 priv->clk_csr = STMMAC_CSR_250_300M;
316 if (priv->plat->has_sun8i) {
317 if (clk_rate > 160000000)
318 priv->clk_csr = 0x03;
319 else if (clk_rate > 80000000)
320 priv->clk_csr = 0x02;
321 else if (clk_rate > 40000000)
322 priv->clk_csr = 0x01;
327 if (priv->plat->has_xgmac) {
328 if (clk_rate > 400000000)
330 else if (clk_rate > 350000000)
332 else if (clk_rate > 300000000)
334 else if (clk_rate > 250000000)
336 else if (clk_rate > 150000000)
343 static void print_pkt(unsigned char *buf, int len)
345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
354 if (tx_q->dirty_tx > tx_q->cur_tx)
355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
363 * stmmac_rx_dirty - Get RX queue dirty
364 * @priv: driver private structure
365 * @queue: RX queue index
367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
372 if (rx_q->dirty_rx <= rx_q->cur_rx)
373 dirty = rx_q->cur_rx - rx_q->dirty_rx;
375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */
385 priv->eee_sw_timer_en = en ? 0 : 1;
386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0;
387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
391 * stmmac_enable_eee_mode - check and enter in LPI mode
392 * @priv: driver private structure
393 * Description: this function is to verify and enter in LPI mode in case of
396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
398 u32 tx_cnt = priv->plat->tx_queues_to_use;
401 /* check if all TX queues have the work finished */
402 for (queue = 0; queue < tx_cnt; queue++) {
403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
405 if (tx_q->dirty_tx != tx_q->cur_tx)
406 return; /* still unfinished work */
409 /* Check and enter in LPI mode */
410 if (!priv->tx_path_in_lpi_mode)
411 stmmac_set_eee_mode(priv, priv->hw,
412 priv->plat->en_tx_lpi_clockgating);
416 * stmmac_disable_eee_mode - disable and exit from LPI mode
417 * @priv: driver private structure
418 * Description: this function is to exit and disable EEE in case of
419 * LPI state is true. This is called by the xmit.
421 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
423 if (!priv->eee_sw_timer_en) {
424 stmmac_lpi_entry_timer_config(priv, 0);
428 stmmac_reset_eee_mode(priv, priv->hw);
429 del_timer_sync(&priv->eee_ctrl_timer);
430 priv->tx_path_in_lpi_mode = false;
434 * stmmac_eee_ctrl_timer - EEE TX SW timer.
435 * @t: timer_list struct containing private info
437 * if there is no data transfer and if we are not in LPI state,
438 * then MAC Transmitter can be moved to LPI state.
440 static void stmmac_eee_ctrl_timer(struct timer_list *t)
442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
444 stmmac_enable_eee_mode(priv);
445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
449 * stmmac_eee_init - init EEE
450 * @priv: driver private structure
452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
453 * can also manage EEE, this function enable the LPI state and start related
456 bool stmmac_eee_init(struct stmmac_priv *priv)
458 int eee_tw_timer = priv->eee_tw_timer;
460 /* Using PCS we cannot dial with the phy registers at this stage
461 * so we do not support extra feature like EEE.
463 if (priv->hw->pcs == STMMAC_PCS_TBI ||
464 priv->hw->pcs == STMMAC_PCS_RTBI)
467 /* Check if MAC core supports the EEE feature. */
468 if (!priv->dma_cap.eee)
471 mutex_lock(&priv->lock);
473 /* Check if it needs to be deactivated */
474 if (!priv->eee_active) {
475 if (priv->eee_enabled) {
476 netdev_dbg(priv->dev, "disable EEE\n");
477 stmmac_lpi_entry_timer_config(priv, 0);
478 del_timer_sync(&priv->eee_ctrl_timer);
479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
481 mutex_unlock(&priv->lock);
485 if (priv->eee_active && !priv->eee_enabled) {
486 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
487 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
491 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
492 del_timer_sync(&priv->eee_ctrl_timer);
493 priv->tx_path_in_lpi_mode = false;
494 stmmac_lpi_entry_timer_config(priv, 1);
496 stmmac_lpi_entry_timer_config(priv, 0);
497 mod_timer(&priv->eee_ctrl_timer,
498 STMMAC_LPI_T(priv->tx_lpi_timer));
501 mutex_unlock(&priv->lock);
502 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
506 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
507 * @priv: driver private structure
508 * @p : descriptor pointer
509 * @skb : the socket buffer
511 * This function will read timestamp from the descriptor & pass it to stack.
512 * and also perform some sanity checks.
514 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
515 struct dma_desc *p, struct sk_buff *skb)
517 struct skb_shared_hwtstamps shhwtstamp;
522 if (!priv->hwts_tx_en)
525 /* exit if skb doesn't support hw tstamp */
526 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
529 /* check tx tstamp status */
530 if (stmmac_get_tx_timestamp_status(priv, p)) {
531 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
533 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
538 /* Correct the clk domain crossing(CDC) error */
539 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
540 adjust += -(2 * (NSEC_PER_SEC /
541 priv->plat->clk_ptp_rate));
545 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
546 shhwtstamp.hwtstamp = ns_to_ktime(ns);
548 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
549 /* pass tstamp to stack */
550 skb_tstamp_tx(skb, &shhwtstamp);
554 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
555 * @priv: driver private structure
556 * @p : descriptor pointer
557 * @np : next descriptor pointer
558 * @skb : the socket buffer
560 * This function will read received packet's timestamp from the descriptor
561 * and pass it to stack. It also perform some sanity checks.
563 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
564 struct dma_desc *np, struct sk_buff *skb)
566 struct skb_shared_hwtstamps *shhwtstamp = NULL;
567 struct dma_desc *desc = p;
571 if (!priv->hwts_rx_en)
573 /* For GMAC4, the valid timestamp is from CTX next desc. */
574 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
577 /* Check if timestamp is available */
578 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
579 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
581 /* Correct the clk domain crossing(CDC) error */
582 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) {
583 adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate);
587 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
588 shhwtstamp = skb_hwtstamps(skb);
589 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
590 shhwtstamp->hwtstamp = ns_to_ktime(ns);
592 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
597 * stmmac_hwtstamp_set - control hardware timestamping.
598 * @dev: device pointer.
599 * @ifr: An IOCTL specific structure, that can contain a pointer to
600 * a proprietary structure used to pass information to the driver.
602 * This function configures the MAC to enable/disable both outgoing(TX)
603 * and incoming(RX) packets time stamping based on user input.
605 * 0 on success and an appropriate -ve integer on failure.
607 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
609 struct stmmac_priv *priv = netdev_priv(dev);
610 struct hwtstamp_config config;
611 struct timespec64 now;
615 u32 ptp_over_ipv4_udp = 0;
616 u32 ptp_over_ipv6_udp = 0;
617 u32 ptp_over_ethernet = 0;
618 u32 snap_type_sel = 0;
619 u32 ts_master_en = 0;
625 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
628 netdev_alert(priv->dev, "No support for HW time stamping\n");
629 priv->hwts_tx_en = 0;
630 priv->hwts_rx_en = 0;
635 if (copy_from_user(&config, ifr->ifr_data,
639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
640 __func__, config.flags, config.tx_type, config.rx_filter);
642 /* reserved for future extensions */
646 if (config.tx_type != HWTSTAMP_TX_OFF &&
647 config.tx_type != HWTSTAMP_TX_ON)
651 switch (config.rx_filter) {
652 case HWTSTAMP_FILTER_NONE:
653 /* time stamp no incoming packet at all */
654 config.rx_filter = HWTSTAMP_FILTER_NONE;
657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
658 /* PTP v1, UDP, any kind of event packet */
659 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
660 /* 'xmac' hardware can support Sync, Pdelay_Req and
661 * Pdelay_resp by setting bit14 and bits17/16 to 01
662 * This leaves Delay_Req timestamps out.
663 * Enable all events *and* general purpose message
666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
671 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
672 /* PTP v1, UDP, Sync packet */
673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
674 /* take time stamp for SYNC messages only */
675 ts_event_en = PTP_TCR_TSEVNTENA;
677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
681 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
682 /* PTP v1, UDP, Delay_req packet */
683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
684 /* take time stamp for Delay_Req messages only */
685 ts_master_en = PTP_TCR_TSMSTRENA;
686 ts_event_en = PTP_TCR_TSEVNTENA;
688 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
689 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
693 /* PTP v2, UDP, any kind of event packet */
694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
695 ptp_v2 = PTP_TCR_TSVER2ENA;
696 /* take time stamp for all event messages */
697 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
699 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
700 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
703 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
704 /* PTP v2, UDP, Sync packet */
705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
706 ptp_v2 = PTP_TCR_TSVER2ENA;
707 /* take time stamp for SYNC messages only */
708 ts_event_en = PTP_TCR_TSEVNTENA;
710 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
711 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
714 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
715 /* PTP v2, UDP, Delay_req packet */
716 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
717 ptp_v2 = PTP_TCR_TSVER2ENA;
718 /* take time stamp for Delay_Req messages only */
719 ts_master_en = PTP_TCR_TSMSTRENA;
720 ts_event_en = PTP_TCR_TSEVNTENA;
722 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
723 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
726 case HWTSTAMP_FILTER_PTP_V2_EVENT:
727 /* PTP v2/802.AS1 any layer, any kind of event packet */
728 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
729 ptp_v2 = PTP_TCR_TSVER2ENA;
730 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
731 if (priv->synopsys_id != DWMAC_CORE_5_10)
732 ts_event_en = PTP_TCR_TSEVNTENA;
733 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
734 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
735 ptp_over_ethernet = PTP_TCR_TSIPENA;
738 case HWTSTAMP_FILTER_PTP_V2_SYNC:
739 /* PTP v2/802.AS1, any layer, Sync packet */
740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
741 ptp_v2 = PTP_TCR_TSVER2ENA;
742 /* take time stamp for SYNC messages only */
743 ts_event_en = PTP_TCR_TSEVNTENA;
745 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
746 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
747 ptp_over_ethernet = PTP_TCR_TSIPENA;
750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
751 /* PTP v2/802.AS1, any layer, Delay_req packet */
752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
753 ptp_v2 = PTP_TCR_TSVER2ENA;
754 /* take time stamp for Delay_Req messages only */
755 ts_master_en = PTP_TCR_TSMSTRENA;
756 ts_event_en = PTP_TCR_TSEVNTENA;
758 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
759 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
760 ptp_over_ethernet = PTP_TCR_TSIPENA;
763 case HWTSTAMP_FILTER_NTP_ALL:
764 case HWTSTAMP_FILTER_ALL:
765 /* time stamp any incoming packet */
766 config.rx_filter = HWTSTAMP_FILTER_ALL;
767 tstamp_all = PTP_TCR_TSENALL;
774 switch (config.rx_filter) {
775 case HWTSTAMP_FILTER_NONE:
776 config.rx_filter = HWTSTAMP_FILTER_NONE;
779 /* PTP v1, UDP, any kind of event packet */
780 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
784 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
785 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
787 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
788 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
790 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
791 tstamp_all | ptp_v2 | ptp_over_ethernet |
792 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
793 ts_master_en | snap_type_sel);
794 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
796 /* program Sub Second Increment reg */
797 stmmac_config_sub_second_increment(priv,
798 priv->ptpaddr, priv->plat->clk_ptp_rate,
800 temp = div_u64(1000000000ULL, sec_inc);
802 /* Store sub second increment and flags for later use */
803 priv->sub_second_inc = sec_inc;
804 priv->systime_flags = value;
806 /* calculate default added value:
808 * addend = (2^32)/freq_div_ratio;
809 * where, freq_div_ratio = 1e9ns/sec_inc
811 temp = (u64)(temp << 32);
812 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
813 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
815 /* initialize system time */
816 ktime_get_real_ts64(&now);
818 /* lower 32 bits of tv_sec are safe until y2106 */
819 stmmac_init_systime(priv, priv->ptpaddr,
820 (u32)now.tv_sec, now.tv_nsec);
823 memcpy(&priv->tstamp_config, &config, sizeof(config));
825 return copy_to_user(ifr->ifr_data, &config,
826 sizeof(config)) ? -EFAULT : 0;
830 * stmmac_hwtstamp_get - read hardware timestamping.
831 * @dev: device pointer.
832 * @ifr: An IOCTL specific structure, that can contain a pointer to
833 * a proprietary structure used to pass information to the driver.
835 * This function obtain the current hardware timestamping settings
838 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
840 struct stmmac_priv *priv = netdev_priv(dev);
841 struct hwtstamp_config *config = &priv->tstamp_config;
843 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
846 return copy_to_user(ifr->ifr_data, config,
847 sizeof(*config)) ? -EFAULT : 0;
851 * stmmac_init_ptp - init PTP
852 * @priv: driver private structure
853 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
854 * This is done by looking at the HW cap. register.
855 * This function also registers the ptp driver.
857 static int stmmac_init_ptp(struct stmmac_priv *priv)
859 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
861 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
865 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
866 if (xmac && priv->dma_cap.atime_stamp)
868 /* Dwmac 3.x core with extend_desc can support adv_ts */
869 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
872 if (priv->dma_cap.time_stamp)
873 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
876 netdev_info(priv->dev,
877 "IEEE 1588-2008 Advanced Timestamp supported\n");
879 priv->hwts_tx_en = 0;
880 priv->hwts_rx_en = 0;
882 stmmac_ptp_register(priv);
887 static void stmmac_release_ptp(struct stmmac_priv *priv)
889 clk_disable_unprepare(priv->plat->clk_ptp_ref);
890 stmmac_ptp_unregister(priv);
894 * stmmac_mac_flow_ctrl - Configure flow control in all queues
895 * @priv: driver private structure
896 * @duplex: duplex passed to the next function
897 * Description: It is used for configuring the flow control in all queues
899 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
901 u32 tx_cnt = priv->plat->tx_queues_to_use;
903 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
904 priv->pause, tx_cnt);
907 static void stmmac_validate(struct phylink_config *config,
908 unsigned long *supported,
909 struct phylink_link_state *state)
911 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
912 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
913 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
914 int tx_cnt = priv->plat->tx_queues_to_use;
915 int max_speed = priv->plat->max_speed;
917 phylink_set(mac_supported, 10baseT_Half);
918 phylink_set(mac_supported, 10baseT_Full);
919 phylink_set(mac_supported, 100baseT_Half);
920 phylink_set(mac_supported, 100baseT_Full);
921 phylink_set(mac_supported, 1000baseT_Half);
922 phylink_set(mac_supported, 1000baseT_Full);
923 phylink_set(mac_supported, 1000baseKX_Full);
925 phylink_set(mac_supported, Autoneg);
926 phylink_set(mac_supported, Pause);
927 phylink_set(mac_supported, Asym_Pause);
928 phylink_set_port_modes(mac_supported);
930 /* Cut down 1G if asked to */
931 if ((max_speed > 0) && (max_speed < 1000)) {
932 phylink_set(mask, 1000baseT_Full);
933 phylink_set(mask, 1000baseX_Full);
934 } else if (priv->plat->has_gmac4) {
935 if (!max_speed || max_speed >= 2500) {
936 phylink_set(mac_supported, 2500baseT_Full);
937 phylink_set(mac_supported, 2500baseX_Full);
939 } else if (priv->plat->has_xgmac) {
940 if (!max_speed || (max_speed >= 2500)) {
941 phylink_set(mac_supported, 2500baseT_Full);
942 phylink_set(mac_supported, 2500baseX_Full);
944 if (!max_speed || (max_speed >= 5000)) {
945 phylink_set(mac_supported, 5000baseT_Full);
947 if (!max_speed || (max_speed >= 10000)) {
948 phylink_set(mac_supported, 10000baseSR_Full);
949 phylink_set(mac_supported, 10000baseLR_Full);
950 phylink_set(mac_supported, 10000baseER_Full);
951 phylink_set(mac_supported, 10000baseLRM_Full);
952 phylink_set(mac_supported, 10000baseT_Full);
953 phylink_set(mac_supported, 10000baseKX4_Full);
954 phylink_set(mac_supported, 10000baseKR_Full);
956 if (!max_speed || (max_speed >= 25000)) {
957 phylink_set(mac_supported, 25000baseCR_Full);
958 phylink_set(mac_supported, 25000baseKR_Full);
959 phylink_set(mac_supported, 25000baseSR_Full);
961 if (!max_speed || (max_speed >= 40000)) {
962 phylink_set(mac_supported, 40000baseKR4_Full);
963 phylink_set(mac_supported, 40000baseCR4_Full);
964 phylink_set(mac_supported, 40000baseSR4_Full);
965 phylink_set(mac_supported, 40000baseLR4_Full);
967 if (!max_speed || (max_speed >= 50000)) {
968 phylink_set(mac_supported, 50000baseCR2_Full);
969 phylink_set(mac_supported, 50000baseKR2_Full);
970 phylink_set(mac_supported, 50000baseSR2_Full);
971 phylink_set(mac_supported, 50000baseKR_Full);
972 phylink_set(mac_supported, 50000baseSR_Full);
973 phylink_set(mac_supported, 50000baseCR_Full);
974 phylink_set(mac_supported, 50000baseLR_ER_FR_Full);
975 phylink_set(mac_supported, 50000baseDR_Full);
977 if (!max_speed || (max_speed >= 100000)) {
978 phylink_set(mac_supported, 100000baseKR4_Full);
979 phylink_set(mac_supported, 100000baseSR4_Full);
980 phylink_set(mac_supported, 100000baseCR4_Full);
981 phylink_set(mac_supported, 100000baseLR4_ER4_Full);
982 phylink_set(mac_supported, 100000baseKR2_Full);
983 phylink_set(mac_supported, 100000baseSR2_Full);
984 phylink_set(mac_supported, 100000baseCR2_Full);
985 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full);
986 phylink_set(mac_supported, 100000baseDR2_Full);
990 /* Half-Duplex can only work with single queue */
992 phylink_set(mask, 10baseT_Half);
993 phylink_set(mask, 100baseT_Half);
994 phylink_set(mask, 1000baseT_Half);
997 linkmode_and(supported, supported, mac_supported);
998 linkmode_andnot(supported, supported, mask);
1000 linkmode_and(state->advertising, state->advertising, mac_supported);
1001 linkmode_andnot(state->advertising, state->advertising, mask);
1003 /* If PCS is supported, check which modes it supports. */
1005 xpcs_validate(priv->hw->xpcs, supported, state);
1008 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
1009 const struct phylink_link_state *state)
1011 /* Nothing to do, xpcs_config() handles everything */
1014 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
1016 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
1017 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
1018 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
1019 bool *hs_enable = &fpe_cfg->hs_enable;
1021 if (is_up && *hs_enable) {
1022 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
1024 *lo_state = FPE_STATE_OFF;
1025 *lp_state = FPE_STATE_OFF;
1029 static void stmmac_mac_link_down(struct phylink_config *config,
1030 unsigned int mode, phy_interface_t interface)
1032 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1034 stmmac_mac_set(priv, priv->ioaddr, false);
1035 priv->eee_active = false;
1036 priv->tx_lpi_enabled = false;
1037 stmmac_eee_init(priv);
1038 stmmac_set_eee_pls(priv, priv->hw, false);
1040 if (priv->dma_cap.fpesel)
1041 stmmac_fpe_link_state_handle(priv, false);
1044 static void stmmac_mac_link_up(struct phylink_config *config,
1045 struct phy_device *phy,
1046 unsigned int mode, phy_interface_t interface,
1047 int speed, int duplex,
1048 bool tx_pause, bool rx_pause)
1050 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
1053 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
1054 ctrl &= ~priv->hw->link.speed_mask;
1056 if (interface == PHY_INTERFACE_MODE_USXGMII) {
1059 ctrl |= priv->hw->link.xgmii.speed10000;
1062 ctrl |= priv->hw->link.xgmii.speed5000;
1065 ctrl |= priv->hw->link.xgmii.speed2500;
1070 } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1073 ctrl |= priv->hw->link.xlgmii.speed100000;
1076 ctrl |= priv->hw->link.xlgmii.speed50000;
1079 ctrl |= priv->hw->link.xlgmii.speed40000;
1082 ctrl |= priv->hw->link.xlgmii.speed25000;
1085 ctrl |= priv->hw->link.xgmii.speed10000;
1088 ctrl |= priv->hw->link.speed2500;
1091 ctrl |= priv->hw->link.speed1000;
1099 ctrl |= priv->hw->link.speed2500;
1102 ctrl |= priv->hw->link.speed1000;
1105 ctrl |= priv->hw->link.speed100;
1108 ctrl |= priv->hw->link.speed10;
1115 priv->speed = speed;
1117 if (priv->plat->fix_mac_speed)
1118 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1121 ctrl &= ~priv->hw->link.duplex;
1123 ctrl |= priv->hw->link.duplex;
1125 /* Flow Control operation */
1126 if (tx_pause && rx_pause)
1127 stmmac_mac_flow_ctrl(priv, duplex);
1129 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1131 stmmac_mac_set(priv, priv->ioaddr, true);
1132 if (phy && priv->dma_cap.eee) {
1133 priv->eee_active = phy_init_eee(phy, 1) >= 0;
1134 priv->eee_enabled = stmmac_eee_init(priv);
1135 priv->tx_lpi_enabled = priv->eee_enabled;
1136 stmmac_set_eee_pls(priv, priv->hw, true);
1139 if (priv->dma_cap.fpesel)
1140 stmmac_fpe_link_state_handle(priv, true);
1143 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1144 .validate = stmmac_validate,
1145 .mac_config = stmmac_mac_config,
1146 .mac_link_down = stmmac_mac_link_down,
1147 .mac_link_up = stmmac_mac_link_up,
1151 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1152 * @priv: driver private structure
1153 * Description: this is to verify if the HW supports the PCS.
1154 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1155 * configured for the TBI, RTBI, or SGMII PHY interface.
1157 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1159 int interface = priv->plat->interface;
1161 if (priv->dma_cap.pcs) {
1162 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1163 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1164 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1165 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1166 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1167 priv->hw->pcs = STMMAC_PCS_RGMII;
1168 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1169 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1170 priv->hw->pcs = STMMAC_PCS_SGMII;
1176 * stmmac_init_phy - PHY initialization
1177 * @dev: net device structure
1178 * Description: it initializes the driver's PHY state, and attaches the PHY
1179 * to the mac driver.
1183 static int stmmac_init_phy(struct net_device *dev)
1185 struct stmmac_priv *priv = netdev_priv(dev);
1186 struct device_node *node;
1189 node = priv->plat->phylink_node;
1192 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1194 /* Some DT bindings do not set-up the PHY handle. Let's try to
1198 int addr = priv->plat->phy_addr;
1199 struct phy_device *phydev;
1201 phydev = mdiobus_get_phy(priv->mii, addr);
1203 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1207 ret = phylink_connect_phy(priv->phylink, phydev);
1210 if (!priv->plat->pmt) {
1211 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1213 phylink_ethtool_get_wol(priv->phylink, &wol);
1214 device_set_wakeup_capable(priv->device, !!wol.supported);
1220 static int stmmac_phy_setup(struct stmmac_priv *priv)
1222 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1223 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1224 int mode = priv->plat->phy_interface;
1225 struct phylink *phylink;
1227 priv->phylink_config.dev = &priv->dev->dev;
1228 priv->phylink_config.type = PHYLINK_NETDEV;
1229 priv->phylink_config.pcs_poll = true;
1230 if (priv->plat->mdio_bus_data)
1231 priv->phylink_config.ovr_an_inband =
1232 mdio_bus_data->xpcs_an_inband;
1235 fwnode = dev_fwnode(priv->device);
1237 phylink = phylink_create(&priv->phylink_config, fwnode,
1238 mode, &stmmac_phylink_mac_ops);
1239 if (IS_ERR(phylink))
1240 return PTR_ERR(phylink);
1243 phylink_set_pcs(phylink, &priv->hw->xpcs->pcs);
1245 priv->phylink = phylink;
1249 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1251 u32 rx_cnt = priv->plat->rx_queues_to_use;
1252 unsigned int desc_size;
1256 /* Display RX rings */
1257 for (queue = 0; queue < rx_cnt; queue++) {
1258 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1260 pr_info("\tRX Queue %u rings\n", queue);
1262 if (priv->extend_desc) {
1263 head_rx = (void *)rx_q->dma_erx;
1264 desc_size = sizeof(struct dma_extended_desc);
1266 head_rx = (void *)rx_q->dma_rx;
1267 desc_size = sizeof(struct dma_desc);
1270 /* Display RX ring */
1271 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true,
1272 rx_q->dma_rx_phy, desc_size);
1276 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1278 u32 tx_cnt = priv->plat->tx_queues_to_use;
1279 unsigned int desc_size;
1283 /* Display TX rings */
1284 for (queue = 0; queue < tx_cnt; queue++) {
1285 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1287 pr_info("\tTX Queue %d rings\n", queue);
1289 if (priv->extend_desc) {
1290 head_tx = (void *)tx_q->dma_etx;
1291 desc_size = sizeof(struct dma_extended_desc);
1292 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1293 head_tx = (void *)tx_q->dma_entx;
1294 desc_size = sizeof(struct dma_edesc);
1296 head_tx = (void *)tx_q->dma_tx;
1297 desc_size = sizeof(struct dma_desc);
1300 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false,
1301 tx_q->dma_tx_phy, desc_size);
1305 static void stmmac_display_rings(struct stmmac_priv *priv)
1307 /* Display RX ring */
1308 stmmac_display_rx_rings(priv);
1310 /* Display TX ring */
1311 stmmac_display_tx_rings(priv);
1314 static int stmmac_set_bfsize(int mtu, int bufsize)
1318 if (mtu >= BUF_SIZE_8KiB)
1319 ret = BUF_SIZE_16KiB;
1320 else if (mtu >= BUF_SIZE_4KiB)
1321 ret = BUF_SIZE_8KiB;
1322 else if (mtu >= BUF_SIZE_2KiB)
1323 ret = BUF_SIZE_4KiB;
1324 else if (mtu > DEFAULT_BUFSIZE)
1325 ret = BUF_SIZE_2KiB;
1327 ret = DEFAULT_BUFSIZE;
1333 * stmmac_clear_rx_descriptors - clear RX descriptors
1334 * @priv: driver private structure
1335 * @queue: RX queue index
1336 * Description: this function is called to clear the RX descriptors
1337 * in case of both basic and extended descriptors are used.
1339 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1341 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1344 /* Clear the RX descriptors */
1345 for (i = 0; i < priv->dma_rx_size; i++)
1346 if (priv->extend_desc)
1347 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1348 priv->use_riwt, priv->mode,
1349 (i == priv->dma_rx_size - 1),
1352 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1353 priv->use_riwt, priv->mode,
1354 (i == priv->dma_rx_size - 1),
1359 * stmmac_clear_tx_descriptors - clear tx descriptors
1360 * @priv: driver private structure
1361 * @queue: TX queue index.
1362 * Description: this function is called to clear the TX descriptors
1363 * in case of both basic and extended descriptors are used.
1365 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1367 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1370 /* Clear the TX descriptors */
1371 for (i = 0; i < priv->dma_tx_size; i++) {
1372 int last = (i == (priv->dma_tx_size - 1));
1375 if (priv->extend_desc)
1376 p = &tx_q->dma_etx[i].basic;
1377 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1378 p = &tx_q->dma_entx[i].basic;
1380 p = &tx_q->dma_tx[i];
1382 stmmac_init_tx_desc(priv, p, priv->mode, last);
1387 * stmmac_clear_descriptors - clear descriptors
1388 * @priv: driver private structure
1389 * Description: this function is called to clear the TX and RX descriptors
1390 * in case of both basic and extended descriptors are used.
1392 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1394 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1395 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1398 /* Clear the RX descriptors */
1399 for (queue = 0; queue < rx_queue_cnt; queue++)
1400 stmmac_clear_rx_descriptors(priv, queue);
1402 /* Clear the TX descriptors */
1403 for (queue = 0; queue < tx_queue_cnt; queue++)
1404 stmmac_clear_tx_descriptors(priv, queue);
1408 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1409 * @priv: driver private structure
1410 * @p: descriptor pointer
1411 * @i: descriptor index
1413 * @queue: RX queue index
1414 * Description: this function is called to allocate a receive buffer, perform
1415 * the DMA mapping and init the descriptor.
1417 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1418 int i, gfp_t flags, u32 queue)
1420 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1421 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1424 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1427 buf->page_offset = stmmac_rx_offset(priv);
1430 if (priv->sph && !buf->sec_page) {
1431 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1435 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1436 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1438 buf->sec_page = NULL;
1439 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1442 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1444 stmmac_set_desc_addr(priv, p, buf->addr);
1445 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1446 stmmac_init_desc3(priv, p);
1452 * stmmac_free_rx_buffer - free RX dma buffers
1453 * @priv: private structure
1454 * @queue: RX queue index
1457 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1459 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1460 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1463 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1467 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1468 buf->sec_page = NULL;
1472 * stmmac_free_tx_buffer - free RX dma buffers
1473 * @priv: private structure
1474 * @queue: RX queue index
1477 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1479 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1481 if (tx_q->tx_skbuff_dma[i].buf &&
1482 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1483 if (tx_q->tx_skbuff_dma[i].map_as_page)
1484 dma_unmap_page(priv->device,
1485 tx_q->tx_skbuff_dma[i].buf,
1486 tx_q->tx_skbuff_dma[i].len,
1489 dma_unmap_single(priv->device,
1490 tx_q->tx_skbuff_dma[i].buf,
1491 tx_q->tx_skbuff_dma[i].len,
1495 if (tx_q->xdpf[i] &&
1496 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1497 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1498 xdp_return_frame(tx_q->xdpf[i]);
1499 tx_q->xdpf[i] = NULL;
1502 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1503 tx_q->xsk_frames_done++;
1505 if (tx_q->tx_skbuff[i] &&
1506 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1507 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1508 tx_q->tx_skbuff[i] = NULL;
1511 tx_q->tx_skbuff_dma[i].buf = 0;
1512 tx_q->tx_skbuff_dma[i].map_as_page = false;
1516 * dma_free_rx_skbufs - free RX dma buffers
1517 * @priv: private structure
1518 * @queue: RX queue index
1520 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1524 for (i = 0; i < priv->dma_rx_size; i++)
1525 stmmac_free_rx_buffer(priv, queue, i);
1528 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue,
1531 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1534 for (i = 0; i < priv->dma_rx_size; i++) {
1538 if (priv->extend_desc)
1539 p = &((rx_q->dma_erx + i)->basic);
1541 p = rx_q->dma_rx + i;
1543 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1548 rx_q->buf_alloc_num++;
1555 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1556 * @priv: private structure
1557 * @queue: RX queue index
1559 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
1561 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1564 for (i = 0; i < priv->dma_rx_size; i++) {
1565 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1570 xsk_buff_free(buf->xdp);
1575 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
1577 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1580 for (i = 0; i < priv->dma_rx_size; i++) {
1581 struct stmmac_rx_buffer *buf;
1582 dma_addr_t dma_addr;
1585 if (priv->extend_desc)
1586 p = (struct dma_desc *)(rx_q->dma_erx + i);
1588 p = rx_q->dma_rx + i;
1590 buf = &rx_q->buf_pool[i];
1592 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1596 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1597 stmmac_set_desc_addr(priv, p, dma_addr);
1598 rx_q->buf_alloc_num++;
1604 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1606 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1609 return xsk_get_pool_from_qid(priv->dev, queue);
1613 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1614 * @priv: driver private structure
1615 * @queue: RX queue index
1617 * Description: this function initializes the DMA RX descriptors
1618 * and allocates the socket buffers. It supports the chained and ring
1621 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
1623 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1626 netif_dbg(priv, probe, priv->dev,
1627 "(%s) dma_rx_phy=0x%08x\n", __func__,
1628 (u32)rx_q->dma_rx_phy);
1630 stmmac_clear_rx_descriptors(priv, queue);
1632 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1634 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1636 if (rx_q->xsk_pool) {
1637 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1638 MEM_TYPE_XSK_BUFF_POOL,
1640 netdev_info(priv->dev,
1641 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1643 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1645 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1648 netdev_info(priv->dev,
1649 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1653 if (rx_q->xsk_pool) {
1654 /* RX XDP ZC buffer pool may not be populated, e.g.
1657 stmmac_alloc_rx_buffers_zc(priv, queue);
1659 ret = stmmac_alloc_rx_buffers(priv, queue, flags);
1667 /* Setup the chained descriptor addresses */
1668 if (priv->mode == STMMAC_CHAIN_MODE) {
1669 if (priv->extend_desc)
1670 stmmac_mode_init(priv, rx_q->dma_erx,
1672 priv->dma_rx_size, 1);
1674 stmmac_mode_init(priv, rx_q->dma_rx,
1676 priv->dma_rx_size, 0);
1682 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1684 struct stmmac_priv *priv = netdev_priv(dev);
1685 u32 rx_count = priv->plat->rx_queues_to_use;
1689 /* RX INITIALIZATION */
1690 netif_dbg(priv, probe, priv->dev,
1691 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1693 for (queue = 0; queue < rx_count; queue++) {
1694 ret = __init_dma_rx_desc_rings(priv, queue, flags);
1696 goto err_init_rx_buffers;
1701 err_init_rx_buffers:
1702 while (queue >= 0) {
1703 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1706 dma_free_rx_xskbufs(priv, queue);
1708 dma_free_rx_skbufs(priv, queue);
1710 rx_q->buf_alloc_num = 0;
1711 rx_q->xsk_pool = NULL;
1723 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1724 * @priv: driver private structure
1725 * @queue : TX queue index
1726 * Description: this function initializes the DMA TX descriptors
1727 * and allocates the socket buffers. It supports the chained and ring
1730 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
1732 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1735 netif_dbg(priv, probe, priv->dev,
1736 "(%s) dma_tx_phy=0x%08x\n", __func__,
1737 (u32)tx_q->dma_tx_phy);
1739 /* Setup the chained descriptor addresses */
1740 if (priv->mode == STMMAC_CHAIN_MODE) {
1741 if (priv->extend_desc)
1742 stmmac_mode_init(priv, tx_q->dma_etx,
1744 priv->dma_tx_size, 1);
1745 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1746 stmmac_mode_init(priv, tx_q->dma_tx,
1748 priv->dma_tx_size, 0);
1751 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1753 for (i = 0; i < priv->dma_tx_size; i++) {
1756 if (priv->extend_desc)
1757 p = &((tx_q->dma_etx + i)->basic);
1758 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1759 p = &((tx_q->dma_entx + i)->basic);
1761 p = tx_q->dma_tx + i;
1763 stmmac_clear_desc(priv, p);
1765 tx_q->tx_skbuff_dma[i].buf = 0;
1766 tx_q->tx_skbuff_dma[i].map_as_page = false;
1767 tx_q->tx_skbuff_dma[i].len = 0;
1768 tx_q->tx_skbuff_dma[i].last_segment = false;
1769 tx_q->tx_skbuff[i] = NULL;
1776 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1781 static int init_dma_tx_desc_rings(struct net_device *dev)
1783 struct stmmac_priv *priv = netdev_priv(dev);
1787 tx_queue_cnt = priv->plat->tx_queues_to_use;
1789 for (queue = 0; queue < tx_queue_cnt; queue++)
1790 __init_dma_tx_desc_rings(priv, queue);
1796 * init_dma_desc_rings - init the RX/TX descriptor rings
1797 * @dev: net device structure
1799 * Description: this function initializes the DMA RX/TX descriptors
1800 * and allocates the socket buffers. It supports the chained and ring
1803 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1805 struct stmmac_priv *priv = netdev_priv(dev);
1808 ret = init_dma_rx_desc_rings(dev, flags);
1812 ret = init_dma_tx_desc_rings(dev);
1814 stmmac_clear_descriptors(priv);
1816 if (netif_msg_hw(priv))
1817 stmmac_display_rings(priv);
1823 * dma_free_tx_skbufs - free TX dma buffers
1824 * @priv: private structure
1825 * @queue: TX queue index
1827 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1829 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1832 tx_q->xsk_frames_done = 0;
1834 for (i = 0; i < priv->dma_tx_size; i++)
1835 stmmac_free_tx_buffer(priv, queue, i);
1837 if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1838 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1839 tx_q->xsk_frames_done = 0;
1840 tx_q->xsk_pool = NULL;
1845 * stmmac_free_tx_skbufs - free TX skb buffers
1846 * @priv: private structure
1848 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1850 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1853 for (queue = 0; queue < tx_queue_cnt; queue++)
1854 dma_free_tx_skbufs(priv, queue);
1858 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1859 * @priv: private structure
1860 * @queue: RX queue index
1862 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1864 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1866 /* Release the DMA RX socket buffers */
1868 dma_free_rx_xskbufs(priv, queue);
1870 dma_free_rx_skbufs(priv, queue);
1872 rx_q->buf_alloc_num = 0;
1873 rx_q->xsk_pool = NULL;
1875 /* Free DMA regions of consistent memory previously allocated */
1876 if (!priv->extend_desc)
1877 dma_free_coherent(priv->device, priv->dma_rx_size *
1878 sizeof(struct dma_desc),
1879 rx_q->dma_rx, rx_q->dma_rx_phy);
1881 dma_free_coherent(priv->device, priv->dma_rx_size *
1882 sizeof(struct dma_extended_desc),
1883 rx_q->dma_erx, rx_q->dma_rx_phy);
1885 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1886 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1888 kfree(rx_q->buf_pool);
1889 if (rx_q->page_pool)
1890 page_pool_destroy(rx_q->page_pool);
1893 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1895 u32 rx_count = priv->plat->rx_queues_to_use;
1898 /* Free RX queue resources */
1899 for (queue = 0; queue < rx_count; queue++)
1900 __free_dma_rx_desc_resources(priv, queue);
1904 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1905 * @priv: private structure
1906 * @queue: TX queue index
1908 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
1910 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1914 /* Release the DMA TX socket buffers */
1915 dma_free_tx_skbufs(priv, queue);
1917 if (priv->extend_desc) {
1918 size = sizeof(struct dma_extended_desc);
1919 addr = tx_q->dma_etx;
1920 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1921 size = sizeof(struct dma_edesc);
1922 addr = tx_q->dma_entx;
1924 size = sizeof(struct dma_desc);
1925 addr = tx_q->dma_tx;
1928 size *= priv->dma_tx_size;
1930 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1932 kfree(tx_q->tx_skbuff_dma);
1933 kfree(tx_q->tx_skbuff);
1936 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1938 u32 tx_count = priv->plat->tx_queues_to_use;
1941 /* Free TX queue resources */
1942 for (queue = 0; queue < tx_count; queue++)
1943 __free_dma_tx_desc_resources(priv, queue);
1947 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
1948 * @priv: private structure
1949 * @queue: RX queue index
1950 * Description: according to which descriptor can be used (extend or basic)
1951 * this function allocates the resources for TX and RX paths. In case of
1952 * reception, for example, it pre-allocated the RX socket buffer in order to
1953 * allow zero-copy mechanism.
1955 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
1957 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1958 struct stmmac_channel *ch = &priv->channel[queue];
1959 bool xdp_prog = stmmac_xdp_is_enabled(priv);
1960 struct page_pool_params pp_params = { 0 };
1961 unsigned int num_pages;
1962 unsigned int napi_id;
1965 rx_q->queue_index = queue;
1966 rx_q->priv_data = priv;
1968 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
1969 pp_params.pool_size = priv->dma_rx_size;
1970 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1971 pp_params.order = ilog2(num_pages);
1972 pp_params.nid = dev_to_node(priv->device);
1973 pp_params.dev = priv->device;
1974 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
1975 pp_params.offset = stmmac_rx_offset(priv);
1976 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
1978 rx_q->page_pool = page_pool_create(&pp_params);
1979 if (IS_ERR(rx_q->page_pool)) {
1980 ret = PTR_ERR(rx_q->page_pool);
1981 rx_q->page_pool = NULL;
1985 rx_q->buf_pool = kcalloc(priv->dma_rx_size,
1986 sizeof(*rx_q->buf_pool),
1988 if (!rx_q->buf_pool)
1991 if (priv->extend_desc) {
1992 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1994 sizeof(struct dma_extended_desc),
2001 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2003 sizeof(struct dma_desc),
2010 if (stmmac_xdp_is_enabled(priv) &&
2011 test_bit(queue, priv->af_xdp_zc_qps))
2012 napi_id = ch->rxtx_napi.napi_id;
2014 napi_id = ch->rx_napi.napi_id;
2016 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2020 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2027 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
2029 u32 rx_count = priv->plat->rx_queues_to_use;
2033 /* RX queues buffers and DMA */
2034 for (queue = 0; queue < rx_count; queue++) {
2035 ret = __alloc_dma_rx_desc_resources(priv, queue);
2043 free_dma_rx_desc_resources(priv);
2049 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2050 * @priv: private structure
2051 * @queue: TX queue index
2052 * Description: according to which descriptor can be used (extend or basic)
2053 * this function allocates the resources for TX and RX paths. In case of
2054 * reception, for example, it pre-allocated the RX socket buffer in order to
2055 * allow zero-copy mechanism.
2057 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
2059 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2063 tx_q->queue_index = queue;
2064 tx_q->priv_data = priv;
2066 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size,
2067 sizeof(*tx_q->tx_skbuff_dma),
2069 if (!tx_q->tx_skbuff_dma)
2072 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size,
2073 sizeof(struct sk_buff *),
2075 if (!tx_q->tx_skbuff)
2078 if (priv->extend_desc)
2079 size = sizeof(struct dma_extended_desc);
2080 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2081 size = sizeof(struct dma_edesc);
2083 size = sizeof(struct dma_desc);
2085 size *= priv->dma_tx_size;
2087 addr = dma_alloc_coherent(priv->device, size,
2088 &tx_q->dma_tx_phy, GFP_KERNEL);
2092 if (priv->extend_desc)
2093 tx_q->dma_etx = addr;
2094 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2095 tx_q->dma_entx = addr;
2097 tx_q->dma_tx = addr;
2102 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
2104 u32 tx_count = priv->plat->tx_queues_to_use;
2108 /* TX queues buffers and DMA */
2109 for (queue = 0; queue < tx_count; queue++) {
2110 ret = __alloc_dma_tx_desc_resources(priv, queue);
2118 free_dma_tx_desc_resources(priv);
2123 * alloc_dma_desc_resources - alloc TX/RX resources.
2124 * @priv: private structure
2125 * Description: according to which descriptor can be used (extend or basic)
2126 * this function allocates the resources for TX and RX paths. In case of
2127 * reception, for example, it pre-allocated the RX socket buffer in order to
2128 * allow zero-copy mechanism.
2130 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
2133 int ret = alloc_dma_rx_desc_resources(priv);
2138 ret = alloc_dma_tx_desc_resources(priv);
2144 * free_dma_desc_resources - free dma desc resources
2145 * @priv: private structure
2147 static void free_dma_desc_resources(struct stmmac_priv *priv)
2149 /* Release the DMA TX socket buffers */
2150 free_dma_tx_desc_resources(priv);
2152 /* Release the DMA RX socket buffers later
2153 * to ensure all pending XDP_TX buffers are returned.
2155 free_dma_rx_desc_resources(priv);
2159 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
2160 * @priv: driver private structure
2161 * Description: It is used for enabling the rx queues in the MAC
2163 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2165 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2169 for (queue = 0; queue < rx_queues_count; queue++) {
2170 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2171 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2176 * stmmac_start_rx_dma - start RX DMA channel
2177 * @priv: driver private structure
2178 * @chan: RX channel index
2180 * This starts a RX DMA channel
2182 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2184 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2185 stmmac_start_rx(priv, priv->ioaddr, chan);
2189 * stmmac_start_tx_dma - start TX DMA channel
2190 * @priv: driver private structure
2191 * @chan: TX channel index
2193 * This starts a TX DMA channel
2195 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2197 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2198 stmmac_start_tx(priv, priv->ioaddr, chan);
2202 * stmmac_stop_rx_dma - stop RX DMA channel
2203 * @priv: driver private structure
2204 * @chan: RX channel index
2206 * This stops a RX DMA channel
2208 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2210 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2211 stmmac_stop_rx(priv, priv->ioaddr, chan);
2215 * stmmac_stop_tx_dma - stop TX DMA channel
2216 * @priv: driver private structure
2217 * @chan: TX channel index
2219 * This stops a TX DMA channel
2221 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2223 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2224 stmmac_stop_tx(priv, priv->ioaddr, chan);
2228 * stmmac_start_all_dma - start all RX and TX DMA channels
2229 * @priv: driver private structure
2231 * This starts all the RX and TX DMA channels
2233 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2235 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2236 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2239 for (chan = 0; chan < rx_channels_count; chan++)
2240 stmmac_start_rx_dma(priv, chan);
2242 for (chan = 0; chan < tx_channels_count; chan++)
2243 stmmac_start_tx_dma(priv, chan);
2247 * stmmac_stop_all_dma - stop all RX and TX DMA channels
2248 * @priv: driver private structure
2250 * This stops the RX and TX DMA channels
2252 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2254 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2255 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2258 for (chan = 0; chan < rx_channels_count; chan++)
2259 stmmac_stop_rx_dma(priv, chan);
2261 for (chan = 0; chan < tx_channels_count; chan++)
2262 stmmac_stop_tx_dma(priv, chan);
2266 * stmmac_dma_operation_mode - HW DMA operation mode
2267 * @priv: driver private structure
2268 * Description: it is used for configuring the DMA operation mode register in
2269 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2271 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2273 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2274 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2275 int rxfifosz = priv->plat->rx_fifo_size;
2276 int txfifosz = priv->plat->tx_fifo_size;
2283 rxfifosz = priv->dma_cap.rx_fifo_size;
2285 txfifosz = priv->dma_cap.tx_fifo_size;
2287 /* Adjust for real per queue fifo size */
2288 rxfifosz /= rx_channels_count;
2289 txfifosz /= tx_channels_count;
2291 if (priv->plat->force_thresh_dma_mode) {
2294 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2296 * In case of GMAC, SF mode can be enabled
2297 * to perform the TX COE in HW. This depends on:
2298 * 1) TX COE if actually supported
2299 * 2) There is no bugged Jumbo frame support
2300 * that needs to not insert csum in the TDES.
2302 txmode = SF_DMA_MODE;
2303 rxmode = SF_DMA_MODE;
2304 priv->xstats.threshold = SF_DMA_MODE;
2307 rxmode = SF_DMA_MODE;
2310 /* configure all channels */
2311 for (chan = 0; chan < rx_channels_count; chan++) {
2312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2315 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2317 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2320 if (rx_q->xsk_pool) {
2321 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2322 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2326 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2332 for (chan = 0; chan < tx_channels_count; chan++) {
2333 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2335 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2340 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2342 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2343 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2344 struct xsk_buff_pool *pool = tx_q->xsk_pool;
2345 unsigned int entry = tx_q->cur_tx;
2346 struct dma_desc *tx_desc = NULL;
2347 struct xdp_desc xdp_desc;
2348 bool work_done = true;
2350 /* Avoids TX time-out as we are sharing with slow path */
2351 nq->trans_start = jiffies;
2353 budget = min(budget, stmmac_tx_avail(priv, queue));
2355 while (budget-- > 0) {
2356 dma_addr_t dma_addr;
2359 /* We are sharing with slow path and stop XSK TX desc submission when
2360 * available TX ring is less than threshold.
2362 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2363 !netif_carrier_ok(priv->dev)) {
2368 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2371 if (likely(priv->extend_desc))
2372 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2373 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2374 tx_desc = &tx_q->dma_entx[entry].basic;
2376 tx_desc = tx_q->dma_tx + entry;
2378 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2379 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2381 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2383 /* To return XDP buffer to XSK pool, we simple call
2384 * xsk_tx_completed(), so we don't need to fill up
2387 tx_q->tx_skbuff_dma[entry].buf = 0;
2388 tx_q->xdpf[entry] = NULL;
2390 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2391 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2392 tx_q->tx_skbuff_dma[entry].last_segment = true;
2393 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2395 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2397 tx_q->tx_count_frames++;
2399 if (!priv->tx_coal_frames[queue])
2401 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2407 tx_q->tx_count_frames = 0;
2408 stmmac_set_tx_ic(priv, tx_desc);
2409 priv->xstats.tx_set_ic_bit++;
2412 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2413 true, priv->mode, true, true,
2416 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2418 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
2419 entry = tx_q->cur_tx;
2423 stmmac_flush_tx_descriptors(priv, queue);
2424 xsk_tx_release(pool);
2427 /* Return true if all of the 3 conditions are met
2428 * a) TX Budget is still available
2429 * b) work_done = true when XSK TX desc peek is empty (no more
2430 * pending XSK TX for transmission)
2432 return !!budget && work_done;
2436 * stmmac_tx_clean - to manage the transmission completion
2437 * @priv: driver private structure
2438 * @budget: napi budget limiting this functions packet handling
2439 * @queue: TX queue index
2440 * Description: it reclaims the transmit resources after transmission completes.
2442 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2444 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2445 unsigned int bytes_compl = 0, pkts_compl = 0;
2446 unsigned int entry, xmits = 0, count = 0;
2448 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2450 priv->xstats.tx_clean++;
2452 tx_q->xsk_frames_done = 0;
2454 entry = tx_q->dirty_tx;
2456 /* Try to clean all TX complete frame in 1 shot */
2457 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) {
2458 struct xdp_frame *xdpf;
2459 struct sk_buff *skb;
2463 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2464 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2465 xdpf = tx_q->xdpf[entry];
2467 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2469 skb = tx_q->tx_skbuff[entry];
2475 if (priv->extend_desc)
2476 p = (struct dma_desc *)(tx_q->dma_etx + entry);
2477 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2478 p = &tx_q->dma_entx[entry].basic;
2480 p = tx_q->dma_tx + entry;
2482 status = stmmac_tx_status(priv, &priv->dev->stats,
2483 &priv->xstats, p, priv->ioaddr);
2484 /* Check if the descriptor is owned by the DMA */
2485 if (unlikely(status & tx_dma_own))
2490 /* Make sure descriptor fields are read after reading
2495 /* Just consider the last segment and ...*/
2496 if (likely(!(status & tx_not_ls))) {
2497 /* ... verify the status error condition */
2498 if (unlikely(status & tx_err)) {
2499 priv->dev->stats.tx_errors++;
2501 priv->dev->stats.tx_packets++;
2502 priv->xstats.tx_pkt_n++;
2503 priv->xstats.txq_stats[queue].tx_pkt_n++;
2506 stmmac_get_tx_hwtstamp(priv, p, skb);
2509 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2510 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2511 if (tx_q->tx_skbuff_dma[entry].map_as_page)
2512 dma_unmap_page(priv->device,
2513 tx_q->tx_skbuff_dma[entry].buf,
2514 tx_q->tx_skbuff_dma[entry].len,
2517 dma_unmap_single(priv->device,
2518 tx_q->tx_skbuff_dma[entry].buf,
2519 tx_q->tx_skbuff_dma[entry].len,
2521 tx_q->tx_skbuff_dma[entry].buf = 0;
2522 tx_q->tx_skbuff_dma[entry].len = 0;
2523 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2526 stmmac_clean_desc3(priv, tx_q, p);
2528 tx_q->tx_skbuff_dma[entry].last_segment = false;
2529 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2532 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2533 xdp_return_frame_rx_napi(xdpf);
2534 tx_q->xdpf[entry] = NULL;
2538 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2539 xdp_return_frame(xdpf);
2540 tx_q->xdpf[entry] = NULL;
2543 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2544 tx_q->xsk_frames_done++;
2546 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2549 bytes_compl += skb->len;
2550 dev_consume_skb_any(skb);
2551 tx_q->tx_skbuff[entry] = NULL;
2555 stmmac_release_tx_desc(priv, p, priv->mode);
2557 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
2559 tx_q->dirty_tx = entry;
2561 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2562 pkts_compl, bytes_compl);
2564 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2566 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2568 netif_dbg(priv, tx_done, priv->dev,
2569 "%s: restart transmit\n", __func__);
2570 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2573 if (tx_q->xsk_pool) {
2576 if (tx_q->xsk_frames_done)
2577 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2579 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2580 xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2582 /* For XSK TX, we try to send as many as possible.
2583 * If XSK work done (XSK TX desc empty and budget still
2584 * available), return "budget - 1" to reenable TX IRQ.
2585 * Else, return "budget" to make NAPI continue polling.
2587 work_done = stmmac_xdp_xmit_zc(priv, queue,
2588 STMMAC_XSK_TX_BUDGET_MAX);
2595 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2596 priv->eee_sw_timer_en) {
2597 stmmac_enable_eee_mode(priv);
2598 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2601 /* We still have pending packets, let's call for a new scheduling */
2602 if (tx_q->dirty_tx != tx_q->cur_tx)
2603 hrtimer_start(&tx_q->txtimer,
2604 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2607 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2609 /* Combine decisions from TX clean and XSK TX */
2610 return max(count, xmits);
2614 * stmmac_tx_err - to manage the tx error
2615 * @priv: driver private structure
2616 * @chan: channel index
2617 * Description: it cleans the descriptors and restarts the transmission
2618 * in case of transmission errors.
2620 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2622 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2624 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2626 stmmac_stop_tx_dma(priv, chan);
2627 dma_free_tx_skbufs(priv, chan);
2628 stmmac_clear_tx_descriptors(priv, chan);
2632 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2633 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2634 tx_q->dma_tx_phy, chan);
2635 stmmac_start_tx_dma(priv, chan);
2637 priv->dev->stats.tx_errors++;
2638 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2642 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2643 * @priv: driver private structure
2644 * @txmode: TX operating mode
2645 * @rxmode: RX operating mode
2646 * @chan: channel index
2647 * Description: it is used for configuring of the DMA operation mode in
2648 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2651 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2652 u32 rxmode, u32 chan)
2654 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2655 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2656 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2657 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2658 int rxfifosz = priv->plat->rx_fifo_size;
2659 int txfifosz = priv->plat->tx_fifo_size;
2662 rxfifosz = priv->dma_cap.rx_fifo_size;
2664 txfifosz = priv->dma_cap.tx_fifo_size;
2666 /* Adjust for real per queue fifo size */
2667 rxfifosz /= rx_channels_count;
2668 txfifosz /= tx_channels_count;
2670 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2671 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2674 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2678 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2679 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2680 if (ret && (ret != -EINVAL)) {
2681 stmmac_global_err(priv);
2688 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2690 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2691 &priv->xstats, chan, dir);
2692 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan];
2693 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2694 struct stmmac_channel *ch = &priv->channel[chan];
2695 struct napi_struct *rx_napi;
2696 struct napi_struct *tx_napi;
2697 unsigned long flags;
2699 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2700 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2702 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2703 if (napi_schedule_prep(rx_napi)) {
2704 spin_lock_irqsave(&ch->lock, flags);
2705 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2706 spin_unlock_irqrestore(&ch->lock, flags);
2707 __napi_schedule(rx_napi);
2711 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2712 if (napi_schedule_prep(tx_napi)) {
2713 spin_lock_irqsave(&ch->lock, flags);
2714 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2715 spin_unlock_irqrestore(&ch->lock, flags);
2716 __napi_schedule(tx_napi);
2724 * stmmac_dma_interrupt - DMA ISR
2725 * @priv: driver private structure
2726 * Description: this is the DMA ISR. It is called by the main ISR.
2727 * It calls the dwmac dma routine and schedule poll method in case of some
2730 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2732 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2733 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2734 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2735 tx_channel_count : rx_channel_count;
2737 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2739 /* Make sure we never check beyond our status buffer. */
2740 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2741 channels_to_check = ARRAY_SIZE(status);
2743 for (chan = 0; chan < channels_to_check; chan++)
2744 status[chan] = stmmac_napi_check(priv, chan,
2747 for (chan = 0; chan < tx_channel_count; chan++) {
2748 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2749 /* Try to bump up the dma threshold on this failure */
2750 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2753 if (priv->plat->force_thresh_dma_mode)
2754 stmmac_set_dma_operation_mode(priv,
2759 stmmac_set_dma_operation_mode(priv,
2763 priv->xstats.threshold = tc;
2765 } else if (unlikely(status[chan] == tx_hard_error)) {
2766 stmmac_tx_err(priv, chan);
2772 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2773 * @priv: driver private structure
2774 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2776 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2778 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2779 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2781 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2783 if (priv->dma_cap.rmon) {
2784 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2785 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2787 netdev_info(priv->dev, "No MAC Management Counters available\n");
2791 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2792 * @priv: driver private structure
2794 * new GMAC chip generations have a new register to indicate the
2795 * presence of the optional feature/functions.
2796 * This can be also used to override the value passed through the
2797 * platform and necessary for old MAC10/100 and GMAC chips.
2799 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2801 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2805 * stmmac_check_ether_addr - check if the MAC addr is valid
2806 * @priv: driver private structure
2808 * it is to verify if the MAC address is valid, in case of failures it
2809 * generates a random MAC address
2811 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2813 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2814 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2815 if (!is_valid_ether_addr(priv->dev->dev_addr))
2816 eth_hw_addr_random(priv->dev);
2817 dev_info(priv->device, "device MAC address %pM\n",
2818 priv->dev->dev_addr);
2823 * stmmac_init_dma_engine - DMA init.
2824 * @priv: driver private structure
2826 * It inits the DMA invoking the specific MAC/GMAC callback.
2827 * Some DMA parameters can be passed from the platform;
2828 * in case of these are not passed a default is kept for the MAC or GMAC.
2830 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2832 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2833 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2834 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2835 struct stmmac_rx_queue *rx_q;
2836 struct stmmac_tx_queue *tx_q;
2841 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2842 dev_err(priv->device, "Invalid DMA configuration\n");
2846 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2849 ret = stmmac_reset(priv, priv->ioaddr);
2851 dev_err(priv->device, "Failed to reset the dma\n");
2855 /* DMA Configuration */
2856 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2858 if (priv->plat->axi)
2859 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2861 /* DMA CSR Channel configuration */
2862 for (chan = 0; chan < dma_csr_ch; chan++)
2863 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2865 /* DMA RX Channel Configuration */
2866 for (chan = 0; chan < rx_channels_count; chan++) {
2867 rx_q = &priv->rx_queue[chan];
2869 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2870 rx_q->dma_rx_phy, chan);
2872 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2873 (rx_q->buf_alloc_num *
2874 sizeof(struct dma_desc));
2875 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2876 rx_q->rx_tail_addr, chan);
2879 /* DMA TX Channel Configuration */
2880 for (chan = 0; chan < tx_channels_count; chan++) {
2881 tx_q = &priv->tx_queue[chan];
2883 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2884 tx_q->dma_tx_phy, chan);
2886 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2887 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2888 tx_q->tx_tail_addr, chan);
2894 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2896 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2898 hrtimer_start(&tx_q->txtimer,
2899 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2904 * stmmac_tx_timer - mitigation sw timer for tx.
2907 * This is the timer handler to directly invoke the stmmac_tx_clean.
2909 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
2911 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
2912 struct stmmac_priv *priv = tx_q->priv_data;
2913 struct stmmac_channel *ch;
2914 struct napi_struct *napi;
2916 ch = &priv->channel[tx_q->queue_index];
2917 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2919 if (likely(napi_schedule_prep(napi))) {
2920 unsigned long flags;
2922 spin_lock_irqsave(&ch->lock, flags);
2923 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
2924 spin_unlock_irqrestore(&ch->lock, flags);
2925 __napi_schedule(napi);
2928 return HRTIMER_NORESTART;
2932 * stmmac_init_coalesce - init mitigation options.
2933 * @priv: driver private structure
2935 * This inits the coalesce parameters: i.e. timer rate,
2936 * timer handler and default threshold used for enabling the
2937 * interrupt on completion bit.
2939 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2941 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2942 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2945 for (chan = 0; chan < tx_channel_count; chan++) {
2946 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2948 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
2949 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
2951 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2952 tx_q->txtimer.function = stmmac_tx_timer;
2955 for (chan = 0; chan < rx_channel_count; chan++)
2956 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
2959 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2961 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2962 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2965 /* set TX ring length */
2966 for (chan = 0; chan < tx_channels_count; chan++)
2967 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2968 (priv->dma_tx_size - 1), chan);
2970 /* set RX ring length */
2971 for (chan = 0; chan < rx_channels_count; chan++)
2972 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2973 (priv->dma_rx_size - 1), chan);
2977 * stmmac_set_tx_queue_weight - Set TX queue weight
2978 * @priv: driver private structure
2979 * Description: It is used for setting TX queues weight
2981 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2983 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2987 for (queue = 0; queue < tx_queues_count; queue++) {
2988 weight = priv->plat->tx_queues_cfg[queue].weight;
2989 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2994 * stmmac_configure_cbs - Configure CBS in TX queue
2995 * @priv: driver private structure
2996 * Description: It is used for configuring CBS in AVB TX queues
2998 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3000 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3004 /* queue 0 is reserved for legacy traffic */
3005 for (queue = 1; queue < tx_queues_count; queue++) {
3006 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3007 if (mode_to_use == MTL_QUEUE_DCB)
3010 stmmac_config_cbs(priv, priv->hw,
3011 priv->plat->tx_queues_cfg[queue].send_slope,
3012 priv->plat->tx_queues_cfg[queue].idle_slope,
3013 priv->plat->tx_queues_cfg[queue].high_credit,
3014 priv->plat->tx_queues_cfg[queue].low_credit,
3020 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3021 * @priv: driver private structure
3022 * Description: It is used for mapping RX queues to RX dma channels
3024 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3026 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3030 for (queue = 0; queue < rx_queues_count; queue++) {
3031 chan = priv->plat->rx_queues_cfg[queue].chan;
3032 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3037 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3038 * @priv: driver private structure
3039 * Description: It is used for configuring the RX Queue Priority
3041 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3043 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3047 for (queue = 0; queue < rx_queues_count; queue++) {
3048 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3051 prio = priv->plat->rx_queues_cfg[queue].prio;
3052 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3057 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3058 * @priv: driver private structure
3059 * Description: It is used for configuring the TX Queue Priority
3061 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3063 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3067 for (queue = 0; queue < tx_queues_count; queue++) {
3068 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3071 prio = priv->plat->tx_queues_cfg[queue].prio;
3072 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3077 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3078 * @priv: driver private structure
3079 * Description: It is used for configuring the RX queue routing
3081 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3083 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3087 for (queue = 0; queue < rx_queues_count; queue++) {
3088 /* no specific packet type routing specified for the queue */
3089 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3092 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3093 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3097 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3099 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3100 priv->rss.enable = false;
3104 if (priv->dev->features & NETIF_F_RXHASH)
3105 priv->rss.enable = true;
3107 priv->rss.enable = false;
3109 stmmac_rss_configure(priv, priv->hw, &priv->rss,
3110 priv->plat->rx_queues_to_use);
3114 * stmmac_mtl_configuration - Configure MTL
3115 * @priv: driver private structure
3116 * Description: It is used for configurring MTL
3118 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3120 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3121 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3123 if (tx_queues_count > 1)
3124 stmmac_set_tx_queue_weight(priv);
3126 /* Configure MTL RX algorithms */
3127 if (rx_queues_count > 1)
3128 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3129 priv->plat->rx_sched_algorithm);
3131 /* Configure MTL TX algorithms */
3132 if (tx_queues_count > 1)
3133 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3134 priv->plat->tx_sched_algorithm);
3136 /* Configure CBS in AVB TX queues */
3137 if (tx_queues_count > 1)
3138 stmmac_configure_cbs(priv);
3140 /* Map RX MTL to DMA channels */
3141 stmmac_rx_queue_dma_chan_map(priv);
3143 /* Enable MAC RX Queues */
3144 stmmac_mac_enable_rx_queues(priv);
3146 /* Set RX priorities */
3147 if (rx_queues_count > 1)
3148 stmmac_mac_config_rx_queues_prio(priv);
3150 /* Set TX priorities */
3151 if (tx_queues_count > 1)
3152 stmmac_mac_config_tx_queues_prio(priv);
3154 /* Set RX routing */
3155 if (rx_queues_count > 1)
3156 stmmac_mac_config_rx_queues_routing(priv);
3158 /* Receive Side Scaling */
3159 if (rx_queues_count > 1)
3160 stmmac_mac_config_rss(priv);
3163 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3165 if (priv->dma_cap.asp) {
3166 netdev_info(priv->dev, "Enabling Safety Features\n");
3167 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3168 priv->plat->safety_feat_cfg);
3170 netdev_info(priv->dev, "No Safety Features support found\n");
3174 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3178 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3179 clear_bit(__FPE_REMOVING, &priv->fpe_task_state);
3181 name = priv->wq_name;
3182 sprintf(name, "%s-fpe", priv->dev->name);
3184 priv->fpe_wq = create_singlethread_workqueue(name);
3185 if (!priv->fpe_wq) {
3186 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3190 netdev_info(priv->dev, "FPE workqueue start");
3196 * stmmac_hw_setup - setup mac in a usable state.
3197 * @dev : pointer to the device structure.
3198 * @init_ptp: initialize PTP if set
3200 * this is the main function to setup the HW in a usable state because the
3201 * dma engine is reset, the core registers are configured (e.g. AXI,
3202 * Checksum features, timers). The DMA is ready to start receiving and
3205 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3208 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
3210 struct stmmac_priv *priv = netdev_priv(dev);
3211 u32 rx_cnt = priv->plat->rx_queues_to_use;
3212 u32 tx_cnt = priv->plat->tx_queues_to_use;
3217 /* DMA initialization and SW reset */
3218 ret = stmmac_init_dma_engine(priv);
3220 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3225 /* Copy the MAC addr into the HW */
3226 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3228 /* PS and related bits will be programmed according to the speed */
3229 if (priv->hw->pcs) {
3230 int speed = priv->plat->mac_port_sel_speed;
3232 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3233 (speed == SPEED_1000)) {
3234 priv->hw->ps = speed;
3236 dev_warn(priv->device, "invalid port speed\n");
3241 /* Initialize the MAC Core */
3242 stmmac_core_init(priv, priv->hw, dev);
3245 stmmac_mtl_configuration(priv);
3247 /* Initialize Safety Features */
3248 stmmac_safety_feat_configuration(priv);
3250 ret = stmmac_rx_ipc(priv, priv->hw);
3252 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3253 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3254 priv->hw->rx_csum = 0;
3257 /* Enable the MAC Rx/Tx */
3258 stmmac_mac_set(priv, priv->ioaddr, true);
3260 /* Set the HW DMA mode and the COE */
3261 stmmac_dma_operation_mode(priv);
3263 stmmac_mmc_setup(priv);
3266 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3268 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
3270 ret = stmmac_init_ptp(priv);
3271 if (ret == -EOPNOTSUPP)
3272 netdev_warn(priv->dev, "PTP not supported by HW\n");
3274 netdev_warn(priv->dev, "PTP init failed\n");
3277 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3279 /* Convert the timer from msec to usec */
3280 if (!priv->tx_lpi_timer)
3281 priv->tx_lpi_timer = eee_timer * 1000;
3283 if (priv->use_riwt) {
3286 for (queue = 0; queue < rx_cnt; queue++) {
3287 if (!priv->rx_riwt[queue])
3288 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3290 stmmac_rx_watchdog(priv, priv->ioaddr,
3291 priv->rx_riwt[queue], queue);
3296 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3298 /* set TX and RX rings length */
3299 stmmac_set_rings_length(priv);
3303 for (chan = 0; chan < tx_cnt; chan++) {
3304 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3306 /* TSO and TBS cannot co-exist */
3307 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3310 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3314 /* Enable Split Header */
3315 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3316 for (chan = 0; chan < rx_cnt; chan++)
3317 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3320 /* VLAN Tag Insertion */
3321 if (priv->dma_cap.vlins)
3322 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3325 for (chan = 0; chan < tx_cnt; chan++) {
3326 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3327 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3329 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3332 /* Configure real RX and TX queues */
3333 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3334 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3336 /* Start the ball rolling... */
3337 stmmac_start_all_dma(priv);
3339 if (priv->dma_cap.fpesel) {
3340 stmmac_fpe_start_wq(priv);
3342 if (priv->plat->fpe_cfg->enable)
3343 stmmac_fpe_handshake(priv, true);
3349 static void stmmac_hw_teardown(struct net_device *dev)
3351 struct stmmac_priv *priv = netdev_priv(dev);
3353 clk_disable_unprepare(priv->plat->clk_ptp_ref);
3356 static void stmmac_free_irq(struct net_device *dev,
3357 enum request_irq_err irq_err, int irq_idx)
3359 struct stmmac_priv *priv = netdev_priv(dev);
3363 case REQ_IRQ_ERR_ALL:
3364 irq_idx = priv->plat->tx_queues_to_use;
3366 case REQ_IRQ_ERR_TX:
3367 for (j = irq_idx - 1; j >= 0; j--) {
3368 if (priv->tx_irq[j] > 0) {
3369 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3370 free_irq(priv->tx_irq[j], &priv->tx_queue[j]);
3373 irq_idx = priv->plat->rx_queues_to_use;
3375 case REQ_IRQ_ERR_RX:
3376 for (j = irq_idx - 1; j >= 0; j--) {
3377 if (priv->rx_irq[j] > 0) {
3378 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3379 free_irq(priv->rx_irq[j], &priv->rx_queue[j]);
3383 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3384 free_irq(priv->sfty_ue_irq, dev);
3386 case REQ_IRQ_ERR_SFTY_UE:
3387 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3388 free_irq(priv->sfty_ce_irq, dev);
3390 case REQ_IRQ_ERR_SFTY_CE:
3391 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3392 free_irq(priv->lpi_irq, dev);
3394 case REQ_IRQ_ERR_LPI:
3395 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3396 free_irq(priv->wol_irq, dev);
3398 case REQ_IRQ_ERR_WOL:
3399 free_irq(dev->irq, dev);
3401 case REQ_IRQ_ERR_MAC:
3402 case REQ_IRQ_ERR_NO:
3403 /* If MAC IRQ request error, no more IRQ to free */
3408 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3410 struct stmmac_priv *priv = netdev_priv(dev);
3411 enum request_irq_err irq_err;
3418 /* For common interrupt */
3419 int_name = priv->int_name_mac;
3420 sprintf(int_name, "%s:%s", dev->name, "mac");
3421 ret = request_irq(dev->irq, stmmac_mac_interrupt,
3423 if (unlikely(ret < 0)) {
3424 netdev_err(priv->dev,
3425 "%s: alloc mac MSI %d (error: %d)\n",
3426 __func__, dev->irq, ret);
3427 irq_err = REQ_IRQ_ERR_MAC;
3431 /* Request the Wake IRQ in case of another line
3434 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3435 int_name = priv->int_name_wol;
3436 sprintf(int_name, "%s:%s", dev->name, "wol");
3437 ret = request_irq(priv->wol_irq,
3438 stmmac_mac_interrupt,
3440 if (unlikely(ret < 0)) {
3441 netdev_err(priv->dev,
3442 "%s: alloc wol MSI %d (error: %d)\n",
3443 __func__, priv->wol_irq, ret);
3444 irq_err = REQ_IRQ_ERR_WOL;
3449 /* Request the LPI IRQ in case of another line
3452 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3453 int_name = priv->int_name_lpi;
3454 sprintf(int_name, "%s:%s", dev->name, "lpi");
3455 ret = request_irq(priv->lpi_irq,
3456 stmmac_mac_interrupt,
3458 if (unlikely(ret < 0)) {
3459 netdev_err(priv->dev,
3460 "%s: alloc lpi MSI %d (error: %d)\n",
3461 __func__, priv->lpi_irq, ret);
3462 irq_err = REQ_IRQ_ERR_LPI;
3467 /* Request the Safety Feature Correctible Error line in
3468 * case of another line is used
3470 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3471 int_name = priv->int_name_sfty_ce;
3472 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3473 ret = request_irq(priv->sfty_ce_irq,
3474 stmmac_safety_interrupt,
3476 if (unlikely(ret < 0)) {
3477 netdev_err(priv->dev,
3478 "%s: alloc sfty ce MSI %d (error: %d)\n",
3479 __func__, priv->sfty_ce_irq, ret);
3480 irq_err = REQ_IRQ_ERR_SFTY_CE;
3485 /* Request the Safety Feature Uncorrectible Error line in
3486 * case of another line is used
3488 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3489 int_name = priv->int_name_sfty_ue;
3490 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3491 ret = request_irq(priv->sfty_ue_irq,
3492 stmmac_safety_interrupt,
3494 if (unlikely(ret < 0)) {
3495 netdev_err(priv->dev,
3496 "%s: alloc sfty ue MSI %d (error: %d)\n",
3497 __func__, priv->sfty_ue_irq, ret);
3498 irq_err = REQ_IRQ_ERR_SFTY_UE;
3503 /* Request Rx MSI irq */
3504 for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3505 if (priv->rx_irq[i] == 0)
3508 int_name = priv->int_name_rx_irq[i];
3509 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3510 ret = request_irq(priv->rx_irq[i],
3512 0, int_name, &priv->rx_queue[i]);
3513 if (unlikely(ret < 0)) {
3514 netdev_err(priv->dev,
3515 "%s: alloc rx-%d MSI %d (error: %d)\n",
3516 __func__, i, priv->rx_irq[i], ret);
3517 irq_err = REQ_IRQ_ERR_RX;
3521 cpumask_clear(&cpu_mask);
3522 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3523 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3526 /* Request Tx MSI irq */
3527 for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3528 if (priv->tx_irq[i] == 0)
3531 int_name = priv->int_name_tx_irq[i];
3532 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3533 ret = request_irq(priv->tx_irq[i],
3535 0, int_name, &priv->tx_queue[i]);
3536 if (unlikely(ret < 0)) {
3537 netdev_err(priv->dev,
3538 "%s: alloc tx-%d MSI %d (error: %d)\n",
3539 __func__, i, priv->tx_irq[i], ret);
3540 irq_err = REQ_IRQ_ERR_TX;
3544 cpumask_clear(&cpu_mask);
3545 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3546 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3552 stmmac_free_irq(dev, irq_err, irq_idx);
3556 static int stmmac_request_irq_single(struct net_device *dev)
3558 struct stmmac_priv *priv = netdev_priv(dev);
3559 enum request_irq_err irq_err;
3562 ret = request_irq(dev->irq, stmmac_interrupt,
3563 IRQF_SHARED, dev->name, dev);
3564 if (unlikely(ret < 0)) {
3565 netdev_err(priv->dev,
3566 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3567 __func__, dev->irq, ret);
3568 irq_err = REQ_IRQ_ERR_MAC;
3572 /* Request the Wake IRQ in case of another line
3575 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3576 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3577 IRQF_SHARED, dev->name, dev);
3578 if (unlikely(ret < 0)) {
3579 netdev_err(priv->dev,
3580 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3581 __func__, priv->wol_irq, ret);
3582 irq_err = REQ_IRQ_ERR_WOL;
3587 /* Request the IRQ lines */
3588 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3589 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3590 IRQF_SHARED, dev->name, dev);
3591 if (unlikely(ret < 0)) {
3592 netdev_err(priv->dev,
3593 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3594 __func__, priv->lpi_irq, ret);
3595 irq_err = REQ_IRQ_ERR_LPI;
3603 stmmac_free_irq(dev, irq_err, 0);
3607 static int stmmac_request_irq(struct net_device *dev)
3609 struct stmmac_priv *priv = netdev_priv(dev);
3612 /* Request the IRQ lines */
3613 if (priv->plat->multi_msi_en)
3614 ret = stmmac_request_irq_multi_msi(dev);
3616 ret = stmmac_request_irq_single(dev);
3622 * stmmac_open - open entry point of the driver
3623 * @dev : pointer to the device structure.
3625 * This function is the open entry point of the driver.
3627 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3630 int stmmac_open(struct net_device *dev)
3632 struct stmmac_priv *priv = netdev_priv(dev);
3633 int mode = priv->plat->phy_interface;
3638 ret = pm_runtime_get_sync(priv->device);
3640 pm_runtime_put_noidle(priv->device);
3644 if (priv->hw->pcs != STMMAC_PCS_TBI &&
3645 priv->hw->pcs != STMMAC_PCS_RTBI &&
3647 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) {
3648 ret = stmmac_init_phy(dev);
3650 netdev_err(priv->dev,
3651 "%s: Cannot attach to PHY (error: %d)\n",
3653 goto init_phy_error;
3657 /* Extra statistics */
3658 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3659 priv->xstats.threshold = tc;
3661 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
3665 if (bfsize < BUF_SIZE_16KiB)
3666 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
3668 priv->dma_buf_sz = bfsize;
3671 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3673 if (!priv->dma_tx_size)
3674 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3675 if (!priv->dma_rx_size)
3676 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3678 /* Earlier check for TBS */
3679 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3680 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
3681 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3683 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3684 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3687 ret = alloc_dma_desc_resources(priv);
3689 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3691 goto dma_desc_error;
3694 ret = init_dma_desc_rings(dev, GFP_KERNEL);
3696 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3701 ret = stmmac_hw_setup(dev, true);
3703 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3707 stmmac_init_coalesce(priv);
3709 phylink_start(priv->phylink);
3710 /* We may have called phylink_speed_down before */
3711 phylink_speed_up(priv->phylink);
3713 ret = stmmac_request_irq(dev);
3717 stmmac_enable_all_queues(priv);
3718 netif_tx_start_all_queues(priv->dev);
3723 phylink_stop(priv->phylink);
3725 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3726 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3728 stmmac_hw_teardown(dev);
3730 free_dma_desc_resources(priv);
3732 phylink_disconnect_phy(priv->phylink);
3734 pm_runtime_put(priv->device);
3738 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3740 set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3743 destroy_workqueue(priv->fpe_wq);
3745 netdev_info(priv->dev, "FPE workqueue stop");
3749 * stmmac_release - close entry point of the driver
3750 * @dev : device pointer.
3752 * This is the stop entry point of the driver.
3754 int stmmac_release(struct net_device *dev)
3756 struct stmmac_priv *priv = netdev_priv(dev);
3759 if (device_may_wakeup(priv->device))
3760 phylink_speed_down(priv->phylink, false);
3761 /* Stop and disconnect the PHY */
3762 phylink_stop(priv->phylink);
3763 phylink_disconnect_phy(priv->phylink);
3765 stmmac_disable_all_queues(priv);
3767 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3768 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
3770 /* Free the IRQ lines */
3771 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3773 if (priv->eee_enabled) {
3774 priv->tx_path_in_lpi_mode = false;
3775 del_timer_sync(&priv->eee_ctrl_timer);
3778 /* Stop TX/RX DMA and clear the descriptors */
3779 stmmac_stop_all_dma(priv);
3781 /* Release and free the Rx/Tx resources */
3782 free_dma_desc_resources(priv);
3784 /* Disable the MAC Rx/Tx */
3785 stmmac_mac_set(priv, priv->ioaddr, false);
3787 netif_carrier_off(dev);
3789 stmmac_release_ptp(priv);
3791 pm_runtime_put(priv->device);
3793 if (priv->dma_cap.fpesel)
3794 stmmac_fpe_stop_wq(priv);
3799 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3800 struct stmmac_tx_queue *tx_q)
3802 u16 tag = 0x0, inner_tag = 0x0;
3803 u32 inner_type = 0x0;
3806 if (!priv->dma_cap.vlins)
3808 if (!skb_vlan_tag_present(skb))
3810 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3811 inner_tag = skb_vlan_tag_get(skb);
3812 inner_type = STMMAC_VLAN_INSERT;
3815 tag = skb_vlan_tag_get(skb);
3817 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3818 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3820 p = &tx_q->dma_tx[tx_q->cur_tx];
3822 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3825 stmmac_set_tx_owner(priv, p);
3826 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
3831 * stmmac_tso_allocator - close entry point of the driver
3832 * @priv: driver private structure
3833 * @des: buffer start address
3834 * @total_len: total length to fill in descriptors
3835 * @last_segment: condition for the last descriptor
3836 * @queue: TX queue index
3838 * This function fills descriptor and request new descriptors according to
3839 * buffer length to fill
3841 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
3842 int total_len, bool last_segment, u32 queue)
3844 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3845 struct dma_desc *desc;
3849 tmp_len = total_len;
3851 while (tmp_len > 0) {
3852 dma_addr_t curr_addr;
3854 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3856 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3858 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3859 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3861 desc = &tx_q->dma_tx[tx_q->cur_tx];
3863 curr_addr = des + (total_len - tmp_len);
3864 if (priv->dma_cap.addr64 <= 32)
3865 desc->des0 = cpu_to_le32(curr_addr);
3867 stmmac_set_desc_addr(priv, desc, curr_addr);
3869 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
3870 TSO_MAX_BUFF_SIZE : tmp_len;
3872 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
3874 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
3877 tmp_len -= TSO_MAX_BUFF_SIZE;
3881 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
3883 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3886 if (likely(priv->extend_desc))
3887 desc_size = sizeof(struct dma_extended_desc);
3888 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
3889 desc_size = sizeof(struct dma_edesc);
3891 desc_size = sizeof(struct dma_desc);
3893 /* The own bit must be the latest setting done when prepare the
3894 * descriptor and then barrier is needed to make sure that
3895 * all is coherent before granting the DMA engine.
3899 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
3900 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3904 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
3905 * @skb : the socket buffer
3906 * @dev : device pointer
3907 * Description: this is the transmit function that is called on TSO frames
3908 * (support available on GMAC4 and newer chips).
3909 * Diagram below show the ring programming in case of TSO frames:
3913 * | DES0 |---> buffer1 = L2/L3/L4 header
3914 * | DES1 |---> TCP Payload (can continue on next descr...)
3915 * | DES2 |---> buffer 1 and 2 len
3916 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
3922 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
3924 * | DES2 | --> buffer 1 and 2 len
3928 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
3930 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
3932 struct dma_desc *desc, *first, *mss_desc = NULL;
3933 struct stmmac_priv *priv = netdev_priv(dev);
3934 int nfrags = skb_shinfo(skb)->nr_frags;
3935 u32 queue = skb_get_queue_mapping(skb);
3936 unsigned int first_entry, tx_packets;
3937 int tmp_pay_len = 0, first_tx;
3938 struct stmmac_tx_queue *tx_q;
3939 bool has_vlan, set_ic;
3940 u8 proto_hdr_len, hdr;
3945 tx_q = &priv->tx_queue[queue];
3946 first_tx = tx_q->cur_tx;
3948 /* Compute header lengths */
3949 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
3950 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
3951 hdr = sizeof(struct udphdr);
3953 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
3954 hdr = tcp_hdrlen(skb);
3957 /* Desc availability based on threshold should be enough safe */
3958 if (unlikely(stmmac_tx_avail(priv, queue) <
3959 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
3960 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3961 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3963 /* This is a hard error, log it. */
3964 netdev_err(priv->dev,
3965 "%s: Tx Ring full when queue awake\n",
3968 return NETDEV_TX_BUSY;
3971 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
3973 mss = skb_shinfo(skb)->gso_size;
3975 /* set new MSS value if needed */
3976 if (mss != tx_q->mss) {
3977 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3978 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
3980 mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
3982 stmmac_set_mss(priv, mss_desc, mss);
3984 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
3986 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
3989 if (netif_msg_tx_queued(priv)) {
3990 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
3991 __func__, hdr, proto_hdr_len, pay_len, mss);
3992 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
3996 /* Check if VLAN can be inserted by HW */
3997 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3999 first_entry = tx_q->cur_tx;
4000 WARN_ON(tx_q->tx_skbuff[first_entry]);
4002 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4003 desc = &tx_q->dma_entx[first_entry].basic;
4005 desc = &tx_q->dma_tx[first_entry];
4009 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4011 /* first descriptor: fill Headers on Buf1 */
4012 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4014 if (dma_mapping_error(priv->device, des))
4017 tx_q->tx_skbuff_dma[first_entry].buf = des;
4018 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4019 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4020 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4022 if (priv->dma_cap.addr64 <= 32) {
4023 first->des0 = cpu_to_le32(des);
4025 /* Fill start of payload in buff2 of first descriptor */
4027 first->des1 = cpu_to_le32(des + proto_hdr_len);
4029 /* If needed take extra descriptors to fill the remaining payload */
4030 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4032 stmmac_set_desc_addr(priv, first, des);
4033 tmp_pay_len = pay_len;
4034 des += proto_hdr_len;
4038 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4040 /* Prepare fragments */
4041 for (i = 0; i < nfrags; i++) {
4042 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4044 des = skb_frag_dma_map(priv->device, frag, 0,
4045 skb_frag_size(frag),
4047 if (dma_mapping_error(priv->device, des))
4050 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4051 (i == nfrags - 1), queue);
4053 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4054 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4055 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4056 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4059 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4061 /* Only the last descriptor gets to point to the skb. */
4062 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4063 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4065 /* Manage tx mitigation */
4066 tx_packets = (tx_q->cur_tx + 1) - first_tx;
4067 tx_q->tx_count_frames += tx_packets;
4069 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4071 else if (!priv->tx_coal_frames[queue])
4073 else if (tx_packets > priv->tx_coal_frames[queue])
4075 else if ((tx_q->tx_count_frames %
4076 priv->tx_coal_frames[queue]) < tx_packets)
4082 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4083 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4085 desc = &tx_q->dma_tx[tx_q->cur_tx];
4087 tx_q->tx_count_frames = 0;
4088 stmmac_set_tx_ic(priv, desc);
4089 priv->xstats.tx_set_ic_bit++;
4092 /* We've used all descriptors we need for this skb, however,
4093 * advance cur_tx so that it references a fresh descriptor.
4094 * ndo_start_xmit will fill this descriptor the next time it's
4095 * called and stmmac_tx_clean may clean up to this descriptor.
4097 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size);
4099 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4100 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4102 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4105 dev->stats.tx_bytes += skb->len;
4106 priv->xstats.tx_tso_frames++;
4107 priv->xstats.tx_tso_nfrags += nfrags;
4109 if (priv->sarc_type)
4110 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4112 skb_tx_timestamp(skb);
4114 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4115 priv->hwts_tx_en)) {
4116 /* declare that device is doing timestamping */
4117 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4118 stmmac_enable_tx_timestamp(priv, first);
4121 /* Complete the first descriptor before granting the DMA */
4122 stmmac_prepare_tso_tx_desc(priv, first, 1,
4125 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4126 hdr / 4, (skb->len - proto_hdr_len));
4128 /* If context desc is used to change MSS */
4130 /* Make sure that first descriptor has been completely
4131 * written, including its own bit. This is because MSS is
4132 * actually before first descriptor, so we need to make
4133 * sure that MSS's own bit is the last thing written.
4136 stmmac_set_tx_owner(priv, mss_desc);
4139 if (netif_msg_pktdata(priv)) {
4140 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4141 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4142 tx_q->cur_tx, first, nfrags);
4143 pr_info(">>> frame to be transmitted: ");
4144 print_pkt(skb->data, skb_headlen(skb));
4147 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4149 stmmac_flush_tx_descriptors(priv, queue);
4150 stmmac_tx_timer_arm(priv, queue);
4152 return NETDEV_TX_OK;
4155 dev_err(priv->device, "Tx dma map failed\n");
4157 priv->dev->stats.tx_dropped++;
4158 return NETDEV_TX_OK;
4162 * stmmac_xmit - Tx entry point of the driver
4163 * @skb : the socket buffer
4164 * @dev : device pointer
4165 * Description : this is the tx entry point of the driver.
4166 * It programs the chain or the ring and supports oversized frames
4169 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4171 unsigned int first_entry, tx_packets, enh_desc;
4172 struct stmmac_priv *priv = netdev_priv(dev);
4173 unsigned int nopaged_len = skb_headlen(skb);
4174 int i, csum_insertion = 0, is_jumbo = 0;
4175 u32 queue = skb_get_queue_mapping(skb);
4176 int nfrags = skb_shinfo(skb)->nr_frags;
4177 int gso = skb_shinfo(skb)->gso_type;
4178 struct dma_edesc *tbs_desc = NULL;
4179 struct dma_desc *desc, *first;
4180 struct stmmac_tx_queue *tx_q;
4181 bool has_vlan, set_ic;
4182 int entry, first_tx;
4185 tx_q = &priv->tx_queue[queue];
4186 first_tx = tx_q->cur_tx;
4188 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4189 stmmac_disable_eee_mode(priv);
4191 /* Manage oversized TCP frames for GMAC4 device */
4192 if (skb_is_gso(skb) && priv->tso) {
4193 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4194 return stmmac_tso_xmit(skb, dev);
4195 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4196 return stmmac_tso_xmit(skb, dev);
4199 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4200 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4201 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4203 /* This is a hard error, log it. */
4204 netdev_err(priv->dev,
4205 "%s: Tx Ring full when queue awake\n",
4208 return NETDEV_TX_BUSY;
4211 /* Check if VLAN can be inserted by HW */
4212 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4214 entry = tx_q->cur_tx;
4215 first_entry = entry;
4216 WARN_ON(tx_q->tx_skbuff[first_entry]);
4218 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4220 if (likely(priv->extend_desc))
4221 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4222 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4223 desc = &tx_q->dma_entx[entry].basic;
4225 desc = tx_q->dma_tx + entry;
4230 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4232 enh_desc = priv->plat->enh_desc;
4233 /* To program the descriptors according to the size of the frame */
4235 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4237 if (unlikely(is_jumbo)) {
4238 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4239 if (unlikely(entry < 0) && (entry != -EINVAL))
4243 for (i = 0; i < nfrags; i++) {
4244 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4245 int len = skb_frag_size(frag);
4246 bool last_segment = (i == (nfrags - 1));
4248 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4249 WARN_ON(tx_q->tx_skbuff[entry]);
4251 if (likely(priv->extend_desc))
4252 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4253 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4254 desc = &tx_q->dma_entx[entry].basic;
4256 desc = tx_q->dma_tx + entry;
4258 des = skb_frag_dma_map(priv->device, frag, 0, len,
4260 if (dma_mapping_error(priv->device, des))
4261 goto dma_map_err; /* should reuse desc w/o issues */
4263 tx_q->tx_skbuff_dma[entry].buf = des;
4265 stmmac_set_desc_addr(priv, desc, des);
4267 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4268 tx_q->tx_skbuff_dma[entry].len = len;
4269 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4270 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4272 /* Prepare the descriptor and set the own bit too */
4273 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4274 priv->mode, 1, last_segment, skb->len);
4277 /* Only the last descriptor gets to point to the skb. */
4278 tx_q->tx_skbuff[entry] = skb;
4279 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4281 /* According to the coalesce parameter the IC bit for the latest
4282 * segment is reset and the timer re-started to clean the tx status.
4283 * This approach takes care about the fragments: desc is the first
4284 * element in case of no SG.
4286 tx_packets = (entry + 1) - first_tx;
4287 tx_q->tx_count_frames += tx_packets;
4289 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4291 else if (!priv->tx_coal_frames[queue])
4293 else if (tx_packets > priv->tx_coal_frames[queue])
4295 else if ((tx_q->tx_count_frames %
4296 priv->tx_coal_frames[queue]) < tx_packets)
4302 if (likely(priv->extend_desc))
4303 desc = &tx_q->dma_etx[entry].basic;
4304 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4305 desc = &tx_q->dma_entx[entry].basic;
4307 desc = &tx_q->dma_tx[entry];
4309 tx_q->tx_count_frames = 0;
4310 stmmac_set_tx_ic(priv, desc);
4311 priv->xstats.tx_set_ic_bit++;
4314 /* We've used all descriptors we need for this skb, however,
4315 * advance cur_tx so that it references a fresh descriptor.
4316 * ndo_start_xmit will fill this descriptor the next time it's
4317 * called and stmmac_tx_clean may clean up to this descriptor.
4319 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4320 tx_q->cur_tx = entry;
4322 if (netif_msg_pktdata(priv)) {
4323 netdev_dbg(priv->dev,
4324 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4325 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4326 entry, first, nfrags);
4328 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4329 print_pkt(skb->data, skb->len);
4332 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4333 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4335 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4338 dev->stats.tx_bytes += skb->len;
4340 if (priv->sarc_type)
4341 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4343 skb_tx_timestamp(skb);
4345 /* Ready to fill the first descriptor and set the OWN bit w/o any
4346 * problems because all the descriptors are actually ready to be
4347 * passed to the DMA engine.
4349 if (likely(!is_jumbo)) {
4350 bool last_segment = (nfrags == 0);
4352 des = dma_map_single(priv->device, skb->data,
4353 nopaged_len, DMA_TO_DEVICE);
4354 if (dma_mapping_error(priv->device, des))
4357 tx_q->tx_skbuff_dma[first_entry].buf = des;
4358 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4359 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4361 stmmac_set_desc_addr(priv, first, des);
4363 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4364 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4366 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4367 priv->hwts_tx_en)) {
4368 /* declare that device is doing timestamping */
4369 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4370 stmmac_enable_tx_timestamp(priv, first);
4373 /* Prepare the first descriptor setting the OWN bit too */
4374 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4375 csum_insertion, priv->mode, 0, last_segment,
4379 if (tx_q->tbs & STMMAC_TBS_EN) {
4380 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4382 tbs_desc = &tx_q->dma_entx[first_entry];
4383 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4386 stmmac_set_tx_owner(priv, first);
4388 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4390 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4392 stmmac_flush_tx_descriptors(priv, queue);
4393 stmmac_tx_timer_arm(priv, queue);
4395 return NETDEV_TX_OK;
4398 netdev_err(priv->dev, "Tx DMA map failed\n");
4400 priv->dev->stats.tx_dropped++;
4401 return NETDEV_TX_OK;
4404 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4406 struct vlan_ethhdr *veth;
4410 veth = (struct vlan_ethhdr *)skb->data;
4411 vlan_proto = veth->h_vlan_proto;
4413 if ((vlan_proto == htons(ETH_P_8021Q) &&
4414 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4415 (vlan_proto == htons(ETH_P_8021AD) &&
4416 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4417 /* pop the vlan tag */
4418 vlanid = ntohs(veth->h_vlan_TCI);
4419 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4420 skb_pull(skb, VLAN_HLEN);
4421 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4426 * stmmac_rx_refill - refill used skb preallocated buffers
4427 * @priv: driver private structure
4428 * @queue: RX queue index
4429 * Description : this is to reallocate the skb for the reception process
4430 * that is based on zero-copy.
4432 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4434 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4435 int dirty = stmmac_rx_dirty(priv, queue);
4436 unsigned int entry = rx_q->dirty_rx;
4438 while (dirty-- > 0) {
4439 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4443 if (priv->extend_desc)
4444 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4446 p = rx_q->dma_rx + entry;
4449 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
4454 if (priv->sph && !buf->sec_page) {
4455 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
4459 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4462 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4464 stmmac_set_desc_addr(priv, p, buf->addr);
4466 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4468 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4469 stmmac_refill_desc3(priv, rx_q, p);
4471 rx_q->rx_count_frames++;
4472 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4473 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4474 rx_q->rx_count_frames = 0;
4476 use_rx_wd = !priv->rx_coal_frames[queue];
4477 use_rx_wd |= rx_q->rx_count_frames > 0;
4478 if (!priv->use_riwt)
4482 stmmac_set_rx_owner(priv, p, use_rx_wd);
4484 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4486 rx_q->dirty_rx = entry;
4487 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4488 (rx_q->dirty_rx * sizeof(struct dma_desc));
4489 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4492 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4494 int status, unsigned int len)
4496 unsigned int plen = 0, hlen = 0;
4497 int coe = priv->hw->rx_csum;
4499 /* Not first descriptor, buffer is always zero */
4500 if (priv->sph && len)
4503 /* First descriptor, get split header length */
4504 stmmac_get_rx_header_len(priv, p, &hlen);
4505 if (priv->sph && hlen) {
4506 priv->xstats.rx_split_hdr_pkt_n++;
4510 /* First descriptor, not last descriptor and not split header */
4511 if (status & rx_not_ls)
4512 return priv->dma_buf_sz;
4514 plen = stmmac_get_rx_frame_len(priv, p, coe);
4516 /* First descriptor and last descriptor and not split header */
4517 return min_t(unsigned int, priv->dma_buf_sz, plen);
4520 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4522 int status, unsigned int len)
4524 int coe = priv->hw->rx_csum;
4525 unsigned int plen = 0;
4527 /* Not split header, buffer is not available */
4531 /* Not last descriptor */
4532 if (status & rx_not_ls)
4533 return priv->dma_buf_sz;
4535 plen = stmmac_get_rx_frame_len(priv, p, coe);
4537 /* Last descriptor */
4541 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4542 struct xdp_frame *xdpf, bool dma_map)
4544 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4545 unsigned int entry = tx_q->cur_tx;
4546 struct dma_desc *tx_desc;
4547 dma_addr_t dma_addr;
4550 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4551 return STMMAC_XDP_CONSUMED;
4553 if (likely(priv->extend_desc))
4554 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4555 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4556 tx_desc = &tx_q->dma_entx[entry].basic;
4558 tx_desc = tx_q->dma_tx + entry;
4561 dma_addr = dma_map_single(priv->device, xdpf->data,
4562 xdpf->len, DMA_TO_DEVICE);
4563 if (dma_mapping_error(priv->device, dma_addr))
4564 return STMMAC_XDP_CONSUMED;
4566 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4568 struct page *page = virt_to_page(xdpf->data);
4570 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4572 dma_sync_single_for_device(priv->device, dma_addr,
4573 xdpf->len, DMA_BIDIRECTIONAL);
4575 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4578 tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4579 tx_q->tx_skbuff_dma[entry].map_as_page = false;
4580 tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4581 tx_q->tx_skbuff_dma[entry].last_segment = true;
4582 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4584 tx_q->xdpf[entry] = xdpf;
4586 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4588 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4589 true, priv->mode, true, true,
4592 tx_q->tx_count_frames++;
4594 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4600 tx_q->tx_count_frames = 0;
4601 stmmac_set_tx_ic(priv, tx_desc);
4602 priv->xstats.tx_set_ic_bit++;
4605 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4607 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size);
4608 tx_q->cur_tx = entry;
4610 return STMMAC_XDP_TX;
4613 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4618 if (unlikely(index < 0))
4621 while (index >= priv->plat->tx_queues_to_use)
4622 index -= priv->plat->tx_queues_to_use;
4627 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4628 struct xdp_buff *xdp)
4630 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4631 int cpu = smp_processor_id();
4632 struct netdev_queue *nq;
4636 if (unlikely(!xdpf))
4637 return STMMAC_XDP_CONSUMED;
4639 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4640 nq = netdev_get_tx_queue(priv->dev, queue);
4642 __netif_tx_lock(nq, cpu);
4643 /* Avoids TX time-out as we are sharing with slow path */
4644 nq->trans_start = jiffies;
4646 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4647 if (res == STMMAC_XDP_TX)
4648 stmmac_flush_tx_descriptors(priv, queue);
4650 __netif_tx_unlock(nq);
4655 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4656 struct bpf_prog *prog,
4657 struct xdp_buff *xdp)
4662 act = bpf_prog_run_xdp(prog, xdp);
4665 res = STMMAC_XDP_PASS;
4668 res = stmmac_xdp_xmit_back(priv, xdp);
4671 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4672 res = STMMAC_XDP_CONSUMED;
4674 res = STMMAC_XDP_REDIRECT;
4677 bpf_warn_invalid_xdp_action(act);
4680 trace_xdp_exception(priv->dev, prog, act);
4683 res = STMMAC_XDP_CONSUMED;
4690 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4691 struct xdp_buff *xdp)
4693 struct bpf_prog *prog;
4696 prog = READ_ONCE(priv->xdp_prog);
4698 res = STMMAC_XDP_PASS;
4702 res = __stmmac_xdp_run_prog(priv, prog, xdp);
4704 return ERR_PTR(-res);
4707 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4710 int cpu = smp_processor_id();
4713 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4715 if (xdp_status & STMMAC_XDP_TX)
4716 stmmac_tx_timer_arm(priv, queue);
4718 if (xdp_status & STMMAC_XDP_REDIRECT)
4722 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4723 struct xdp_buff *xdp)
4725 unsigned int metasize = xdp->data - xdp->data_meta;
4726 unsigned int datasize = xdp->data_end - xdp->data;
4727 struct sk_buff *skb;
4729 skb = __napi_alloc_skb(&ch->rxtx_napi,
4730 xdp->data_end - xdp->data_hard_start,
4731 GFP_ATOMIC | __GFP_NOWARN);
4735 skb_reserve(skb, xdp->data - xdp->data_hard_start);
4736 memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4738 skb_metadata_set(skb, metasize);
4743 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4744 struct dma_desc *p, struct dma_desc *np,
4745 struct xdp_buff *xdp)
4747 struct stmmac_channel *ch = &priv->channel[queue];
4748 unsigned int len = xdp->data_end - xdp->data;
4749 enum pkt_hash_types hash_type;
4750 int coe = priv->hw->rx_csum;
4751 struct sk_buff *skb;
4754 skb = stmmac_construct_skb_zc(ch, xdp);
4756 priv->dev->stats.rx_dropped++;
4760 stmmac_get_rx_hwtstamp(priv, p, np, skb);
4761 stmmac_rx_vlan(priv->dev, skb);
4762 skb->protocol = eth_type_trans(skb, priv->dev);
4765 skb_checksum_none_assert(skb);
4767 skb->ip_summed = CHECKSUM_UNNECESSARY;
4769 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4770 skb_set_hash(skb, hash, hash_type);
4772 skb_record_rx_queue(skb, queue);
4773 napi_gro_receive(&ch->rxtx_napi, skb);
4775 priv->dev->stats.rx_packets++;
4776 priv->dev->stats.rx_bytes += len;
4779 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4781 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4782 unsigned int entry = rx_q->dirty_rx;
4783 struct dma_desc *rx_desc = NULL;
4786 budget = min(budget, stmmac_rx_dirty(priv, queue));
4788 while (budget-- > 0 && entry != rx_q->cur_rx) {
4789 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4790 dma_addr_t dma_addr;
4794 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4801 if (priv->extend_desc)
4802 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4804 rx_desc = rx_q->dma_rx + entry;
4806 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4807 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4808 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4809 stmmac_refill_desc3(priv, rx_q, rx_desc);
4811 rx_q->rx_count_frames++;
4812 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4813 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4814 rx_q->rx_count_frames = 0;
4816 use_rx_wd = !priv->rx_coal_frames[queue];
4817 use_rx_wd |= rx_q->rx_count_frames > 0;
4818 if (!priv->use_riwt)
4822 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4824 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size);
4828 rx_q->dirty_rx = entry;
4829 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4830 (rx_q->dirty_rx * sizeof(struct dma_desc));
4831 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4837 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
4839 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4840 unsigned int count = 0, error = 0, len = 0;
4841 int dirty = stmmac_rx_dirty(priv, queue);
4842 unsigned int next_entry = rx_q->cur_rx;
4843 unsigned int desc_size;
4844 struct bpf_prog *prog;
4845 bool failure = false;
4849 if (netif_msg_rx_status(priv)) {
4852 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
4853 if (priv->extend_desc) {
4854 rx_head = (void *)rx_q->dma_erx;
4855 desc_size = sizeof(struct dma_extended_desc);
4857 rx_head = (void *)rx_q->dma_rx;
4858 desc_size = sizeof(struct dma_desc);
4861 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
4862 rx_q->dma_rx_phy, desc_size);
4864 while (count < limit) {
4865 struct stmmac_rx_buffer *buf;
4866 unsigned int buf1_len = 0;
4867 struct dma_desc *np, *p;
4871 if (!count && rx_q->state_saved) {
4872 error = rx_q->state.error;
4873 len = rx_q->state.len;
4875 rx_q->state_saved = false;
4886 buf = &rx_q->buf_pool[entry];
4888 if (dirty >= STMMAC_RX_FILL_BATCH) {
4889 failure = failure ||
4890 !stmmac_rx_refill_zc(priv, queue, dirty);
4894 if (priv->extend_desc)
4895 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4897 p = rx_q->dma_rx + entry;
4899 /* read the status of the incoming frame */
4900 status = stmmac_rx_status(priv, &priv->dev->stats,
4902 /* check if managed by the DMA otherwise go ahead */
4903 if (unlikely(status & dma_own))
4906 /* Prefetch the next RX descriptor */
4907 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
4909 next_entry = rx_q->cur_rx;
4911 if (priv->extend_desc)
4912 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
4914 np = rx_q->dma_rx + next_entry;
4918 /* Ensure a valid XSK buffer before proceed */
4922 if (priv->extend_desc)
4923 stmmac_rx_extended_status(priv, &priv->dev->stats,
4925 rx_q->dma_erx + entry);
4926 if (unlikely(status == discard_frame)) {
4927 xsk_buff_free(buf->xdp);
4931 if (!priv->hwts_rx_en)
4932 priv->dev->stats.rx_errors++;
4935 if (unlikely(error && (status & rx_not_ls)))
4937 if (unlikely(error)) {
4942 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
4943 if (likely(status & rx_not_ls)) {
4944 xsk_buff_free(buf->xdp);
4951 /* XDP ZC Frame only support primary buffers for now */
4952 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
4955 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
4956 * Type frames (LLC/LLC-SNAP)
4958 * llc_snap is never checked in GMAC >= 4, so this ACS
4959 * feature is always disabled and packets need to be
4960 * stripped manually.
4962 if (likely(!(status & rx_not_ls)) &&
4963 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
4964 unlikely(status != llc_snap))) {
4965 buf1_len -= ETH_FCS_LEN;
4969 /* RX buffer is good and fit into a XSK pool buffer */
4970 buf->xdp->data_end = buf->xdp->data + buf1_len;
4971 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
4973 prog = READ_ONCE(priv->xdp_prog);
4974 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
4977 case STMMAC_XDP_PASS:
4978 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
4979 xsk_buff_free(buf->xdp);
4981 case STMMAC_XDP_CONSUMED:
4982 xsk_buff_free(buf->xdp);
4983 priv->dev->stats.rx_dropped++;
4986 case STMMAC_XDP_REDIRECT:
4996 if (status & rx_not_ls) {
4997 rx_q->state_saved = true;
4998 rx_q->state.error = error;
4999 rx_q->state.len = len;
5002 stmmac_finalize_xdp_rx(priv, xdp_status);
5004 priv->xstats.rx_pkt_n += count;
5005 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5007 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5008 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5009 xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5011 xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5016 return failure ? limit : (int)count;
5020 * stmmac_rx - manage the receive process
5021 * @priv: driver private structure
5022 * @limit: napi bugget
5023 * @queue: RX queue index.
5024 * Description : this the function called by the napi poll method.
5025 * It gets all the frames inside the ring.
5027 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5029 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5030 struct stmmac_channel *ch = &priv->channel[queue];
5031 unsigned int count = 0, error = 0, len = 0;
5032 int status = 0, coe = priv->hw->rx_csum;
5033 unsigned int next_entry = rx_q->cur_rx;
5034 enum dma_data_direction dma_dir;
5035 unsigned int desc_size;
5036 struct sk_buff *skb = NULL;
5037 struct xdp_buff xdp;
5041 dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5042 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5044 if (netif_msg_rx_status(priv)) {
5047 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5048 if (priv->extend_desc) {
5049 rx_head = (void *)rx_q->dma_erx;
5050 desc_size = sizeof(struct dma_extended_desc);
5052 rx_head = (void *)rx_q->dma_rx;
5053 desc_size = sizeof(struct dma_desc);
5056 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true,
5057 rx_q->dma_rx_phy, desc_size);
5059 while (count < limit) {
5060 unsigned int buf1_len = 0, buf2_len = 0;
5061 enum pkt_hash_types hash_type;
5062 struct stmmac_rx_buffer *buf;
5063 struct dma_desc *np, *p;
5067 if (!count && rx_q->state_saved) {
5068 skb = rx_q->state.skb;
5069 error = rx_q->state.error;
5070 len = rx_q->state.len;
5072 rx_q->state_saved = false;
5085 buf = &rx_q->buf_pool[entry];
5087 if (priv->extend_desc)
5088 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5090 p = rx_q->dma_rx + entry;
5092 /* read the status of the incoming frame */
5093 status = stmmac_rx_status(priv, &priv->dev->stats,
5095 /* check if managed by the DMA otherwise go ahead */
5096 if (unlikely(status & dma_own))
5099 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5101 next_entry = rx_q->cur_rx;
5103 if (priv->extend_desc)
5104 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5106 np = rx_q->dma_rx + next_entry;
5110 if (priv->extend_desc)
5111 stmmac_rx_extended_status(priv, &priv->dev->stats,
5112 &priv->xstats, rx_q->dma_erx + entry);
5113 if (unlikely(status == discard_frame)) {
5114 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5117 if (!priv->hwts_rx_en)
5118 priv->dev->stats.rx_errors++;
5121 if (unlikely(error && (status & rx_not_ls)))
5123 if (unlikely(error)) {
5130 /* Buffer is good. Go on. */
5132 prefetch(page_address(buf->page) + buf->page_offset);
5134 prefetch(page_address(buf->sec_page));
5136 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5138 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5141 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
5142 * Type frames (LLC/LLC-SNAP)
5144 * llc_snap is never checked in GMAC >= 4, so this ACS
5145 * feature is always disabled and packets need to be
5146 * stripped manually.
5148 if (likely(!(status & rx_not_ls)) &&
5149 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
5150 unlikely(status != llc_snap))) {
5152 buf2_len -= ETH_FCS_LEN;
5154 buf1_len -= ETH_FCS_LEN;
5160 unsigned int pre_len, sync_len;
5162 dma_sync_single_for_cpu(priv->device, buf->addr,
5165 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq);
5166 xdp_prepare_buff(&xdp, page_address(buf->page),
5167 buf->page_offset, buf1_len, false);
5169 pre_len = xdp.data_end - xdp.data_hard_start -
5171 skb = stmmac_xdp_run_prog(priv, &xdp);
5172 /* Due xdp_adjust_tail: DMA sync for_device
5173 * cover max len CPU touch
5175 sync_len = xdp.data_end - xdp.data_hard_start -
5177 sync_len = max(sync_len, pre_len);
5179 /* For Not XDP_PASS verdict */
5181 unsigned int xdp_res = -PTR_ERR(skb);
5183 if (xdp_res & STMMAC_XDP_CONSUMED) {
5184 page_pool_put_page(rx_q->page_pool,
5185 virt_to_head_page(xdp.data),
5188 priv->dev->stats.rx_dropped++;
5190 /* Clear skb as it was set as
5191 * status by XDP program.
5195 if (unlikely((status & rx_not_ls)))
5200 } else if (xdp_res & (STMMAC_XDP_TX |
5201 STMMAC_XDP_REDIRECT)) {
5202 xdp_status |= xdp_res;
5212 /* XDP program may expand or reduce tail */
5213 buf1_len = xdp.data_end - xdp.data;
5215 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5217 priv->dev->stats.rx_dropped++;
5222 /* XDP program may adjust header */
5223 skb_copy_to_linear_data(skb, xdp.data, buf1_len);
5224 skb_put(skb, buf1_len);
5226 /* Data payload copied into SKB, page ready for recycle */
5227 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5229 } else if (buf1_len) {
5230 dma_sync_single_for_cpu(priv->device, buf->addr,
5232 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5233 buf->page, buf->page_offset, buf1_len,
5236 /* Data payload appended into SKB */
5237 page_pool_release_page(rx_q->page_pool, buf->page);
5242 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5244 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5245 buf->sec_page, 0, buf2_len,
5248 /* Data payload appended into SKB */
5249 page_pool_release_page(rx_q->page_pool, buf->sec_page);
5250 buf->sec_page = NULL;
5254 if (likely(status & rx_not_ls))
5259 /* Got entire packet into SKB. Finish it. */
5261 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5262 stmmac_rx_vlan(priv->dev, skb);
5263 skb->protocol = eth_type_trans(skb, priv->dev);
5266 skb_checksum_none_assert(skb);
5268 skb->ip_summed = CHECKSUM_UNNECESSARY;
5270 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5271 skb_set_hash(skb, hash, hash_type);
5273 skb_record_rx_queue(skb, queue);
5274 napi_gro_receive(&ch->rx_napi, skb);
5277 priv->dev->stats.rx_packets++;
5278 priv->dev->stats.rx_bytes += len;
5282 if (status & rx_not_ls || skb) {
5283 rx_q->state_saved = true;
5284 rx_q->state.skb = skb;
5285 rx_q->state.error = error;
5286 rx_q->state.len = len;
5289 stmmac_finalize_xdp_rx(priv, xdp_status);
5291 stmmac_rx_refill(priv, queue);
5293 priv->xstats.rx_pkt_n += count;
5294 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5299 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5301 struct stmmac_channel *ch =
5302 container_of(napi, struct stmmac_channel, rx_napi);
5303 struct stmmac_priv *priv = ch->priv_data;
5304 u32 chan = ch->index;
5307 priv->xstats.napi_poll++;
5309 work_done = stmmac_rx(priv, budget, chan);
5310 if (work_done < budget && napi_complete_done(napi, work_done)) {
5311 unsigned long flags;
5313 spin_lock_irqsave(&ch->lock, flags);
5314 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5315 spin_unlock_irqrestore(&ch->lock, flags);
5321 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5323 struct stmmac_channel *ch =
5324 container_of(napi, struct stmmac_channel, tx_napi);
5325 struct stmmac_priv *priv = ch->priv_data;
5326 u32 chan = ch->index;
5329 priv->xstats.napi_poll++;
5331 work_done = stmmac_tx_clean(priv, budget, chan);
5332 work_done = min(work_done, budget);
5334 if (work_done < budget && napi_complete_done(napi, work_done)) {
5335 unsigned long flags;
5337 spin_lock_irqsave(&ch->lock, flags);
5338 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5339 spin_unlock_irqrestore(&ch->lock, flags);
5345 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5347 struct stmmac_channel *ch =
5348 container_of(napi, struct stmmac_channel, rxtx_napi);
5349 struct stmmac_priv *priv = ch->priv_data;
5350 int rx_done, tx_done, rxtx_done;
5351 u32 chan = ch->index;
5353 priv->xstats.napi_poll++;
5355 tx_done = stmmac_tx_clean(priv, budget, chan);
5356 tx_done = min(tx_done, budget);
5358 rx_done = stmmac_rx_zc(priv, budget, chan);
5360 rxtx_done = max(tx_done, rx_done);
5362 /* If either TX or RX work is not complete, return budget
5365 if (rxtx_done >= budget)
5368 /* all work done, exit the polling mode */
5369 if (napi_complete_done(napi, rxtx_done)) {
5370 unsigned long flags;
5372 spin_lock_irqsave(&ch->lock, flags);
5373 /* Both RX and TX work done are compelte,
5374 * so enable both RX & TX IRQs.
5376 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5377 spin_unlock_irqrestore(&ch->lock, flags);
5380 return min(rxtx_done, budget - 1);
5385 * @dev : Pointer to net device structure
5386 * @txqueue: the index of the hanging transmit queue
5387 * Description: this function is called when a packet transmission fails to
5388 * complete within a reasonable time. The driver will mark the error in the
5389 * netdev structure and arrange for the device to be reset to a sane state
5390 * in order to transmit a new packet.
5392 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5394 struct stmmac_priv *priv = netdev_priv(dev);
5396 stmmac_global_err(priv);
5400 * stmmac_set_rx_mode - entry point for multicast addressing
5401 * @dev : pointer to the device structure
5403 * This function is a driver entry point which gets called by the kernel
5404 * whenever multicast addresses must be enabled/disabled.
5408 static void stmmac_set_rx_mode(struct net_device *dev)
5410 struct stmmac_priv *priv = netdev_priv(dev);
5412 stmmac_set_filter(priv, priv->hw, dev);
5416 * stmmac_change_mtu - entry point to change MTU size for the device.
5417 * @dev : device pointer.
5418 * @new_mtu : the new MTU size for the device.
5419 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
5420 * to drive packet transmission. Ethernet has an MTU of 1500 octets
5421 * (ETH_DATA_LEN). This value can be changed with ifconfig.
5423 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5426 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5428 struct stmmac_priv *priv = netdev_priv(dev);
5429 int txfifosz = priv->plat->tx_fifo_size;
5430 const int mtu = new_mtu;
5433 txfifosz = priv->dma_cap.tx_fifo_size;
5435 txfifosz /= priv->plat->tx_queues_to_use;
5437 if (netif_running(dev)) {
5438 netdev_err(priv->dev, "must be stopped to change its MTU\n");
5442 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5443 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5447 new_mtu = STMMAC_ALIGN(new_mtu);
5449 /* If condition true, FIFO is too small or MTU too large */
5450 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5455 netdev_update_features(dev);
5460 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5461 netdev_features_t features)
5463 struct stmmac_priv *priv = netdev_priv(dev);
5465 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5466 features &= ~NETIF_F_RXCSUM;
5468 if (!priv->plat->tx_coe)
5469 features &= ~NETIF_F_CSUM_MASK;
5471 /* Some GMAC devices have a bugged Jumbo frame support that
5472 * needs to have the Tx COE disabled for oversized frames
5473 * (due to limited buffer sizes). In this case we disable
5474 * the TX csum insertion in the TDES and not use SF.
5476 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5477 features &= ~NETIF_F_CSUM_MASK;
5479 /* Disable tso if asked by ethtool */
5480 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
5481 if (features & NETIF_F_TSO)
5490 static int stmmac_set_features(struct net_device *netdev,
5491 netdev_features_t features)
5493 struct stmmac_priv *priv = netdev_priv(netdev);
5497 /* Keep the COE Type in case of csum is supporting */
5498 if (features & NETIF_F_RXCSUM)
5499 priv->hw->rx_csum = priv->plat->rx_coe;
5501 priv->hw->rx_csum = 0;
5502 /* No check needed because rx_coe has been set before and it will be
5503 * fixed in case of issue.
5505 stmmac_rx_ipc(priv, priv->hw);
5507 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5509 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5510 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5515 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5517 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5518 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5519 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5520 bool *hs_enable = &fpe_cfg->hs_enable;
5522 if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5525 /* If LP has sent verify mPacket, LP is FPE capable */
5526 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5527 if (*lp_state < FPE_STATE_CAPABLE)
5528 *lp_state = FPE_STATE_CAPABLE;
5530 /* If user has requested FPE enable, quickly response */
5532 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5536 /* If Local has sent verify mPacket, Local is FPE capable */
5537 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5538 if (*lo_state < FPE_STATE_CAPABLE)
5539 *lo_state = FPE_STATE_CAPABLE;
5542 /* If LP has sent response mPacket, LP is entering FPE ON */
5543 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5544 *lp_state = FPE_STATE_ENTERING_ON;
5546 /* If Local has sent response mPacket, Local is entering FPE ON */
5547 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5548 *lo_state = FPE_STATE_ENTERING_ON;
5550 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5551 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5553 queue_work(priv->fpe_wq, &priv->fpe_task);
5557 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5559 u32 rx_cnt = priv->plat->rx_queues_to_use;
5560 u32 tx_cnt = priv->plat->tx_queues_to_use;
5565 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5566 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5569 pm_wakeup_event(priv->device, 0);
5571 if (priv->dma_cap.estsel)
5572 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5573 &priv->xstats, tx_cnt);
5575 if (priv->dma_cap.fpesel) {
5576 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5579 stmmac_fpe_event_status(priv, status);
5582 /* To handle GMAC own interrupts */
5583 if ((priv->plat->has_gmac) || xmac) {
5584 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5586 if (unlikely(status)) {
5587 /* For LPI we need to save the tx status */
5588 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5589 priv->tx_path_in_lpi_mode = true;
5590 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5591 priv->tx_path_in_lpi_mode = false;
5594 for (queue = 0; queue < queues_count; queue++) {
5595 status = stmmac_host_mtl_irq_status(priv, priv->hw,
5599 /* PCS link status */
5600 if (priv->hw->pcs) {
5601 if (priv->xstats.pcs_link)
5602 netif_carrier_on(priv->dev);
5604 netif_carrier_off(priv->dev);
5607 stmmac_timestamp_interrupt(priv, priv);
5612 * stmmac_interrupt - main ISR
5613 * @irq: interrupt number.
5614 * @dev_id: to pass the net device pointer.
5615 * Description: this is the main driver interrupt service routine.
5617 * o DMA service routine (to manage incoming frame reception and transmission
5619 * o Core interrupts to manage: remote wake-up, management counter, LPI
5622 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5624 struct net_device *dev = (struct net_device *)dev_id;
5625 struct stmmac_priv *priv = netdev_priv(dev);
5627 /* Check if adapter is up */
5628 if (test_bit(STMMAC_DOWN, &priv->state))
5631 /* Check if a fatal error happened */
5632 if (stmmac_safety_feat_interrupt(priv))
5635 /* To handle Common interrupts */
5636 stmmac_common_interrupt(priv);
5638 /* To handle DMA interrupts */
5639 stmmac_dma_interrupt(priv);
5644 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5646 struct net_device *dev = (struct net_device *)dev_id;
5647 struct stmmac_priv *priv = netdev_priv(dev);
5649 if (unlikely(!dev)) {
5650 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5654 /* Check if adapter is up */
5655 if (test_bit(STMMAC_DOWN, &priv->state))
5658 /* To handle Common interrupts */
5659 stmmac_common_interrupt(priv);
5664 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5666 struct net_device *dev = (struct net_device *)dev_id;
5667 struct stmmac_priv *priv = netdev_priv(dev);
5669 if (unlikely(!dev)) {
5670 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5674 /* Check if adapter is up */
5675 if (test_bit(STMMAC_DOWN, &priv->state))
5678 /* Check if a fatal error happened */
5679 stmmac_safety_feat_interrupt(priv);
5684 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5686 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5687 int chan = tx_q->queue_index;
5688 struct stmmac_priv *priv;
5691 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]);
5693 if (unlikely(!data)) {
5694 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5698 /* Check if adapter is up */
5699 if (test_bit(STMMAC_DOWN, &priv->state))
5702 status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5704 if (unlikely(status & tx_hard_error_bump_tc)) {
5705 /* Try to bump up the dma threshold on this failure */
5706 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
5709 if (priv->plat->force_thresh_dma_mode)
5710 stmmac_set_dma_operation_mode(priv,
5715 stmmac_set_dma_operation_mode(priv,
5719 priv->xstats.threshold = tc;
5721 } else if (unlikely(status == tx_hard_error)) {
5722 stmmac_tx_err(priv, chan);
5728 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5730 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5731 int chan = rx_q->queue_index;
5732 struct stmmac_priv *priv;
5734 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]);
5736 if (unlikely(!data)) {
5737 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5741 /* Check if adapter is up */
5742 if (test_bit(STMMAC_DOWN, &priv->state))
5745 stmmac_napi_check(priv, chan, DMA_DIR_RX);
5750 #ifdef CONFIG_NET_POLL_CONTROLLER
5751 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5752 * to allow network I/O with interrupts disabled.
5754 static void stmmac_poll_controller(struct net_device *dev)
5756 struct stmmac_priv *priv = netdev_priv(dev);
5759 /* If adapter is down, do nothing */
5760 if (test_bit(STMMAC_DOWN, &priv->state))
5763 if (priv->plat->multi_msi_en) {
5764 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5765 stmmac_msi_intr_rx(0, &priv->rx_queue[i]);
5767 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5768 stmmac_msi_intr_tx(0, &priv->tx_queue[i]);
5770 disable_irq(dev->irq);
5771 stmmac_interrupt(dev->irq, dev);
5772 enable_irq(dev->irq);
5778 * stmmac_ioctl - Entry point for the Ioctl
5779 * @dev: Device pointer.
5780 * @rq: An IOCTL specefic structure, that can contain a pointer to
5781 * a proprietary structure used to pass information to the driver.
5782 * @cmd: IOCTL command
5784 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5786 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5788 struct stmmac_priv *priv = netdev_priv (dev);
5789 int ret = -EOPNOTSUPP;
5791 if (!netif_running(dev))
5798 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5801 ret = stmmac_hwtstamp_set(dev, rq);
5804 ret = stmmac_hwtstamp_get(dev, rq);
5813 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5816 struct stmmac_priv *priv = cb_priv;
5817 int ret = -EOPNOTSUPP;
5819 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
5822 __stmmac_disable_all_queues(priv);
5825 case TC_SETUP_CLSU32:
5826 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
5828 case TC_SETUP_CLSFLOWER:
5829 ret = stmmac_tc_setup_cls(priv, priv, type_data);
5835 stmmac_enable_all_queues(priv);
5839 static LIST_HEAD(stmmac_block_cb_list);
5841 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
5844 struct stmmac_priv *priv = netdev_priv(ndev);
5847 case TC_SETUP_BLOCK:
5848 return flow_block_cb_setup_simple(type_data,
5849 &stmmac_block_cb_list,
5850 stmmac_setup_tc_block_cb,
5852 case TC_SETUP_QDISC_CBS:
5853 return stmmac_tc_setup_cbs(priv, priv, type_data);
5854 case TC_SETUP_QDISC_TAPRIO:
5855 return stmmac_tc_setup_taprio(priv, priv, type_data);
5856 case TC_SETUP_QDISC_ETF:
5857 return stmmac_tc_setup_etf(priv, priv, type_data);
5863 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
5864 struct net_device *sb_dev)
5866 int gso = skb_shinfo(skb)->gso_type;
5868 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
5870 * There is no way to determine the number of TSO/USO
5871 * capable Queues. Let's use always the Queue 0
5872 * because if TSO/USO is supported then at least this
5873 * one will be capable.
5878 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
5881 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
5883 struct stmmac_priv *priv = netdev_priv(ndev);
5886 ret = pm_runtime_get_sync(priv->device);
5888 pm_runtime_put_noidle(priv->device);
5892 ret = eth_mac_addr(ndev, addr);
5896 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
5899 pm_runtime_put(priv->device);
5904 #ifdef CONFIG_DEBUG_FS
5905 static struct dentry *stmmac_fs_dir;
5907 static void sysfs_display_ring(void *head, int size, int extend_desc,
5908 struct seq_file *seq, dma_addr_t dma_phy_addr)
5911 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
5912 struct dma_desc *p = (struct dma_desc *)head;
5913 dma_addr_t dma_addr;
5915 for (i = 0; i < size; i++) {
5917 dma_addr = dma_phy_addr + i * sizeof(*ep);
5918 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5920 le32_to_cpu(ep->basic.des0),
5921 le32_to_cpu(ep->basic.des1),
5922 le32_to_cpu(ep->basic.des2),
5923 le32_to_cpu(ep->basic.des3));
5926 dma_addr = dma_phy_addr + i * sizeof(*p);
5927 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
5929 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
5930 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
5933 seq_printf(seq, "\n");
5937 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
5939 struct net_device *dev = seq->private;
5940 struct stmmac_priv *priv = netdev_priv(dev);
5941 u32 rx_count = priv->plat->rx_queues_to_use;
5942 u32 tx_count = priv->plat->tx_queues_to_use;
5945 if ((dev->flags & IFF_UP) == 0)
5948 for (queue = 0; queue < rx_count; queue++) {
5949 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
5951 seq_printf(seq, "RX Queue %d:\n", queue);
5953 if (priv->extend_desc) {
5954 seq_printf(seq, "Extended descriptor ring:\n");
5955 sysfs_display_ring((void *)rx_q->dma_erx,
5956 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy);
5958 seq_printf(seq, "Descriptor ring:\n");
5959 sysfs_display_ring((void *)rx_q->dma_rx,
5960 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy);
5964 for (queue = 0; queue < tx_count; queue++) {
5965 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
5967 seq_printf(seq, "TX Queue %d:\n", queue);
5969 if (priv->extend_desc) {
5970 seq_printf(seq, "Extended descriptor ring:\n");
5971 sysfs_display_ring((void *)tx_q->dma_etx,
5972 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy);
5973 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
5974 seq_printf(seq, "Descriptor ring:\n");
5975 sysfs_display_ring((void *)tx_q->dma_tx,
5976 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy);
5982 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
5984 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
5986 struct net_device *dev = seq->private;
5987 struct stmmac_priv *priv = netdev_priv(dev);
5989 if (!priv->hw_cap_support) {
5990 seq_printf(seq, "DMA HW features not supported\n");
5994 seq_printf(seq, "==============================\n");
5995 seq_printf(seq, "\tDMA HW features\n");
5996 seq_printf(seq, "==============================\n");
5998 seq_printf(seq, "\t10/100 Mbps: %s\n",
5999 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6000 seq_printf(seq, "\t1000 Mbps: %s\n",
6001 (priv->dma_cap.mbps_1000) ? "Y" : "N");
6002 seq_printf(seq, "\tHalf duplex: %s\n",
6003 (priv->dma_cap.half_duplex) ? "Y" : "N");
6004 seq_printf(seq, "\tHash Filter: %s\n",
6005 (priv->dma_cap.hash_filter) ? "Y" : "N");
6006 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6007 (priv->dma_cap.multi_addr) ? "Y" : "N");
6008 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6009 (priv->dma_cap.pcs) ? "Y" : "N");
6010 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6011 (priv->dma_cap.sma_mdio) ? "Y" : "N");
6012 seq_printf(seq, "\tPMT Remote wake up: %s\n",
6013 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6014 seq_printf(seq, "\tPMT Magic Frame: %s\n",
6015 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6016 seq_printf(seq, "\tRMON module: %s\n",
6017 (priv->dma_cap.rmon) ? "Y" : "N");
6018 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6019 (priv->dma_cap.time_stamp) ? "Y" : "N");
6020 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6021 (priv->dma_cap.atime_stamp) ? "Y" : "N");
6022 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6023 (priv->dma_cap.eee) ? "Y" : "N");
6024 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6025 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6026 (priv->dma_cap.tx_coe) ? "Y" : "N");
6027 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6028 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6029 (priv->dma_cap.rx_coe) ? "Y" : "N");
6031 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6032 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6033 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6034 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6036 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6037 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6038 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6039 priv->dma_cap.number_rx_channel);
6040 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6041 priv->dma_cap.number_tx_channel);
6042 seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6043 priv->dma_cap.number_rx_queues);
6044 seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6045 priv->dma_cap.number_tx_queues);
6046 seq_printf(seq, "\tEnhanced descriptors: %s\n",
6047 (priv->dma_cap.enh_desc) ? "Y" : "N");
6048 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6049 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6050 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6051 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6052 seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6053 priv->dma_cap.pps_out_num);
6054 seq_printf(seq, "\tSafety Features: %s\n",
6055 priv->dma_cap.asp ? "Y" : "N");
6056 seq_printf(seq, "\tFlexible RX Parser: %s\n",
6057 priv->dma_cap.frpsel ? "Y" : "N");
6058 seq_printf(seq, "\tEnhanced Addressing: %d\n",
6059 priv->dma_cap.addr64);
6060 seq_printf(seq, "\tReceive Side Scaling: %s\n",
6061 priv->dma_cap.rssen ? "Y" : "N");
6062 seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6063 priv->dma_cap.vlhash ? "Y" : "N");
6064 seq_printf(seq, "\tSplit Header: %s\n",
6065 priv->dma_cap.sphen ? "Y" : "N");
6066 seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6067 priv->dma_cap.vlins ? "Y" : "N");
6068 seq_printf(seq, "\tDouble VLAN: %s\n",
6069 priv->dma_cap.dvlan ? "Y" : "N");
6070 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6071 priv->dma_cap.l3l4fnum);
6072 seq_printf(seq, "\tARP Offloading: %s\n",
6073 priv->dma_cap.arpoffsel ? "Y" : "N");
6074 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6075 priv->dma_cap.estsel ? "Y" : "N");
6076 seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6077 priv->dma_cap.fpesel ? "Y" : "N");
6078 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6079 priv->dma_cap.tbssel ? "Y" : "N");
6082 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6084 /* Use network device events to rename debugfs file entries.
6086 static int stmmac_device_event(struct notifier_block *unused,
6087 unsigned long event, void *ptr)
6089 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6090 struct stmmac_priv *priv = netdev_priv(dev);
6092 if (dev->netdev_ops != &stmmac_netdev_ops)
6096 case NETDEV_CHANGENAME:
6097 if (priv->dbgfs_dir)
6098 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6108 static struct notifier_block stmmac_notifier = {
6109 .notifier_call = stmmac_device_event,
6112 static void stmmac_init_fs(struct net_device *dev)
6114 struct stmmac_priv *priv = netdev_priv(dev);
6118 /* Create per netdev entries */
6119 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6121 /* Entry to report DMA RX/TX rings */
6122 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6123 &stmmac_rings_status_fops);
6125 /* Entry to report the DMA HW features */
6126 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6127 &stmmac_dma_cap_fops);
6132 static void stmmac_exit_fs(struct net_device *dev)
6134 struct stmmac_priv *priv = netdev_priv(dev);
6136 debugfs_remove_recursive(priv->dbgfs_dir);
6138 #endif /* CONFIG_DEBUG_FS */
6140 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6142 unsigned char *data = (unsigned char *)&vid_le;
6143 unsigned char data_byte = 0;
6148 bits = get_bitmask_order(VLAN_VID_MASK);
6149 for (i = 0; i < bits; i++) {
6151 data_byte = data[i / 8];
6153 temp = ((crc & 1) ^ data_byte) & 1;
6164 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6171 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6172 __le16 vid_le = cpu_to_le16(vid);
6173 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6178 if (!priv->dma_cap.vlhash) {
6179 if (count > 2) /* VID = 0 always passes filter */
6182 pmatch = cpu_to_le16(vid);
6186 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6189 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6191 struct stmmac_priv *priv = netdev_priv(ndev);
6192 bool is_double = false;
6195 if (be16_to_cpu(proto) == ETH_P_8021AD)
6198 set_bit(vid, priv->active_vlans);
6199 ret = stmmac_vlan_update(priv, is_double);
6201 clear_bit(vid, priv->active_vlans);
6205 if (priv->hw->num_vlan) {
6206 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6214 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6216 struct stmmac_priv *priv = netdev_priv(ndev);
6217 bool is_double = false;
6220 ret = pm_runtime_get_sync(priv->device);
6222 pm_runtime_put_noidle(priv->device);
6226 if (be16_to_cpu(proto) == ETH_P_8021AD)
6229 clear_bit(vid, priv->active_vlans);
6231 if (priv->hw->num_vlan) {
6232 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6234 goto del_vlan_error;
6237 ret = stmmac_vlan_update(priv, is_double);
6240 pm_runtime_put(priv->device);
6245 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6247 struct stmmac_priv *priv = netdev_priv(dev);
6249 switch (bpf->command) {
6250 case XDP_SETUP_PROG:
6251 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6252 case XDP_SETUP_XSK_POOL:
6253 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6260 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6261 struct xdp_frame **frames, u32 flags)
6263 struct stmmac_priv *priv = netdev_priv(dev);
6264 int cpu = smp_processor_id();
6265 struct netdev_queue *nq;
6269 if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6272 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6275 queue = stmmac_xdp_get_tx_queue(priv, cpu);
6276 nq = netdev_get_tx_queue(priv->dev, queue);
6278 __netif_tx_lock(nq, cpu);
6279 /* Avoids TX time-out as we are sharing with slow path */
6280 nq->trans_start = jiffies;
6282 for (i = 0; i < num_frames; i++) {
6285 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6286 if (res == STMMAC_XDP_CONSUMED)
6292 if (flags & XDP_XMIT_FLUSH) {
6293 stmmac_flush_tx_descriptors(priv, queue);
6294 stmmac_tx_timer_arm(priv, queue);
6297 __netif_tx_unlock(nq);
6302 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6304 struct stmmac_channel *ch = &priv->channel[queue];
6305 unsigned long flags;
6307 spin_lock_irqsave(&ch->lock, flags);
6308 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6309 spin_unlock_irqrestore(&ch->lock, flags);
6311 stmmac_stop_rx_dma(priv, queue);
6312 __free_dma_rx_desc_resources(priv, queue);
6315 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6317 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
6318 struct stmmac_channel *ch = &priv->channel[queue];
6319 unsigned long flags;
6323 ret = __alloc_dma_rx_desc_resources(priv, queue);
6325 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6329 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL);
6331 __free_dma_rx_desc_resources(priv, queue);
6332 netdev_err(priv->dev, "Failed to init RX desc.\n");
6336 stmmac_clear_rx_descriptors(priv, queue);
6338 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6339 rx_q->dma_rx_phy, rx_q->queue_index);
6341 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6342 sizeof(struct dma_desc));
6343 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6344 rx_q->rx_tail_addr, rx_q->queue_index);
6346 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6347 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6348 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6352 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6357 stmmac_start_rx_dma(priv, queue);
6359 spin_lock_irqsave(&ch->lock, flags);
6360 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6361 spin_unlock_irqrestore(&ch->lock, flags);
6364 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6366 struct stmmac_channel *ch = &priv->channel[queue];
6367 unsigned long flags;
6369 spin_lock_irqsave(&ch->lock, flags);
6370 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6371 spin_unlock_irqrestore(&ch->lock, flags);
6373 stmmac_stop_tx_dma(priv, queue);
6374 __free_dma_tx_desc_resources(priv, queue);
6377 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6379 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
6380 struct stmmac_channel *ch = &priv->channel[queue];
6381 unsigned long flags;
6384 ret = __alloc_dma_tx_desc_resources(priv, queue);
6386 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6390 ret = __init_dma_tx_desc_rings(priv, queue);
6392 __free_dma_tx_desc_resources(priv, queue);
6393 netdev_err(priv->dev, "Failed to init TX desc.\n");
6397 stmmac_clear_tx_descriptors(priv, queue);
6399 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6400 tx_q->dma_tx_phy, tx_q->queue_index);
6402 if (tx_q->tbs & STMMAC_TBS_AVAIL)
6403 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6405 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6406 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6407 tx_q->tx_tail_addr, tx_q->queue_index);
6409 stmmac_start_tx_dma(priv, queue);
6411 spin_lock_irqsave(&ch->lock, flags);
6412 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6413 spin_unlock_irqrestore(&ch->lock, flags);
6416 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6418 struct stmmac_priv *priv = netdev_priv(dev);
6419 struct stmmac_rx_queue *rx_q;
6420 struct stmmac_tx_queue *tx_q;
6421 struct stmmac_channel *ch;
6423 if (test_bit(STMMAC_DOWN, &priv->state) ||
6424 !netif_carrier_ok(priv->dev))
6427 if (!stmmac_xdp_is_enabled(priv))
6430 if (queue >= priv->plat->rx_queues_to_use ||
6431 queue >= priv->plat->tx_queues_to_use)
6434 rx_q = &priv->rx_queue[queue];
6435 tx_q = &priv->tx_queue[queue];
6436 ch = &priv->channel[queue];
6438 if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6441 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6442 /* EQoS does not have per-DMA channel SW interrupt,
6443 * so we schedule RX Napi straight-away.
6445 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6446 __napi_schedule(&ch->rxtx_napi);
6452 static const struct net_device_ops stmmac_netdev_ops = {
6453 .ndo_open = stmmac_open,
6454 .ndo_start_xmit = stmmac_xmit,
6455 .ndo_stop = stmmac_release,
6456 .ndo_change_mtu = stmmac_change_mtu,
6457 .ndo_fix_features = stmmac_fix_features,
6458 .ndo_set_features = stmmac_set_features,
6459 .ndo_set_rx_mode = stmmac_set_rx_mode,
6460 .ndo_tx_timeout = stmmac_tx_timeout,
6461 .ndo_eth_ioctl = stmmac_ioctl,
6462 .ndo_setup_tc = stmmac_setup_tc,
6463 .ndo_select_queue = stmmac_select_queue,
6464 #ifdef CONFIG_NET_POLL_CONTROLLER
6465 .ndo_poll_controller = stmmac_poll_controller,
6467 .ndo_set_mac_address = stmmac_set_mac_address,
6468 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6469 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6470 .ndo_bpf = stmmac_bpf,
6471 .ndo_xdp_xmit = stmmac_xdp_xmit,
6472 .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6475 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6477 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6479 if (test_bit(STMMAC_DOWN, &priv->state))
6482 netdev_err(priv->dev, "Reset adapter.\n");
6485 netif_trans_update(priv->dev);
6486 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6487 usleep_range(1000, 2000);
6489 set_bit(STMMAC_DOWN, &priv->state);
6490 dev_close(priv->dev);
6491 dev_open(priv->dev, NULL);
6492 clear_bit(STMMAC_DOWN, &priv->state);
6493 clear_bit(STMMAC_RESETING, &priv->state);
6497 static void stmmac_service_task(struct work_struct *work)
6499 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6502 stmmac_reset_subtask(priv);
6503 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6507 * stmmac_hw_init - Init the MAC device
6508 * @priv: driver private structure
6509 * Description: this function is to configure the MAC device according to
6510 * some platform parameters or the HW capability register. It prepares the
6511 * driver to use either ring or chain modes and to setup either enhanced or
6512 * normal descriptors.
6514 static int stmmac_hw_init(struct stmmac_priv *priv)
6518 /* dwmac-sun8i only work in chain mode */
6519 if (priv->plat->has_sun8i)
6521 priv->chain_mode = chain_mode;
6523 /* Initialize HW Interface */
6524 ret = stmmac_hwif_init(priv);
6528 /* Get the HW capability (new GMAC newer than 3.50a) */
6529 priv->hw_cap_support = stmmac_get_hw_features(priv);
6530 if (priv->hw_cap_support) {
6531 dev_info(priv->device, "DMA HW capability register supported\n");
6533 /* We can override some gmac/dma configuration fields: e.g.
6534 * enh_desc, tx_coe (e.g. that are passed through the
6535 * platform) with the values from the HW capability
6536 * register (if supported).
6538 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6539 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6540 !priv->plat->use_phy_wol;
6541 priv->hw->pmt = priv->plat->pmt;
6542 if (priv->dma_cap.hash_tb_sz) {
6543 priv->hw->multicast_filter_bins =
6544 (BIT(priv->dma_cap.hash_tb_sz) << 5);
6545 priv->hw->mcast_bits_log2 =
6546 ilog2(priv->hw->multicast_filter_bins);
6549 /* TXCOE doesn't work in thresh DMA mode */
6550 if (priv->plat->force_thresh_dma_mode)
6551 priv->plat->tx_coe = 0;
6553 priv->plat->tx_coe = priv->dma_cap.tx_coe;
6555 /* In case of GMAC4 rx_coe is from HW cap register. */
6556 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6558 if (priv->dma_cap.rx_coe_type2)
6559 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6560 else if (priv->dma_cap.rx_coe_type1)
6561 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6564 dev_info(priv->device, "No HW DMA feature register supported\n");
6567 if (priv->plat->rx_coe) {
6568 priv->hw->rx_csum = priv->plat->rx_coe;
6569 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6570 if (priv->synopsys_id < DWMAC_CORE_4_00)
6571 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6573 if (priv->plat->tx_coe)
6574 dev_info(priv->device, "TX Checksum insertion supported\n");
6576 if (priv->plat->pmt) {
6577 dev_info(priv->device, "Wake-Up On Lan supported\n");
6578 device_set_wakeup_capable(priv->device, 1);
6581 if (priv->dma_cap.tsoen)
6582 dev_info(priv->device, "TSO supported\n");
6584 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6585 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6587 /* Run HW quirks, if any */
6588 if (priv->hwif_quirks) {
6589 ret = priv->hwif_quirks(priv);
6594 /* Rx Watchdog is available in the COREs newer than the 3.40.
6595 * In some case, for example on bugged HW this feature
6596 * has to be disable and this can be done by passing the
6597 * riwt_off field from the platform.
6599 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6600 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6602 dev_info(priv->device,
6603 "Enable RX Mitigation via HW Watchdog Timer\n");
6609 static void stmmac_napi_add(struct net_device *dev)
6611 struct stmmac_priv *priv = netdev_priv(dev);
6614 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6616 for (queue = 0; queue < maxq; queue++) {
6617 struct stmmac_channel *ch = &priv->channel[queue];
6619 ch->priv_data = priv;
6621 spin_lock_init(&ch->lock);
6623 if (queue < priv->plat->rx_queues_to_use) {
6624 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx,
6627 if (queue < priv->plat->tx_queues_to_use) {
6628 netif_tx_napi_add(dev, &ch->tx_napi,
6629 stmmac_napi_poll_tx,
6632 if (queue < priv->plat->rx_queues_to_use &&
6633 queue < priv->plat->tx_queues_to_use) {
6634 netif_napi_add(dev, &ch->rxtx_napi,
6635 stmmac_napi_poll_rxtx,
6641 static void stmmac_napi_del(struct net_device *dev)
6643 struct stmmac_priv *priv = netdev_priv(dev);
6646 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6648 for (queue = 0; queue < maxq; queue++) {
6649 struct stmmac_channel *ch = &priv->channel[queue];
6651 if (queue < priv->plat->rx_queues_to_use)
6652 netif_napi_del(&ch->rx_napi);
6653 if (queue < priv->plat->tx_queues_to_use)
6654 netif_napi_del(&ch->tx_napi);
6655 if (queue < priv->plat->rx_queues_to_use &&
6656 queue < priv->plat->tx_queues_to_use) {
6657 netif_napi_del(&ch->rxtx_napi);
6662 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
6664 struct stmmac_priv *priv = netdev_priv(dev);
6667 if (netif_running(dev))
6668 stmmac_release(dev);
6670 stmmac_napi_del(dev);
6672 priv->plat->rx_queues_to_use = rx_cnt;
6673 priv->plat->tx_queues_to_use = tx_cnt;
6675 stmmac_napi_add(dev);
6677 if (netif_running(dev))
6678 ret = stmmac_open(dev);
6683 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
6685 struct stmmac_priv *priv = netdev_priv(dev);
6688 if (netif_running(dev))
6689 stmmac_release(dev);
6691 priv->dma_rx_size = rx_size;
6692 priv->dma_tx_size = tx_size;
6694 if (netif_running(dev))
6695 ret = stmmac_open(dev);
6700 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
6701 static void stmmac_fpe_lp_task(struct work_struct *work)
6703 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6705 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
6706 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
6707 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
6708 bool *hs_enable = &fpe_cfg->hs_enable;
6709 bool *enable = &fpe_cfg->enable;
6712 while (retries-- > 0) {
6713 /* Bail out immediately if FPE handshake is OFF */
6714 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
6717 if (*lo_state == FPE_STATE_ENTERING_ON &&
6718 *lp_state == FPE_STATE_ENTERING_ON) {
6719 stmmac_fpe_configure(priv, priv->ioaddr,
6720 priv->plat->tx_queues_to_use,
6721 priv->plat->rx_queues_to_use,
6724 netdev_info(priv->dev, "configured FPE\n");
6726 *lo_state = FPE_STATE_ON;
6727 *lp_state = FPE_STATE_ON;
6728 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
6732 if ((*lo_state == FPE_STATE_CAPABLE ||
6733 *lo_state == FPE_STATE_ENTERING_ON) &&
6734 *lp_state != FPE_STATE_ON) {
6735 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
6736 *lo_state, *lp_state);
6737 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6740 /* Sleep then retry */
6744 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
6747 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
6749 if (priv->plat->fpe_cfg->hs_enable != enable) {
6751 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
6754 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
6755 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
6758 priv->plat->fpe_cfg->hs_enable = enable;
6764 * @device: device pointer
6765 * @plat_dat: platform data pointer
6766 * @res: stmmac resource pointer
6767 * Description: this is the main probe function used to
6768 * call the alloc_etherdev, allocate the priv structure.
6770 * returns 0 on success, otherwise errno.
6772 int stmmac_dvr_probe(struct device *device,
6773 struct plat_stmmacenet_data *plat_dat,
6774 struct stmmac_resources *res)
6776 struct net_device *ndev = NULL;
6777 struct stmmac_priv *priv;
6781 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
6782 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
6786 SET_NETDEV_DEV(ndev, device);
6788 priv = netdev_priv(ndev);
6789 priv->device = device;
6792 stmmac_set_ethtool_ops(ndev);
6793 priv->pause = pause;
6794 priv->plat = plat_dat;
6795 priv->ioaddr = res->addr;
6796 priv->dev->base_addr = (unsigned long)res->addr;
6797 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
6799 priv->dev->irq = res->irq;
6800 priv->wol_irq = res->wol_irq;
6801 priv->lpi_irq = res->lpi_irq;
6802 priv->sfty_ce_irq = res->sfty_ce_irq;
6803 priv->sfty_ue_irq = res->sfty_ue_irq;
6804 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
6805 priv->rx_irq[i] = res->rx_irq[i];
6806 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
6807 priv->tx_irq[i] = res->tx_irq[i];
6809 if (!is_zero_ether_addr(res->mac))
6810 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
6812 dev_set_drvdata(device, priv->dev);
6814 /* Verify driver arguments */
6815 stmmac_verify_args();
6817 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
6818 if (!priv->af_xdp_zc_qps)
6821 /* Allocate workqueue */
6822 priv->wq = create_singlethread_workqueue("stmmac_wq");
6824 dev_err(priv->device, "failed to create workqueue\n");
6828 INIT_WORK(&priv->service_task, stmmac_service_task);
6830 /* Initialize Link Partner FPE workqueue */
6831 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
6833 /* Override with kernel parameters if supplied XXX CRS XXX
6834 * this needs to have multiple instances
6836 if ((phyaddr >= 0) && (phyaddr <= 31))
6837 priv->plat->phy_addr = phyaddr;
6839 if (priv->plat->stmmac_rst) {
6840 ret = reset_control_assert(priv->plat->stmmac_rst);
6841 reset_control_deassert(priv->plat->stmmac_rst);
6842 /* Some reset controllers have only reset callback instead of
6843 * assert + deassert callbacks pair.
6845 if (ret == -ENOTSUPP)
6846 reset_control_reset(priv->plat->stmmac_rst);
6849 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
6850 if (ret == -ENOTSUPP)
6851 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
6854 /* Init MAC and get the capabilities */
6855 ret = stmmac_hw_init(priv);
6859 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
6861 if (priv->synopsys_id < DWMAC_CORE_5_20)
6862 priv->plat->dma_cfg->dche = false;
6864 stmmac_check_ether_addr(priv);
6866 ndev->netdev_ops = &stmmac_netdev_ops;
6868 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6871 ret = stmmac_tc_init(priv, priv);
6873 ndev->hw_features |= NETIF_F_HW_TC;
6876 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
6877 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
6878 if (priv->plat->has_gmac4)
6879 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
6881 dev_info(priv->device, "TSO feature enabled\n");
6884 if (priv->dma_cap.sphen) {
6885 ndev->hw_features |= NETIF_F_GRO;
6886 priv->sph_cap = true;
6887 priv->sph = priv->sph_cap;
6888 dev_info(priv->device, "SPH feature enabled\n");
6891 /* The current IP register MAC_HW_Feature1[ADDR64] only define
6892 * 32/40/64 bit width, but some SOC support others like i.MX8MP
6893 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
6894 * So overwrite dma_cap.addr64 according to HW real design.
6896 if (priv->plat->addr64)
6897 priv->dma_cap.addr64 = priv->plat->addr64;
6899 if (priv->dma_cap.addr64) {
6900 ret = dma_set_mask_and_coherent(device,
6901 DMA_BIT_MASK(priv->dma_cap.addr64));
6903 dev_info(priv->device, "Using %d bits DMA width\n",
6904 priv->dma_cap.addr64);
6907 * If more than 32 bits can be addressed, make sure to
6908 * enable enhanced addressing mode.
6910 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
6911 priv->plat->dma_cfg->eame = true;
6913 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
6915 dev_err(priv->device, "Failed to set DMA Mask\n");
6919 priv->dma_cap.addr64 = 32;
6923 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
6924 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
6925 #ifdef STMMAC_VLAN_TAG_USED
6926 /* Both mac100 and gmac support receive VLAN tag detection */
6927 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
6928 if (priv->dma_cap.vlhash) {
6929 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
6930 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
6932 if (priv->dma_cap.vlins) {
6933 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
6934 if (priv->dma_cap.dvlan)
6935 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
6938 priv->msg_enable = netif_msg_init(debug, default_msg_level);
6940 /* Initialize RSS */
6941 rxq = priv->plat->rx_queues_to_use;
6942 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
6943 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
6944 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
6946 if (priv->dma_cap.rssen && priv->plat->rss_en)
6947 ndev->features |= NETIF_F_RXHASH;
6949 /* MTU range: 46 - hw-specific max */
6950 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
6951 if (priv->plat->has_xgmac)
6952 ndev->max_mtu = XGMAC_JUMBO_LEN;
6953 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
6954 ndev->max_mtu = JUMBO_LEN;
6956 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
6957 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
6958 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
6960 if ((priv->plat->maxmtu < ndev->max_mtu) &&
6961 (priv->plat->maxmtu >= ndev->min_mtu))
6962 ndev->max_mtu = priv->plat->maxmtu;
6963 else if (priv->plat->maxmtu < ndev->min_mtu)
6964 dev_warn(priv->device,
6965 "%s: warning: maxmtu having invalid value (%d)\n",
6966 __func__, priv->plat->maxmtu);
6969 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
6971 /* Setup channels NAPI */
6972 stmmac_napi_add(ndev);
6974 mutex_init(&priv->lock);
6976 /* If a specific clk_csr value is passed from the platform
6977 * this means that the CSR Clock Range selection cannot be
6978 * changed at run-time and it is fixed. Viceversa the driver'll try to
6979 * set the MDC clock dynamically according to the csr actual
6982 if (priv->plat->clk_csr >= 0)
6983 priv->clk_csr = priv->plat->clk_csr;
6985 stmmac_clk_csr_set(priv);
6987 stmmac_check_pcs_mode(priv);
6989 pm_runtime_get_noresume(device);
6990 pm_runtime_set_active(device);
6991 pm_runtime_enable(device);
6993 if (priv->hw->pcs != STMMAC_PCS_TBI &&
6994 priv->hw->pcs != STMMAC_PCS_RTBI) {
6995 /* MDIO bus Registration */
6996 ret = stmmac_mdio_register(ndev);
6998 dev_err(priv->device,
6999 "%s: MDIO bus (id: %d) registration failed",
7000 __func__, priv->plat->bus_id);
7001 goto error_mdio_register;
7005 if (priv->plat->speed_mode_2500)
7006 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7008 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7009 ret = stmmac_xpcs_setup(priv->mii);
7011 goto error_xpcs_setup;
7014 ret = stmmac_phy_setup(priv);
7016 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7017 goto error_phy_setup;
7020 ret = register_netdev(ndev);
7022 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7024 goto error_netdev_register;
7027 if (priv->plat->serdes_powerup) {
7028 ret = priv->plat->serdes_powerup(ndev,
7029 priv->plat->bsp_priv);
7032 goto error_serdes_powerup;
7035 #ifdef CONFIG_DEBUG_FS
7036 stmmac_init_fs(ndev);
7039 /* Let pm_runtime_put() disable the clocks.
7040 * If CONFIG_PM is not enabled, the clocks will stay powered.
7042 pm_runtime_put(device);
7046 error_serdes_powerup:
7047 unregister_netdev(ndev);
7048 error_netdev_register:
7049 phylink_destroy(priv->phylink);
7052 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7053 priv->hw->pcs != STMMAC_PCS_RTBI)
7054 stmmac_mdio_unregister(ndev);
7055 error_mdio_register:
7056 stmmac_napi_del(ndev);
7058 destroy_workqueue(priv->wq);
7059 bitmap_free(priv->af_xdp_zc_qps);
7063 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7067 * @dev: device pointer
7068 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7069 * changes the link status, releases the DMA descriptor rings.
7071 int stmmac_dvr_remove(struct device *dev)
7073 struct net_device *ndev = dev_get_drvdata(dev);
7074 struct stmmac_priv *priv = netdev_priv(ndev);
7076 netdev_info(priv->dev, "%s: removing driver", __func__);
7078 stmmac_stop_all_dma(priv);
7079 stmmac_mac_set(priv, priv->ioaddr, false);
7080 netif_carrier_off(ndev);
7081 unregister_netdev(ndev);
7083 /* Serdes power down needs to happen after VLAN filter
7084 * is deleted that is triggered by unregister_netdev().
7086 if (priv->plat->serdes_powerdown)
7087 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7089 #ifdef CONFIG_DEBUG_FS
7090 stmmac_exit_fs(ndev);
7092 phylink_destroy(priv->phylink);
7093 if (priv->plat->stmmac_rst)
7094 reset_control_assert(priv->plat->stmmac_rst);
7095 reset_control_assert(priv->plat->stmmac_ahb_rst);
7096 pm_runtime_put(dev);
7097 pm_runtime_disable(dev);
7098 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7099 priv->hw->pcs != STMMAC_PCS_RTBI)
7100 stmmac_mdio_unregister(ndev);
7101 destroy_workqueue(priv->wq);
7102 mutex_destroy(&priv->lock);
7103 bitmap_free(priv->af_xdp_zc_qps);
7107 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7110 * stmmac_suspend - suspend callback
7111 * @dev: device pointer
7112 * Description: this is the function to suspend the device and it is called
7113 * by the platform driver to stop the network queue, release the resources,
7114 * program the PMT register (for WoL), clean and release driver resources.
7116 int stmmac_suspend(struct device *dev)
7118 struct net_device *ndev = dev_get_drvdata(dev);
7119 struct stmmac_priv *priv = netdev_priv(ndev);
7123 if (!ndev || !netif_running(ndev))
7126 mutex_lock(&priv->lock);
7128 netif_device_detach(ndev);
7130 stmmac_disable_all_queues(priv);
7132 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7133 hrtimer_cancel(&priv->tx_queue[chan].txtimer);
7135 if (priv->eee_enabled) {
7136 priv->tx_path_in_lpi_mode = false;
7137 del_timer_sync(&priv->eee_ctrl_timer);
7140 /* Stop TX/RX DMA */
7141 stmmac_stop_all_dma(priv);
7143 if (priv->plat->serdes_powerdown)
7144 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7146 /* Enable Power down mode by programming the PMT regs */
7147 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7148 stmmac_pmt(priv, priv->hw, priv->wolopts);
7151 stmmac_mac_set(priv, priv->ioaddr, false);
7152 pinctrl_pm_select_sleep_state(priv->device);
7153 /* Disable clock in case of PWM is off */
7154 clk_disable_unprepare(priv->plat->clk_ptp_ref);
7155 ret = pm_runtime_force_suspend(dev);
7157 mutex_unlock(&priv->lock);
7162 mutex_unlock(&priv->lock);
7165 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7166 phylink_suspend(priv->phylink, true);
7168 if (device_may_wakeup(priv->device))
7169 phylink_speed_down(priv->phylink, false);
7170 phylink_suspend(priv->phylink, false);
7174 if (priv->dma_cap.fpesel) {
7176 stmmac_fpe_configure(priv, priv->ioaddr,
7177 priv->plat->tx_queues_to_use,
7178 priv->plat->rx_queues_to_use, false);
7180 stmmac_fpe_handshake(priv, false);
7181 stmmac_fpe_stop_wq(priv);
7184 priv->speed = SPEED_UNKNOWN;
7187 EXPORT_SYMBOL_GPL(stmmac_suspend);
7190 * stmmac_reset_queues_param - reset queue parameters
7191 * @priv: device pointer
7193 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7195 u32 rx_cnt = priv->plat->rx_queues_to_use;
7196 u32 tx_cnt = priv->plat->tx_queues_to_use;
7199 for (queue = 0; queue < rx_cnt; queue++) {
7200 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
7206 for (queue = 0; queue < tx_cnt; queue++) {
7207 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
7213 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7218 * stmmac_resume - resume callback
7219 * @dev: device pointer
7220 * Description: when resume this function is invoked to setup the DMA and CORE
7221 * in a usable state.
7223 int stmmac_resume(struct device *dev)
7225 struct net_device *ndev = dev_get_drvdata(dev);
7226 struct stmmac_priv *priv = netdev_priv(ndev);
7229 if (!netif_running(ndev))
7232 /* Power Down bit, into the PM register, is cleared
7233 * automatically as soon as a magic packet or a Wake-up frame
7234 * is received. Anyway, it's better to manually clear
7235 * this bit because it can generate problems while resuming
7236 * from another devices (e.g. serial console).
7238 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7239 mutex_lock(&priv->lock);
7240 stmmac_pmt(priv, priv->hw, 0);
7241 mutex_unlock(&priv->lock);
7244 pinctrl_pm_select_default_state(priv->device);
7245 /* enable the clk previously disabled */
7246 ret = pm_runtime_force_resume(dev);
7249 if (priv->plat->clk_ptp_ref)
7250 clk_prepare_enable(priv->plat->clk_ptp_ref);
7251 /* reset the phy so that it's ready */
7253 stmmac_mdio_reset(priv->mii);
7256 if (priv->plat->serdes_powerup) {
7257 ret = priv->plat->serdes_powerup(ndev,
7258 priv->plat->bsp_priv);
7265 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7266 phylink_resume(priv->phylink);
7268 phylink_resume(priv->phylink);
7269 if (device_may_wakeup(priv->device))
7270 phylink_speed_up(priv->phylink);
7275 mutex_lock(&priv->lock);
7277 stmmac_reset_queues_param(priv);
7279 stmmac_free_tx_skbufs(priv);
7280 stmmac_clear_descriptors(priv);
7282 stmmac_hw_setup(ndev, false);
7283 stmmac_init_coalesce(priv);
7284 stmmac_set_rx_mode(ndev);
7286 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7288 stmmac_enable_all_queues(priv);
7290 mutex_unlock(&priv->lock);
7293 netif_device_attach(ndev);
7297 EXPORT_SYMBOL_GPL(stmmac_resume);
7300 static int __init stmmac_cmdline_opt(char *str)
7306 while ((opt = strsep(&str, ",")) != NULL) {
7307 if (!strncmp(opt, "debug:", 6)) {
7308 if (kstrtoint(opt + 6, 0, &debug))
7310 } else if (!strncmp(opt, "phyaddr:", 8)) {
7311 if (kstrtoint(opt + 8, 0, &phyaddr))
7313 } else if (!strncmp(opt, "buf_sz:", 7)) {
7314 if (kstrtoint(opt + 7, 0, &buf_sz))
7316 } else if (!strncmp(opt, "tc:", 3)) {
7317 if (kstrtoint(opt + 3, 0, &tc))
7319 } else if (!strncmp(opt, "watchdog:", 9)) {
7320 if (kstrtoint(opt + 9, 0, &watchdog))
7322 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7323 if (kstrtoint(opt + 10, 0, &flow_ctrl))
7325 } else if (!strncmp(opt, "pause:", 6)) {
7326 if (kstrtoint(opt + 6, 0, &pause))
7328 } else if (!strncmp(opt, "eee_timer:", 10)) {
7329 if (kstrtoint(opt + 10, 0, &eee_timer))
7331 } else if (!strncmp(opt, "chain_mode:", 11)) {
7332 if (kstrtoint(opt + 11, 0, &chain_mode))
7339 pr_err("%s: ERROR broken module parameter conversion", __func__);
7343 __setup("stmmaceth=", stmmac_cmdline_opt);
7346 static int __init stmmac_init(void)
7348 #ifdef CONFIG_DEBUG_FS
7349 /* Create debugfs main directory if it doesn't exist yet */
7351 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7352 register_netdevice_notifier(&stmmac_notifier);
7358 static void __exit stmmac_exit(void)
7360 #ifdef CONFIG_DEBUG_FS
7361 unregister_netdevice_notifier(&stmmac_notifier);
7362 debugfs_remove_recursive(stmmac_fs_dir);
7366 module_init(stmmac_init)
7367 module_exit(stmmac_exit)
7369 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7370 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7371 MODULE_LICENSE("GPL");