1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/prefetch.h>
33 #include <linux/pinctrl/consumer.h>
34 #ifdef CONFIG_DEBUG_FS
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #endif /* CONFIG_DEBUG_FS */
38 #include <linux/net_tstamp.h>
39 #include <linux/phylink.h>
40 #include <linux/udp.h>
41 #include <linux/bpf_trace.h>
42 #include <net/pkt_cls.h>
43 #include <net/xdp_sock_drv.h>
44 #include "stmmac_ptp.h"
46 #include "stmmac_xdp.h"
47 #include <linux/reset.h>
48 #include <linux/of_mdio.h>
49 #include "dwmac1000.h"
53 /* As long as the interface is active, we keep the timestamping counter enabled
54 * with fine resolution and binary rollover. This avoid non-monotonic behavior
55 * (clock jumps) when changing timestamping settings at runtime.
57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
63 /* Module parameters */
65 static int watchdog = TX_TIMEO;
66 module_param(watchdog, int, 0644);
67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
69 static int debug = -1;
70 module_param(debug, int, 0644);
71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
73 static int phyaddr = -1;
74 module_param(phyaddr, int, 0444);
75 MODULE_PARM_DESC(phyaddr, "Physical device address");
77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4)
78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4)
80 /* Limit to make sure XDP TX and slow path can coexist */
81 #define STMMAC_XSK_TX_BUDGET_MAX 256
82 #define STMMAC_TX_XSK_AVAIL 16
83 #define STMMAC_RX_FILL_BATCH 16
85 #define STMMAC_XDP_PASS 0
86 #define STMMAC_XDP_CONSUMED BIT(0)
87 #define STMMAC_XDP_TX BIT(1)
88 #define STMMAC_XDP_REDIRECT BIT(2)
90 static int flow_ctrl = FLOW_AUTO;
91 module_param(flow_ctrl, int, 0644);
92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
94 static int pause = PAUSE_TIME;
95 module_param(pause, int, 0644);
96 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
99 static int tc = TC_DEFAULT;
100 module_param(tc, int, 0644);
101 MODULE_PARM_DESC(tc, "DMA threshold control value");
103 #define DEFAULT_BUFSIZE 1536
104 static int buf_sz = DEFAULT_BUFSIZE;
105 module_param(buf_sz, int, 0644);
106 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
108 #define STMMAC_RX_COPYBREAK 256
110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
111 NETIF_MSG_LINK | NETIF_MSG_IFUP |
112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
114 #define STMMAC_DEFAULT_LPI_TIMER 1000
115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
116 module_param(eee_timer, int, 0644);
117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
120 /* By default the driver will use the ring mode to manage tx and rx descriptors,
121 * but allow user to force to use the chain instead of the ring
123 static unsigned int chain_mode;
124 module_param(chain_mode, int, 0444);
125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
128 /* For MSI interrupts handling */
129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue);
134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue);
135 static void stmmac_reset_queues_param(struct stmmac_priv *priv);
136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
139 u32 rxmode, u32 chan);
141 #ifdef CONFIG_DEBUG_FS
142 static const struct net_device_ops stmmac_netdev_ops;
143 static void stmmac_init_fs(struct net_device *dev);
144 static void stmmac_exit_fs(struct net_device *dev);
147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
154 ret = clk_prepare_enable(priv->plat->stmmac_clk);
157 ret = clk_prepare_enable(priv->plat->pclk);
159 clk_disable_unprepare(priv->plat->stmmac_clk);
162 if (priv->plat->clks_config) {
163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
165 clk_disable_unprepare(priv->plat->stmmac_clk);
166 clk_disable_unprepare(priv->plat->pclk);
171 clk_disable_unprepare(priv->plat->stmmac_clk);
172 clk_disable_unprepare(priv->plat->pclk);
173 if (priv->plat->clks_config)
174 priv->plat->clks_config(priv->plat->bsp_priv, enabled);
179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
182 * stmmac_verify_args - verify the driver parameters.
183 * Description: it checks the driver parameters and set a default in case of
186 static void stmmac_verify_args(void)
188 if (unlikely(watchdog < 0))
190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
191 buf_sz = DEFAULT_BUFSIZE;
192 if (unlikely(flow_ctrl > 1))
193 flow_ctrl = FLOW_AUTO;
194 else if (likely(flow_ctrl < 0))
195 flow_ctrl = FLOW_OFF;
196 if (unlikely((pause < 0) || (pause > 0xffff)))
199 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
209 for (queue = 0; queue < maxq; queue++) {
210 struct stmmac_channel *ch = &priv->channel[queue];
212 if (stmmac_xdp_is_enabled(priv) &&
213 test_bit(queue, priv->af_xdp_zc_qps)) {
214 napi_disable(&ch->rxtx_napi);
218 if (queue < rx_queues_cnt)
219 napi_disable(&ch->rx_napi);
220 if (queue < tx_queues_cnt)
221 napi_disable(&ch->tx_napi);
226 * stmmac_disable_all_queues - Disable all queues
227 * @priv: driver private structure
229 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
232 struct stmmac_rx_queue *rx_q;
235 /* synchronize_rcu() needed for pending XDP buffers to drain */
236 for (queue = 0; queue < rx_queues_cnt; queue++) {
237 rx_q = &priv->dma_conf.rx_queue[queue];
238 if (rx_q->xsk_pool) {
244 __stmmac_disable_all_queues(priv);
248 * stmmac_enable_all_queues - Enable all queues
249 * @priv: driver private structure
251 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
258 for (queue = 0; queue < maxq; queue++) {
259 struct stmmac_channel *ch = &priv->channel[queue];
261 if (stmmac_xdp_is_enabled(priv) &&
262 test_bit(queue, priv->af_xdp_zc_qps)) {
263 napi_enable(&ch->rxtx_napi);
267 if (queue < rx_queues_cnt)
268 napi_enable(&ch->rx_napi);
269 if (queue < tx_queues_cnt)
270 napi_enable(&ch->tx_napi);
274 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
276 if (!test_bit(STMMAC_DOWN, &priv->state) &&
277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
278 queue_work(priv->wq, &priv->service_task);
281 static void stmmac_global_err(struct stmmac_priv *priv)
283 netif_carrier_off(priv->dev);
284 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
285 stmmac_service_event_schedule(priv);
289 * stmmac_clk_csr_set - dynamically set the MDC clock
290 * @priv: driver private structure
291 * Description: this is to dynamically set the MDC clock according to the csr
294 * If a specific clk_csr value is passed from the platform
295 * this means that the CSR Clock Range selection cannot be
296 * changed at run-time and it is fixed (as reported in the driver
297 * documentation). Viceversa the driver will try to set the MDC
298 * clock dynamically according to the actual clock input.
300 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
304 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
306 /* Platform provided default clk_csr would be assumed valid
307 * for all other cases except for the below mentioned ones.
308 * For values higher than the IEEE 802.3 specified frequency
309 * we can not estimate the proper divider as it is not known
310 * the frequency of clk_csr_i. So we do not change the default
313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
314 if (clk_rate < CSR_F_35M)
315 priv->clk_csr = STMMAC_CSR_20_35M;
316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
317 priv->clk_csr = STMMAC_CSR_35_60M;
318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
319 priv->clk_csr = STMMAC_CSR_60_100M;
320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
321 priv->clk_csr = STMMAC_CSR_100_150M;
322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
323 priv->clk_csr = STMMAC_CSR_150_250M;
324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
325 priv->clk_csr = STMMAC_CSR_250_300M;
328 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
329 if (clk_rate > 160000000)
330 priv->clk_csr = 0x03;
331 else if (clk_rate > 80000000)
332 priv->clk_csr = 0x02;
333 else if (clk_rate > 40000000)
334 priv->clk_csr = 0x01;
339 if (priv->plat->has_xgmac) {
340 if (clk_rate > 400000000)
342 else if (clk_rate > 350000000)
344 else if (clk_rate > 300000000)
346 else if (clk_rate > 250000000)
348 else if (clk_rate > 150000000)
355 static void print_pkt(unsigned char *buf, int len)
357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
366 if (tx_q->dirty_tx > tx_q->cur_tx)
367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
375 * stmmac_rx_dirty - Get RX queue dirty
376 * @priv: driver private structure
377 * @queue: RX queue index
379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
384 if (rx_q->dirty_rx <= rx_q->cur_rx)
385 dirty = rx_q->cur_rx - rx_q->dirty_rx;
387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */
397 priv->eee_sw_timer_en = en ? 0 : 1;
398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0;
399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
403 * stmmac_enable_eee_mode - check and enter in LPI mode
404 * @priv: driver private structure
405 * Description: this function is to verify and enter in LPI mode in case of
408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
410 u32 tx_cnt = priv->plat->tx_queues_to_use;
413 /* check if all TX queues have the work finished */
414 for (queue = 0; queue < tx_cnt; queue++) {
415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
417 if (tx_q->dirty_tx != tx_q->cur_tx)
418 return -EBUSY; /* still unfinished work */
421 /* Check and enter in LPI mode */
422 if (!priv->tx_path_in_lpi_mode)
423 stmmac_set_eee_mode(priv, priv->hw,
424 priv->plat->en_tx_lpi_clockgating);
429 * stmmac_disable_eee_mode - disable and exit from LPI mode
430 * @priv: driver private structure
431 * Description: this function is to exit and disable EEE in case of
432 * LPI state is true. This is called by the xmit.
434 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
436 if (!priv->eee_sw_timer_en) {
437 stmmac_lpi_entry_timer_config(priv, 0);
441 stmmac_reset_eee_mode(priv, priv->hw);
442 del_timer_sync(&priv->eee_ctrl_timer);
443 priv->tx_path_in_lpi_mode = false;
447 * stmmac_eee_ctrl_timer - EEE TX SW timer.
448 * @t: timer_list struct containing private info
450 * if there is no data transfer and if we are not in LPI state,
451 * then MAC Transmitter can be moved to LPI state.
453 static void stmmac_eee_ctrl_timer(struct timer_list *t)
455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
457 if (stmmac_enable_eee_mode(priv))
458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
462 * stmmac_eee_init - init EEE
463 * @priv: driver private structure
465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
466 * can also manage EEE, this function enable the LPI state and start related
469 bool stmmac_eee_init(struct stmmac_priv *priv)
471 int eee_tw_timer = priv->eee_tw_timer;
473 /* Using PCS we cannot dial with the phy registers at this stage
474 * so we do not support extra feature like EEE.
476 if (priv->hw->pcs == STMMAC_PCS_TBI ||
477 priv->hw->pcs == STMMAC_PCS_RTBI)
480 /* Check if MAC core supports the EEE feature. */
481 if (!priv->dma_cap.eee)
484 mutex_lock(&priv->lock);
486 /* Check if it needs to be deactivated */
487 if (!priv->eee_active) {
488 if (priv->eee_enabled) {
489 netdev_dbg(priv->dev, "disable EEE\n");
490 stmmac_lpi_entry_timer_config(priv, 0);
491 del_timer_sync(&priv->eee_ctrl_timer);
492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
494 xpcs_config_eee(priv->hw->xpcs,
495 priv->plat->mult_fact_100ns,
498 mutex_unlock(&priv->lock);
502 if (priv->eee_active && !priv->eee_enabled) {
503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
507 xpcs_config_eee(priv->hw->xpcs,
508 priv->plat->mult_fact_100ns,
512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
513 del_timer_sync(&priv->eee_ctrl_timer);
514 priv->tx_path_in_lpi_mode = false;
515 stmmac_lpi_entry_timer_config(priv, 1);
517 stmmac_lpi_entry_timer_config(priv, 0);
518 mod_timer(&priv->eee_ctrl_timer,
519 STMMAC_LPI_T(priv->tx_lpi_timer));
522 mutex_unlock(&priv->lock);
523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
528 * @priv: driver private structure
529 * @p : descriptor pointer
530 * @skb : the socket buffer
532 * This function will read timestamp from the descriptor & pass it to stack.
533 * and also perform some sanity checks.
535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
536 struct dma_desc *p, struct sk_buff *skb)
538 struct skb_shared_hwtstamps shhwtstamp;
542 if (!priv->hwts_tx_en)
545 /* exit if skb doesn't support hw tstamp */
546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
549 /* check tx tstamp status */
550 if (stmmac_get_tx_timestamp_status(priv, p)) {
551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
558 ns -= priv->plat->cdc_error_adj;
560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
561 shhwtstamp.hwtstamp = ns_to_ktime(ns);
563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
564 /* pass tstamp to stack */
565 skb_tstamp_tx(skb, &shhwtstamp);
569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
570 * @priv: driver private structure
571 * @p : descriptor pointer
572 * @np : next descriptor pointer
573 * @skb : the socket buffer
575 * This function will read received packet's timestamp from the descriptor
576 * and pass it to stack. It also perform some sanity checks.
578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
579 struct dma_desc *np, struct sk_buff *skb)
581 struct skb_shared_hwtstamps *shhwtstamp = NULL;
582 struct dma_desc *desc = p;
585 if (!priv->hwts_rx_en)
587 /* For GMAC4, the valid timestamp is from CTX next desc. */
588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
591 /* Check if timestamp is available */
592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
595 ns -= priv->plat->cdc_error_adj;
597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
598 shhwtstamp = skb_hwtstamps(skb);
599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
600 shhwtstamp->hwtstamp = ns_to_ktime(ns);
602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
607 * stmmac_hwtstamp_set - control hardware timestamping.
608 * @dev: device pointer.
609 * @ifr: An IOCTL specific structure, that can contain a pointer to
610 * a proprietary structure used to pass information to the driver.
612 * This function configures the MAC to enable/disable both outgoing(TX)
613 * and incoming(RX) packets time stamping based on user input.
615 * 0 on success and an appropriate -ve integer on failure.
617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
619 struct stmmac_priv *priv = netdev_priv(dev);
620 struct hwtstamp_config config;
623 u32 ptp_over_ipv4_udp = 0;
624 u32 ptp_over_ipv6_udp = 0;
625 u32 ptp_over_ethernet = 0;
626 u32 snap_type_sel = 0;
627 u32 ts_master_en = 0;
630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
631 netdev_alert(priv->dev, "No support for HW time stamping\n");
632 priv->hwts_tx_en = 0;
633 priv->hwts_rx_en = 0;
638 if (copy_from_user(&config, ifr->ifr_data,
642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
643 __func__, config.flags, config.tx_type, config.rx_filter);
645 if (config.tx_type != HWTSTAMP_TX_OFF &&
646 config.tx_type != HWTSTAMP_TX_ON)
650 switch (config.rx_filter) {
651 case HWTSTAMP_FILTER_NONE:
652 /* time stamp no incoming packet at all */
653 config.rx_filter = HWTSTAMP_FILTER_NONE;
656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
657 /* PTP v1, UDP, any kind of event packet */
658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
659 /* 'xmac' hardware can support Sync, Pdelay_Req and
660 * Pdelay_resp by setting bit14 and bits17/16 to 01
661 * This leaves Delay_Req timestamps out.
662 * Enable all events *and* general purpose message
665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
671 /* PTP v1, UDP, Sync packet */
672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
673 /* take time stamp for SYNC messages only */
674 ts_event_en = PTP_TCR_TSEVNTENA;
676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
681 /* PTP v1, UDP, Delay_req packet */
682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
683 /* take time stamp for Delay_Req messages only */
684 ts_master_en = PTP_TCR_TSMSTRENA;
685 ts_event_en = PTP_TCR_TSEVNTENA;
687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
692 /* PTP v2, UDP, any kind of event packet */
693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
694 ptp_v2 = PTP_TCR_TSVER2ENA;
695 /* take time stamp for all event messages */
696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
703 /* PTP v2, UDP, Sync packet */
704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
705 ptp_v2 = PTP_TCR_TSVER2ENA;
706 /* take time stamp for SYNC messages only */
707 ts_event_en = PTP_TCR_TSEVNTENA;
709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
714 /* PTP v2, UDP, Delay_req packet */
715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
716 ptp_v2 = PTP_TCR_TSVER2ENA;
717 /* take time stamp for Delay_Req messages only */
718 ts_master_en = PTP_TCR_TSMSTRENA;
719 ts_event_en = PTP_TCR_TSEVNTENA;
721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
725 case HWTSTAMP_FILTER_PTP_V2_EVENT:
726 /* PTP v2/802.AS1 any layer, any kind of event packet */
727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
728 ptp_v2 = PTP_TCR_TSVER2ENA;
729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
730 if (priv->synopsys_id < DWMAC_CORE_4_10)
731 ts_event_en = PTP_TCR_TSEVNTENA;
732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
734 ptp_over_ethernet = PTP_TCR_TSIPENA;
737 case HWTSTAMP_FILTER_PTP_V2_SYNC:
738 /* PTP v2/802.AS1, any layer, Sync packet */
739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
740 ptp_v2 = PTP_TCR_TSVER2ENA;
741 /* take time stamp for SYNC messages only */
742 ts_event_en = PTP_TCR_TSEVNTENA;
744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
746 ptp_over_ethernet = PTP_TCR_TSIPENA;
749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
750 /* PTP v2/802.AS1, any layer, Delay_req packet */
751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
752 ptp_v2 = PTP_TCR_TSVER2ENA;
753 /* take time stamp for Delay_Req messages only */
754 ts_master_en = PTP_TCR_TSMSTRENA;
755 ts_event_en = PTP_TCR_TSEVNTENA;
757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
759 ptp_over_ethernet = PTP_TCR_TSIPENA;
762 case HWTSTAMP_FILTER_NTP_ALL:
763 case HWTSTAMP_FILTER_ALL:
764 /* time stamp any incoming packet */
765 config.rx_filter = HWTSTAMP_FILTER_ALL;
766 tstamp_all = PTP_TCR_TSENALL;
773 switch (config.rx_filter) {
774 case HWTSTAMP_FILTER_NONE:
775 config.rx_filter = HWTSTAMP_FILTER_NONE;
778 /* PTP v1, UDP, any kind of event packet */
779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
786 priv->systime_flags = STMMAC_HWTS_ACTIVE;
788 if (priv->hwts_tx_en || priv->hwts_rx_en) {
789 priv->systime_flags |= tstamp_all | ptp_v2 |
790 ptp_over_ethernet | ptp_over_ipv6_udp |
791 ptp_over_ipv4_udp | ts_event_en |
792 ts_master_en | snap_type_sel;
795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
797 memcpy(&priv->tstamp_config, &config, sizeof(config));
799 return copy_to_user(ifr->ifr_data, &config,
800 sizeof(config)) ? -EFAULT : 0;
804 * stmmac_hwtstamp_get - read hardware timestamping.
805 * @dev: device pointer.
806 * @ifr: An IOCTL specific structure, that can contain a pointer to
807 * a proprietary structure used to pass information to the driver.
809 * This function obtain the current hardware timestamping settings
812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
814 struct stmmac_priv *priv = netdev_priv(dev);
815 struct hwtstamp_config *config = &priv->tstamp_config;
817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
820 return copy_to_user(ifr->ifr_data, config,
821 sizeof(*config)) ? -EFAULT : 0;
825 * stmmac_init_tstamp_counter - init hardware timestamping counter
826 * @priv: driver private structure
827 * @systime_flags: timestamping flags
829 * Initialize hardware counter for packet timestamping.
830 * This is valid as long as the interface is open and not suspended.
831 * Will be rerun after resuming from suspend, case in which the timestamping
832 * flags updated by stmmac_hwtstamp_set() also need to be restored.
834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
837 struct timespec64 now;
841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
845 priv->systime_flags = systime_flags;
847 /* program Sub Second Increment reg */
848 stmmac_config_sub_second_increment(priv, priv->ptpaddr,
849 priv->plat->clk_ptp_rate,
851 temp = div_u64(1000000000ULL, sec_inc);
853 /* Store sub second increment for later use */
854 priv->sub_second_inc = sec_inc;
856 /* calculate default added value:
858 * addend = (2^32)/freq_div_ratio;
859 * where, freq_div_ratio = 1e9ns/sec_inc
861 temp = (u64)(temp << 32);
862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
865 /* initialize system time */
866 ktime_get_real_ts64(&now);
868 /* lower 32 bits of tv_sec are safe until y2106 */
869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
876 * stmmac_init_ptp - init PTP
877 * @priv: driver private structure
878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
879 * This is done by looking at the HW cap. register.
880 * This function also registers the ptp driver.
882 static int stmmac_init_ptp(struct stmmac_priv *priv)
884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
887 if (priv->plat->ptp_clk_freq_config)
888 priv->plat->ptp_clk_freq_config(priv);
890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
896 if (xmac && priv->dma_cap.atime_stamp)
898 /* Dwmac 3.x core with extend_desc can support adv_ts */
899 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
902 if (priv->dma_cap.time_stamp)
903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
906 netdev_info(priv->dev,
907 "IEEE 1588-2008 Advanced Timestamp supported\n");
909 priv->hwts_tx_en = 0;
910 priv->hwts_rx_en = 0;
915 static void stmmac_release_ptp(struct stmmac_priv *priv)
917 clk_disable_unprepare(priv->plat->clk_ptp_ref);
918 stmmac_ptp_unregister(priv);
922 * stmmac_mac_flow_ctrl - Configure flow control in all queues
923 * @priv: driver private structure
924 * @duplex: duplex passed to the next function
925 * Description: It is used for configuring the flow control in all queues
927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
929 u32 tx_cnt = priv->plat->tx_queues_to_use;
931 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
932 priv->pause, tx_cnt);
935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
936 phy_interface_t interface)
938 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
941 return &priv->hw->xpcs->pcs;
943 if (priv->hw->lynx_pcs)
944 return priv->hw->lynx_pcs;
949 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
950 const struct phylink_link_state *state)
952 /* Nothing to do, xpcs_config() handles everything */
955 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
957 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
958 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
959 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
960 bool *hs_enable = &fpe_cfg->hs_enable;
962 if (is_up && *hs_enable) {
963 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
965 *lo_state = FPE_STATE_OFF;
966 *lp_state = FPE_STATE_OFF;
970 static void stmmac_mac_link_down(struct phylink_config *config,
971 unsigned int mode, phy_interface_t interface)
973 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
975 stmmac_mac_set(priv, priv->ioaddr, false);
976 priv->eee_active = false;
977 priv->tx_lpi_enabled = false;
978 priv->eee_enabled = stmmac_eee_init(priv);
979 stmmac_set_eee_pls(priv, priv->hw, false);
981 if (priv->dma_cap.fpesel)
982 stmmac_fpe_link_state_handle(priv, false);
985 static void stmmac_mac_link_up(struct phylink_config *config,
986 struct phy_device *phy,
987 unsigned int mode, phy_interface_t interface,
988 int speed, int duplex,
989 bool tx_pause, bool rx_pause)
991 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
994 if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
995 priv->plat->serdes_powerup)
996 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv);
998 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
999 ctrl = old_ctrl & ~priv->hw->link.speed_mask;
1001 if (interface == PHY_INTERFACE_MODE_USXGMII) {
1004 ctrl |= priv->hw->link.xgmii.speed10000;
1007 ctrl |= priv->hw->link.xgmii.speed5000;
1010 ctrl |= priv->hw->link.xgmii.speed2500;
1015 } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1018 ctrl |= priv->hw->link.xlgmii.speed100000;
1021 ctrl |= priv->hw->link.xlgmii.speed50000;
1024 ctrl |= priv->hw->link.xlgmii.speed40000;
1027 ctrl |= priv->hw->link.xlgmii.speed25000;
1030 ctrl |= priv->hw->link.xgmii.speed10000;
1033 ctrl |= priv->hw->link.speed2500;
1036 ctrl |= priv->hw->link.speed1000;
1044 ctrl |= priv->hw->link.speed2500;
1047 ctrl |= priv->hw->link.speed1000;
1050 ctrl |= priv->hw->link.speed100;
1053 ctrl |= priv->hw->link.speed10;
1060 priv->speed = speed;
1062 if (priv->plat->fix_mac_speed)
1063 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1066 ctrl &= ~priv->hw->link.duplex;
1068 ctrl |= priv->hw->link.duplex;
1070 /* Flow Control operation */
1071 if (rx_pause && tx_pause)
1072 priv->flow_ctrl = FLOW_AUTO;
1073 else if (rx_pause && !tx_pause)
1074 priv->flow_ctrl = FLOW_RX;
1075 else if (!rx_pause && tx_pause)
1076 priv->flow_ctrl = FLOW_TX;
1078 priv->flow_ctrl = FLOW_OFF;
1080 stmmac_mac_flow_ctrl(priv, duplex);
1082 if (ctrl != old_ctrl)
1083 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1085 stmmac_mac_set(priv, priv->ioaddr, true);
1086 if (phy && priv->dma_cap.eee) {
1088 phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0;
1089 priv->eee_enabled = stmmac_eee_init(priv);
1090 priv->tx_lpi_enabled = priv->eee_enabled;
1091 stmmac_set_eee_pls(priv, priv->hw, true);
1094 if (priv->dma_cap.fpesel)
1095 stmmac_fpe_link_state_handle(priv, true);
1098 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1099 .mac_select_pcs = stmmac_mac_select_pcs,
1100 .mac_config = stmmac_mac_config,
1101 .mac_link_down = stmmac_mac_link_down,
1102 .mac_link_up = stmmac_mac_link_up,
1106 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1107 * @priv: driver private structure
1108 * Description: this is to verify if the HW supports the PCS.
1109 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1110 * configured for the TBI, RTBI, or SGMII PHY interface.
1112 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1114 int interface = priv->plat->interface;
1116 if (priv->dma_cap.pcs) {
1117 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1118 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1119 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1120 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1121 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1122 priv->hw->pcs = STMMAC_PCS_RGMII;
1123 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1124 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1125 priv->hw->pcs = STMMAC_PCS_SGMII;
1131 * stmmac_init_phy - PHY initialization
1132 * @dev: net device structure
1133 * Description: it initializes the driver's PHY state, and attaches the PHY
1134 * to the mac driver.
1138 static int stmmac_init_phy(struct net_device *dev)
1140 struct stmmac_priv *priv = netdev_priv(dev);
1141 struct fwnode_handle *phy_fwnode;
1142 struct fwnode_handle *fwnode;
1145 if (!phylink_expects_phy(priv->phylink))
1148 fwnode = of_fwnode_handle(priv->plat->phylink_node);
1150 fwnode = dev_fwnode(priv->device);
1153 phy_fwnode = fwnode_get_phy_node(fwnode);
1157 /* Some DT bindings do not set-up the PHY handle. Let's try to
1160 if (!phy_fwnode || IS_ERR(phy_fwnode)) {
1161 int addr = priv->plat->phy_addr;
1162 struct phy_device *phydev;
1165 netdev_err(priv->dev, "no phy found\n");
1169 phydev = mdiobus_get_phy(priv->mii, addr);
1171 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1175 ret = phylink_connect_phy(priv->phylink, phydev);
1177 fwnode_handle_put(phy_fwnode);
1178 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
1181 if (!priv->plat->pmt) {
1182 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1184 phylink_ethtool_get_wol(priv->phylink, &wol);
1185 device_set_wakeup_capable(priv->device, !!wol.supported);
1186 device_set_wakeup_enable(priv->device, !!wol.wolopts);
1192 static int stmmac_phy_setup(struct stmmac_priv *priv)
1194 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1195 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1196 int max_speed = priv->plat->max_speed;
1197 int mode = priv->plat->phy_interface;
1198 struct phylink *phylink;
1200 priv->phylink_config.dev = &priv->dev->dev;
1201 priv->phylink_config.type = PHYLINK_NETDEV;
1202 if (priv->plat->mdio_bus_data)
1203 priv->phylink_config.ovr_an_inband =
1204 mdio_bus_data->xpcs_an_inband;
1207 fwnode = dev_fwnode(priv->device);
1209 /* Set the platform/firmware specified interface mode */
1210 __set_bit(mode, priv->phylink_config.supported_interfaces);
1212 /* If we have an xpcs, it defines which PHY interfaces are supported. */
1214 xpcs_get_interfaces(priv->hw->xpcs,
1215 priv->phylink_config.supported_interfaces);
1217 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1220 if (!max_speed || max_speed >= 1000)
1221 priv->phylink_config.mac_capabilities |= MAC_1000;
1223 if (priv->plat->has_gmac4) {
1224 if (!max_speed || max_speed >= 2500)
1225 priv->phylink_config.mac_capabilities |= MAC_2500FD;
1226 } else if (priv->plat->has_xgmac) {
1227 if (!max_speed || max_speed >= 2500)
1228 priv->phylink_config.mac_capabilities |= MAC_2500FD;
1229 if (!max_speed || max_speed >= 5000)
1230 priv->phylink_config.mac_capabilities |= MAC_5000FD;
1231 if (!max_speed || max_speed >= 10000)
1232 priv->phylink_config.mac_capabilities |= MAC_10000FD;
1233 if (!max_speed || max_speed >= 25000)
1234 priv->phylink_config.mac_capabilities |= MAC_25000FD;
1235 if (!max_speed || max_speed >= 40000)
1236 priv->phylink_config.mac_capabilities |= MAC_40000FD;
1237 if (!max_speed || max_speed >= 50000)
1238 priv->phylink_config.mac_capabilities |= MAC_50000FD;
1239 if (!max_speed || max_speed >= 100000)
1240 priv->phylink_config.mac_capabilities |= MAC_100000FD;
1243 /* Half-Duplex can only work with single queue */
1244 if (priv->plat->tx_queues_to_use > 1)
1245 priv->phylink_config.mac_capabilities &=
1246 ~(MAC_10HD | MAC_100HD | MAC_1000HD);
1247 priv->phylink_config.mac_managed_pm = true;
1249 phylink = phylink_create(&priv->phylink_config, fwnode,
1250 mode, &stmmac_phylink_mac_ops);
1251 if (IS_ERR(phylink))
1252 return PTR_ERR(phylink);
1254 priv->phylink = phylink;
1258 static void stmmac_display_rx_rings(struct stmmac_priv *priv,
1259 struct stmmac_dma_conf *dma_conf)
1261 u32 rx_cnt = priv->plat->rx_queues_to_use;
1262 unsigned int desc_size;
1266 /* Display RX rings */
1267 for (queue = 0; queue < rx_cnt; queue++) {
1268 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1270 pr_info("\tRX Queue %u rings\n", queue);
1272 if (priv->extend_desc) {
1273 head_rx = (void *)rx_q->dma_erx;
1274 desc_size = sizeof(struct dma_extended_desc);
1276 head_rx = (void *)rx_q->dma_rx;
1277 desc_size = sizeof(struct dma_desc);
1280 /* Display RX ring */
1281 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true,
1282 rx_q->dma_rx_phy, desc_size);
1286 static void stmmac_display_tx_rings(struct stmmac_priv *priv,
1287 struct stmmac_dma_conf *dma_conf)
1289 u32 tx_cnt = priv->plat->tx_queues_to_use;
1290 unsigned int desc_size;
1294 /* Display TX rings */
1295 for (queue = 0; queue < tx_cnt; queue++) {
1296 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1298 pr_info("\tTX Queue %d rings\n", queue);
1300 if (priv->extend_desc) {
1301 head_tx = (void *)tx_q->dma_etx;
1302 desc_size = sizeof(struct dma_extended_desc);
1303 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1304 head_tx = (void *)tx_q->dma_entx;
1305 desc_size = sizeof(struct dma_edesc);
1307 head_tx = (void *)tx_q->dma_tx;
1308 desc_size = sizeof(struct dma_desc);
1311 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false,
1312 tx_q->dma_tx_phy, desc_size);
1316 static void stmmac_display_rings(struct stmmac_priv *priv,
1317 struct stmmac_dma_conf *dma_conf)
1319 /* Display RX ring */
1320 stmmac_display_rx_rings(priv, dma_conf);
1322 /* Display TX ring */
1323 stmmac_display_tx_rings(priv, dma_conf);
1326 static int stmmac_set_bfsize(int mtu, int bufsize)
1330 if (mtu >= BUF_SIZE_8KiB)
1331 ret = BUF_SIZE_16KiB;
1332 else if (mtu >= BUF_SIZE_4KiB)
1333 ret = BUF_SIZE_8KiB;
1334 else if (mtu >= BUF_SIZE_2KiB)
1335 ret = BUF_SIZE_4KiB;
1336 else if (mtu > DEFAULT_BUFSIZE)
1337 ret = BUF_SIZE_2KiB;
1339 ret = DEFAULT_BUFSIZE;
1345 * stmmac_clear_rx_descriptors - clear RX descriptors
1346 * @priv: driver private structure
1347 * @dma_conf: structure to take the dma data
1348 * @queue: RX queue index
1349 * Description: this function is called to clear the RX descriptors
1350 * in case of both basic and extended descriptors are used.
1352 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv,
1353 struct stmmac_dma_conf *dma_conf,
1356 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1359 /* Clear the RX descriptors */
1360 for (i = 0; i < dma_conf->dma_rx_size; i++)
1361 if (priv->extend_desc)
1362 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1363 priv->use_riwt, priv->mode,
1364 (i == dma_conf->dma_rx_size - 1),
1365 dma_conf->dma_buf_sz);
1367 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1368 priv->use_riwt, priv->mode,
1369 (i == dma_conf->dma_rx_size - 1),
1370 dma_conf->dma_buf_sz);
1374 * stmmac_clear_tx_descriptors - clear tx descriptors
1375 * @priv: driver private structure
1376 * @dma_conf: structure to take the dma data
1377 * @queue: TX queue index.
1378 * Description: this function is called to clear the TX descriptors
1379 * in case of both basic and extended descriptors are used.
1381 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv,
1382 struct stmmac_dma_conf *dma_conf,
1385 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1388 /* Clear the TX descriptors */
1389 for (i = 0; i < dma_conf->dma_tx_size; i++) {
1390 int last = (i == (dma_conf->dma_tx_size - 1));
1393 if (priv->extend_desc)
1394 p = &tx_q->dma_etx[i].basic;
1395 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1396 p = &tx_q->dma_entx[i].basic;
1398 p = &tx_q->dma_tx[i];
1400 stmmac_init_tx_desc(priv, p, priv->mode, last);
1405 * stmmac_clear_descriptors - clear descriptors
1406 * @priv: driver private structure
1407 * @dma_conf: structure to take the dma data
1408 * Description: this function is called to clear the TX and RX descriptors
1409 * in case of both basic and extended descriptors are used.
1411 static void stmmac_clear_descriptors(struct stmmac_priv *priv,
1412 struct stmmac_dma_conf *dma_conf)
1414 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1415 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1418 /* Clear the RX descriptors */
1419 for (queue = 0; queue < rx_queue_cnt; queue++)
1420 stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1422 /* Clear the TX descriptors */
1423 for (queue = 0; queue < tx_queue_cnt; queue++)
1424 stmmac_clear_tx_descriptors(priv, dma_conf, queue);
1428 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1429 * @priv: driver private structure
1430 * @dma_conf: structure to take the dma data
1431 * @p: descriptor pointer
1432 * @i: descriptor index
1434 * @queue: RX queue index
1435 * Description: this function is called to allocate a receive buffer, perform
1436 * the DMA mapping and init the descriptor.
1438 static int stmmac_init_rx_buffers(struct stmmac_priv *priv,
1439 struct stmmac_dma_conf *dma_conf,
1441 int i, gfp_t flags, u32 queue)
1443 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1444 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1445 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1447 if (priv->dma_cap.host_dma_width <= 32)
1451 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1454 buf->page_offset = stmmac_rx_offset(priv);
1457 if (priv->sph && !buf->sec_page) {
1458 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1462 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1463 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1465 buf->sec_page = NULL;
1466 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1469 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1471 stmmac_set_desc_addr(priv, p, buf->addr);
1472 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB)
1473 stmmac_init_desc3(priv, p);
1479 * stmmac_free_rx_buffer - free RX dma buffers
1480 * @priv: private structure
1484 static void stmmac_free_rx_buffer(struct stmmac_priv *priv,
1485 struct stmmac_rx_queue *rx_q,
1488 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1491 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1495 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1496 buf->sec_page = NULL;
1500 * stmmac_free_tx_buffer - free RX dma buffers
1501 * @priv: private structure
1502 * @dma_conf: structure to take the dma data
1503 * @queue: RX queue index
1506 static void stmmac_free_tx_buffer(struct stmmac_priv *priv,
1507 struct stmmac_dma_conf *dma_conf,
1510 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1512 if (tx_q->tx_skbuff_dma[i].buf &&
1513 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1514 if (tx_q->tx_skbuff_dma[i].map_as_page)
1515 dma_unmap_page(priv->device,
1516 tx_q->tx_skbuff_dma[i].buf,
1517 tx_q->tx_skbuff_dma[i].len,
1520 dma_unmap_single(priv->device,
1521 tx_q->tx_skbuff_dma[i].buf,
1522 tx_q->tx_skbuff_dma[i].len,
1526 if (tx_q->xdpf[i] &&
1527 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1528 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1529 xdp_return_frame(tx_q->xdpf[i]);
1530 tx_q->xdpf[i] = NULL;
1533 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1534 tx_q->xsk_frames_done++;
1536 if (tx_q->tx_skbuff[i] &&
1537 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1538 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1539 tx_q->tx_skbuff[i] = NULL;
1542 tx_q->tx_skbuff_dma[i].buf = 0;
1543 tx_q->tx_skbuff_dma[i].map_as_page = false;
1547 * dma_free_rx_skbufs - free RX dma buffers
1548 * @priv: private structure
1549 * @dma_conf: structure to take the dma data
1550 * @queue: RX queue index
1552 static void dma_free_rx_skbufs(struct stmmac_priv *priv,
1553 struct stmmac_dma_conf *dma_conf,
1556 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1559 for (i = 0; i < dma_conf->dma_rx_size; i++)
1560 stmmac_free_rx_buffer(priv, rx_q, i);
1563 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv,
1564 struct stmmac_dma_conf *dma_conf,
1565 u32 queue, gfp_t flags)
1567 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1570 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1574 if (priv->extend_desc)
1575 p = &((rx_q->dma_erx + i)->basic);
1577 p = rx_q->dma_rx + i;
1579 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags,
1584 rx_q->buf_alloc_num++;
1591 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1592 * @priv: private structure
1593 * @dma_conf: structure to take the dma data
1594 * @queue: RX queue index
1596 static void dma_free_rx_xskbufs(struct stmmac_priv *priv,
1597 struct stmmac_dma_conf *dma_conf,
1600 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1603 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1604 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1609 xsk_buff_free(buf->xdp);
1614 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv,
1615 struct stmmac_dma_conf *dma_conf,
1618 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1621 /* struct stmmac_xdp_buff is using cb field (maximum size of 24 bytes)
1622 * in struct xdp_buff_xsk to stash driver specific information. Thus,
1623 * use this macro to make sure no size violations.
1625 XSK_CHECK_PRIV_TYPE(struct stmmac_xdp_buff);
1627 for (i = 0; i < dma_conf->dma_rx_size; i++) {
1628 struct stmmac_rx_buffer *buf;
1629 dma_addr_t dma_addr;
1632 if (priv->extend_desc)
1633 p = (struct dma_desc *)(rx_q->dma_erx + i);
1635 p = rx_q->dma_rx + i;
1637 buf = &rx_q->buf_pool[i];
1639 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1643 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1644 stmmac_set_desc_addr(priv, p, dma_addr);
1645 rx_q->buf_alloc_num++;
1651 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1653 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1656 return xsk_get_pool_from_qid(priv->dev, queue);
1660 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1661 * @priv: driver private structure
1662 * @dma_conf: structure to take the dma data
1663 * @queue: RX queue index
1665 * Description: this function initializes the DMA RX descriptors
1666 * and allocates the socket buffers. It supports the chained and ring
1669 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv,
1670 struct stmmac_dma_conf *dma_conf,
1671 u32 queue, gfp_t flags)
1673 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1676 netif_dbg(priv, probe, priv->dev,
1677 "(%s) dma_rx_phy=0x%08x\n", __func__,
1678 (u32)rx_q->dma_rx_phy);
1680 stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1682 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1684 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1686 if (rx_q->xsk_pool) {
1687 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1688 MEM_TYPE_XSK_BUFF_POOL,
1690 netdev_info(priv->dev,
1691 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1693 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1695 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1698 netdev_info(priv->dev,
1699 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1703 if (rx_q->xsk_pool) {
1704 /* RX XDP ZC buffer pool may not be populated, e.g.
1707 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue);
1709 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags);
1714 /* Setup the chained descriptor addresses */
1715 if (priv->mode == STMMAC_CHAIN_MODE) {
1716 if (priv->extend_desc)
1717 stmmac_mode_init(priv, rx_q->dma_erx,
1719 dma_conf->dma_rx_size, 1);
1721 stmmac_mode_init(priv, rx_q->dma_rx,
1723 dma_conf->dma_rx_size, 0);
1729 static int init_dma_rx_desc_rings(struct net_device *dev,
1730 struct stmmac_dma_conf *dma_conf,
1733 struct stmmac_priv *priv = netdev_priv(dev);
1734 u32 rx_count = priv->plat->rx_queues_to_use;
1738 /* RX INITIALIZATION */
1739 netif_dbg(priv, probe, priv->dev,
1740 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1742 for (queue = 0; queue < rx_count; queue++) {
1743 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags);
1745 goto err_init_rx_buffers;
1750 err_init_rx_buffers:
1751 while (queue >= 0) {
1752 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1755 dma_free_rx_xskbufs(priv, dma_conf, queue);
1757 dma_free_rx_skbufs(priv, dma_conf, queue);
1759 rx_q->buf_alloc_num = 0;
1760 rx_q->xsk_pool = NULL;
1769 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1770 * @priv: driver private structure
1771 * @dma_conf: structure to take the dma data
1772 * @queue: TX queue index
1773 * Description: this function initializes the DMA TX descriptors
1774 * and allocates the socket buffers. It supports the chained and ring
1777 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv,
1778 struct stmmac_dma_conf *dma_conf,
1781 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1784 netif_dbg(priv, probe, priv->dev,
1785 "(%s) dma_tx_phy=0x%08x\n", __func__,
1786 (u32)tx_q->dma_tx_phy);
1788 /* Setup the chained descriptor addresses */
1789 if (priv->mode == STMMAC_CHAIN_MODE) {
1790 if (priv->extend_desc)
1791 stmmac_mode_init(priv, tx_q->dma_etx,
1793 dma_conf->dma_tx_size, 1);
1794 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1795 stmmac_mode_init(priv, tx_q->dma_tx,
1797 dma_conf->dma_tx_size, 0);
1800 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1802 for (i = 0; i < dma_conf->dma_tx_size; i++) {
1805 if (priv->extend_desc)
1806 p = &((tx_q->dma_etx + i)->basic);
1807 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1808 p = &((tx_q->dma_entx + i)->basic);
1810 p = tx_q->dma_tx + i;
1812 stmmac_clear_desc(priv, p);
1814 tx_q->tx_skbuff_dma[i].buf = 0;
1815 tx_q->tx_skbuff_dma[i].map_as_page = false;
1816 tx_q->tx_skbuff_dma[i].len = 0;
1817 tx_q->tx_skbuff_dma[i].last_segment = false;
1818 tx_q->tx_skbuff[i] = NULL;
1824 static int init_dma_tx_desc_rings(struct net_device *dev,
1825 struct stmmac_dma_conf *dma_conf)
1827 struct stmmac_priv *priv = netdev_priv(dev);
1831 tx_queue_cnt = priv->plat->tx_queues_to_use;
1833 for (queue = 0; queue < tx_queue_cnt; queue++)
1834 __init_dma_tx_desc_rings(priv, dma_conf, queue);
1840 * init_dma_desc_rings - init the RX/TX descriptor rings
1841 * @dev: net device structure
1842 * @dma_conf: structure to take the dma data
1844 * Description: this function initializes the DMA RX/TX descriptors
1845 * and allocates the socket buffers. It supports the chained and ring
1848 static int init_dma_desc_rings(struct net_device *dev,
1849 struct stmmac_dma_conf *dma_conf,
1852 struct stmmac_priv *priv = netdev_priv(dev);
1855 ret = init_dma_rx_desc_rings(dev, dma_conf, flags);
1859 ret = init_dma_tx_desc_rings(dev, dma_conf);
1861 stmmac_clear_descriptors(priv, dma_conf);
1863 if (netif_msg_hw(priv))
1864 stmmac_display_rings(priv, dma_conf);
1870 * dma_free_tx_skbufs - free TX dma buffers
1871 * @priv: private structure
1872 * @dma_conf: structure to take the dma data
1873 * @queue: TX queue index
1875 static void dma_free_tx_skbufs(struct stmmac_priv *priv,
1876 struct stmmac_dma_conf *dma_conf,
1879 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1882 tx_q->xsk_frames_done = 0;
1884 for (i = 0; i < dma_conf->dma_tx_size; i++)
1885 stmmac_free_tx_buffer(priv, dma_conf, queue, i);
1887 if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1888 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1889 tx_q->xsk_frames_done = 0;
1890 tx_q->xsk_pool = NULL;
1895 * stmmac_free_tx_skbufs - free TX skb buffers
1896 * @priv: private structure
1898 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1900 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1903 for (queue = 0; queue < tx_queue_cnt; queue++)
1904 dma_free_tx_skbufs(priv, &priv->dma_conf, queue);
1908 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1909 * @priv: private structure
1910 * @dma_conf: structure to take the dma data
1911 * @queue: RX queue index
1913 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv,
1914 struct stmmac_dma_conf *dma_conf,
1917 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1919 /* Release the DMA RX socket buffers */
1921 dma_free_rx_xskbufs(priv, dma_conf, queue);
1923 dma_free_rx_skbufs(priv, dma_conf, queue);
1925 rx_q->buf_alloc_num = 0;
1926 rx_q->xsk_pool = NULL;
1928 /* Free DMA regions of consistent memory previously allocated */
1929 if (!priv->extend_desc)
1930 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1931 sizeof(struct dma_desc),
1932 rx_q->dma_rx, rx_q->dma_rx_phy);
1934 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1935 sizeof(struct dma_extended_desc),
1936 rx_q->dma_erx, rx_q->dma_rx_phy);
1938 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1939 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1941 kfree(rx_q->buf_pool);
1942 if (rx_q->page_pool)
1943 page_pool_destroy(rx_q->page_pool);
1946 static void free_dma_rx_desc_resources(struct stmmac_priv *priv,
1947 struct stmmac_dma_conf *dma_conf)
1949 u32 rx_count = priv->plat->rx_queues_to_use;
1952 /* Free RX queue resources */
1953 for (queue = 0; queue < rx_count; queue++)
1954 __free_dma_rx_desc_resources(priv, dma_conf, queue);
1958 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1959 * @priv: private structure
1960 * @dma_conf: structure to take the dma data
1961 * @queue: TX queue index
1963 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv,
1964 struct stmmac_dma_conf *dma_conf,
1967 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1971 /* Release the DMA TX socket buffers */
1972 dma_free_tx_skbufs(priv, dma_conf, queue);
1974 if (priv->extend_desc) {
1975 size = sizeof(struct dma_extended_desc);
1976 addr = tx_q->dma_etx;
1977 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1978 size = sizeof(struct dma_edesc);
1979 addr = tx_q->dma_entx;
1981 size = sizeof(struct dma_desc);
1982 addr = tx_q->dma_tx;
1985 size *= dma_conf->dma_tx_size;
1987 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1989 kfree(tx_q->tx_skbuff_dma);
1990 kfree(tx_q->tx_skbuff);
1993 static void free_dma_tx_desc_resources(struct stmmac_priv *priv,
1994 struct stmmac_dma_conf *dma_conf)
1996 u32 tx_count = priv->plat->tx_queues_to_use;
1999 /* Free TX queue resources */
2000 for (queue = 0; queue < tx_count; queue++)
2001 __free_dma_tx_desc_resources(priv, dma_conf, queue);
2005 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
2006 * @priv: private structure
2007 * @dma_conf: structure to take the dma data
2008 * @queue: RX queue index
2009 * Description: according to which descriptor can be used (extend or basic)
2010 * this function allocates the resources for TX and RX paths. In case of
2011 * reception, for example, it pre-allocated the RX socket buffer in order to
2012 * allow zero-copy mechanism.
2014 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2015 struct stmmac_dma_conf *dma_conf,
2018 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
2019 struct stmmac_channel *ch = &priv->channel[queue];
2020 bool xdp_prog = stmmac_xdp_is_enabled(priv);
2021 struct page_pool_params pp_params = { 0 };
2022 unsigned int num_pages;
2023 unsigned int napi_id;
2026 rx_q->queue_index = queue;
2027 rx_q->priv_data = priv;
2029 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
2030 pp_params.pool_size = dma_conf->dma_rx_size;
2031 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE);
2032 pp_params.order = ilog2(num_pages);
2033 pp_params.nid = dev_to_node(priv->device);
2034 pp_params.dev = priv->device;
2035 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
2036 pp_params.offset = stmmac_rx_offset(priv);
2037 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
2039 rx_q->page_pool = page_pool_create(&pp_params);
2040 if (IS_ERR(rx_q->page_pool)) {
2041 ret = PTR_ERR(rx_q->page_pool);
2042 rx_q->page_pool = NULL;
2046 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size,
2047 sizeof(*rx_q->buf_pool),
2049 if (!rx_q->buf_pool)
2052 if (priv->extend_desc) {
2053 rx_q->dma_erx = dma_alloc_coherent(priv->device,
2054 dma_conf->dma_rx_size *
2055 sizeof(struct dma_extended_desc),
2062 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2063 dma_conf->dma_rx_size *
2064 sizeof(struct dma_desc),
2071 if (stmmac_xdp_is_enabled(priv) &&
2072 test_bit(queue, priv->af_xdp_zc_qps))
2073 napi_id = ch->rxtx_napi.napi_id;
2075 napi_id = ch->rx_napi.napi_id;
2077 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2081 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2088 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2089 struct stmmac_dma_conf *dma_conf)
2091 u32 rx_count = priv->plat->rx_queues_to_use;
2095 /* RX queues buffers and DMA */
2096 for (queue = 0; queue < rx_count; queue++) {
2097 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue);
2105 free_dma_rx_desc_resources(priv, dma_conf);
2111 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2112 * @priv: private structure
2113 * @dma_conf: structure to take the dma data
2114 * @queue: TX queue index
2115 * Description: according to which descriptor can be used (extend or basic)
2116 * this function allocates the resources for TX and RX paths. In case of
2117 * reception, for example, it pre-allocated the RX socket buffer in order to
2118 * allow zero-copy mechanism.
2120 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2121 struct stmmac_dma_conf *dma_conf,
2124 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
2128 tx_q->queue_index = queue;
2129 tx_q->priv_data = priv;
2131 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size,
2132 sizeof(*tx_q->tx_skbuff_dma),
2134 if (!tx_q->tx_skbuff_dma)
2137 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size,
2138 sizeof(struct sk_buff *),
2140 if (!tx_q->tx_skbuff)
2143 if (priv->extend_desc)
2144 size = sizeof(struct dma_extended_desc);
2145 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2146 size = sizeof(struct dma_edesc);
2148 size = sizeof(struct dma_desc);
2150 size *= dma_conf->dma_tx_size;
2152 addr = dma_alloc_coherent(priv->device, size,
2153 &tx_q->dma_tx_phy, GFP_KERNEL);
2157 if (priv->extend_desc)
2158 tx_q->dma_etx = addr;
2159 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2160 tx_q->dma_entx = addr;
2162 tx_q->dma_tx = addr;
2167 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2168 struct stmmac_dma_conf *dma_conf)
2170 u32 tx_count = priv->plat->tx_queues_to_use;
2174 /* TX queues buffers and DMA */
2175 for (queue = 0; queue < tx_count; queue++) {
2176 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue);
2184 free_dma_tx_desc_resources(priv, dma_conf);
2189 * alloc_dma_desc_resources - alloc TX/RX resources.
2190 * @priv: private structure
2191 * @dma_conf: structure to take the dma data
2192 * Description: according to which descriptor can be used (extend or basic)
2193 * this function allocates the resources for TX and RX paths. In case of
2194 * reception, for example, it pre-allocated the RX socket buffer in order to
2195 * allow zero-copy mechanism.
2197 static int alloc_dma_desc_resources(struct stmmac_priv *priv,
2198 struct stmmac_dma_conf *dma_conf)
2201 int ret = alloc_dma_rx_desc_resources(priv, dma_conf);
2206 ret = alloc_dma_tx_desc_resources(priv, dma_conf);
2212 * free_dma_desc_resources - free dma desc resources
2213 * @priv: private structure
2214 * @dma_conf: structure to take the dma data
2216 static void free_dma_desc_resources(struct stmmac_priv *priv,
2217 struct stmmac_dma_conf *dma_conf)
2219 /* Release the DMA TX socket buffers */
2220 free_dma_tx_desc_resources(priv, dma_conf);
2222 /* Release the DMA RX socket buffers later
2223 * to ensure all pending XDP_TX buffers are returned.
2225 free_dma_rx_desc_resources(priv, dma_conf);
2229 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
2230 * @priv: driver private structure
2231 * Description: It is used for enabling the rx queues in the MAC
2233 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2235 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2239 for (queue = 0; queue < rx_queues_count; queue++) {
2240 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2241 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2246 * stmmac_start_rx_dma - start RX DMA channel
2247 * @priv: driver private structure
2248 * @chan: RX channel index
2250 * This starts a RX DMA channel
2252 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2254 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2255 stmmac_start_rx(priv, priv->ioaddr, chan);
2259 * stmmac_start_tx_dma - start TX DMA channel
2260 * @priv: driver private structure
2261 * @chan: TX channel index
2263 * This starts a TX DMA channel
2265 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2267 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2268 stmmac_start_tx(priv, priv->ioaddr, chan);
2272 * stmmac_stop_rx_dma - stop RX DMA channel
2273 * @priv: driver private structure
2274 * @chan: RX channel index
2276 * This stops a RX DMA channel
2278 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2280 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2281 stmmac_stop_rx(priv, priv->ioaddr, chan);
2285 * stmmac_stop_tx_dma - stop TX DMA channel
2286 * @priv: driver private structure
2287 * @chan: TX channel index
2289 * This stops a TX DMA channel
2291 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2293 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2294 stmmac_stop_tx(priv, priv->ioaddr, chan);
2297 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
2299 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2300 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2301 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2304 for (chan = 0; chan < dma_csr_ch; chan++) {
2305 struct stmmac_channel *ch = &priv->channel[chan];
2306 unsigned long flags;
2308 spin_lock_irqsave(&ch->lock, flags);
2309 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2310 spin_unlock_irqrestore(&ch->lock, flags);
2315 * stmmac_start_all_dma - start all RX and TX DMA channels
2316 * @priv: driver private structure
2318 * This starts all the RX and TX DMA channels
2320 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2322 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2323 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2326 for (chan = 0; chan < rx_channels_count; chan++)
2327 stmmac_start_rx_dma(priv, chan);
2329 for (chan = 0; chan < tx_channels_count; chan++)
2330 stmmac_start_tx_dma(priv, chan);
2334 * stmmac_stop_all_dma - stop all RX and TX DMA channels
2335 * @priv: driver private structure
2337 * This stops the RX and TX DMA channels
2339 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2341 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2342 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2345 for (chan = 0; chan < rx_channels_count; chan++)
2346 stmmac_stop_rx_dma(priv, chan);
2348 for (chan = 0; chan < tx_channels_count; chan++)
2349 stmmac_stop_tx_dma(priv, chan);
2353 * stmmac_dma_operation_mode - HW DMA operation mode
2354 * @priv: driver private structure
2355 * Description: it is used for configuring the DMA operation mode register in
2356 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2358 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2360 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2361 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2362 int rxfifosz = priv->plat->rx_fifo_size;
2363 int txfifosz = priv->plat->tx_fifo_size;
2370 rxfifosz = priv->dma_cap.rx_fifo_size;
2372 txfifosz = priv->dma_cap.tx_fifo_size;
2374 /* Adjust for real per queue fifo size */
2375 rxfifosz /= rx_channels_count;
2376 txfifosz /= tx_channels_count;
2378 if (priv->plat->force_thresh_dma_mode) {
2381 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2383 * In case of GMAC, SF mode can be enabled
2384 * to perform the TX COE in HW. This depends on:
2385 * 1) TX COE if actually supported
2386 * 2) There is no bugged Jumbo frame support
2387 * that needs to not insert csum in the TDES.
2389 txmode = SF_DMA_MODE;
2390 rxmode = SF_DMA_MODE;
2391 priv->xstats.threshold = SF_DMA_MODE;
2394 rxmode = SF_DMA_MODE;
2397 /* configure all channels */
2398 for (chan = 0; chan < rx_channels_count; chan++) {
2399 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2402 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2404 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2407 if (rx_q->xsk_pool) {
2408 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2409 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2413 stmmac_set_dma_bfsize(priv, priv->ioaddr,
2414 priv->dma_conf.dma_buf_sz,
2419 for (chan = 0; chan < tx_channels_count; chan++) {
2420 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2422 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2427 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2429 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2430 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2431 struct xsk_buff_pool *pool = tx_q->xsk_pool;
2432 unsigned int entry = tx_q->cur_tx;
2433 struct dma_desc *tx_desc = NULL;
2434 struct xdp_desc xdp_desc;
2435 bool work_done = true;
2437 /* Avoids TX time-out as we are sharing with slow path */
2438 txq_trans_cond_update(nq);
2440 budget = min(budget, stmmac_tx_avail(priv, queue));
2442 while (budget-- > 0) {
2443 dma_addr_t dma_addr;
2446 /* We are sharing with slow path and stop XSK TX desc submission when
2447 * available TX ring is less than threshold.
2449 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2450 !netif_carrier_ok(priv->dev)) {
2455 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2458 if (likely(priv->extend_desc))
2459 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2460 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2461 tx_desc = &tx_q->dma_entx[entry].basic;
2463 tx_desc = tx_q->dma_tx + entry;
2465 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2466 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2468 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2470 /* To return XDP buffer to XSK pool, we simple call
2471 * xsk_tx_completed(), so we don't need to fill up
2474 tx_q->tx_skbuff_dma[entry].buf = 0;
2475 tx_q->xdpf[entry] = NULL;
2477 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2478 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2479 tx_q->tx_skbuff_dma[entry].last_segment = true;
2480 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2482 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2484 tx_q->tx_count_frames++;
2486 if (!priv->tx_coal_frames[queue])
2488 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2494 tx_q->tx_count_frames = 0;
2495 stmmac_set_tx_ic(priv, tx_desc);
2496 priv->xstats.tx_set_ic_bit++;
2499 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2500 true, priv->mode, true, true,
2503 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2505 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
2506 entry = tx_q->cur_tx;
2510 stmmac_flush_tx_descriptors(priv, queue);
2511 xsk_tx_release(pool);
2514 /* Return true if all of the 3 conditions are met
2515 * a) TX Budget is still available
2516 * b) work_done = true when XSK TX desc peek is empty (no more
2517 * pending XSK TX for transmission)
2519 return !!budget && work_done;
2522 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2524 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2527 if (priv->plat->force_thresh_dma_mode)
2528 stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2530 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2533 priv->xstats.threshold = tc;
2538 * stmmac_tx_clean - to manage the transmission completion
2539 * @priv: driver private structure
2540 * @budget: napi budget limiting this functions packet handling
2541 * @queue: TX queue index
2542 * Description: it reclaims the transmit resources after transmission completes.
2544 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2546 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2547 unsigned int bytes_compl = 0, pkts_compl = 0;
2548 unsigned int entry, xmits = 0, count = 0;
2550 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2552 priv->xstats.tx_clean++;
2554 tx_q->xsk_frames_done = 0;
2556 entry = tx_q->dirty_tx;
2558 /* Try to clean all TX complete frame in 1 shot */
2559 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) {
2560 struct xdp_frame *xdpf;
2561 struct sk_buff *skb;
2565 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2566 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2567 xdpf = tx_q->xdpf[entry];
2569 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2571 skb = tx_q->tx_skbuff[entry];
2577 if (priv->extend_desc)
2578 p = (struct dma_desc *)(tx_q->dma_etx + entry);
2579 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2580 p = &tx_q->dma_entx[entry].basic;
2582 p = tx_q->dma_tx + entry;
2584 status = stmmac_tx_status(priv, &priv->dev->stats,
2585 &priv->xstats, p, priv->ioaddr);
2586 /* Check if the descriptor is owned by the DMA */
2587 if (unlikely(status & tx_dma_own))
2592 /* Make sure descriptor fields are read after reading
2597 /* Just consider the last segment and ...*/
2598 if (likely(!(status & tx_not_ls))) {
2599 /* ... verify the status error condition */
2600 if (unlikely(status & tx_err)) {
2601 priv->dev->stats.tx_errors++;
2602 if (unlikely(status & tx_err_bump_tc))
2603 stmmac_bump_dma_threshold(priv, queue);
2605 priv->dev->stats.tx_packets++;
2606 priv->xstats.tx_pkt_n++;
2607 priv->xstats.txq_stats[queue].tx_pkt_n++;
2610 stmmac_get_tx_hwtstamp(priv, p, skb);
2613 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2614 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2615 if (tx_q->tx_skbuff_dma[entry].map_as_page)
2616 dma_unmap_page(priv->device,
2617 tx_q->tx_skbuff_dma[entry].buf,
2618 tx_q->tx_skbuff_dma[entry].len,
2621 dma_unmap_single(priv->device,
2622 tx_q->tx_skbuff_dma[entry].buf,
2623 tx_q->tx_skbuff_dma[entry].len,
2625 tx_q->tx_skbuff_dma[entry].buf = 0;
2626 tx_q->tx_skbuff_dma[entry].len = 0;
2627 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2630 stmmac_clean_desc3(priv, tx_q, p);
2632 tx_q->tx_skbuff_dma[entry].last_segment = false;
2633 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2636 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2637 xdp_return_frame_rx_napi(xdpf);
2638 tx_q->xdpf[entry] = NULL;
2642 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2643 xdp_return_frame(xdpf);
2644 tx_q->xdpf[entry] = NULL;
2647 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2648 tx_q->xsk_frames_done++;
2650 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2653 bytes_compl += skb->len;
2654 dev_consume_skb_any(skb);
2655 tx_q->tx_skbuff[entry] = NULL;
2659 stmmac_release_tx_desc(priv, p, priv->mode);
2661 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
2663 tx_q->dirty_tx = entry;
2665 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2666 pkts_compl, bytes_compl);
2668 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2670 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2672 netif_dbg(priv, tx_done, priv->dev,
2673 "%s: restart transmit\n", __func__);
2674 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2677 if (tx_q->xsk_pool) {
2680 if (tx_q->xsk_frames_done)
2681 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2683 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2684 xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2686 /* For XSK TX, we try to send as many as possible.
2687 * If XSK work done (XSK TX desc empty and budget still
2688 * available), return "budget - 1" to reenable TX IRQ.
2689 * Else, return "budget" to make NAPI continue polling.
2691 work_done = stmmac_xdp_xmit_zc(priv, queue,
2692 STMMAC_XSK_TX_BUDGET_MAX);
2699 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2700 priv->eee_sw_timer_en) {
2701 if (stmmac_enable_eee_mode(priv))
2702 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2705 /* We still have pending packets, let's call for a new scheduling */
2706 if (tx_q->dirty_tx != tx_q->cur_tx)
2707 hrtimer_start(&tx_q->txtimer,
2708 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2711 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2713 /* Combine decisions from TX clean and XSK TX */
2714 return max(count, xmits);
2718 * stmmac_tx_err - to manage the tx error
2719 * @priv: driver private structure
2720 * @chan: channel index
2721 * Description: it cleans the descriptors and restarts the transmission
2722 * in case of transmission errors.
2724 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2726 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2728 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2730 stmmac_stop_tx_dma(priv, chan);
2731 dma_free_tx_skbufs(priv, &priv->dma_conf, chan);
2732 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan);
2733 stmmac_reset_tx_queue(priv, chan);
2734 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2735 tx_q->dma_tx_phy, chan);
2736 stmmac_start_tx_dma(priv, chan);
2738 priv->dev->stats.tx_errors++;
2739 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2743 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2744 * @priv: driver private structure
2745 * @txmode: TX operating mode
2746 * @rxmode: RX operating mode
2747 * @chan: channel index
2748 * Description: it is used for configuring of the DMA operation mode in
2749 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2752 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2753 u32 rxmode, u32 chan)
2755 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2756 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2757 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2758 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2759 int rxfifosz = priv->plat->rx_fifo_size;
2760 int txfifosz = priv->plat->tx_fifo_size;
2763 rxfifosz = priv->dma_cap.rx_fifo_size;
2765 txfifosz = priv->dma_cap.tx_fifo_size;
2767 /* Adjust for real per queue fifo size */
2768 rxfifosz /= rx_channels_count;
2769 txfifosz /= tx_channels_count;
2771 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2772 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2775 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2779 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2780 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2781 if (ret && (ret != -EINVAL)) {
2782 stmmac_global_err(priv);
2789 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2791 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2792 &priv->xstats, chan, dir);
2793 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2794 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2795 struct stmmac_channel *ch = &priv->channel[chan];
2796 struct napi_struct *rx_napi;
2797 struct napi_struct *tx_napi;
2798 unsigned long flags;
2800 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2801 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2803 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2804 if (napi_schedule_prep(rx_napi)) {
2805 spin_lock_irqsave(&ch->lock, flags);
2806 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2807 spin_unlock_irqrestore(&ch->lock, flags);
2808 __napi_schedule(rx_napi);
2812 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2813 if (napi_schedule_prep(tx_napi)) {
2814 spin_lock_irqsave(&ch->lock, flags);
2815 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2816 spin_unlock_irqrestore(&ch->lock, flags);
2817 __napi_schedule(tx_napi);
2825 * stmmac_dma_interrupt - DMA ISR
2826 * @priv: driver private structure
2827 * Description: this is the DMA ISR. It is called by the main ISR.
2828 * It calls the dwmac dma routine and schedule poll method in case of some
2831 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2833 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2834 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2835 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2836 tx_channel_count : rx_channel_count;
2838 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2840 /* Make sure we never check beyond our status buffer. */
2841 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2842 channels_to_check = ARRAY_SIZE(status);
2844 for (chan = 0; chan < channels_to_check; chan++)
2845 status[chan] = stmmac_napi_check(priv, chan,
2848 for (chan = 0; chan < tx_channel_count; chan++) {
2849 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2850 /* Try to bump up the dma threshold on this failure */
2851 stmmac_bump_dma_threshold(priv, chan);
2852 } else if (unlikely(status[chan] == tx_hard_error)) {
2853 stmmac_tx_err(priv, chan);
2859 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2860 * @priv: driver private structure
2861 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2863 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2865 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2866 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2868 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2870 if (priv->dma_cap.rmon) {
2871 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2872 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2874 netdev_info(priv->dev, "No MAC Management Counters available\n");
2878 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2879 * @priv: driver private structure
2881 * new GMAC chip generations have a new register to indicate the
2882 * presence of the optional feature/functions.
2883 * This can be also used to override the value passed through the
2884 * platform and necessary for old MAC10/100 and GMAC chips.
2886 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2888 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2892 * stmmac_check_ether_addr - check if the MAC addr is valid
2893 * @priv: driver private structure
2895 * it is to verify if the MAC address is valid, in case of failures it
2896 * generates a random MAC address
2898 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2902 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2903 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2904 if (is_valid_ether_addr(addr))
2905 eth_hw_addr_set(priv->dev, addr);
2907 eth_hw_addr_random(priv->dev);
2908 dev_info(priv->device, "device MAC address %pM\n",
2909 priv->dev->dev_addr);
2914 * stmmac_init_dma_engine - DMA init.
2915 * @priv: driver private structure
2917 * It inits the DMA invoking the specific MAC/GMAC callback.
2918 * Some DMA parameters can be passed from the platform;
2919 * in case of these are not passed a default is kept for the MAC or GMAC.
2921 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2923 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2924 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2925 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2926 struct stmmac_rx_queue *rx_q;
2927 struct stmmac_tx_queue *tx_q;
2932 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2933 dev_err(priv->device, "Invalid DMA configuration\n");
2937 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2940 ret = stmmac_reset(priv, priv->ioaddr);
2942 dev_err(priv->device, "Failed to reset the dma\n");
2946 /* DMA Configuration */
2947 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2949 if (priv->plat->axi)
2950 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2952 /* DMA CSR Channel configuration */
2953 for (chan = 0; chan < dma_csr_ch; chan++) {
2954 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2955 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2958 /* DMA RX Channel Configuration */
2959 for (chan = 0; chan < rx_channels_count; chan++) {
2960 rx_q = &priv->dma_conf.rx_queue[chan];
2962 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2963 rx_q->dma_rx_phy, chan);
2965 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2966 (rx_q->buf_alloc_num *
2967 sizeof(struct dma_desc));
2968 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2969 rx_q->rx_tail_addr, chan);
2972 /* DMA TX Channel Configuration */
2973 for (chan = 0; chan < tx_channels_count; chan++) {
2974 tx_q = &priv->dma_conf.tx_queue[chan];
2976 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2977 tx_q->dma_tx_phy, chan);
2979 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2980 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2981 tx_q->tx_tail_addr, chan);
2987 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2989 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2991 hrtimer_start(&tx_q->txtimer,
2992 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2997 * stmmac_tx_timer - mitigation sw timer for tx.
3000 * This is the timer handler to directly invoke the stmmac_tx_clean.
3002 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
3004 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
3005 struct stmmac_priv *priv = tx_q->priv_data;
3006 struct stmmac_channel *ch;
3007 struct napi_struct *napi;
3009 ch = &priv->channel[tx_q->queue_index];
3010 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
3012 if (likely(napi_schedule_prep(napi))) {
3013 unsigned long flags;
3015 spin_lock_irqsave(&ch->lock, flags);
3016 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
3017 spin_unlock_irqrestore(&ch->lock, flags);
3018 __napi_schedule(napi);
3021 return HRTIMER_NORESTART;
3025 * stmmac_init_coalesce - init mitigation options.
3026 * @priv: driver private structure
3028 * This inits the coalesce parameters: i.e. timer rate,
3029 * timer handler and default threshold used for enabling the
3030 * interrupt on completion bit.
3032 static void stmmac_init_coalesce(struct stmmac_priv *priv)
3034 u32 tx_channel_count = priv->plat->tx_queues_to_use;
3035 u32 rx_channel_count = priv->plat->rx_queues_to_use;
3038 for (chan = 0; chan < tx_channel_count; chan++) {
3039 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3041 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
3042 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
3044 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3045 tx_q->txtimer.function = stmmac_tx_timer;
3048 for (chan = 0; chan < rx_channel_count; chan++)
3049 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
3052 static void stmmac_set_rings_length(struct stmmac_priv *priv)
3054 u32 rx_channels_count = priv->plat->rx_queues_to_use;
3055 u32 tx_channels_count = priv->plat->tx_queues_to_use;
3058 /* set TX ring length */
3059 for (chan = 0; chan < tx_channels_count; chan++)
3060 stmmac_set_tx_ring_len(priv, priv->ioaddr,
3061 (priv->dma_conf.dma_tx_size - 1), chan);
3063 /* set RX ring length */
3064 for (chan = 0; chan < rx_channels_count; chan++)
3065 stmmac_set_rx_ring_len(priv, priv->ioaddr,
3066 (priv->dma_conf.dma_rx_size - 1), chan);
3070 * stmmac_set_tx_queue_weight - Set TX queue weight
3071 * @priv: driver private structure
3072 * Description: It is used for setting TX queues weight
3074 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
3076 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3080 for (queue = 0; queue < tx_queues_count; queue++) {
3081 weight = priv->plat->tx_queues_cfg[queue].weight;
3082 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3087 * stmmac_configure_cbs - Configure CBS in TX queue
3088 * @priv: driver private structure
3089 * Description: It is used for configuring CBS in AVB TX queues
3091 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3093 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3097 /* queue 0 is reserved for legacy traffic */
3098 for (queue = 1; queue < tx_queues_count; queue++) {
3099 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3100 if (mode_to_use == MTL_QUEUE_DCB)
3103 stmmac_config_cbs(priv, priv->hw,
3104 priv->plat->tx_queues_cfg[queue].send_slope,
3105 priv->plat->tx_queues_cfg[queue].idle_slope,
3106 priv->plat->tx_queues_cfg[queue].high_credit,
3107 priv->plat->tx_queues_cfg[queue].low_credit,
3113 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3114 * @priv: driver private structure
3115 * Description: It is used for mapping RX queues to RX dma channels
3117 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3119 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3123 for (queue = 0; queue < rx_queues_count; queue++) {
3124 chan = priv->plat->rx_queues_cfg[queue].chan;
3125 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3130 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3131 * @priv: driver private structure
3132 * Description: It is used for configuring the RX Queue Priority
3134 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3136 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3140 for (queue = 0; queue < rx_queues_count; queue++) {
3141 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3144 prio = priv->plat->rx_queues_cfg[queue].prio;
3145 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3150 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3151 * @priv: driver private structure
3152 * Description: It is used for configuring the TX Queue Priority
3154 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3156 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3160 for (queue = 0; queue < tx_queues_count; queue++) {
3161 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3164 prio = priv->plat->tx_queues_cfg[queue].prio;
3165 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3170 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3171 * @priv: driver private structure
3172 * Description: It is used for configuring the RX queue routing
3174 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3176 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3180 for (queue = 0; queue < rx_queues_count; queue++) {
3181 /* no specific packet type routing specified for the queue */
3182 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3185 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3186 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3190 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3192 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3193 priv->rss.enable = false;
3197 if (priv->dev->features & NETIF_F_RXHASH)
3198 priv->rss.enable = true;
3200 priv->rss.enable = false;
3202 stmmac_rss_configure(priv, priv->hw, &priv->rss,
3203 priv->plat->rx_queues_to_use);
3207 * stmmac_mtl_configuration - Configure MTL
3208 * @priv: driver private structure
3209 * Description: It is used for configurring MTL
3211 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3213 u32 rx_queues_count = priv->plat->rx_queues_to_use;
3214 u32 tx_queues_count = priv->plat->tx_queues_to_use;
3216 if (tx_queues_count > 1)
3217 stmmac_set_tx_queue_weight(priv);
3219 /* Configure MTL RX algorithms */
3220 if (rx_queues_count > 1)
3221 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3222 priv->plat->rx_sched_algorithm);
3224 /* Configure MTL TX algorithms */
3225 if (tx_queues_count > 1)
3226 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3227 priv->plat->tx_sched_algorithm);
3229 /* Configure CBS in AVB TX queues */
3230 if (tx_queues_count > 1)
3231 stmmac_configure_cbs(priv);
3233 /* Map RX MTL to DMA channels */
3234 stmmac_rx_queue_dma_chan_map(priv);
3236 /* Enable MAC RX Queues */
3237 stmmac_mac_enable_rx_queues(priv);
3239 /* Set RX priorities */
3240 if (rx_queues_count > 1)
3241 stmmac_mac_config_rx_queues_prio(priv);
3243 /* Set TX priorities */
3244 if (tx_queues_count > 1)
3245 stmmac_mac_config_tx_queues_prio(priv);
3247 /* Set RX routing */
3248 if (rx_queues_count > 1)
3249 stmmac_mac_config_rx_queues_routing(priv);
3251 /* Receive Side Scaling */
3252 if (rx_queues_count > 1)
3253 stmmac_mac_config_rss(priv);
3256 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3258 if (priv->dma_cap.asp) {
3259 netdev_info(priv->dev, "Enabling Safety Features\n");
3260 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3261 priv->plat->safety_feat_cfg);
3263 netdev_info(priv->dev, "No Safety Features support found\n");
3267 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3271 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3272 clear_bit(__FPE_REMOVING, &priv->fpe_task_state);
3274 name = priv->wq_name;
3275 sprintf(name, "%s-fpe", priv->dev->name);
3277 priv->fpe_wq = create_singlethread_workqueue(name);
3278 if (!priv->fpe_wq) {
3279 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3283 netdev_info(priv->dev, "FPE workqueue start");
3289 * stmmac_hw_setup - setup mac in a usable state.
3290 * @dev : pointer to the device structure.
3291 * @ptp_register: register PTP if set
3293 * this is the main function to setup the HW in a usable state because the
3294 * dma engine is reset, the core registers are configured (e.g. AXI,
3295 * Checksum features, timers). The DMA is ready to start receiving and
3298 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3301 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)
3303 struct stmmac_priv *priv = netdev_priv(dev);
3304 u32 rx_cnt = priv->plat->rx_queues_to_use;
3305 u32 tx_cnt = priv->plat->tx_queues_to_use;
3310 /* DMA initialization and SW reset */
3311 ret = stmmac_init_dma_engine(priv);
3313 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3318 /* Copy the MAC addr into the HW */
3319 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3321 /* PS and related bits will be programmed according to the speed */
3322 if (priv->hw->pcs) {
3323 int speed = priv->plat->mac_port_sel_speed;
3325 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3326 (speed == SPEED_1000)) {
3327 priv->hw->ps = speed;
3329 dev_warn(priv->device, "invalid port speed\n");
3334 /* Initialize the MAC Core */
3335 stmmac_core_init(priv, priv->hw, dev);
3338 stmmac_mtl_configuration(priv);
3340 /* Initialize Safety Features */
3341 stmmac_safety_feat_configuration(priv);
3343 ret = stmmac_rx_ipc(priv, priv->hw);
3345 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3346 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3347 priv->hw->rx_csum = 0;
3350 /* Enable the MAC Rx/Tx */
3351 stmmac_mac_set(priv, priv->ioaddr, true);
3353 /* Set the HW DMA mode and the COE */
3354 stmmac_dma_operation_mode(priv);
3356 stmmac_mmc_setup(priv);
3359 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3361 netdev_warn(priv->dev,
3362 "failed to enable PTP reference clock: %pe\n",
3366 ret = stmmac_init_ptp(priv);
3367 if (ret == -EOPNOTSUPP)
3368 netdev_info(priv->dev, "PTP not supported by HW\n");
3370 netdev_warn(priv->dev, "PTP init failed\n");
3371 else if (ptp_register)
3372 stmmac_ptp_register(priv);
3374 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3376 /* Convert the timer from msec to usec */
3377 if (!priv->tx_lpi_timer)
3378 priv->tx_lpi_timer = eee_timer * 1000;
3380 if (priv->use_riwt) {
3383 for (queue = 0; queue < rx_cnt; queue++) {
3384 if (!priv->rx_riwt[queue])
3385 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3387 stmmac_rx_watchdog(priv, priv->ioaddr,
3388 priv->rx_riwt[queue], queue);
3393 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3395 /* set TX and RX rings length */
3396 stmmac_set_rings_length(priv);
3400 for (chan = 0; chan < tx_cnt; chan++) {
3401 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3403 /* TSO and TBS cannot co-exist */
3404 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3407 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3411 /* Enable Split Header */
3412 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3413 for (chan = 0; chan < rx_cnt; chan++)
3414 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3417 /* VLAN Tag Insertion */
3418 if (priv->dma_cap.vlins)
3419 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3422 for (chan = 0; chan < tx_cnt; chan++) {
3423 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3424 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3426 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3429 /* Configure real RX and TX queues */
3430 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3431 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3433 /* Start the ball rolling... */
3434 stmmac_start_all_dma(priv);
3436 if (priv->dma_cap.fpesel) {
3437 stmmac_fpe_start_wq(priv);
3439 if (priv->plat->fpe_cfg->enable)
3440 stmmac_fpe_handshake(priv, true);
3446 static void stmmac_hw_teardown(struct net_device *dev)
3448 struct stmmac_priv *priv = netdev_priv(dev);
3450 clk_disable_unprepare(priv->plat->clk_ptp_ref);
3453 static void stmmac_free_irq(struct net_device *dev,
3454 enum request_irq_err irq_err, int irq_idx)
3456 struct stmmac_priv *priv = netdev_priv(dev);
3460 case REQ_IRQ_ERR_ALL:
3461 irq_idx = priv->plat->tx_queues_to_use;
3463 case REQ_IRQ_ERR_TX:
3464 for (j = irq_idx - 1; j >= 0; j--) {
3465 if (priv->tx_irq[j] > 0) {
3466 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3467 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]);
3470 irq_idx = priv->plat->rx_queues_to_use;
3472 case REQ_IRQ_ERR_RX:
3473 for (j = irq_idx - 1; j >= 0; j--) {
3474 if (priv->rx_irq[j] > 0) {
3475 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3476 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]);
3480 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3481 free_irq(priv->sfty_ue_irq, dev);
3483 case REQ_IRQ_ERR_SFTY_UE:
3484 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3485 free_irq(priv->sfty_ce_irq, dev);
3487 case REQ_IRQ_ERR_SFTY_CE:
3488 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3489 free_irq(priv->lpi_irq, dev);
3491 case REQ_IRQ_ERR_LPI:
3492 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3493 free_irq(priv->wol_irq, dev);
3495 case REQ_IRQ_ERR_WOL:
3496 free_irq(dev->irq, dev);
3498 case REQ_IRQ_ERR_MAC:
3499 case REQ_IRQ_ERR_NO:
3500 /* If MAC IRQ request error, no more IRQ to free */
3505 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3507 struct stmmac_priv *priv = netdev_priv(dev);
3508 enum request_irq_err irq_err;
3515 /* For common interrupt */
3516 int_name = priv->int_name_mac;
3517 sprintf(int_name, "%s:%s", dev->name, "mac");
3518 ret = request_irq(dev->irq, stmmac_mac_interrupt,
3520 if (unlikely(ret < 0)) {
3521 netdev_err(priv->dev,
3522 "%s: alloc mac MSI %d (error: %d)\n",
3523 __func__, dev->irq, ret);
3524 irq_err = REQ_IRQ_ERR_MAC;
3528 /* Request the Wake IRQ in case of another line
3531 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3532 int_name = priv->int_name_wol;
3533 sprintf(int_name, "%s:%s", dev->name, "wol");
3534 ret = request_irq(priv->wol_irq,
3535 stmmac_mac_interrupt,
3537 if (unlikely(ret < 0)) {
3538 netdev_err(priv->dev,
3539 "%s: alloc wol MSI %d (error: %d)\n",
3540 __func__, priv->wol_irq, ret);
3541 irq_err = REQ_IRQ_ERR_WOL;
3546 /* Request the LPI IRQ in case of another line
3549 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3550 int_name = priv->int_name_lpi;
3551 sprintf(int_name, "%s:%s", dev->name, "lpi");
3552 ret = request_irq(priv->lpi_irq,
3553 stmmac_mac_interrupt,
3555 if (unlikely(ret < 0)) {
3556 netdev_err(priv->dev,
3557 "%s: alloc lpi MSI %d (error: %d)\n",
3558 __func__, priv->lpi_irq, ret);
3559 irq_err = REQ_IRQ_ERR_LPI;
3564 /* Request the Safety Feature Correctible Error line in
3565 * case of another line is used
3567 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3568 int_name = priv->int_name_sfty_ce;
3569 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3570 ret = request_irq(priv->sfty_ce_irq,
3571 stmmac_safety_interrupt,
3573 if (unlikely(ret < 0)) {
3574 netdev_err(priv->dev,
3575 "%s: alloc sfty ce MSI %d (error: %d)\n",
3576 __func__, priv->sfty_ce_irq, ret);
3577 irq_err = REQ_IRQ_ERR_SFTY_CE;
3582 /* Request the Safety Feature Uncorrectible Error line in
3583 * case of another line is used
3585 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3586 int_name = priv->int_name_sfty_ue;
3587 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3588 ret = request_irq(priv->sfty_ue_irq,
3589 stmmac_safety_interrupt,
3591 if (unlikely(ret < 0)) {
3592 netdev_err(priv->dev,
3593 "%s: alloc sfty ue MSI %d (error: %d)\n",
3594 __func__, priv->sfty_ue_irq, ret);
3595 irq_err = REQ_IRQ_ERR_SFTY_UE;
3600 /* Request Rx MSI irq */
3601 for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3602 if (i >= MTL_MAX_RX_QUEUES)
3604 if (priv->rx_irq[i] == 0)
3607 int_name = priv->int_name_rx_irq[i];
3608 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3609 ret = request_irq(priv->rx_irq[i],
3611 0, int_name, &priv->dma_conf.rx_queue[i]);
3612 if (unlikely(ret < 0)) {
3613 netdev_err(priv->dev,
3614 "%s: alloc rx-%d MSI %d (error: %d)\n",
3615 __func__, i, priv->rx_irq[i], ret);
3616 irq_err = REQ_IRQ_ERR_RX;
3620 cpumask_clear(&cpu_mask);
3621 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3622 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3625 /* Request Tx MSI irq */
3626 for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3627 if (i >= MTL_MAX_TX_QUEUES)
3629 if (priv->tx_irq[i] == 0)
3632 int_name = priv->int_name_tx_irq[i];
3633 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3634 ret = request_irq(priv->tx_irq[i],
3636 0, int_name, &priv->dma_conf.tx_queue[i]);
3637 if (unlikely(ret < 0)) {
3638 netdev_err(priv->dev,
3639 "%s: alloc tx-%d MSI %d (error: %d)\n",
3640 __func__, i, priv->tx_irq[i], ret);
3641 irq_err = REQ_IRQ_ERR_TX;
3645 cpumask_clear(&cpu_mask);
3646 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3647 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3653 stmmac_free_irq(dev, irq_err, irq_idx);
3657 static int stmmac_request_irq_single(struct net_device *dev)
3659 struct stmmac_priv *priv = netdev_priv(dev);
3660 enum request_irq_err irq_err;
3663 ret = request_irq(dev->irq, stmmac_interrupt,
3664 IRQF_SHARED, dev->name, dev);
3665 if (unlikely(ret < 0)) {
3666 netdev_err(priv->dev,
3667 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3668 __func__, dev->irq, ret);
3669 irq_err = REQ_IRQ_ERR_MAC;
3673 /* Request the Wake IRQ in case of another line
3676 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3677 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3678 IRQF_SHARED, dev->name, dev);
3679 if (unlikely(ret < 0)) {
3680 netdev_err(priv->dev,
3681 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3682 __func__, priv->wol_irq, ret);
3683 irq_err = REQ_IRQ_ERR_WOL;
3688 /* Request the IRQ lines */
3689 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3690 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3691 IRQF_SHARED, dev->name, dev);
3692 if (unlikely(ret < 0)) {
3693 netdev_err(priv->dev,
3694 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3695 __func__, priv->lpi_irq, ret);
3696 irq_err = REQ_IRQ_ERR_LPI;
3704 stmmac_free_irq(dev, irq_err, 0);
3708 static int stmmac_request_irq(struct net_device *dev)
3710 struct stmmac_priv *priv = netdev_priv(dev);
3713 /* Request the IRQ lines */
3714 if (priv->plat->multi_msi_en)
3715 ret = stmmac_request_irq_multi_msi(dev);
3717 ret = stmmac_request_irq_single(dev);
3723 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue
3724 * @priv: driver private structure
3725 * @mtu: MTU to setup the dma queue and buf with
3726 * Description: Allocate and generate a dma_conf based on the provided MTU.
3727 * Allocate the Tx/Rx DMA queue and init them.
3729 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure.
3731 static struct stmmac_dma_conf *
3732 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu)
3734 struct stmmac_dma_conf *dma_conf;
3735 int chan, bfsize, ret;
3737 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL);
3739 netdev_err(priv->dev, "%s: DMA conf allocation failed\n",
3741 return ERR_PTR(-ENOMEM);
3744 bfsize = stmmac_set_16kib_bfsize(priv, mtu);
3748 if (bfsize < BUF_SIZE_16KiB)
3749 bfsize = stmmac_set_bfsize(mtu, 0);
3751 dma_conf->dma_buf_sz = bfsize;
3752 /* Chose the tx/rx size from the already defined one in the
3753 * priv struct. (if defined)
3755 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size;
3756 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size;
3758 if (!dma_conf->dma_tx_size)
3759 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3760 if (!dma_conf->dma_rx_size)
3761 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3763 /* Earlier check for TBS */
3764 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3765 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan];
3766 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3768 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3769 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3772 ret = alloc_dma_desc_resources(priv, dma_conf);
3774 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3779 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL);
3781 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3789 free_dma_desc_resources(priv, dma_conf);
3792 return ERR_PTR(ret);
3796 * __stmmac_open - open entry point of the driver
3797 * @dev : pointer to the device structure.
3798 * @dma_conf : structure to take the dma data
3800 * This function is the open entry point of the driver.
3802 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3805 static int __stmmac_open(struct net_device *dev,
3806 struct stmmac_dma_conf *dma_conf)
3808 struct stmmac_priv *priv = netdev_priv(dev);
3809 int mode = priv->plat->phy_interface;
3813 ret = pm_runtime_resume_and_get(priv->device);
3817 if (priv->hw->pcs != STMMAC_PCS_TBI &&
3818 priv->hw->pcs != STMMAC_PCS_RTBI &&
3820 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) &&
3821 !priv->hw->lynx_pcs) {
3822 ret = stmmac_init_phy(dev);
3824 netdev_err(priv->dev,
3825 "%s: Cannot attach to PHY (error: %d)\n",
3827 goto init_phy_error;
3831 /* Extra statistics */
3832 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3833 priv->xstats.threshold = tc;
3835 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3837 buf_sz = dma_conf->dma_buf_sz;
3838 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf));
3840 stmmac_reset_queues_param(priv);
3842 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
3843 priv->plat->serdes_powerup) {
3844 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
3846 netdev_err(priv->dev, "%s: Serdes powerup failed\n",
3852 ret = stmmac_hw_setup(dev, true);
3854 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3858 stmmac_init_coalesce(priv);
3860 phylink_start(priv->phylink);
3861 /* We may have called phylink_speed_down before */
3862 phylink_speed_up(priv->phylink);
3864 ret = stmmac_request_irq(dev);
3868 stmmac_enable_all_queues(priv);
3869 netif_tx_start_all_queues(priv->dev);
3870 stmmac_enable_all_dma_irq(priv);
3875 phylink_stop(priv->phylink);
3877 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3878 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
3880 stmmac_hw_teardown(dev);
3882 phylink_disconnect_phy(priv->phylink);
3884 pm_runtime_put(priv->device);
3888 static int stmmac_open(struct net_device *dev)
3890 struct stmmac_priv *priv = netdev_priv(dev);
3891 struct stmmac_dma_conf *dma_conf;
3894 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu);
3895 if (IS_ERR(dma_conf))
3896 return PTR_ERR(dma_conf);
3898 ret = __stmmac_open(dev, dma_conf);
3900 free_dma_desc_resources(priv, dma_conf);
3906 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3908 set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3911 destroy_workqueue(priv->fpe_wq);
3913 netdev_info(priv->dev, "FPE workqueue stop");
3917 * stmmac_release - close entry point of the driver
3918 * @dev : device pointer.
3920 * This is the stop entry point of the driver.
3922 static int stmmac_release(struct net_device *dev)
3924 struct stmmac_priv *priv = netdev_priv(dev);
3927 if (device_may_wakeup(priv->device))
3928 phylink_speed_down(priv->phylink, false);
3929 /* Stop and disconnect the PHY */
3930 phylink_stop(priv->phylink);
3931 phylink_disconnect_phy(priv->phylink);
3933 stmmac_disable_all_queues(priv);
3935 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3936 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
3938 netif_tx_disable(dev);
3940 /* Free the IRQ lines */
3941 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3943 if (priv->eee_enabled) {
3944 priv->tx_path_in_lpi_mode = false;
3945 del_timer_sync(&priv->eee_ctrl_timer);
3948 /* Stop TX/RX DMA and clear the descriptors */
3949 stmmac_stop_all_dma(priv);
3951 /* Release and free the Rx/Tx resources */
3952 free_dma_desc_resources(priv, &priv->dma_conf);
3954 /* Disable the MAC Rx/Tx */
3955 stmmac_mac_set(priv, priv->ioaddr, false);
3957 /* Powerdown Serdes if there is */
3958 if (priv->plat->serdes_powerdown)
3959 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv);
3961 netif_carrier_off(dev);
3963 stmmac_release_ptp(priv);
3965 pm_runtime_put(priv->device);
3967 if (priv->dma_cap.fpesel)
3968 stmmac_fpe_stop_wq(priv);
3973 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3974 struct stmmac_tx_queue *tx_q)
3976 u16 tag = 0x0, inner_tag = 0x0;
3977 u32 inner_type = 0x0;
3980 if (!priv->dma_cap.vlins)
3982 if (!skb_vlan_tag_present(skb))
3984 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3985 inner_tag = skb_vlan_tag_get(skb);
3986 inner_type = STMMAC_VLAN_INSERT;
3989 tag = skb_vlan_tag_get(skb);
3991 if (tx_q->tbs & STMMAC_TBS_AVAIL)
3992 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3994 p = &tx_q->dma_tx[tx_q->cur_tx];
3996 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3999 stmmac_set_tx_owner(priv, p);
4000 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4005 * stmmac_tso_allocator - close entry point of the driver
4006 * @priv: driver private structure
4007 * @des: buffer start address
4008 * @total_len: total length to fill in descriptors
4009 * @last_segment: condition for the last descriptor
4010 * @queue: TX queue index
4012 * This function fills descriptor and request new descriptors according to
4013 * buffer length to fill
4015 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
4016 int total_len, bool last_segment, u32 queue)
4018 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4019 struct dma_desc *desc;
4023 tmp_len = total_len;
4025 while (tmp_len > 0) {
4026 dma_addr_t curr_addr;
4028 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4029 priv->dma_conf.dma_tx_size);
4030 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4032 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4033 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4035 desc = &tx_q->dma_tx[tx_q->cur_tx];
4037 curr_addr = des + (total_len - tmp_len);
4038 if (priv->dma_cap.addr64 <= 32)
4039 desc->des0 = cpu_to_le32(curr_addr);
4041 stmmac_set_desc_addr(priv, desc, curr_addr);
4043 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
4044 TSO_MAX_BUFF_SIZE : tmp_len;
4046 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
4048 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
4051 tmp_len -= TSO_MAX_BUFF_SIZE;
4055 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
4057 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4060 if (likely(priv->extend_desc))
4061 desc_size = sizeof(struct dma_extended_desc);
4062 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4063 desc_size = sizeof(struct dma_edesc);
4065 desc_size = sizeof(struct dma_desc);
4067 /* The own bit must be the latest setting done when prepare the
4068 * descriptor and then barrier is needed to make sure that
4069 * all is coherent before granting the DMA engine.
4073 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
4074 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
4078 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
4079 * @skb : the socket buffer
4080 * @dev : device pointer
4081 * Description: this is the transmit function that is called on TSO frames
4082 * (support available on GMAC4 and newer chips).
4083 * Diagram below show the ring programming in case of TSO frames:
4087 * | DES0 |---> buffer1 = L2/L3/L4 header
4088 * | DES1 |---> TCP Payload (can continue on next descr...)
4089 * | DES2 |---> buffer 1 and 2 len
4090 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
4096 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
4098 * | DES2 | --> buffer 1 and 2 len
4102 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
4104 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
4106 struct dma_desc *desc, *first, *mss_desc = NULL;
4107 struct stmmac_priv *priv = netdev_priv(dev);
4108 int nfrags = skb_shinfo(skb)->nr_frags;
4109 u32 queue = skb_get_queue_mapping(skb);
4110 unsigned int first_entry, tx_packets;
4111 int tmp_pay_len = 0, first_tx;
4112 struct stmmac_tx_queue *tx_q;
4113 bool has_vlan, set_ic;
4114 u8 proto_hdr_len, hdr;
4119 tx_q = &priv->dma_conf.tx_queue[queue];
4120 first_tx = tx_q->cur_tx;
4122 /* Compute header lengths */
4123 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
4124 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
4125 hdr = sizeof(struct udphdr);
4127 proto_hdr_len = skb_tcp_all_headers(skb);
4128 hdr = tcp_hdrlen(skb);
4131 /* Desc availability based on threshold should be enough safe */
4132 if (unlikely(stmmac_tx_avail(priv, queue) <
4133 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
4134 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4135 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4137 /* This is a hard error, log it. */
4138 netdev_err(priv->dev,
4139 "%s: Tx Ring full when queue awake\n",
4142 return NETDEV_TX_BUSY;
4145 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
4147 mss = skb_shinfo(skb)->gso_size;
4149 /* set new MSS value if needed */
4150 if (mss != tx_q->mss) {
4151 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4152 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4154 mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
4156 stmmac_set_mss(priv, mss_desc, mss);
4158 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4159 priv->dma_conf.dma_tx_size);
4160 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4163 if (netif_msg_tx_queued(priv)) {
4164 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
4165 __func__, hdr, proto_hdr_len, pay_len, mss);
4166 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4170 /* Check if VLAN can be inserted by HW */
4171 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4173 first_entry = tx_q->cur_tx;
4174 WARN_ON(tx_q->tx_skbuff[first_entry]);
4176 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4177 desc = &tx_q->dma_entx[first_entry].basic;
4179 desc = &tx_q->dma_tx[first_entry];
4183 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4185 /* first descriptor: fill Headers on Buf1 */
4186 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4188 if (dma_mapping_error(priv->device, des))
4191 tx_q->tx_skbuff_dma[first_entry].buf = des;
4192 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4193 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4194 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4196 if (priv->dma_cap.addr64 <= 32) {
4197 first->des0 = cpu_to_le32(des);
4199 /* Fill start of payload in buff2 of first descriptor */
4201 first->des1 = cpu_to_le32(des + proto_hdr_len);
4203 /* If needed take extra descriptors to fill the remaining payload */
4204 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4206 stmmac_set_desc_addr(priv, first, des);
4207 tmp_pay_len = pay_len;
4208 des += proto_hdr_len;
4212 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4214 /* Prepare fragments */
4215 for (i = 0; i < nfrags; i++) {
4216 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4218 des = skb_frag_dma_map(priv->device, frag, 0,
4219 skb_frag_size(frag),
4221 if (dma_mapping_error(priv->device, des))
4224 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4225 (i == nfrags - 1), queue);
4227 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4228 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4229 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4230 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4233 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4235 /* Only the last descriptor gets to point to the skb. */
4236 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4237 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4239 /* Manage tx mitigation */
4240 tx_packets = (tx_q->cur_tx + 1) - first_tx;
4241 tx_q->tx_count_frames += tx_packets;
4243 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4245 else if (!priv->tx_coal_frames[queue])
4247 else if (tx_packets > priv->tx_coal_frames[queue])
4249 else if ((tx_q->tx_count_frames %
4250 priv->tx_coal_frames[queue]) < tx_packets)
4256 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4257 desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4259 desc = &tx_q->dma_tx[tx_q->cur_tx];
4261 tx_q->tx_count_frames = 0;
4262 stmmac_set_tx_ic(priv, desc);
4263 priv->xstats.tx_set_ic_bit++;
4266 /* We've used all descriptors we need for this skb, however,
4267 * advance cur_tx so that it references a fresh descriptor.
4268 * ndo_start_xmit will fill this descriptor the next time it's
4269 * called and stmmac_tx_clean may clean up to this descriptor.
4271 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4273 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4274 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4276 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4279 dev->stats.tx_bytes += skb->len;
4280 priv->xstats.tx_tso_frames++;
4281 priv->xstats.tx_tso_nfrags += nfrags;
4283 if (priv->sarc_type)
4284 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4286 skb_tx_timestamp(skb);
4288 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4289 priv->hwts_tx_en)) {
4290 /* declare that device is doing timestamping */
4291 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4292 stmmac_enable_tx_timestamp(priv, first);
4295 /* Complete the first descriptor before granting the DMA */
4296 stmmac_prepare_tso_tx_desc(priv, first, 1,
4299 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4300 hdr / 4, (skb->len - proto_hdr_len));
4302 /* If context desc is used to change MSS */
4304 /* Make sure that first descriptor has been completely
4305 * written, including its own bit. This is because MSS is
4306 * actually before first descriptor, so we need to make
4307 * sure that MSS's own bit is the last thing written.
4310 stmmac_set_tx_owner(priv, mss_desc);
4313 if (netif_msg_pktdata(priv)) {
4314 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4315 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4316 tx_q->cur_tx, first, nfrags);
4317 pr_info(">>> frame to be transmitted: ");
4318 print_pkt(skb->data, skb_headlen(skb));
4321 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4323 stmmac_flush_tx_descriptors(priv, queue);
4324 stmmac_tx_timer_arm(priv, queue);
4326 return NETDEV_TX_OK;
4329 dev_err(priv->device, "Tx dma map failed\n");
4331 priv->dev->stats.tx_dropped++;
4332 return NETDEV_TX_OK;
4336 * stmmac_xmit - Tx entry point of the driver
4337 * @skb : the socket buffer
4338 * @dev : device pointer
4339 * Description : this is the tx entry point of the driver.
4340 * It programs the chain or the ring and supports oversized frames
4343 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4345 unsigned int first_entry, tx_packets, enh_desc;
4346 struct stmmac_priv *priv = netdev_priv(dev);
4347 unsigned int nopaged_len = skb_headlen(skb);
4348 int i, csum_insertion = 0, is_jumbo = 0;
4349 u32 queue = skb_get_queue_mapping(skb);
4350 int nfrags = skb_shinfo(skb)->nr_frags;
4351 int gso = skb_shinfo(skb)->gso_type;
4352 struct dma_edesc *tbs_desc = NULL;
4353 struct dma_desc *desc, *first;
4354 struct stmmac_tx_queue *tx_q;
4355 bool has_vlan, set_ic;
4356 int entry, first_tx;
4359 tx_q = &priv->dma_conf.tx_queue[queue];
4360 first_tx = tx_q->cur_tx;
4362 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4363 stmmac_disable_eee_mode(priv);
4365 /* Manage oversized TCP frames for GMAC4 device */
4366 if (skb_is_gso(skb) && priv->tso) {
4367 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4368 return stmmac_tso_xmit(skb, dev);
4369 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4370 return stmmac_tso_xmit(skb, dev);
4373 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4374 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4375 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4377 /* This is a hard error, log it. */
4378 netdev_err(priv->dev,
4379 "%s: Tx Ring full when queue awake\n",
4382 return NETDEV_TX_BUSY;
4385 /* Check if VLAN can be inserted by HW */
4386 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4388 entry = tx_q->cur_tx;
4389 first_entry = entry;
4390 WARN_ON(tx_q->tx_skbuff[first_entry]);
4392 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4394 if (likely(priv->extend_desc))
4395 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4396 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4397 desc = &tx_q->dma_entx[entry].basic;
4399 desc = tx_q->dma_tx + entry;
4404 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4406 enh_desc = priv->plat->enh_desc;
4407 /* To program the descriptors according to the size of the frame */
4409 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4411 if (unlikely(is_jumbo)) {
4412 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4413 if (unlikely(entry < 0) && (entry != -EINVAL))
4417 for (i = 0; i < nfrags; i++) {
4418 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4419 int len = skb_frag_size(frag);
4420 bool last_segment = (i == (nfrags - 1));
4422 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4423 WARN_ON(tx_q->tx_skbuff[entry]);
4425 if (likely(priv->extend_desc))
4426 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4427 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4428 desc = &tx_q->dma_entx[entry].basic;
4430 desc = tx_q->dma_tx + entry;
4432 des = skb_frag_dma_map(priv->device, frag, 0, len,
4434 if (dma_mapping_error(priv->device, des))
4435 goto dma_map_err; /* should reuse desc w/o issues */
4437 tx_q->tx_skbuff_dma[entry].buf = des;
4439 stmmac_set_desc_addr(priv, desc, des);
4441 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4442 tx_q->tx_skbuff_dma[entry].len = len;
4443 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4444 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4446 /* Prepare the descriptor and set the own bit too */
4447 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4448 priv->mode, 1, last_segment, skb->len);
4451 /* Only the last descriptor gets to point to the skb. */
4452 tx_q->tx_skbuff[entry] = skb;
4453 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4455 /* According to the coalesce parameter the IC bit for the latest
4456 * segment is reset and the timer re-started to clean the tx status.
4457 * This approach takes care about the fragments: desc is the first
4458 * element in case of no SG.
4460 tx_packets = (entry + 1) - first_tx;
4461 tx_q->tx_count_frames += tx_packets;
4463 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4465 else if (!priv->tx_coal_frames[queue])
4467 else if (tx_packets > priv->tx_coal_frames[queue])
4469 else if ((tx_q->tx_count_frames %
4470 priv->tx_coal_frames[queue]) < tx_packets)
4476 if (likely(priv->extend_desc))
4477 desc = &tx_q->dma_etx[entry].basic;
4478 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4479 desc = &tx_q->dma_entx[entry].basic;
4481 desc = &tx_q->dma_tx[entry];
4483 tx_q->tx_count_frames = 0;
4484 stmmac_set_tx_ic(priv, desc);
4485 priv->xstats.tx_set_ic_bit++;
4488 /* We've used all descriptors we need for this skb, however,
4489 * advance cur_tx so that it references a fresh descriptor.
4490 * ndo_start_xmit will fill this descriptor the next time it's
4491 * called and stmmac_tx_clean may clean up to this descriptor.
4493 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4494 tx_q->cur_tx = entry;
4496 if (netif_msg_pktdata(priv)) {
4497 netdev_dbg(priv->dev,
4498 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4499 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4500 entry, first, nfrags);
4502 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4503 print_pkt(skb->data, skb->len);
4506 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4507 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4509 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4512 dev->stats.tx_bytes += skb->len;
4514 if (priv->sarc_type)
4515 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4517 skb_tx_timestamp(skb);
4519 /* Ready to fill the first descriptor and set the OWN bit w/o any
4520 * problems because all the descriptors are actually ready to be
4521 * passed to the DMA engine.
4523 if (likely(!is_jumbo)) {
4524 bool last_segment = (nfrags == 0);
4526 des = dma_map_single(priv->device, skb->data,
4527 nopaged_len, DMA_TO_DEVICE);
4528 if (dma_mapping_error(priv->device, des))
4531 tx_q->tx_skbuff_dma[first_entry].buf = des;
4532 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4533 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4535 stmmac_set_desc_addr(priv, first, des);
4537 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4538 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4540 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4541 priv->hwts_tx_en)) {
4542 /* declare that device is doing timestamping */
4543 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4544 stmmac_enable_tx_timestamp(priv, first);
4547 /* Prepare the first descriptor setting the OWN bit too */
4548 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4549 csum_insertion, priv->mode, 0, last_segment,
4553 if (tx_q->tbs & STMMAC_TBS_EN) {
4554 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4556 tbs_desc = &tx_q->dma_entx[first_entry];
4557 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4560 stmmac_set_tx_owner(priv, first);
4562 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4564 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4566 stmmac_flush_tx_descriptors(priv, queue);
4567 stmmac_tx_timer_arm(priv, queue);
4569 return NETDEV_TX_OK;
4572 netdev_err(priv->dev, "Tx DMA map failed\n");
4574 priv->dev->stats.tx_dropped++;
4575 return NETDEV_TX_OK;
4578 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4580 struct vlan_ethhdr *veth = skb_vlan_eth_hdr(skb);
4581 __be16 vlan_proto = veth->h_vlan_proto;
4584 if ((vlan_proto == htons(ETH_P_8021Q) &&
4585 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4586 (vlan_proto == htons(ETH_P_8021AD) &&
4587 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4588 /* pop the vlan tag */
4589 vlanid = ntohs(veth->h_vlan_TCI);
4590 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4591 skb_pull(skb, VLAN_HLEN);
4592 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4597 * stmmac_rx_refill - refill used skb preallocated buffers
4598 * @priv: driver private structure
4599 * @queue: RX queue index
4600 * Description : this is to reallocate the skb for the reception process
4601 * that is based on zero-copy.
4603 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4605 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
4606 int dirty = stmmac_rx_dirty(priv, queue);
4607 unsigned int entry = rx_q->dirty_rx;
4608 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4610 if (priv->dma_cap.host_dma_width <= 32)
4613 while (dirty-- > 0) {
4614 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4618 if (priv->extend_desc)
4619 p = (struct dma_desc *)(rx_q->dma_erx + entry);
4621 p = rx_q->dma_rx + entry;
4624 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4629 if (priv->sph && !buf->sec_page) {
4630 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4634 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4637 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4639 stmmac_set_desc_addr(priv, p, buf->addr);
4641 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4643 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4644 stmmac_refill_desc3(priv, rx_q, p);
4646 rx_q->rx_count_frames++;
4647 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4648 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4649 rx_q->rx_count_frames = 0;
4651 use_rx_wd = !priv->rx_coal_frames[queue];
4652 use_rx_wd |= rx_q->rx_count_frames > 0;
4653 if (!priv->use_riwt)
4657 stmmac_set_rx_owner(priv, p, use_rx_wd);
4659 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
4661 rx_q->dirty_rx = entry;
4662 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4663 (rx_q->dirty_rx * sizeof(struct dma_desc));
4664 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4667 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4669 int status, unsigned int len)
4671 unsigned int plen = 0, hlen = 0;
4672 int coe = priv->hw->rx_csum;
4674 /* Not first descriptor, buffer is always zero */
4675 if (priv->sph && len)
4678 /* First descriptor, get split header length */
4679 stmmac_get_rx_header_len(priv, p, &hlen);
4680 if (priv->sph && hlen) {
4681 priv->xstats.rx_split_hdr_pkt_n++;
4685 /* First descriptor, not last descriptor and not split header */
4686 if (status & rx_not_ls)
4687 return priv->dma_conf.dma_buf_sz;
4689 plen = stmmac_get_rx_frame_len(priv, p, coe);
4691 /* First descriptor and last descriptor and not split header */
4692 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen);
4695 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4697 int status, unsigned int len)
4699 int coe = priv->hw->rx_csum;
4700 unsigned int plen = 0;
4702 /* Not split header, buffer is not available */
4706 /* Not last descriptor */
4707 if (status & rx_not_ls)
4708 return priv->dma_conf.dma_buf_sz;
4710 plen = stmmac_get_rx_frame_len(priv, p, coe);
4712 /* Last descriptor */
4716 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4717 struct xdp_frame *xdpf, bool dma_map)
4719 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4720 unsigned int entry = tx_q->cur_tx;
4721 struct dma_desc *tx_desc;
4722 dma_addr_t dma_addr;
4725 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4726 return STMMAC_XDP_CONSUMED;
4728 if (likely(priv->extend_desc))
4729 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4730 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4731 tx_desc = &tx_q->dma_entx[entry].basic;
4733 tx_desc = tx_q->dma_tx + entry;
4736 dma_addr = dma_map_single(priv->device, xdpf->data,
4737 xdpf->len, DMA_TO_DEVICE);
4738 if (dma_mapping_error(priv->device, dma_addr))
4739 return STMMAC_XDP_CONSUMED;
4741 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4743 struct page *page = virt_to_page(xdpf->data);
4745 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4747 dma_sync_single_for_device(priv->device, dma_addr,
4748 xdpf->len, DMA_BIDIRECTIONAL);
4750 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4753 tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4754 tx_q->tx_skbuff_dma[entry].map_as_page = false;
4755 tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4756 tx_q->tx_skbuff_dma[entry].last_segment = true;
4757 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4759 tx_q->xdpf[entry] = xdpf;
4761 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4763 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4764 true, priv->mode, true, true,
4767 tx_q->tx_count_frames++;
4769 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4775 tx_q->tx_count_frames = 0;
4776 stmmac_set_tx_ic(priv, tx_desc);
4777 priv->xstats.tx_set_ic_bit++;
4780 stmmac_enable_dma_transmission(priv, priv->ioaddr);
4782 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4783 tx_q->cur_tx = entry;
4785 return STMMAC_XDP_TX;
4788 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4793 if (unlikely(index < 0))
4796 while (index >= priv->plat->tx_queues_to_use)
4797 index -= priv->plat->tx_queues_to_use;
4802 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4803 struct xdp_buff *xdp)
4805 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4806 int cpu = smp_processor_id();
4807 struct netdev_queue *nq;
4811 if (unlikely(!xdpf))
4812 return STMMAC_XDP_CONSUMED;
4814 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4815 nq = netdev_get_tx_queue(priv->dev, queue);
4817 __netif_tx_lock(nq, cpu);
4818 /* Avoids TX time-out as we are sharing with slow path */
4819 txq_trans_cond_update(nq);
4821 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4822 if (res == STMMAC_XDP_TX)
4823 stmmac_flush_tx_descriptors(priv, queue);
4825 __netif_tx_unlock(nq);
4830 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4831 struct bpf_prog *prog,
4832 struct xdp_buff *xdp)
4837 act = bpf_prog_run_xdp(prog, xdp);
4840 res = STMMAC_XDP_PASS;
4843 res = stmmac_xdp_xmit_back(priv, xdp);
4846 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4847 res = STMMAC_XDP_CONSUMED;
4849 res = STMMAC_XDP_REDIRECT;
4852 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
4855 trace_xdp_exception(priv->dev, prog, act);
4858 res = STMMAC_XDP_CONSUMED;
4865 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4866 struct xdp_buff *xdp)
4868 struct bpf_prog *prog;
4871 prog = READ_ONCE(priv->xdp_prog);
4873 res = STMMAC_XDP_PASS;
4877 res = __stmmac_xdp_run_prog(priv, prog, xdp);
4879 return ERR_PTR(-res);
4882 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4885 int cpu = smp_processor_id();
4888 queue = stmmac_xdp_get_tx_queue(priv, cpu);
4890 if (xdp_status & STMMAC_XDP_TX)
4891 stmmac_tx_timer_arm(priv, queue);
4893 if (xdp_status & STMMAC_XDP_REDIRECT)
4897 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4898 struct xdp_buff *xdp)
4900 unsigned int metasize = xdp->data - xdp->data_meta;
4901 unsigned int datasize = xdp->data_end - xdp->data;
4902 struct sk_buff *skb;
4904 skb = __napi_alloc_skb(&ch->rxtx_napi,
4905 xdp->data_end - xdp->data_hard_start,
4906 GFP_ATOMIC | __GFP_NOWARN);
4910 skb_reserve(skb, xdp->data - xdp->data_hard_start);
4911 memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4913 skb_metadata_set(skb, metasize);
4918 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4919 struct dma_desc *p, struct dma_desc *np,
4920 struct xdp_buff *xdp)
4922 struct stmmac_channel *ch = &priv->channel[queue];
4923 unsigned int len = xdp->data_end - xdp->data;
4924 enum pkt_hash_types hash_type;
4925 int coe = priv->hw->rx_csum;
4926 struct sk_buff *skb;
4929 skb = stmmac_construct_skb_zc(ch, xdp);
4931 priv->dev->stats.rx_dropped++;
4935 stmmac_get_rx_hwtstamp(priv, p, np, skb);
4936 stmmac_rx_vlan(priv->dev, skb);
4937 skb->protocol = eth_type_trans(skb, priv->dev);
4940 skb_checksum_none_assert(skb);
4942 skb->ip_summed = CHECKSUM_UNNECESSARY;
4944 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4945 skb_set_hash(skb, hash, hash_type);
4947 skb_record_rx_queue(skb, queue);
4948 napi_gro_receive(&ch->rxtx_napi, skb);
4950 priv->dev->stats.rx_packets++;
4951 priv->dev->stats.rx_bytes += len;
4954 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4956 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
4957 unsigned int entry = rx_q->dirty_rx;
4958 struct dma_desc *rx_desc = NULL;
4961 budget = min(budget, stmmac_rx_dirty(priv, queue));
4963 while (budget-- > 0 && entry != rx_q->cur_rx) {
4964 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4965 dma_addr_t dma_addr;
4969 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4976 if (priv->extend_desc)
4977 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4979 rx_desc = rx_q->dma_rx + entry;
4981 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4982 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4983 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4984 stmmac_refill_desc3(priv, rx_q, rx_desc);
4986 rx_q->rx_count_frames++;
4987 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4988 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4989 rx_q->rx_count_frames = 0;
4991 use_rx_wd = !priv->rx_coal_frames[queue];
4992 use_rx_wd |= rx_q->rx_count_frames > 0;
4993 if (!priv->use_riwt)
4997 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4999 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
5003 rx_q->dirty_rx = entry;
5004 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
5005 (rx_q->dirty_rx * sizeof(struct dma_desc));
5006 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
5012 static struct stmmac_xdp_buff *xsk_buff_to_stmmac_ctx(struct xdp_buff *xdp)
5014 /* In XDP zero copy data path, xdp field in struct xdp_buff_xsk is used
5015 * to represent incoming packet, whereas cb field in the same structure
5016 * is used to store driver specific info. Thus, struct stmmac_xdp_buff
5017 * is laid on top of xdp and cb fields of struct xdp_buff_xsk.
5019 return (struct stmmac_xdp_buff *)xdp;
5022 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
5024 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5025 unsigned int count = 0, error = 0, len = 0;
5026 int dirty = stmmac_rx_dirty(priv, queue);
5027 unsigned int next_entry = rx_q->cur_rx;
5028 unsigned int desc_size;
5029 struct bpf_prog *prog;
5030 bool failure = false;
5034 if (netif_msg_rx_status(priv)) {
5037 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5038 if (priv->extend_desc) {
5039 rx_head = (void *)rx_q->dma_erx;
5040 desc_size = sizeof(struct dma_extended_desc);
5042 rx_head = (void *)rx_q->dma_rx;
5043 desc_size = sizeof(struct dma_desc);
5046 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5047 rx_q->dma_rx_phy, desc_size);
5049 while (count < limit) {
5050 struct stmmac_rx_buffer *buf;
5051 struct stmmac_xdp_buff *ctx;
5052 unsigned int buf1_len = 0;
5053 struct dma_desc *np, *p;
5057 if (!count && rx_q->state_saved) {
5058 error = rx_q->state.error;
5059 len = rx_q->state.len;
5061 rx_q->state_saved = false;
5072 buf = &rx_q->buf_pool[entry];
5074 if (dirty >= STMMAC_RX_FILL_BATCH) {
5075 failure = failure ||
5076 !stmmac_rx_refill_zc(priv, queue, dirty);
5080 if (priv->extend_desc)
5081 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5083 p = rx_q->dma_rx + entry;
5085 /* read the status of the incoming frame */
5086 status = stmmac_rx_status(priv, &priv->dev->stats,
5088 /* check if managed by the DMA otherwise go ahead */
5089 if (unlikely(status & dma_own))
5092 /* Prefetch the next RX descriptor */
5093 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5094 priv->dma_conf.dma_rx_size);
5095 next_entry = rx_q->cur_rx;
5097 if (priv->extend_desc)
5098 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5100 np = rx_q->dma_rx + next_entry;
5104 /* Ensure a valid XSK buffer before proceed */
5108 if (priv->extend_desc)
5109 stmmac_rx_extended_status(priv, &priv->dev->stats,
5111 rx_q->dma_erx + entry);
5112 if (unlikely(status == discard_frame)) {
5113 xsk_buff_free(buf->xdp);
5117 if (!priv->hwts_rx_en)
5118 priv->dev->stats.rx_errors++;
5121 if (unlikely(error && (status & rx_not_ls)))
5123 if (unlikely(error)) {
5128 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
5129 if (likely(status & rx_not_ls)) {
5130 xsk_buff_free(buf->xdp);
5137 ctx = xsk_buff_to_stmmac_ctx(buf->xdp);
5142 /* XDP ZC Frame only support primary buffers for now */
5143 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5146 /* ACS is disabled; strip manually. */
5147 if (likely(!(status & rx_not_ls))) {
5148 buf1_len -= ETH_FCS_LEN;
5152 /* RX buffer is good and fit into a XSK pool buffer */
5153 buf->xdp->data_end = buf->xdp->data + buf1_len;
5154 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
5156 prog = READ_ONCE(priv->xdp_prog);
5157 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
5160 case STMMAC_XDP_PASS:
5161 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
5162 xsk_buff_free(buf->xdp);
5164 case STMMAC_XDP_CONSUMED:
5165 xsk_buff_free(buf->xdp);
5166 priv->dev->stats.rx_dropped++;
5169 case STMMAC_XDP_REDIRECT:
5179 if (status & rx_not_ls) {
5180 rx_q->state_saved = true;
5181 rx_q->state.error = error;
5182 rx_q->state.len = len;
5185 stmmac_finalize_xdp_rx(priv, xdp_status);
5187 priv->xstats.rx_pkt_n += count;
5188 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5190 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5191 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5192 xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5194 xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5199 return failure ? limit : (int)count;
5203 * stmmac_rx - manage the receive process
5204 * @priv: driver private structure
5205 * @limit: napi bugget
5206 * @queue: RX queue index.
5207 * Description : this the function called by the napi poll method.
5208 * It gets all the frames inside the ring.
5210 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5212 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5213 struct stmmac_channel *ch = &priv->channel[queue];
5214 unsigned int count = 0, error = 0, len = 0;
5215 int status = 0, coe = priv->hw->rx_csum;
5216 unsigned int next_entry = rx_q->cur_rx;
5217 enum dma_data_direction dma_dir;
5218 unsigned int desc_size;
5219 struct sk_buff *skb = NULL;
5220 struct stmmac_xdp_buff ctx;
5224 dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5225 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5227 if (netif_msg_rx_status(priv)) {
5230 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5231 if (priv->extend_desc) {
5232 rx_head = (void *)rx_q->dma_erx;
5233 desc_size = sizeof(struct dma_extended_desc);
5235 rx_head = (void *)rx_q->dma_rx;
5236 desc_size = sizeof(struct dma_desc);
5239 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5240 rx_q->dma_rx_phy, desc_size);
5242 while (count < limit) {
5243 unsigned int buf1_len = 0, buf2_len = 0;
5244 enum pkt_hash_types hash_type;
5245 struct stmmac_rx_buffer *buf;
5246 struct dma_desc *np, *p;
5250 if (!count && rx_q->state_saved) {
5251 skb = rx_q->state.skb;
5252 error = rx_q->state.error;
5253 len = rx_q->state.len;
5255 rx_q->state_saved = false;
5268 buf = &rx_q->buf_pool[entry];
5270 if (priv->extend_desc)
5271 p = (struct dma_desc *)(rx_q->dma_erx + entry);
5273 p = rx_q->dma_rx + entry;
5275 /* read the status of the incoming frame */
5276 status = stmmac_rx_status(priv, &priv->dev->stats,
5278 /* check if managed by the DMA otherwise go ahead */
5279 if (unlikely(status & dma_own))
5282 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5283 priv->dma_conf.dma_rx_size);
5284 next_entry = rx_q->cur_rx;
5286 if (priv->extend_desc)
5287 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5289 np = rx_q->dma_rx + next_entry;
5293 if (priv->extend_desc)
5294 stmmac_rx_extended_status(priv, &priv->dev->stats,
5295 &priv->xstats, rx_q->dma_erx + entry);
5296 if (unlikely(status == discard_frame)) {
5297 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5300 if (!priv->hwts_rx_en)
5301 priv->dev->stats.rx_errors++;
5304 if (unlikely(error && (status & rx_not_ls)))
5306 if (unlikely(error)) {
5313 /* Buffer is good. Go on. */
5315 prefetch(page_address(buf->page) + buf->page_offset);
5317 prefetch(page_address(buf->sec_page));
5319 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5321 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5324 /* ACS is disabled; strip manually. */
5325 if (likely(!(status & rx_not_ls))) {
5327 buf2_len -= ETH_FCS_LEN;
5329 } else if (buf1_len) {
5330 buf1_len -= ETH_FCS_LEN;
5336 unsigned int pre_len, sync_len;
5338 dma_sync_single_for_cpu(priv->device, buf->addr,
5341 xdp_init_buff(&ctx.xdp, buf_sz, &rx_q->xdp_rxq);
5342 xdp_prepare_buff(&ctx.xdp, page_address(buf->page),
5343 buf->page_offset, buf1_len, true);
5345 pre_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5352 skb = stmmac_xdp_run_prog(priv, &ctx.xdp);
5353 /* Due xdp_adjust_tail: DMA sync for_device
5354 * cover max len CPU touch
5356 sync_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5358 sync_len = max(sync_len, pre_len);
5360 /* For Not XDP_PASS verdict */
5362 unsigned int xdp_res = -PTR_ERR(skb);
5364 if (xdp_res & STMMAC_XDP_CONSUMED) {
5365 page_pool_put_page(rx_q->page_pool,
5366 virt_to_head_page(ctx.xdp.data),
5369 priv->dev->stats.rx_dropped++;
5371 /* Clear skb as it was set as
5372 * status by XDP program.
5376 if (unlikely((status & rx_not_ls)))
5381 } else if (xdp_res & (STMMAC_XDP_TX |
5382 STMMAC_XDP_REDIRECT)) {
5383 xdp_status |= xdp_res;
5393 /* XDP program may expand or reduce tail */
5394 buf1_len = ctx.xdp.data_end - ctx.xdp.data;
5396 skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5398 priv->dev->stats.rx_dropped++;
5403 /* XDP program may adjust header */
5404 skb_copy_to_linear_data(skb, ctx.xdp.data, buf1_len);
5405 skb_put(skb, buf1_len);
5407 /* Data payload copied into SKB, page ready for recycle */
5408 page_pool_recycle_direct(rx_q->page_pool, buf->page);
5410 } else if (buf1_len) {
5411 dma_sync_single_for_cpu(priv->device, buf->addr,
5413 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5414 buf->page, buf->page_offset, buf1_len,
5415 priv->dma_conf.dma_buf_sz);
5417 /* Data payload appended into SKB */
5418 page_pool_release_page(rx_q->page_pool, buf->page);
5423 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5425 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5426 buf->sec_page, 0, buf2_len,
5427 priv->dma_conf.dma_buf_sz);
5429 /* Data payload appended into SKB */
5430 page_pool_release_page(rx_q->page_pool, buf->sec_page);
5431 buf->sec_page = NULL;
5435 if (likely(status & rx_not_ls))
5440 /* Got entire packet into SKB. Finish it. */
5442 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5443 stmmac_rx_vlan(priv->dev, skb);
5444 skb->protocol = eth_type_trans(skb, priv->dev);
5447 skb_checksum_none_assert(skb);
5449 skb->ip_summed = CHECKSUM_UNNECESSARY;
5451 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5452 skb_set_hash(skb, hash, hash_type);
5454 skb_record_rx_queue(skb, queue);
5455 napi_gro_receive(&ch->rx_napi, skb);
5458 priv->dev->stats.rx_packets++;
5459 priv->dev->stats.rx_bytes += len;
5463 if (status & rx_not_ls || skb) {
5464 rx_q->state_saved = true;
5465 rx_q->state.skb = skb;
5466 rx_q->state.error = error;
5467 rx_q->state.len = len;
5470 stmmac_finalize_xdp_rx(priv, xdp_status);
5472 stmmac_rx_refill(priv, queue);
5474 priv->xstats.rx_pkt_n += count;
5475 priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5480 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5482 struct stmmac_channel *ch =
5483 container_of(napi, struct stmmac_channel, rx_napi);
5484 struct stmmac_priv *priv = ch->priv_data;
5485 u32 chan = ch->index;
5488 priv->xstats.napi_poll++;
5490 work_done = stmmac_rx(priv, budget, chan);
5491 if (work_done < budget && napi_complete_done(napi, work_done)) {
5492 unsigned long flags;
5494 spin_lock_irqsave(&ch->lock, flags);
5495 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5496 spin_unlock_irqrestore(&ch->lock, flags);
5502 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5504 struct stmmac_channel *ch =
5505 container_of(napi, struct stmmac_channel, tx_napi);
5506 struct stmmac_priv *priv = ch->priv_data;
5507 u32 chan = ch->index;
5510 priv->xstats.napi_poll++;
5512 work_done = stmmac_tx_clean(priv, budget, chan);
5513 work_done = min(work_done, budget);
5515 if (work_done < budget && napi_complete_done(napi, work_done)) {
5516 unsigned long flags;
5518 spin_lock_irqsave(&ch->lock, flags);
5519 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5520 spin_unlock_irqrestore(&ch->lock, flags);
5526 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5528 struct stmmac_channel *ch =
5529 container_of(napi, struct stmmac_channel, rxtx_napi);
5530 struct stmmac_priv *priv = ch->priv_data;
5531 int rx_done, tx_done, rxtx_done;
5532 u32 chan = ch->index;
5534 priv->xstats.napi_poll++;
5536 tx_done = stmmac_tx_clean(priv, budget, chan);
5537 tx_done = min(tx_done, budget);
5539 rx_done = stmmac_rx_zc(priv, budget, chan);
5541 rxtx_done = max(tx_done, rx_done);
5543 /* If either TX or RX work is not complete, return budget
5546 if (rxtx_done >= budget)
5549 /* all work done, exit the polling mode */
5550 if (napi_complete_done(napi, rxtx_done)) {
5551 unsigned long flags;
5553 spin_lock_irqsave(&ch->lock, flags);
5554 /* Both RX and TX work done are compelte,
5555 * so enable both RX & TX IRQs.
5557 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5558 spin_unlock_irqrestore(&ch->lock, flags);
5561 return min(rxtx_done, budget - 1);
5566 * @dev : Pointer to net device structure
5567 * @txqueue: the index of the hanging transmit queue
5568 * Description: this function is called when a packet transmission fails to
5569 * complete within a reasonable time. The driver will mark the error in the
5570 * netdev structure and arrange for the device to be reset to a sane state
5571 * in order to transmit a new packet.
5573 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5575 struct stmmac_priv *priv = netdev_priv(dev);
5577 stmmac_global_err(priv);
5581 * stmmac_set_rx_mode - entry point for multicast addressing
5582 * @dev : pointer to the device structure
5584 * This function is a driver entry point which gets called by the kernel
5585 * whenever multicast addresses must be enabled/disabled.
5589 static void stmmac_set_rx_mode(struct net_device *dev)
5591 struct stmmac_priv *priv = netdev_priv(dev);
5593 stmmac_set_filter(priv, priv->hw, dev);
5597 * stmmac_change_mtu - entry point to change MTU size for the device.
5598 * @dev : device pointer.
5599 * @new_mtu : the new MTU size for the device.
5600 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
5601 * to drive packet transmission. Ethernet has an MTU of 1500 octets
5602 * (ETH_DATA_LEN). This value can be changed with ifconfig.
5604 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5607 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5609 struct stmmac_priv *priv = netdev_priv(dev);
5610 int txfifosz = priv->plat->tx_fifo_size;
5611 struct stmmac_dma_conf *dma_conf;
5612 const int mtu = new_mtu;
5616 txfifosz = priv->dma_cap.tx_fifo_size;
5618 txfifosz /= priv->plat->tx_queues_to_use;
5620 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5621 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5625 new_mtu = STMMAC_ALIGN(new_mtu);
5627 /* If condition true, FIFO is too small or MTU too large */
5628 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5631 if (netif_running(dev)) {
5632 netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
5633 /* Try to allocate the new DMA conf with the new mtu */
5634 dma_conf = stmmac_setup_dma_desc(priv, mtu);
5635 if (IS_ERR(dma_conf)) {
5636 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n",
5638 return PTR_ERR(dma_conf);
5641 stmmac_release(dev);
5643 ret = __stmmac_open(dev, dma_conf);
5645 free_dma_desc_resources(priv, dma_conf);
5647 netdev_err(priv->dev, "failed reopening the interface after MTU change\n");
5653 stmmac_set_rx_mode(dev);
5657 netdev_update_features(dev);
5662 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5663 netdev_features_t features)
5665 struct stmmac_priv *priv = netdev_priv(dev);
5667 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5668 features &= ~NETIF_F_RXCSUM;
5670 if (!priv->plat->tx_coe)
5671 features &= ~NETIF_F_CSUM_MASK;
5673 /* Some GMAC devices have a bugged Jumbo frame support that
5674 * needs to have the Tx COE disabled for oversized frames
5675 * (due to limited buffer sizes). In this case we disable
5676 * the TX csum insertion in the TDES and not use SF.
5678 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5679 features &= ~NETIF_F_CSUM_MASK;
5681 /* Disable tso if asked by ethtool */
5682 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
5683 if (features & NETIF_F_TSO)
5692 static int stmmac_set_features(struct net_device *netdev,
5693 netdev_features_t features)
5695 struct stmmac_priv *priv = netdev_priv(netdev);
5697 /* Keep the COE Type in case of csum is supporting */
5698 if (features & NETIF_F_RXCSUM)
5699 priv->hw->rx_csum = priv->plat->rx_coe;
5701 priv->hw->rx_csum = 0;
5702 /* No check needed because rx_coe has been set before and it will be
5703 * fixed in case of issue.
5705 stmmac_rx_ipc(priv, priv->hw);
5707 if (priv->sph_cap) {
5708 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5711 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5712 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5718 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5720 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5721 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5722 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5723 bool *hs_enable = &fpe_cfg->hs_enable;
5725 if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5728 /* If LP has sent verify mPacket, LP is FPE capable */
5729 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5730 if (*lp_state < FPE_STATE_CAPABLE)
5731 *lp_state = FPE_STATE_CAPABLE;
5733 /* If user has requested FPE enable, quickly response */
5735 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5739 /* If Local has sent verify mPacket, Local is FPE capable */
5740 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5741 if (*lo_state < FPE_STATE_CAPABLE)
5742 *lo_state = FPE_STATE_CAPABLE;
5745 /* If LP has sent response mPacket, LP is entering FPE ON */
5746 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5747 *lp_state = FPE_STATE_ENTERING_ON;
5749 /* If Local has sent response mPacket, Local is entering FPE ON */
5750 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5751 *lo_state = FPE_STATE_ENTERING_ON;
5753 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5754 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5756 queue_work(priv->fpe_wq, &priv->fpe_task);
5760 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5762 u32 rx_cnt = priv->plat->rx_queues_to_use;
5763 u32 tx_cnt = priv->plat->tx_queues_to_use;
5768 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5769 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5772 pm_wakeup_event(priv->device, 0);
5774 if (priv->dma_cap.estsel)
5775 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5776 &priv->xstats, tx_cnt);
5778 if (priv->dma_cap.fpesel) {
5779 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5782 stmmac_fpe_event_status(priv, status);
5785 /* To handle GMAC own interrupts */
5786 if ((priv->plat->has_gmac) || xmac) {
5787 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5789 if (unlikely(status)) {
5790 /* For LPI we need to save the tx status */
5791 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5792 priv->tx_path_in_lpi_mode = true;
5793 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5794 priv->tx_path_in_lpi_mode = false;
5797 for (queue = 0; queue < queues_count; queue++) {
5798 status = stmmac_host_mtl_irq_status(priv, priv->hw,
5802 /* PCS link status */
5803 if (priv->hw->pcs &&
5804 !(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS)) {
5805 if (priv->xstats.pcs_link)
5806 netif_carrier_on(priv->dev);
5808 netif_carrier_off(priv->dev);
5811 stmmac_timestamp_interrupt(priv, priv);
5816 * stmmac_interrupt - main ISR
5817 * @irq: interrupt number.
5818 * @dev_id: to pass the net device pointer.
5819 * Description: this is the main driver interrupt service routine.
5821 * o DMA service routine (to manage incoming frame reception and transmission
5823 * o Core interrupts to manage: remote wake-up, management counter, LPI
5826 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5828 struct net_device *dev = (struct net_device *)dev_id;
5829 struct stmmac_priv *priv = netdev_priv(dev);
5831 /* Check if adapter is up */
5832 if (test_bit(STMMAC_DOWN, &priv->state))
5835 /* Check if a fatal error happened */
5836 if (stmmac_safety_feat_interrupt(priv))
5839 /* To handle Common interrupts */
5840 stmmac_common_interrupt(priv);
5842 /* To handle DMA interrupts */
5843 stmmac_dma_interrupt(priv);
5848 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5850 struct net_device *dev = (struct net_device *)dev_id;
5851 struct stmmac_priv *priv = netdev_priv(dev);
5853 if (unlikely(!dev)) {
5854 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5858 /* Check if adapter is up */
5859 if (test_bit(STMMAC_DOWN, &priv->state))
5862 /* To handle Common interrupts */
5863 stmmac_common_interrupt(priv);
5868 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5870 struct net_device *dev = (struct net_device *)dev_id;
5871 struct stmmac_priv *priv = netdev_priv(dev);
5873 if (unlikely(!dev)) {
5874 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5878 /* Check if adapter is up */
5879 if (test_bit(STMMAC_DOWN, &priv->state))
5882 /* Check if a fatal error happened */
5883 stmmac_safety_feat_interrupt(priv);
5888 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5890 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5891 struct stmmac_dma_conf *dma_conf;
5892 int chan = tx_q->queue_index;
5893 struct stmmac_priv *priv;
5896 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]);
5897 priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
5899 if (unlikely(!data)) {
5900 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5904 /* Check if adapter is up */
5905 if (test_bit(STMMAC_DOWN, &priv->state))
5908 status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5910 if (unlikely(status & tx_hard_error_bump_tc)) {
5911 /* Try to bump up the dma threshold on this failure */
5912 stmmac_bump_dma_threshold(priv, chan);
5913 } else if (unlikely(status == tx_hard_error)) {
5914 stmmac_tx_err(priv, chan);
5920 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5922 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5923 struct stmmac_dma_conf *dma_conf;
5924 int chan = rx_q->queue_index;
5925 struct stmmac_priv *priv;
5927 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]);
5928 priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
5930 if (unlikely(!data)) {
5931 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5935 /* Check if adapter is up */
5936 if (test_bit(STMMAC_DOWN, &priv->state))
5939 stmmac_napi_check(priv, chan, DMA_DIR_RX);
5944 #ifdef CONFIG_NET_POLL_CONTROLLER
5945 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5946 * to allow network I/O with interrupts disabled.
5948 static void stmmac_poll_controller(struct net_device *dev)
5950 struct stmmac_priv *priv = netdev_priv(dev);
5953 /* If adapter is down, do nothing */
5954 if (test_bit(STMMAC_DOWN, &priv->state))
5957 if (priv->plat->multi_msi_en) {
5958 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5959 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]);
5961 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5962 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]);
5964 disable_irq(dev->irq);
5965 stmmac_interrupt(dev->irq, dev);
5966 enable_irq(dev->irq);
5972 * stmmac_ioctl - Entry point for the Ioctl
5973 * @dev: Device pointer.
5974 * @rq: An IOCTL specefic structure, that can contain a pointer to
5975 * a proprietary structure used to pass information to the driver.
5976 * @cmd: IOCTL command
5978 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5980 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5982 struct stmmac_priv *priv = netdev_priv (dev);
5983 int ret = -EOPNOTSUPP;
5985 if (!netif_running(dev))
5992 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5995 ret = stmmac_hwtstamp_set(dev, rq);
5998 ret = stmmac_hwtstamp_get(dev, rq);
6007 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
6010 struct stmmac_priv *priv = cb_priv;
6011 int ret = -EOPNOTSUPP;
6013 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
6016 __stmmac_disable_all_queues(priv);
6019 case TC_SETUP_CLSU32:
6020 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
6022 case TC_SETUP_CLSFLOWER:
6023 ret = stmmac_tc_setup_cls(priv, priv, type_data);
6029 stmmac_enable_all_queues(priv);
6033 static LIST_HEAD(stmmac_block_cb_list);
6035 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
6038 struct stmmac_priv *priv = netdev_priv(ndev);
6042 return stmmac_tc_query_caps(priv, priv, type_data);
6043 case TC_SETUP_BLOCK:
6044 return flow_block_cb_setup_simple(type_data,
6045 &stmmac_block_cb_list,
6046 stmmac_setup_tc_block_cb,
6048 case TC_SETUP_QDISC_CBS:
6049 return stmmac_tc_setup_cbs(priv, priv, type_data);
6050 case TC_SETUP_QDISC_TAPRIO:
6051 return stmmac_tc_setup_taprio(priv, priv, type_data);
6052 case TC_SETUP_QDISC_ETF:
6053 return stmmac_tc_setup_etf(priv, priv, type_data);
6059 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
6060 struct net_device *sb_dev)
6062 int gso = skb_shinfo(skb)->gso_type;
6064 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
6066 * There is no way to determine the number of TSO/USO
6067 * capable Queues. Let's use always the Queue 0
6068 * because if TSO/USO is supported then at least this
6069 * one will be capable.
6074 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
6077 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
6079 struct stmmac_priv *priv = netdev_priv(ndev);
6082 ret = pm_runtime_resume_and_get(priv->device);
6086 ret = eth_mac_addr(ndev, addr);
6090 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
6093 pm_runtime_put(priv->device);
6098 #ifdef CONFIG_DEBUG_FS
6099 static struct dentry *stmmac_fs_dir;
6101 static void sysfs_display_ring(void *head, int size, int extend_desc,
6102 struct seq_file *seq, dma_addr_t dma_phy_addr)
6105 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
6106 struct dma_desc *p = (struct dma_desc *)head;
6107 dma_addr_t dma_addr;
6109 for (i = 0; i < size; i++) {
6111 dma_addr = dma_phy_addr + i * sizeof(*ep);
6112 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
6114 le32_to_cpu(ep->basic.des0),
6115 le32_to_cpu(ep->basic.des1),
6116 le32_to_cpu(ep->basic.des2),
6117 le32_to_cpu(ep->basic.des3));
6120 dma_addr = dma_phy_addr + i * sizeof(*p);
6121 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
6123 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
6124 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
6127 seq_printf(seq, "\n");
6131 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
6133 struct net_device *dev = seq->private;
6134 struct stmmac_priv *priv = netdev_priv(dev);
6135 u32 rx_count = priv->plat->rx_queues_to_use;
6136 u32 tx_count = priv->plat->tx_queues_to_use;
6139 if ((dev->flags & IFF_UP) == 0)
6142 for (queue = 0; queue < rx_count; queue++) {
6143 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6145 seq_printf(seq, "RX Queue %d:\n", queue);
6147 if (priv->extend_desc) {
6148 seq_printf(seq, "Extended descriptor ring:\n");
6149 sysfs_display_ring((void *)rx_q->dma_erx,
6150 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy);
6152 seq_printf(seq, "Descriptor ring:\n");
6153 sysfs_display_ring((void *)rx_q->dma_rx,
6154 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy);
6158 for (queue = 0; queue < tx_count; queue++) {
6159 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6161 seq_printf(seq, "TX Queue %d:\n", queue);
6163 if (priv->extend_desc) {
6164 seq_printf(seq, "Extended descriptor ring:\n");
6165 sysfs_display_ring((void *)tx_q->dma_etx,
6166 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy);
6167 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
6168 seq_printf(seq, "Descriptor ring:\n");
6169 sysfs_display_ring((void *)tx_q->dma_tx,
6170 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy);
6176 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
6178 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
6180 struct net_device *dev = seq->private;
6181 struct stmmac_priv *priv = netdev_priv(dev);
6183 if (!priv->hw_cap_support) {
6184 seq_printf(seq, "DMA HW features not supported\n");
6188 seq_printf(seq, "==============================\n");
6189 seq_printf(seq, "\tDMA HW features\n");
6190 seq_printf(seq, "==============================\n");
6192 seq_printf(seq, "\t10/100 Mbps: %s\n",
6193 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6194 seq_printf(seq, "\t1000 Mbps: %s\n",
6195 (priv->dma_cap.mbps_1000) ? "Y" : "N");
6196 seq_printf(seq, "\tHalf duplex: %s\n",
6197 (priv->dma_cap.half_duplex) ? "Y" : "N");
6198 seq_printf(seq, "\tHash Filter: %s\n",
6199 (priv->dma_cap.hash_filter) ? "Y" : "N");
6200 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6201 (priv->dma_cap.multi_addr) ? "Y" : "N");
6202 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6203 (priv->dma_cap.pcs) ? "Y" : "N");
6204 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6205 (priv->dma_cap.sma_mdio) ? "Y" : "N");
6206 seq_printf(seq, "\tPMT Remote wake up: %s\n",
6207 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6208 seq_printf(seq, "\tPMT Magic Frame: %s\n",
6209 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6210 seq_printf(seq, "\tRMON module: %s\n",
6211 (priv->dma_cap.rmon) ? "Y" : "N");
6212 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6213 (priv->dma_cap.time_stamp) ? "Y" : "N");
6214 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6215 (priv->dma_cap.atime_stamp) ? "Y" : "N");
6216 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6217 (priv->dma_cap.eee) ? "Y" : "N");
6218 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6219 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6220 (priv->dma_cap.tx_coe) ? "Y" : "N");
6221 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6222 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6223 (priv->dma_cap.rx_coe) ? "Y" : "N");
6225 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6226 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6227 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6228 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6230 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6231 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6232 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6233 priv->dma_cap.number_rx_channel);
6234 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6235 priv->dma_cap.number_tx_channel);
6236 seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6237 priv->dma_cap.number_rx_queues);
6238 seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6239 priv->dma_cap.number_tx_queues);
6240 seq_printf(seq, "\tEnhanced descriptors: %s\n",
6241 (priv->dma_cap.enh_desc) ? "Y" : "N");
6242 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6243 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6244 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6245 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6246 seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6247 priv->dma_cap.pps_out_num);
6248 seq_printf(seq, "\tSafety Features: %s\n",
6249 priv->dma_cap.asp ? "Y" : "N");
6250 seq_printf(seq, "\tFlexible RX Parser: %s\n",
6251 priv->dma_cap.frpsel ? "Y" : "N");
6252 seq_printf(seq, "\tEnhanced Addressing: %d\n",
6253 priv->dma_cap.host_dma_width);
6254 seq_printf(seq, "\tReceive Side Scaling: %s\n",
6255 priv->dma_cap.rssen ? "Y" : "N");
6256 seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6257 priv->dma_cap.vlhash ? "Y" : "N");
6258 seq_printf(seq, "\tSplit Header: %s\n",
6259 priv->dma_cap.sphen ? "Y" : "N");
6260 seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6261 priv->dma_cap.vlins ? "Y" : "N");
6262 seq_printf(seq, "\tDouble VLAN: %s\n",
6263 priv->dma_cap.dvlan ? "Y" : "N");
6264 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6265 priv->dma_cap.l3l4fnum);
6266 seq_printf(seq, "\tARP Offloading: %s\n",
6267 priv->dma_cap.arpoffsel ? "Y" : "N");
6268 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6269 priv->dma_cap.estsel ? "Y" : "N");
6270 seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6271 priv->dma_cap.fpesel ? "Y" : "N");
6272 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6273 priv->dma_cap.tbssel ? "Y" : "N");
6276 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6278 /* Use network device events to rename debugfs file entries.
6280 static int stmmac_device_event(struct notifier_block *unused,
6281 unsigned long event, void *ptr)
6283 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6284 struct stmmac_priv *priv = netdev_priv(dev);
6286 if (dev->netdev_ops != &stmmac_netdev_ops)
6290 case NETDEV_CHANGENAME:
6291 if (priv->dbgfs_dir)
6292 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6302 static struct notifier_block stmmac_notifier = {
6303 .notifier_call = stmmac_device_event,
6306 static void stmmac_init_fs(struct net_device *dev)
6308 struct stmmac_priv *priv = netdev_priv(dev);
6312 /* Create per netdev entries */
6313 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6315 /* Entry to report DMA RX/TX rings */
6316 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6317 &stmmac_rings_status_fops);
6319 /* Entry to report the DMA HW features */
6320 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6321 &stmmac_dma_cap_fops);
6326 static void stmmac_exit_fs(struct net_device *dev)
6328 struct stmmac_priv *priv = netdev_priv(dev);
6330 debugfs_remove_recursive(priv->dbgfs_dir);
6332 #endif /* CONFIG_DEBUG_FS */
6334 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6336 unsigned char *data = (unsigned char *)&vid_le;
6337 unsigned char data_byte = 0;
6342 bits = get_bitmask_order(VLAN_VID_MASK);
6343 for (i = 0; i < bits; i++) {
6345 data_byte = data[i / 8];
6347 temp = ((crc & 1) ^ data_byte) & 1;
6358 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6365 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6366 __le16 vid_le = cpu_to_le16(vid);
6367 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6372 if (!priv->dma_cap.vlhash) {
6373 if (count > 2) /* VID = 0 always passes filter */
6376 pmatch = cpu_to_le16(vid);
6380 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6383 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6385 struct stmmac_priv *priv = netdev_priv(ndev);
6386 bool is_double = false;
6389 ret = pm_runtime_resume_and_get(priv->device);
6393 if (be16_to_cpu(proto) == ETH_P_8021AD)
6396 set_bit(vid, priv->active_vlans);
6397 ret = stmmac_vlan_update(priv, is_double);
6399 clear_bit(vid, priv->active_vlans);
6403 if (priv->hw->num_vlan) {
6404 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6409 pm_runtime_put(priv->device);
6414 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6416 struct stmmac_priv *priv = netdev_priv(ndev);
6417 bool is_double = false;
6420 ret = pm_runtime_resume_and_get(priv->device);
6424 if (be16_to_cpu(proto) == ETH_P_8021AD)
6427 clear_bit(vid, priv->active_vlans);
6429 if (priv->hw->num_vlan) {
6430 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6432 goto del_vlan_error;
6435 ret = stmmac_vlan_update(priv, is_double);
6438 pm_runtime_put(priv->device);
6443 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6445 struct stmmac_priv *priv = netdev_priv(dev);
6447 switch (bpf->command) {
6448 case XDP_SETUP_PROG:
6449 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6450 case XDP_SETUP_XSK_POOL:
6451 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6458 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6459 struct xdp_frame **frames, u32 flags)
6461 struct stmmac_priv *priv = netdev_priv(dev);
6462 int cpu = smp_processor_id();
6463 struct netdev_queue *nq;
6467 if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6470 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6473 queue = stmmac_xdp_get_tx_queue(priv, cpu);
6474 nq = netdev_get_tx_queue(priv->dev, queue);
6476 __netif_tx_lock(nq, cpu);
6477 /* Avoids TX time-out as we are sharing with slow path */
6478 txq_trans_cond_update(nq);
6480 for (i = 0; i < num_frames; i++) {
6483 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6484 if (res == STMMAC_XDP_CONSUMED)
6490 if (flags & XDP_XMIT_FLUSH) {
6491 stmmac_flush_tx_descriptors(priv, queue);
6492 stmmac_tx_timer_arm(priv, queue);
6495 __netif_tx_unlock(nq);
6500 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6502 struct stmmac_channel *ch = &priv->channel[queue];
6503 unsigned long flags;
6505 spin_lock_irqsave(&ch->lock, flags);
6506 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6507 spin_unlock_irqrestore(&ch->lock, flags);
6509 stmmac_stop_rx_dma(priv, queue);
6510 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6513 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6515 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6516 struct stmmac_channel *ch = &priv->channel[queue];
6517 unsigned long flags;
6521 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6523 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6527 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL);
6529 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6530 netdev_err(priv->dev, "Failed to init RX desc.\n");
6534 stmmac_reset_rx_queue(priv, queue);
6535 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue);
6537 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6538 rx_q->dma_rx_phy, rx_q->queue_index);
6540 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6541 sizeof(struct dma_desc));
6542 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6543 rx_q->rx_tail_addr, rx_q->queue_index);
6545 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6546 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6547 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6551 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6552 priv->dma_conf.dma_buf_sz,
6556 stmmac_start_rx_dma(priv, queue);
6558 spin_lock_irqsave(&ch->lock, flags);
6559 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6560 spin_unlock_irqrestore(&ch->lock, flags);
6563 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6565 struct stmmac_channel *ch = &priv->channel[queue];
6566 unsigned long flags;
6568 spin_lock_irqsave(&ch->lock, flags);
6569 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6570 spin_unlock_irqrestore(&ch->lock, flags);
6572 stmmac_stop_tx_dma(priv, queue);
6573 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6576 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6578 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6579 struct stmmac_channel *ch = &priv->channel[queue];
6580 unsigned long flags;
6583 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6585 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6589 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue);
6591 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6592 netdev_err(priv->dev, "Failed to init TX desc.\n");
6596 stmmac_reset_tx_queue(priv, queue);
6597 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue);
6599 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6600 tx_q->dma_tx_phy, tx_q->queue_index);
6602 if (tx_q->tbs & STMMAC_TBS_AVAIL)
6603 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6605 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6606 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6607 tx_q->tx_tail_addr, tx_q->queue_index);
6609 stmmac_start_tx_dma(priv, queue);
6611 spin_lock_irqsave(&ch->lock, flags);
6612 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6613 spin_unlock_irqrestore(&ch->lock, flags);
6616 void stmmac_xdp_release(struct net_device *dev)
6618 struct stmmac_priv *priv = netdev_priv(dev);
6621 /* Ensure tx function is not running */
6622 netif_tx_disable(dev);
6624 /* Disable NAPI process */
6625 stmmac_disable_all_queues(priv);
6627 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6628 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
6630 /* Free the IRQ lines */
6631 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6633 /* Stop TX/RX DMA channels */
6634 stmmac_stop_all_dma(priv);
6636 /* Release and free the Rx/Tx resources */
6637 free_dma_desc_resources(priv, &priv->dma_conf);
6639 /* Disable the MAC Rx/Tx */
6640 stmmac_mac_set(priv, priv->ioaddr, false);
6642 /* set trans_start so we don't get spurious
6643 * watchdogs during reset
6645 netif_trans_update(dev);
6646 netif_carrier_off(dev);
6649 int stmmac_xdp_open(struct net_device *dev)
6651 struct stmmac_priv *priv = netdev_priv(dev);
6652 u32 rx_cnt = priv->plat->rx_queues_to_use;
6653 u32 tx_cnt = priv->plat->tx_queues_to_use;
6654 u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6655 struct stmmac_rx_queue *rx_q;
6656 struct stmmac_tx_queue *tx_q;
6662 ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
6664 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6666 goto dma_desc_error;
6669 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL);
6671 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6676 stmmac_reset_queues_param(priv);
6678 /* DMA CSR Channel configuration */
6679 for (chan = 0; chan < dma_csr_ch; chan++) {
6680 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6681 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
6684 /* Adjust Split header */
6685 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6687 /* DMA RX Channel Configuration */
6688 for (chan = 0; chan < rx_cnt; chan++) {
6689 rx_q = &priv->dma_conf.rx_queue[chan];
6691 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6692 rx_q->dma_rx_phy, chan);
6694 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6695 (rx_q->buf_alloc_num *
6696 sizeof(struct dma_desc));
6697 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6698 rx_q->rx_tail_addr, chan);
6700 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6701 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6702 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6706 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6707 priv->dma_conf.dma_buf_sz,
6711 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6714 /* DMA TX Channel Configuration */
6715 for (chan = 0; chan < tx_cnt; chan++) {
6716 tx_q = &priv->dma_conf.tx_queue[chan];
6718 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6719 tx_q->dma_tx_phy, chan);
6721 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6722 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6723 tx_q->tx_tail_addr, chan);
6725 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6726 tx_q->txtimer.function = stmmac_tx_timer;
6729 /* Enable the MAC Rx/Tx */
6730 stmmac_mac_set(priv, priv->ioaddr, true);
6732 /* Start Rx & Tx DMA Channels */
6733 stmmac_start_all_dma(priv);
6735 ret = stmmac_request_irq(dev);
6739 /* Enable NAPI process*/
6740 stmmac_enable_all_queues(priv);
6741 netif_carrier_on(dev);
6742 netif_tx_start_all_queues(dev);
6743 stmmac_enable_all_dma_irq(priv);
6748 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6749 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
6751 stmmac_hw_teardown(dev);
6753 free_dma_desc_resources(priv, &priv->dma_conf);
6758 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6760 struct stmmac_priv *priv = netdev_priv(dev);
6761 struct stmmac_rx_queue *rx_q;
6762 struct stmmac_tx_queue *tx_q;
6763 struct stmmac_channel *ch;
6765 if (test_bit(STMMAC_DOWN, &priv->state) ||
6766 !netif_carrier_ok(priv->dev))
6769 if (!stmmac_xdp_is_enabled(priv))
6772 if (queue >= priv->plat->rx_queues_to_use ||
6773 queue >= priv->plat->tx_queues_to_use)
6776 rx_q = &priv->dma_conf.rx_queue[queue];
6777 tx_q = &priv->dma_conf.tx_queue[queue];
6778 ch = &priv->channel[queue];
6780 if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6783 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6784 /* EQoS does not have per-DMA channel SW interrupt,
6785 * so we schedule RX Napi straight-away.
6787 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6788 __napi_schedule(&ch->rxtx_napi);
6794 static const struct net_device_ops stmmac_netdev_ops = {
6795 .ndo_open = stmmac_open,
6796 .ndo_start_xmit = stmmac_xmit,
6797 .ndo_stop = stmmac_release,
6798 .ndo_change_mtu = stmmac_change_mtu,
6799 .ndo_fix_features = stmmac_fix_features,
6800 .ndo_set_features = stmmac_set_features,
6801 .ndo_set_rx_mode = stmmac_set_rx_mode,
6802 .ndo_tx_timeout = stmmac_tx_timeout,
6803 .ndo_eth_ioctl = stmmac_ioctl,
6804 .ndo_setup_tc = stmmac_setup_tc,
6805 .ndo_select_queue = stmmac_select_queue,
6806 #ifdef CONFIG_NET_POLL_CONTROLLER
6807 .ndo_poll_controller = stmmac_poll_controller,
6809 .ndo_set_mac_address = stmmac_set_mac_address,
6810 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6811 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6812 .ndo_bpf = stmmac_bpf,
6813 .ndo_xdp_xmit = stmmac_xdp_xmit,
6814 .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6817 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6819 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6821 if (test_bit(STMMAC_DOWN, &priv->state))
6824 netdev_err(priv->dev, "Reset adapter.\n");
6827 netif_trans_update(priv->dev);
6828 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6829 usleep_range(1000, 2000);
6831 set_bit(STMMAC_DOWN, &priv->state);
6832 dev_close(priv->dev);
6833 dev_open(priv->dev, NULL);
6834 clear_bit(STMMAC_DOWN, &priv->state);
6835 clear_bit(STMMAC_RESETING, &priv->state);
6839 static void stmmac_service_task(struct work_struct *work)
6841 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6844 stmmac_reset_subtask(priv);
6845 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6849 * stmmac_hw_init - Init the MAC device
6850 * @priv: driver private structure
6851 * Description: this function is to configure the MAC device according to
6852 * some platform parameters or the HW capability register. It prepares the
6853 * driver to use either ring or chain modes and to setup either enhanced or
6854 * normal descriptors.
6856 static int stmmac_hw_init(struct stmmac_priv *priv)
6860 /* dwmac-sun8i only work in chain mode */
6861 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
6863 priv->chain_mode = chain_mode;
6865 /* Initialize HW Interface */
6866 ret = stmmac_hwif_init(priv);
6870 /* Get the HW capability (new GMAC newer than 3.50a) */
6871 priv->hw_cap_support = stmmac_get_hw_features(priv);
6872 if (priv->hw_cap_support) {
6873 dev_info(priv->device, "DMA HW capability register supported\n");
6875 /* We can override some gmac/dma configuration fields: e.g.
6876 * enh_desc, tx_coe (e.g. that are passed through the
6877 * platform) with the values from the HW capability
6878 * register (if supported).
6880 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6881 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6882 !(priv->plat->flags & STMMAC_FLAG_USE_PHY_WOL);
6883 priv->hw->pmt = priv->plat->pmt;
6884 if (priv->dma_cap.hash_tb_sz) {
6885 priv->hw->multicast_filter_bins =
6886 (BIT(priv->dma_cap.hash_tb_sz) << 5);
6887 priv->hw->mcast_bits_log2 =
6888 ilog2(priv->hw->multicast_filter_bins);
6891 /* TXCOE doesn't work in thresh DMA mode */
6892 if (priv->plat->force_thresh_dma_mode)
6893 priv->plat->tx_coe = 0;
6895 priv->plat->tx_coe = priv->dma_cap.tx_coe;
6897 /* In case of GMAC4 rx_coe is from HW cap register. */
6898 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6900 if (priv->dma_cap.rx_coe_type2)
6901 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6902 else if (priv->dma_cap.rx_coe_type1)
6903 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6906 dev_info(priv->device, "No HW DMA feature register supported\n");
6909 if (priv->plat->rx_coe) {
6910 priv->hw->rx_csum = priv->plat->rx_coe;
6911 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6912 if (priv->synopsys_id < DWMAC_CORE_4_00)
6913 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6915 if (priv->plat->tx_coe)
6916 dev_info(priv->device, "TX Checksum insertion supported\n");
6918 if (priv->plat->pmt) {
6919 dev_info(priv->device, "Wake-Up On Lan supported\n");
6920 device_set_wakeup_capable(priv->device, 1);
6923 if (priv->dma_cap.tsoen)
6924 dev_info(priv->device, "TSO supported\n");
6926 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en;
6927 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6929 /* Run HW quirks, if any */
6930 if (priv->hwif_quirks) {
6931 ret = priv->hwif_quirks(priv);
6936 /* Rx Watchdog is available in the COREs newer than the 3.40.
6937 * In some case, for example on bugged HW this feature
6938 * has to be disable and this can be done by passing the
6939 * riwt_off field from the platform.
6941 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6942 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6944 dev_info(priv->device,
6945 "Enable RX Mitigation via HW Watchdog Timer\n");
6951 static void stmmac_napi_add(struct net_device *dev)
6953 struct stmmac_priv *priv = netdev_priv(dev);
6956 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6958 for (queue = 0; queue < maxq; queue++) {
6959 struct stmmac_channel *ch = &priv->channel[queue];
6961 ch->priv_data = priv;
6963 spin_lock_init(&ch->lock);
6965 if (queue < priv->plat->rx_queues_to_use) {
6966 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx);
6968 if (queue < priv->plat->tx_queues_to_use) {
6969 netif_napi_add_tx(dev, &ch->tx_napi,
6970 stmmac_napi_poll_tx);
6972 if (queue < priv->plat->rx_queues_to_use &&
6973 queue < priv->plat->tx_queues_to_use) {
6974 netif_napi_add(dev, &ch->rxtx_napi,
6975 stmmac_napi_poll_rxtx);
6980 static void stmmac_napi_del(struct net_device *dev)
6982 struct stmmac_priv *priv = netdev_priv(dev);
6985 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6987 for (queue = 0; queue < maxq; queue++) {
6988 struct stmmac_channel *ch = &priv->channel[queue];
6990 if (queue < priv->plat->rx_queues_to_use)
6991 netif_napi_del(&ch->rx_napi);
6992 if (queue < priv->plat->tx_queues_to_use)
6993 netif_napi_del(&ch->tx_napi);
6994 if (queue < priv->plat->rx_queues_to_use &&
6995 queue < priv->plat->tx_queues_to_use) {
6996 netif_napi_del(&ch->rxtx_napi);
7001 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
7003 struct stmmac_priv *priv = netdev_priv(dev);
7006 if (netif_running(dev))
7007 stmmac_release(dev);
7009 stmmac_napi_del(dev);
7011 priv->plat->rx_queues_to_use = rx_cnt;
7012 priv->plat->tx_queues_to_use = tx_cnt;
7013 if (!netif_is_rxfh_configured(dev))
7014 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7015 priv->rss.table[i] = ethtool_rxfh_indir_default(i,
7018 stmmac_napi_add(dev);
7020 if (netif_running(dev))
7021 ret = stmmac_open(dev);
7026 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
7028 struct stmmac_priv *priv = netdev_priv(dev);
7031 if (netif_running(dev))
7032 stmmac_release(dev);
7034 priv->dma_conf.dma_rx_size = rx_size;
7035 priv->dma_conf.dma_tx_size = tx_size;
7037 if (netif_running(dev))
7038 ret = stmmac_open(dev);
7043 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
7044 static void stmmac_fpe_lp_task(struct work_struct *work)
7046 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
7048 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
7049 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
7050 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
7051 bool *hs_enable = &fpe_cfg->hs_enable;
7052 bool *enable = &fpe_cfg->enable;
7055 while (retries-- > 0) {
7056 /* Bail out immediately if FPE handshake is OFF */
7057 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
7060 if (*lo_state == FPE_STATE_ENTERING_ON &&
7061 *lp_state == FPE_STATE_ENTERING_ON) {
7062 stmmac_fpe_configure(priv, priv->ioaddr,
7063 priv->plat->tx_queues_to_use,
7064 priv->plat->rx_queues_to_use,
7067 netdev_info(priv->dev, "configured FPE\n");
7069 *lo_state = FPE_STATE_ON;
7070 *lp_state = FPE_STATE_ON;
7071 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
7075 if ((*lo_state == FPE_STATE_CAPABLE ||
7076 *lo_state == FPE_STATE_ENTERING_ON) &&
7077 *lp_state != FPE_STATE_ON) {
7078 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
7079 *lo_state, *lp_state);
7080 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7083 /* Sleep then retry */
7087 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
7090 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
7092 if (priv->plat->fpe_cfg->hs_enable != enable) {
7094 stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7097 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
7098 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
7101 priv->plat->fpe_cfg->hs_enable = enable;
7105 static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)
7107 const struct stmmac_xdp_buff *ctx = (void *)_ctx;
7108 struct dma_desc *desc_contains_ts = ctx->desc;
7109 struct stmmac_priv *priv = ctx->priv;
7110 struct dma_desc *ndesc = ctx->ndesc;
7111 struct dma_desc *desc = ctx->desc;
7114 if (!priv->hwts_rx_en)
7117 /* For GMAC4, the valid timestamp is from CTX next desc. */
7118 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
7119 desc_contains_ts = ndesc;
7121 /* Check if timestamp is available */
7122 if (stmmac_get_rx_timestamp_status(priv, desc, ndesc, priv->adv_ts)) {
7123 stmmac_get_timestamp(priv, desc_contains_ts, priv->adv_ts, &ns);
7124 ns -= priv->plat->cdc_error_adj;
7125 *timestamp = ns_to_ktime(ns);
7132 static const struct xdp_metadata_ops stmmac_xdp_metadata_ops = {
7133 .xmo_rx_timestamp = stmmac_xdp_rx_timestamp,
7138 * @device: device pointer
7139 * @plat_dat: platform data pointer
7140 * @res: stmmac resource pointer
7141 * Description: this is the main probe function used to
7142 * call the alloc_etherdev, allocate the priv structure.
7144 * returns 0 on success, otherwise errno.
7146 int stmmac_dvr_probe(struct device *device,
7147 struct plat_stmmacenet_data *plat_dat,
7148 struct stmmac_resources *res)
7150 struct net_device *ndev = NULL;
7151 struct stmmac_priv *priv;
7155 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
7156 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
7160 SET_NETDEV_DEV(ndev, device);
7162 priv = netdev_priv(ndev);
7163 priv->device = device;
7166 stmmac_set_ethtool_ops(ndev);
7167 priv->pause = pause;
7168 priv->plat = plat_dat;
7169 priv->ioaddr = res->addr;
7170 priv->dev->base_addr = (unsigned long)res->addr;
7171 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
7173 priv->dev->irq = res->irq;
7174 priv->wol_irq = res->wol_irq;
7175 priv->lpi_irq = res->lpi_irq;
7176 priv->sfty_ce_irq = res->sfty_ce_irq;
7177 priv->sfty_ue_irq = res->sfty_ue_irq;
7178 for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
7179 priv->rx_irq[i] = res->rx_irq[i];
7180 for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
7181 priv->tx_irq[i] = res->tx_irq[i];
7183 if (!is_zero_ether_addr(res->mac))
7184 eth_hw_addr_set(priv->dev, res->mac);
7186 dev_set_drvdata(device, priv->dev);
7188 /* Verify driver arguments */
7189 stmmac_verify_args();
7191 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
7192 if (!priv->af_xdp_zc_qps)
7195 /* Allocate workqueue */
7196 priv->wq = create_singlethread_workqueue("stmmac_wq");
7198 dev_err(priv->device, "failed to create workqueue\n");
7203 INIT_WORK(&priv->service_task, stmmac_service_task);
7205 /* Initialize Link Partner FPE workqueue */
7206 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
7208 /* Override with kernel parameters if supplied XXX CRS XXX
7209 * this needs to have multiple instances
7211 if ((phyaddr >= 0) && (phyaddr <= 31))
7212 priv->plat->phy_addr = phyaddr;
7214 if (priv->plat->stmmac_rst) {
7215 ret = reset_control_assert(priv->plat->stmmac_rst);
7216 reset_control_deassert(priv->plat->stmmac_rst);
7217 /* Some reset controllers have only reset callback instead of
7218 * assert + deassert callbacks pair.
7220 if (ret == -ENOTSUPP)
7221 reset_control_reset(priv->plat->stmmac_rst);
7224 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
7225 if (ret == -ENOTSUPP)
7226 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
7229 /* Init MAC and get the capabilities */
7230 ret = stmmac_hw_init(priv);
7234 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
7236 if (priv->synopsys_id < DWMAC_CORE_5_20)
7237 priv->plat->dma_cfg->dche = false;
7239 stmmac_check_ether_addr(priv);
7241 ndev->netdev_ops = &stmmac_netdev_ops;
7243 ndev->xdp_metadata_ops = &stmmac_xdp_metadata_ops;
7245 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7247 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
7248 NETDEV_XDP_ACT_XSK_ZEROCOPY;
7250 ret = stmmac_tc_init(priv, priv);
7252 ndev->hw_features |= NETIF_F_HW_TC;
7255 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
7256 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7257 if (priv->plat->has_gmac4)
7258 ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7260 dev_info(priv->device, "TSO feature enabled\n");
7263 if (priv->dma_cap.sphen &&
7264 !(priv->plat->flags & STMMAC_FLAG_SPH_DISABLE)) {
7265 ndev->hw_features |= NETIF_F_GRO;
7266 priv->sph_cap = true;
7267 priv->sph = priv->sph_cap;
7268 dev_info(priv->device, "SPH feature enabled\n");
7271 /* Ideally our host DMA address width is the same as for the
7272 * device. However, it may differ and then we have to use our
7273 * host DMA width for allocation and the device DMA width for
7274 * register handling.
7276 if (priv->plat->host_dma_width)
7277 priv->dma_cap.host_dma_width = priv->plat->host_dma_width;
7279 priv->dma_cap.host_dma_width = priv->dma_cap.addr64;
7281 if (priv->dma_cap.host_dma_width) {
7282 ret = dma_set_mask_and_coherent(device,
7283 DMA_BIT_MASK(priv->dma_cap.host_dma_width));
7285 dev_info(priv->device, "Using %d/%d bits DMA host/device width\n",
7286 priv->dma_cap.host_dma_width, priv->dma_cap.addr64);
7289 * If more than 32 bits can be addressed, make sure to
7290 * enable enhanced addressing mode.
7292 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7293 priv->plat->dma_cfg->eame = true;
7295 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7297 dev_err(priv->device, "Failed to set DMA Mask\n");
7301 priv->dma_cap.host_dma_width = 32;
7305 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7306 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7307 #ifdef STMMAC_VLAN_TAG_USED
7308 /* Both mac100 and gmac support receive VLAN tag detection */
7309 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7310 if (priv->dma_cap.vlhash) {
7311 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7312 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7314 if (priv->dma_cap.vlins) {
7315 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7316 if (priv->dma_cap.dvlan)
7317 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7320 priv->msg_enable = netif_msg_init(debug, default_msg_level);
7322 /* Initialize RSS */
7323 rxq = priv->plat->rx_queues_to_use;
7324 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7325 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7326 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7328 if (priv->dma_cap.rssen && priv->plat->rss_en)
7329 ndev->features |= NETIF_F_RXHASH;
7331 ndev->vlan_features |= ndev->features;
7332 /* TSO doesn't work on VLANs yet */
7333 ndev->vlan_features &= ~NETIF_F_TSO;
7335 /* MTU range: 46 - hw-specific max */
7336 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7337 if (priv->plat->has_xgmac)
7338 ndev->max_mtu = XGMAC_JUMBO_LEN;
7339 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7340 ndev->max_mtu = JUMBO_LEN;
7342 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7343 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7344 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7346 if ((priv->plat->maxmtu < ndev->max_mtu) &&
7347 (priv->plat->maxmtu >= ndev->min_mtu))
7348 ndev->max_mtu = priv->plat->maxmtu;
7349 else if (priv->plat->maxmtu < ndev->min_mtu)
7350 dev_warn(priv->device,
7351 "%s: warning: maxmtu having invalid value (%d)\n",
7352 __func__, priv->plat->maxmtu);
7355 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
7357 ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7359 /* Setup channels NAPI */
7360 stmmac_napi_add(ndev);
7362 mutex_init(&priv->lock);
7364 /* If a specific clk_csr value is passed from the platform
7365 * this means that the CSR Clock Range selection cannot be
7366 * changed at run-time and it is fixed. Viceversa the driver'll try to
7367 * set the MDC clock dynamically according to the csr actual
7370 if (priv->plat->clk_csr >= 0)
7371 priv->clk_csr = priv->plat->clk_csr;
7373 stmmac_clk_csr_set(priv);
7375 stmmac_check_pcs_mode(priv);
7377 pm_runtime_get_noresume(device);
7378 pm_runtime_set_active(device);
7379 if (!pm_runtime_enabled(device))
7380 pm_runtime_enable(device);
7382 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7383 priv->hw->pcs != STMMAC_PCS_RTBI) {
7384 /* MDIO bus Registration */
7385 ret = stmmac_mdio_register(ndev);
7387 dev_err_probe(priv->device, ret,
7388 "%s: MDIO bus (id: %d) registration failed\n",
7389 __func__, priv->plat->bus_id);
7390 goto error_mdio_register;
7394 if (priv->plat->speed_mode_2500)
7395 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7397 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7398 ret = stmmac_xpcs_setup(priv->mii);
7400 goto error_xpcs_setup;
7403 ret = stmmac_phy_setup(priv);
7405 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7406 goto error_phy_setup;
7409 ret = register_netdev(ndev);
7411 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7413 goto error_netdev_register;
7416 #ifdef CONFIG_DEBUG_FS
7417 stmmac_init_fs(ndev);
7420 if (priv->plat->dump_debug_regs)
7421 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7423 /* Let pm_runtime_put() disable the clocks.
7424 * If CONFIG_PM is not enabled, the clocks will stay powered.
7426 pm_runtime_put(device);
7430 error_netdev_register:
7431 phylink_destroy(priv->phylink);
7434 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7435 priv->hw->pcs != STMMAC_PCS_RTBI)
7436 stmmac_mdio_unregister(ndev);
7437 error_mdio_register:
7438 stmmac_napi_del(ndev);
7440 destroy_workqueue(priv->wq);
7442 bitmap_free(priv->af_xdp_zc_qps);
7446 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7450 * @dev: device pointer
7451 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7452 * changes the link status, releases the DMA descriptor rings.
7454 void stmmac_dvr_remove(struct device *dev)
7456 struct net_device *ndev = dev_get_drvdata(dev);
7457 struct stmmac_priv *priv = netdev_priv(ndev);
7459 netdev_info(priv->dev, "%s: removing driver", __func__);
7461 pm_runtime_get_sync(dev);
7463 stmmac_stop_all_dma(priv);
7464 stmmac_mac_set(priv, priv->ioaddr, false);
7465 netif_carrier_off(ndev);
7466 unregister_netdev(ndev);
7468 #ifdef CONFIG_DEBUG_FS
7469 stmmac_exit_fs(ndev);
7471 phylink_destroy(priv->phylink);
7472 if (priv->plat->stmmac_rst)
7473 reset_control_assert(priv->plat->stmmac_rst);
7474 reset_control_assert(priv->plat->stmmac_ahb_rst);
7475 if (priv->hw->pcs != STMMAC_PCS_TBI &&
7476 priv->hw->pcs != STMMAC_PCS_RTBI)
7477 stmmac_mdio_unregister(ndev);
7478 destroy_workqueue(priv->wq);
7479 mutex_destroy(&priv->lock);
7480 bitmap_free(priv->af_xdp_zc_qps);
7482 pm_runtime_disable(dev);
7483 pm_runtime_put_noidle(dev);
7485 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7488 * stmmac_suspend - suspend callback
7489 * @dev: device pointer
7490 * Description: this is the function to suspend the device and it is called
7491 * by the platform driver to stop the network queue, release the resources,
7492 * program the PMT register (for WoL), clean and release driver resources.
7494 int stmmac_suspend(struct device *dev)
7496 struct net_device *ndev = dev_get_drvdata(dev);
7497 struct stmmac_priv *priv = netdev_priv(ndev);
7500 if (!ndev || !netif_running(ndev))
7503 mutex_lock(&priv->lock);
7505 netif_device_detach(ndev);
7507 stmmac_disable_all_queues(priv);
7509 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7510 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
7512 if (priv->eee_enabled) {
7513 priv->tx_path_in_lpi_mode = false;
7514 del_timer_sync(&priv->eee_ctrl_timer);
7517 /* Stop TX/RX DMA */
7518 stmmac_stop_all_dma(priv);
7520 if (priv->plat->serdes_powerdown)
7521 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7523 /* Enable Power down mode by programming the PMT regs */
7524 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7525 stmmac_pmt(priv, priv->hw, priv->wolopts);
7528 stmmac_mac_set(priv, priv->ioaddr, false);
7529 pinctrl_pm_select_sleep_state(priv->device);
7532 mutex_unlock(&priv->lock);
7535 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7536 phylink_suspend(priv->phylink, true);
7538 if (device_may_wakeup(priv->device))
7539 phylink_speed_down(priv->phylink, false);
7540 phylink_suspend(priv->phylink, false);
7544 if (priv->dma_cap.fpesel) {
7546 stmmac_fpe_configure(priv, priv->ioaddr,
7547 priv->plat->tx_queues_to_use,
7548 priv->plat->rx_queues_to_use, false);
7550 stmmac_fpe_handshake(priv, false);
7551 stmmac_fpe_stop_wq(priv);
7554 priv->speed = SPEED_UNKNOWN;
7557 EXPORT_SYMBOL_GPL(stmmac_suspend);
7559 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
7561 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
7567 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
7569 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
7575 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7579 * stmmac_reset_queues_param - reset queue parameters
7580 * @priv: device pointer
7582 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7584 u32 rx_cnt = priv->plat->rx_queues_to_use;
7585 u32 tx_cnt = priv->plat->tx_queues_to_use;
7588 for (queue = 0; queue < rx_cnt; queue++)
7589 stmmac_reset_rx_queue(priv, queue);
7591 for (queue = 0; queue < tx_cnt; queue++)
7592 stmmac_reset_tx_queue(priv, queue);
7596 * stmmac_resume - resume callback
7597 * @dev: device pointer
7598 * Description: when resume this function is invoked to setup the DMA and CORE
7599 * in a usable state.
7601 int stmmac_resume(struct device *dev)
7603 struct net_device *ndev = dev_get_drvdata(dev);
7604 struct stmmac_priv *priv = netdev_priv(ndev);
7607 if (!netif_running(ndev))
7610 /* Power Down bit, into the PM register, is cleared
7611 * automatically as soon as a magic packet or a Wake-up frame
7612 * is received. Anyway, it's better to manually clear
7613 * this bit because it can generate problems while resuming
7614 * from another devices (e.g. serial console).
7616 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7617 mutex_lock(&priv->lock);
7618 stmmac_pmt(priv, priv->hw, 0);
7619 mutex_unlock(&priv->lock);
7622 pinctrl_pm_select_default_state(priv->device);
7623 /* reset the phy so that it's ready */
7625 stmmac_mdio_reset(priv->mii);
7628 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
7629 priv->plat->serdes_powerup) {
7630 ret = priv->plat->serdes_powerup(ndev,
7631 priv->plat->bsp_priv);
7638 if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7639 phylink_resume(priv->phylink);
7641 phylink_resume(priv->phylink);
7642 if (device_may_wakeup(priv->device))
7643 phylink_speed_up(priv->phylink);
7648 mutex_lock(&priv->lock);
7650 stmmac_reset_queues_param(priv);
7652 stmmac_free_tx_skbufs(priv);
7653 stmmac_clear_descriptors(priv, &priv->dma_conf);
7655 stmmac_hw_setup(ndev, false);
7656 stmmac_init_coalesce(priv);
7657 stmmac_set_rx_mode(ndev);
7659 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7661 stmmac_enable_all_queues(priv);
7662 stmmac_enable_all_dma_irq(priv);
7664 mutex_unlock(&priv->lock);
7667 netif_device_attach(ndev);
7671 EXPORT_SYMBOL_GPL(stmmac_resume);
7674 static int __init stmmac_cmdline_opt(char *str)
7680 while ((opt = strsep(&str, ",")) != NULL) {
7681 if (!strncmp(opt, "debug:", 6)) {
7682 if (kstrtoint(opt + 6, 0, &debug))
7684 } else if (!strncmp(opt, "phyaddr:", 8)) {
7685 if (kstrtoint(opt + 8, 0, &phyaddr))
7687 } else if (!strncmp(opt, "buf_sz:", 7)) {
7688 if (kstrtoint(opt + 7, 0, &buf_sz))
7690 } else if (!strncmp(opt, "tc:", 3)) {
7691 if (kstrtoint(opt + 3, 0, &tc))
7693 } else if (!strncmp(opt, "watchdog:", 9)) {
7694 if (kstrtoint(opt + 9, 0, &watchdog))
7696 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7697 if (kstrtoint(opt + 10, 0, &flow_ctrl))
7699 } else if (!strncmp(opt, "pause:", 6)) {
7700 if (kstrtoint(opt + 6, 0, &pause))
7702 } else if (!strncmp(opt, "eee_timer:", 10)) {
7703 if (kstrtoint(opt + 10, 0, &eee_timer))
7705 } else if (!strncmp(opt, "chain_mode:", 11)) {
7706 if (kstrtoint(opt + 11, 0, &chain_mode))
7713 pr_err("%s: ERROR broken module parameter conversion", __func__);
7717 __setup("stmmaceth=", stmmac_cmdline_opt);
7720 static int __init stmmac_init(void)
7722 #ifdef CONFIG_DEBUG_FS
7723 /* Create debugfs main directory if it doesn't exist yet */
7725 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7726 register_netdevice_notifier(&stmmac_notifier);
7732 static void __exit stmmac_exit(void)
7734 #ifdef CONFIG_DEBUG_FS
7735 unregister_netdevice_notifier(&stmmac_notifier);
7736 debugfs_remove_recursive(stmmac_fs_dir);
7740 module_init(stmmac_init)
7741 module_exit(stmmac_exit)
7743 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7744 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7745 MODULE_LICENSE("GPL");