drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pinctrl/consumer.h>
  34 #ifdef CONFIG_DEBUG_FS
  35 #include <linux/debugfs.h>
  36 #include <linux/seq_file.h>
  37 #endif /* CONFIG_DEBUG_FS */
  38 #include <linux/net_tstamp.h>
  39 #include <linux/phylink.h>
  40 #include <linux/udp.h>
  41 #include <linux/bpf_trace.h>
  42 #include <net/pkt_cls.h>
  43 #include <net/xdp_sock_drv.h>
  44 #include "stmmac_ptp.h"
  45 #include "stmmac.h"
  46 #include "stmmac_xdp.h"
  47 #include <linux/reset.h>
  48 #include <linux/of_mdio.h>
  49 #include "dwmac1000.h"
  50 #include "dwxgmac2.h"
  51 #include "hwif.h"
  52
  53 /* As long as the interface is active, we keep the timestamping counter enabled
  54  * with fine resolution and binary rollover. This avoid non-monotonic behavior
  55  * (clock jumps) when changing timestamping settings at runtime.
  56  */
  57 #define STMMAC_HWTS_ACTIVE      (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \
  58                                  PTP_TCR_TSCTRLSSR)
  59
  60 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  61 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  62
  63 /* Module parameters */
  64 #define TX_TIMEO        5000
  65 static int watchdog = TX_TIMEO;
  66 module_param(watchdog, int, 0644);
  67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  68
  69 static int debug = -1;
  70 module_param(debug, int, 0644);
  71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  72
  73 static int phyaddr = -1;
  74 module_param(phyaddr, int, 0444);
  75 MODULE_PARM_DESC(phyaddr, "Physical device address");
  76
  77 #define STMMAC_TX_THRESH(x)     ((x)->dma_conf.dma_tx_size / 4)
  78 #define STMMAC_RX_THRESH(x)     ((x)->dma_conf.dma_rx_size / 4)
  79
  80 /* Limit to make sure XDP TX and slow path can coexist */
  81 #define STMMAC_XSK_TX_BUDGET_MAX        256
  82 #define STMMAC_TX_XSK_AVAIL             16
  83 #define STMMAC_RX_FILL_BATCH            16
  84
  85 #define STMMAC_XDP_PASS         0
  86 #define STMMAC_XDP_CONSUMED     BIT(0)
  87 #define STMMAC_XDP_TX           BIT(1)
  88 #define STMMAC_XDP_REDIRECT     BIT(2)
  89
  90 static int flow_ctrl = FLOW_AUTO;
  91 module_param(flow_ctrl, int, 0644);
  92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  93
  94 static int pause = PAUSE_TIME;
  95 module_param(pause, int, 0644);
  96 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  97
  98 #define TC_DEFAULT 64
  99 static int tc = TC_DEFAULT;
 100 module_param(tc, int, 0644);
 101 MODULE_PARM_DESC(tc, "DMA threshold control value");
 102
 103 #define DEFAULT_BUFSIZE 1536
 104 static int buf_sz = DEFAULT_BUFSIZE;
 105 module_param(buf_sz, int, 0644);
 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 107
 108 #define STMMAC_RX_COPYBREAK     256
 109
 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 111                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 112                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 113
 114 #define STMMAC_DEFAULT_LPI_TIMER        1000
 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 116 module_param(eee_timer, int, 0644);
 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x))
 119
 120 /* By default the driver will use the ring mode to manage tx and rx descriptors,
 121  * but allow user to force to use the chain instead of the ring
 122  */
 123 static unsigned int chain_mode;
 124 module_param(chain_mode, int, 0444);
 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 126
 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 128 /* For MSI interrupts handling */
 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id);
 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id);
 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data);
 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data);
 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue);
 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue);
 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv);
 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
 139                                           u32 rxmode, u32 chan);
 140
 141 #ifdef CONFIG_DEBUG_FS
 142 static const struct net_device_ops stmmac_netdev_ops;
 143 static void stmmac_init_fs(struct net_device *dev);
 144 static void stmmac_exit_fs(struct net_device *dev);
 145 #endif
 146
 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
 148
 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
 150 {
 151         int ret = 0;
 152
 153         if (enabled) {
 154                 ret = clk_prepare_enable(priv->plat->stmmac_clk);
 155                 if (ret)
 156                         return ret;
 157                 ret = clk_prepare_enable(priv->plat->pclk);
 158                 if (ret) {
 159                         clk_disable_unprepare(priv->plat->stmmac_clk);
 160                         return ret;
 161                 }
 162                 if (priv->plat->clks_config) {
 163                         ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 164                         if (ret) {
 165                                 clk_disable_unprepare(priv->plat->stmmac_clk);
 166                                 clk_disable_unprepare(priv->plat->pclk);
 167                                 return ret;
 168                         }
 169                 }
 170         } else {
 171                 clk_disable_unprepare(priv->plat->stmmac_clk);
 172                 clk_disable_unprepare(priv->plat->pclk);
 173                 if (priv->plat->clks_config)
 174                         priv->plat->clks_config(priv->plat->bsp_priv, enabled);
 175         }
 176
 177         return ret;
 178 }
 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
 180
 181 /**
 182  * stmmac_verify_args - verify the driver parameters.
 183  * Description: it checks the driver parameters and set a default in case of
 184  * errors.
 185  */
 186 static void stmmac_verify_args(void)
 187 {
 188         if (unlikely(watchdog < 0))
 189                 watchdog = TX_TIMEO;
 190         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 191                 buf_sz = DEFAULT_BUFSIZE;
 192         if (unlikely(flow_ctrl > 1))
 193                 flow_ctrl = FLOW_AUTO;
 194         else if (likely(flow_ctrl < 0))
 195                 flow_ctrl = FLOW_OFF;
 196         if (unlikely((pause < 0) || (pause > 0xffff)))
 197                 pause = PAUSE_TIME;
 198         if (eee_timer < 0)
 199                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 200 }
 201
 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
 203 {
 204         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 205         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 206         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 207         u32 queue;
 208
 209         for (queue = 0; queue < maxq; queue++) {
 210                 struct stmmac_channel *ch = &priv->channel[queue];
 211
 212                 if (stmmac_xdp_is_enabled(priv) &&
 213                     test_bit(queue, priv->af_xdp_zc_qps)) {
 214                         napi_disable(&ch->rxtx_napi);
 215                         continue;
 216                 }
 217
 218                 if (queue < rx_queues_cnt)
 219                         napi_disable(&ch->rx_napi);
 220                 if (queue < tx_queues_cnt)
 221                         napi_disable(&ch->tx_napi);
 222         }
 223 }
 224
 225 /**
 226  * stmmac_disable_all_queues - Disable all queues
 227  * @priv: driver private structure
 228  */
 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 230 {
 231         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 232         struct stmmac_rx_queue *rx_q;
 233         u32 queue;
 234
 235         /* synchronize_rcu() needed for pending XDP buffers to drain */
 236         for (queue = 0; queue < rx_queues_cnt; queue++) {
 237                 rx_q = &priv->dma_conf.rx_queue[queue];
 238                 if (rx_q->xsk_pool) {
 239                         synchronize_rcu();
 240                         break;
 241                 }
 242         }
 243
 244         __stmmac_disable_all_queues(priv);
 245 }
 246
 247 /**
 248  * stmmac_enable_all_queues - Enable all queues
 249  * @priv: driver private structure
 250  */
 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 252 {
 253         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 254         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 255         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 256         u32 queue;
 257
 258         for (queue = 0; queue < maxq; queue++) {
 259                 struct stmmac_channel *ch = &priv->channel[queue];
 260
 261                 if (stmmac_xdp_is_enabled(priv) &&
 262                     test_bit(queue, priv->af_xdp_zc_qps)) {
 263                         napi_enable(&ch->rxtx_napi);
 264                         continue;
 265                 }
 266
 267                 if (queue < rx_queues_cnt)
 268                         napi_enable(&ch->rx_napi);
 269                 if (queue < tx_queues_cnt)
 270                         napi_enable(&ch->tx_napi);
 271         }
 272 }
 273
 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 275 {
 276         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 277             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 278                 queue_work(priv->wq, &priv->service_task);
 279 }
 280
 281 static void stmmac_global_err(struct stmmac_priv *priv)
 282 {
 283         netif_carrier_off(priv->dev);
 284         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 285         stmmac_service_event_schedule(priv);
 286 }
 287
 288 /**
 289  * stmmac_clk_csr_set - dynamically set the MDC clock
 290  * @priv: driver private structure
 291  * Description: this is to dynamically set the MDC clock according to the csr
 292  * clock input.
 293  * Note:
 294  *      If a specific clk_csr value is passed from the platform
 295  *      this means that the CSR Clock Range selection cannot be
 296  *      changed at run-time and it is fixed (as reported in the driver
 297  *      documentation). Viceversa the driver will try to set the MDC
 298  *      clock dynamically according to the actual clock input.
 299  */
 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 301 {
 302         u32 clk_rate;
 303
 304         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 305
 306         /* Platform provided default clk_csr would be assumed valid
 307          * for all other cases except for the below mentioned ones.
 308          * For values higher than the IEEE 802.3 specified frequency
 309          * we can not estimate the proper divider as it is not known
 310          * the frequency of clk_csr_i. So we do not change the default
 311          * divider.
 312          */
 313         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 314                 if (clk_rate < CSR_F_35M)
 315                         priv->clk_csr = STMMAC_CSR_20_35M;
 316                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 317                         priv->clk_csr = STMMAC_CSR_35_60M;
 318                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 319                         priv->clk_csr = STMMAC_CSR_60_100M;
 320                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 321                         priv->clk_csr = STMMAC_CSR_100_150M;
 322                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 323                         priv->clk_csr = STMMAC_CSR_150_250M;
 324                 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 325                         priv->clk_csr = STMMAC_CSR_250_300M;
 326         }
 327
 328         if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
 329                 if (clk_rate > 160000000)
 330                         priv->clk_csr = 0x03;
 331                 else if (clk_rate > 80000000)
 332                         priv->clk_csr = 0x02;
 333                 else if (clk_rate > 40000000)
 334                         priv->clk_csr = 0x01;
 335                 else
 336                         priv->clk_csr = 0;
 337         }
 338
 339         if (priv->plat->has_xgmac) {
 340                 if (clk_rate > 400000000)
 341                         priv->clk_csr = 0x5;
 342                 else if (clk_rate > 350000000)
 343                         priv->clk_csr = 0x4;
 344                 else if (clk_rate > 300000000)
 345                         priv->clk_csr = 0x3;
 346                 else if (clk_rate > 250000000)
 347                         priv->clk_csr = 0x2;
 348                 else if (clk_rate > 150000000)
 349                         priv->clk_csr = 0x1;
 350                 else
 351                         priv->clk_csr = 0x0;
 352         }
 353 }
 354
 355 static void print_pkt(unsigned char *buf, int len)
 356 {
 357         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 358         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 359 }
 360
 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 362 {
 363         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
 364         u32 avail;
 365
 366         if (tx_q->dirty_tx > tx_q->cur_tx)
 367                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 368         else
 369                 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1;
 370
 371         return avail;
 372 }
 373
 374 /**
 375  * stmmac_rx_dirty - Get RX queue dirty
 376  * @priv: driver private structure
 377  * @queue: RX queue index
 378  */
 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 380 {
 381         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
 382         u32 dirty;
 383
 384         if (rx_q->dirty_rx <= rx_q->cur_rx)
 385                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 386         else
 387                 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx;
 388
 389         return dirty;
 390 }
 391
 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en)
 393 {
 394         int tx_lpi_timer;
 395
 396         /* Clear/set the SW EEE timer flag based on LPI ET enablement */
 397         priv->eee_sw_timer_en = en ? 0 : 1;
 398         tx_lpi_timer  = en ? priv->tx_lpi_timer : 0;
 399         stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer);
 400 }
 401
 402 /**
 403  * stmmac_enable_eee_mode - check and enter in LPI mode
 404  * @priv: driver private structure
 405  * Description: this function is to verify and enter in LPI mode in case of
 406  * EEE.
 407  */
 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv)
 409 {
 410         u32 tx_cnt = priv->plat->tx_queues_to_use;
 411         u32 queue;
 412
 413         /* check if all TX queues have the work finished */
 414         for (queue = 0; queue < tx_cnt; queue++) {
 415                 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
 416
 417                 if (tx_q->dirty_tx != tx_q->cur_tx)
 418                         return -EBUSY; /* still unfinished work */
 419         }
 420
 421         /* Check and enter in LPI mode */
 422         if (!priv->tx_path_in_lpi_mode)
 423                 stmmac_set_eee_mode(priv, priv->hw,
 424                                 priv->plat->en_tx_lpi_clockgating);
 425         return 0;
 426 }
 427
 428 /**
 429  * stmmac_disable_eee_mode - disable and exit from LPI mode
 430  * @priv: driver private structure
 431  * Description: this function is to exit and disable EEE in case of
 432  * LPI state is true. This is called by the xmit.
 433  */
 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 435 {
 436         if (!priv->eee_sw_timer_en) {
 437                 stmmac_lpi_entry_timer_config(priv, 0);
 438                 return;
 439         }
 440
 441         stmmac_reset_eee_mode(priv, priv->hw);
 442         del_timer_sync(&priv->eee_ctrl_timer);
 443         priv->tx_path_in_lpi_mode = false;
 444 }
 445
 446 /**
 447  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 448  * @t:  timer_list struct containing private info
 449  * Description:
 450  *  if there is no data transfer and if we are not in LPI state,
 451  *  then MAC Transmitter can be moved to LPI state.
 452  */
 453 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 454 {
 455         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 456
 457         if (stmmac_enable_eee_mode(priv))
 458                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
 459 }
 460
 461 /**
 462  * stmmac_eee_init - init EEE
 463  * @priv: driver private structure
 464  * Description:
 465  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 466  *  can also manage EEE, this function enable the LPI state and start related
 467  *  timer.
 468  */
 469 bool stmmac_eee_init(struct stmmac_priv *priv)
 470 {
 471         int eee_tw_timer = priv->eee_tw_timer;
 472
 473         /* Using PCS we cannot dial with the phy registers at this stage
 474          * so we do not support extra feature like EEE.
 475          */
 476         if (priv->hw->pcs == STMMAC_PCS_TBI ||
 477             priv->hw->pcs == STMMAC_PCS_RTBI)
 478                 return false;
 479
 480         /* Check if MAC core supports the EEE feature. */
 481         if (!priv->dma_cap.eee)
 482                 return false;
 483
 484         mutex_lock(&priv->lock);
 485
 486         /* Check if it needs to be deactivated */
 487         if (!priv->eee_active) {
 488                 if (priv->eee_enabled) {
 489                         netdev_dbg(priv->dev, "disable EEE\n");
 490                         stmmac_lpi_entry_timer_config(priv, 0);
 491                         del_timer_sync(&priv->eee_ctrl_timer);
 492                         stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer);
 493                         if (priv->hw->xpcs)
 494                                 xpcs_config_eee(priv->hw->xpcs,
 495                                                 priv->plat->mult_fact_100ns,
 496                                                 false);
 497                 }
 498                 mutex_unlock(&priv->lock);
 499                 return false;
 500         }
 501
 502         if (priv->eee_active && !priv->eee_enabled) {
 503                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 504                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 505                                      eee_tw_timer);
 506                 if (priv->hw->xpcs)
 507                         xpcs_config_eee(priv->hw->xpcs,
 508                                         priv->plat->mult_fact_100ns,
 509                                         true);
 510         }
 511
 512         if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) {
 513                 del_timer_sync(&priv->eee_ctrl_timer);
 514                 priv->tx_path_in_lpi_mode = false;
 515                 stmmac_lpi_entry_timer_config(priv, 1);
 516         } else {
 517                 stmmac_lpi_entry_timer_config(priv, 0);
 518                 mod_timer(&priv->eee_ctrl_timer,
 519                           STMMAC_LPI_T(priv->tx_lpi_timer));
 520         }
 521
 522         mutex_unlock(&priv->lock);
 523         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 524         return true;
 525 }
 526
 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 528  * @priv: driver private structure
 529  * @p : descriptor pointer
 530  * @skb : the socket buffer
 531  * Description :
 532  * This function will read timestamp from the descriptor & pass it to stack.
 533  * and also perform some sanity checks.
 534  */
 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 536                                    struct dma_desc *p, struct sk_buff *skb)
 537 {
 538         struct skb_shared_hwtstamps shhwtstamp;
 539         bool found = false;
 540         u64 ns = 0;
 541
 542         if (!priv->hwts_tx_en)
 543                 return;
 544
 545         /* exit if skb doesn't support hw tstamp */
 546         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 547                 return;
 548
 549         /* check tx tstamp status */
 550         if (stmmac_get_tx_timestamp_status(priv, p)) {
 551                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 552                 found = true;
 553         } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
 554                 found = true;
 555         }
 556
 557         if (found) {
 558                 ns -= priv->plat->cdc_error_adj;
 559
 560                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 561                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 562
 563                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 564                 /* pass tstamp to stack */
 565                 skb_tstamp_tx(skb, &shhwtstamp);
 566         }
 567 }
 568
 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 570  * @priv: driver private structure
 571  * @p : descriptor pointer
 572  * @np : next descriptor pointer
 573  * @skb : the socket buffer
 574  * Description :
 575  * This function will read received packet's timestamp from the descriptor
 576  * and pass it to stack. It also perform some sanity checks.
 577  */
 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 579                                    struct dma_desc *np, struct sk_buff *skb)
 580 {
 581         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 582         struct dma_desc *desc = p;
 583         u64 ns = 0;
 584
 585         if (!priv->hwts_rx_en)
 586                 return;
 587         /* For GMAC4, the valid timestamp is from CTX next desc. */
 588         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 589                 desc = np;
 590
 591         /* Check if timestamp is available */
 592         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 593                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 594
 595                 ns -= priv->plat->cdc_error_adj;
 596
 597                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 598                 shhwtstamp = skb_hwtstamps(skb);
 599                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 600                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 601         } else  {
 602                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 603         }
 604 }
 605
 606 /**
 607  *  stmmac_hwtstamp_set - control hardware timestamping.
 608  *  @dev: device pointer.
 609  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 610  *  a proprietary structure used to pass information to the driver.
 611  *  Description:
 612  *  This function configures the MAC to enable/disable both outgoing(TX)
 613  *  and incoming(RX) packets time stamping based on user input.
 614  *  Return Value:
 615  *  0 on success and an appropriate -ve integer on failure.
 616  */
 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 618 {
 619         struct stmmac_priv *priv = netdev_priv(dev);
 620         struct hwtstamp_config config;
 621         u32 ptp_v2 = 0;
 622         u32 tstamp_all = 0;
 623         u32 ptp_over_ipv4_udp = 0;
 624         u32 ptp_over_ipv6_udp = 0;
 625         u32 ptp_over_ethernet = 0;
 626         u32 snap_type_sel = 0;
 627         u32 ts_master_en = 0;
 628         u32 ts_event_en = 0;
 629
 630         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 631                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 632                 priv->hwts_tx_en = 0;
 633                 priv->hwts_rx_en = 0;
 634
 635                 return -EOPNOTSUPP;
 636         }
 637
 638         if (copy_from_user(&config, ifr->ifr_data,
 639                            sizeof(config)))
 640                 return -EFAULT;
 641
 642         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 643                    __func__, config.flags, config.tx_type, config.rx_filter);
 644
 645         if (config.tx_type != HWTSTAMP_TX_OFF &&
 646             config.tx_type != HWTSTAMP_TX_ON)
 647                 return -ERANGE;
 648
 649         if (priv->adv_ts) {
 650                 switch (config.rx_filter) {
 651                 case HWTSTAMP_FILTER_NONE:
 652                         /* time stamp no incoming packet at all */
 653                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 654                         break;
 655
 656                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 657                         /* PTP v1, UDP, any kind of event packet */
 658                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 659                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 660                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 661                          * This leaves Delay_Req timestamps out.
 662                          * Enable all events *and* general purpose message
 663                          * timestamping
 664                          */
 665                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 666                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 667                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 668                         break;
 669
 670                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 671                         /* PTP v1, UDP, Sync packet */
 672                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 673                         /* take time stamp for SYNC messages only */
 674                         ts_event_en = PTP_TCR_TSEVNTENA;
 675
 676                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 677                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 678                         break;
 679
 680                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 681                         /* PTP v1, UDP, Delay_req packet */
 682                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 683                         /* take time stamp for Delay_Req messages only */
 684                         ts_master_en = PTP_TCR_TSMSTRENA;
 685                         ts_event_en = PTP_TCR_TSEVNTENA;
 686
 687                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 688                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 689                         break;
 690
 691                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 692                         /* PTP v2, UDP, any kind of event packet */
 693                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 694                         ptp_v2 = PTP_TCR_TSVER2ENA;
 695                         /* take time stamp for all event messages */
 696                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 697
 698                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 699                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 700                         break;
 701
 702                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 703                         /* PTP v2, UDP, Sync packet */
 704                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 705                         ptp_v2 = PTP_TCR_TSVER2ENA;
 706                         /* take time stamp for SYNC messages only */
 707                         ts_event_en = PTP_TCR_TSEVNTENA;
 708
 709                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 710                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 711                         break;
 712
 713                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 714                         /* PTP v2, UDP, Delay_req packet */
 715                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 716                         ptp_v2 = PTP_TCR_TSVER2ENA;
 717                         /* take time stamp for Delay_Req messages only */
 718                         ts_master_en = PTP_TCR_TSMSTRENA;
 719                         ts_event_en = PTP_TCR_TSEVNTENA;
 720
 721                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 722                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 723                         break;
 724
 725                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 726                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 727                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 728                         ptp_v2 = PTP_TCR_TSVER2ENA;
 729                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 730                         if (priv->synopsys_id < DWMAC_CORE_4_10)
 731                                 ts_event_en = PTP_TCR_TSEVNTENA;
 732                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 733                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 734                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 735                         break;
 736
 737                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 738                         /* PTP v2/802.AS1, any layer, Sync packet */
 739                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 740                         ptp_v2 = PTP_TCR_TSVER2ENA;
 741                         /* take time stamp for SYNC messages only */
 742                         ts_event_en = PTP_TCR_TSEVNTENA;
 743
 744                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 745                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 746                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 747                         break;
 748
 749                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 750                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 751                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 752                         ptp_v2 = PTP_TCR_TSVER2ENA;
 753                         /* take time stamp for Delay_Req messages only */
 754                         ts_master_en = PTP_TCR_TSMSTRENA;
 755                         ts_event_en = PTP_TCR_TSEVNTENA;
 756
 757                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 758                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 759                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 760                         break;
 761
 762                 case HWTSTAMP_FILTER_NTP_ALL:
 763                 case HWTSTAMP_FILTER_ALL:
 764                         /* time stamp any incoming packet */
 765                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 766                         tstamp_all = PTP_TCR_TSENALL;
 767                         break;
 768
 769                 default:
 770                         return -ERANGE;
 771                 }
 772         } else {
 773                 switch (config.rx_filter) {
 774                 case HWTSTAMP_FILTER_NONE:
 775                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 776                         break;
 777                 default:
 778                         /* PTP v1, UDP, any kind of event packet */
 779                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 780                         break;
 781                 }
 782         }
 783         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 784         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 785
 786         priv->systime_flags = STMMAC_HWTS_ACTIVE;
 787
 788         if (priv->hwts_tx_en || priv->hwts_rx_en) {
 789                 priv->systime_flags |= tstamp_all | ptp_v2 |
 790                                        ptp_over_ethernet | ptp_over_ipv6_udp |
 791                                        ptp_over_ipv4_udp | ts_event_en |
 792                                        ts_master_en | snap_type_sel;
 793         }
 794
 795         stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags);
 796
 797         memcpy(&priv->tstamp_config, &config, sizeof(config));
 798
 799         return copy_to_user(ifr->ifr_data, &config,
 800                             sizeof(config)) ? -EFAULT : 0;
 801 }
 802
 803 /**
 804  *  stmmac_hwtstamp_get - read hardware timestamping.
 805  *  @dev: device pointer.
 806  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 807  *  a proprietary structure used to pass information to the driver.
 808  *  Description:
 809  *  This function obtain the current hardware timestamping settings
 810  *  as requested.
 811  */
 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 813 {
 814         struct stmmac_priv *priv = netdev_priv(dev);
 815         struct hwtstamp_config *config = &priv->tstamp_config;
 816
 817         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 818                 return -EOPNOTSUPP;
 819
 820         return copy_to_user(ifr->ifr_data, config,
 821                             sizeof(*config)) ? -EFAULT : 0;
 822 }
 823
 824 /**
 825  * stmmac_init_tstamp_counter - init hardware timestamping counter
 826  * @priv: driver private structure
 827  * @systime_flags: timestamping flags
 828  * Description:
 829  * Initialize hardware counter for packet timestamping.
 830  * This is valid as long as the interface is open and not suspended.
 831  * Will be rerun after resuming from suspend, case in which the timestamping
 832  * flags updated by stmmac_hwtstamp_set() also need to be restored.
 833  */
 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags)
 835 {
 836         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 837         struct timespec64 now;
 838         u32 sec_inc = 0;
 839         u64 temp = 0;
 840
 841         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 842                 return -EOPNOTSUPP;
 843
 844         stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags);
 845         priv->systime_flags = systime_flags;
 846
 847         /* program Sub Second Increment reg */
 848         stmmac_config_sub_second_increment(priv, priv->ptpaddr,
 849                                            priv->plat->clk_ptp_rate,
 850                                            xmac, &sec_inc);
 851         temp = div_u64(1000000000ULL, sec_inc);
 852
 853         /* Store sub second increment for later use */
 854         priv->sub_second_inc = sec_inc;
 855
 856         /* calculate default added value:
 857          * formula is :
 858          * addend = (2^32)/freq_div_ratio;
 859          * where, freq_div_ratio = 1e9ns/sec_inc
 860          */
 861         temp = (u64)(temp << 32);
 862         priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 863         stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 864
 865         /* initialize system time */
 866         ktime_get_real_ts64(&now);
 867
 868         /* lower 32 bits of tv_sec are safe until y2106 */
 869         stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec);
 870
 871         return 0;
 872 }
 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter);
 874
 875 /**
 876  * stmmac_init_ptp - init PTP
 877  * @priv: driver private structure
 878  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 879  * This is done by looking at the HW cap. register.
 880  * This function also registers the ptp driver.
 881  */
 882 static int stmmac_init_ptp(struct stmmac_priv *priv)
 883 {
 884         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 885         int ret;
 886
 887         if (priv->plat->ptp_clk_freq_config)
 888                 priv->plat->ptp_clk_freq_config(priv);
 889
 890         ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE);
 891         if (ret)
 892                 return ret;
 893
 894         priv->adv_ts = 0;
 895         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 896         if (xmac && priv->dma_cap.atime_stamp)
 897                 priv->adv_ts = 1;
 898         /* Dwmac 3.x core with extend_desc can support adv_ts */
 899         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 900                 priv->adv_ts = 1;
 901
 902         if (priv->dma_cap.time_stamp)
 903                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 904
 905         if (priv->adv_ts)
 906                 netdev_info(priv->dev,
 907                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 908
 909         priv->hwts_tx_en = 0;
 910         priv->hwts_rx_en = 0;
 911
 912         return 0;
 913 }
 914
 915 static void stmmac_release_ptp(struct stmmac_priv *priv)
 916 {
 917         clk_disable_unprepare(priv->plat->clk_ptp_ref);
 918         stmmac_ptp_unregister(priv);
 919 }
 920
 921 /**
 922  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 923  *  @priv: driver private structure
 924  *  @duplex: duplex passed to the next function
 925  *  Description: It is used for configuring the flow control in all queues
 926  */
 927 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 928 {
 929         u32 tx_cnt = priv->plat->tx_queues_to_use;
 930
 931         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 932                         priv->pause, tx_cnt);
 933 }
 934
 935 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
 936                                                  phy_interface_t interface)
 937 {
 938         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 939
 940         if (priv->hw->xpcs)
 941                 return &priv->hw->xpcs->pcs;
 942
 943         if (priv->hw->lynx_pcs)
 944                 return priv->hw->lynx_pcs;
 945
 946         return NULL;
 947 }
 948
 949 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 950                               const struct phylink_link_state *state)
 951 {
 952         /* Nothing to do, xpcs_config() handles everything */
 953 }
 954
 955 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up)
 956 {
 957         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
 958         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
 959         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
 960         bool *hs_enable = &fpe_cfg->hs_enable;
 961
 962         if (is_up && *hs_enable) {
 963                 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY);
 964         } else {
 965                 *lo_state = FPE_STATE_OFF;
 966                 *lp_state = FPE_STATE_OFF;
 967         }
 968 }
 969
 970 static void stmmac_mac_link_down(struct phylink_config *config,
 971                                  unsigned int mode, phy_interface_t interface)
 972 {
 973         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 974
 975         stmmac_mac_set(priv, priv->ioaddr, false);
 976         priv->eee_active = false;
 977         priv->tx_lpi_enabled = false;
 978         priv->eee_enabled = stmmac_eee_init(priv);
 979         stmmac_set_eee_pls(priv, priv->hw, false);
 980
 981         if (priv->dma_cap.fpesel)
 982                 stmmac_fpe_link_state_handle(priv, false);
 983 }
 984
 985 static void stmmac_mac_link_up(struct phylink_config *config,
 986                                struct phy_device *phy,
 987                                unsigned int mode, phy_interface_t interface,
 988                                int speed, int duplex,
 989                                bool tx_pause, bool rx_pause)
 990 {
 991         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 992         u32 old_ctrl, ctrl;
 993
 994         if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
 995             priv->plat->serdes_powerup)
 996                 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv);
 997
 998         old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 999         ctrl = old_ctrl & ~priv->hw->link.speed_mask;
1000
1001         if (interface == PHY_INTERFACE_MODE_USXGMII) {
1002                 switch (speed) {
1003                 case SPEED_10000:
1004                         ctrl |= priv->hw->link.xgmii.speed10000;
1005                         break;
1006                 case SPEED_5000:
1007                         ctrl |= priv->hw->link.xgmii.speed5000;
1008                         break;
1009                 case SPEED_2500:
1010                         ctrl |= priv->hw->link.xgmii.speed2500;
1011                         break;
1012                 default:
1013                         return;
1014                 }
1015         } else if (interface == PHY_INTERFACE_MODE_XLGMII) {
1016                 switch (speed) {
1017                 case SPEED_100000:
1018                         ctrl |= priv->hw->link.xlgmii.speed100000;
1019                         break;
1020                 case SPEED_50000:
1021                         ctrl |= priv->hw->link.xlgmii.speed50000;
1022                         break;
1023                 case SPEED_40000:
1024                         ctrl |= priv->hw->link.xlgmii.speed40000;
1025                         break;
1026                 case SPEED_25000:
1027                         ctrl |= priv->hw->link.xlgmii.speed25000;
1028                         break;
1029                 case SPEED_10000:
1030                         ctrl |= priv->hw->link.xgmii.speed10000;
1031                         break;
1032                 case SPEED_2500:
1033                         ctrl |= priv->hw->link.speed2500;
1034                         break;
1035                 case SPEED_1000:
1036                         ctrl |= priv->hw->link.speed1000;
1037                         break;
1038                 default:
1039                         return;
1040                 }
1041         } else {
1042                 switch (speed) {
1043                 case SPEED_2500:
1044                         ctrl |= priv->hw->link.speed2500;
1045                         break;
1046                 case SPEED_1000:
1047                         ctrl |= priv->hw->link.speed1000;
1048                         break;
1049                 case SPEED_100:
1050                         ctrl |= priv->hw->link.speed100;
1051                         break;
1052                 case SPEED_10:
1053                         ctrl |= priv->hw->link.speed10;
1054                         break;
1055                 default:
1056                         return;
1057                 }
1058         }
1059
1060         priv->speed = speed;
1061
1062         if (priv->plat->fix_mac_speed)
1063                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed);
1064
1065         if (!duplex)
1066                 ctrl &= ~priv->hw->link.duplex;
1067         else
1068                 ctrl |= priv->hw->link.duplex;
1069
1070         /* Flow Control operation */
1071         if (rx_pause && tx_pause)
1072                 priv->flow_ctrl = FLOW_AUTO;
1073         else if (rx_pause && !tx_pause)
1074                 priv->flow_ctrl = FLOW_RX;
1075         else if (!rx_pause && tx_pause)
1076                 priv->flow_ctrl = FLOW_TX;
1077         else
1078                 priv->flow_ctrl = FLOW_OFF;
1079
1080         stmmac_mac_flow_ctrl(priv, duplex);
1081
1082         if (ctrl != old_ctrl)
1083                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
1084
1085         stmmac_mac_set(priv, priv->ioaddr, true);
1086         if (phy && priv->dma_cap.eee) {
1087                 priv->eee_active =
1088                         phy_init_eee(phy, !priv->plat->rx_clk_runs_in_lpi) >= 0;
1089                 priv->eee_enabled = stmmac_eee_init(priv);
1090                 priv->tx_lpi_enabled = priv->eee_enabled;
1091                 stmmac_set_eee_pls(priv, priv->hw, true);
1092         }
1093
1094         if (priv->dma_cap.fpesel)
1095                 stmmac_fpe_link_state_handle(priv, true);
1096 }
1097
1098 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
1099         .mac_select_pcs = stmmac_mac_select_pcs,
1100         .mac_config = stmmac_mac_config,
1101         .mac_link_down = stmmac_mac_link_down,
1102         .mac_link_up = stmmac_mac_link_up,
1103 };
1104
1105 /**
1106  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
1107  * @priv: driver private structure
1108  * Description: this is to verify if the HW supports the PCS.
1109  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
1110  * configured for the TBI, RTBI, or SGMII PHY interface.
1111  */
1112 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
1113 {
1114         int interface = priv->plat->interface;
1115
1116         if (priv->dma_cap.pcs) {
1117                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
1118                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
1119                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1120                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
1121                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
1122                         priv->hw->pcs = STMMAC_PCS_RGMII;
1123                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
1124                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
1125                         priv->hw->pcs = STMMAC_PCS_SGMII;
1126                 }
1127         }
1128 }
1129
1130 /**
1131  * stmmac_init_phy - PHY initialization
1132  * @dev: net device structure
1133  * Description: it initializes the driver's PHY state, and attaches the PHY
1134  * to the mac driver.
1135  *  Return value:
1136  *  0 on success
1137  */
1138 static int stmmac_init_phy(struct net_device *dev)
1139 {
1140         struct stmmac_priv *priv = netdev_priv(dev);
1141         struct fwnode_handle *phy_fwnode;
1142         struct fwnode_handle *fwnode;
1143         int ret;
1144
1145         if (!phylink_expects_phy(priv->phylink))
1146                 return 0;
1147
1148         fwnode = of_fwnode_handle(priv->plat->phylink_node);
1149         if (!fwnode)
1150                 fwnode = dev_fwnode(priv->device);
1151
1152         if (fwnode)
1153                 phy_fwnode = fwnode_get_phy_node(fwnode);
1154         else
1155                 phy_fwnode = NULL;
1156
1157         /* Some DT bindings do not set-up the PHY handle. Let's try to
1158          * manually parse it
1159          */
1160         if (!phy_fwnode || IS_ERR(phy_fwnode)) {
1161                 int addr = priv->plat->phy_addr;
1162                 struct phy_device *phydev;
1163
1164                 if (addr < 0) {
1165                         netdev_err(priv->dev, "no phy found\n");
1166                         return -ENODEV;
1167                 }
1168
1169                 phydev = mdiobus_get_phy(priv->mii, addr);
1170                 if (!phydev) {
1171                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1172                         return -ENODEV;
1173                 }
1174
1175                 ret = phylink_connect_phy(priv->phylink, phydev);
1176         } else {
1177                 fwnode_handle_put(phy_fwnode);
1178                 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
1179         }
1180
1181         if (!priv->plat->pmt) {
1182                 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1183
1184                 phylink_ethtool_get_wol(priv->phylink, &wol);
1185                 device_set_wakeup_capable(priv->device, !!wol.supported);
1186                 device_set_wakeup_enable(priv->device, !!wol.wolopts);
1187         }
1188
1189         return ret;
1190 }
1191
1192 static int stmmac_phy_setup(struct stmmac_priv *priv)
1193 {
1194         struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
1195         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1196         int max_speed = priv->plat->max_speed;
1197         int mode = priv->plat->phy_interface;
1198         struct phylink *phylink;
1199
1200         priv->phylink_config.dev = &priv->dev->dev;
1201         priv->phylink_config.type = PHYLINK_NETDEV;
1202         if (priv->plat->mdio_bus_data)
1203                 priv->phylink_config.ovr_an_inband =
1204                         mdio_bus_data->xpcs_an_inband;
1205
1206         if (!fwnode)
1207                 fwnode = dev_fwnode(priv->device);
1208
1209         /* Set the platform/firmware specified interface mode */
1210         __set_bit(mode, priv->phylink_config.supported_interfaces);
1211
1212         /* If we have an xpcs, it defines which PHY interfaces are supported. */
1213         if (priv->hw->xpcs)
1214                 xpcs_get_interfaces(priv->hw->xpcs,
1215                                     priv->phylink_config.supported_interfaces);
1216
1217         priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1218                 MAC_10 | MAC_100;
1219
1220         if (!max_speed || max_speed >= 1000)
1221                 priv->phylink_config.mac_capabilities |= MAC_1000;
1222
1223         if (priv->plat->has_gmac4) {
1224                 if (!max_speed || max_speed >= 2500)
1225                         priv->phylink_config.mac_capabilities |= MAC_2500FD;
1226         } else if (priv->plat->has_xgmac) {
1227                 if (!max_speed || max_speed >= 2500)
1228                         priv->phylink_config.mac_capabilities |= MAC_2500FD;
1229                 if (!max_speed || max_speed >= 5000)
1230                         priv->phylink_config.mac_capabilities |= MAC_5000FD;
1231                 if (!max_speed || max_speed >= 10000)
1232                         priv->phylink_config.mac_capabilities |= MAC_10000FD;
1233                 if (!max_speed || max_speed >= 25000)
1234                         priv->phylink_config.mac_capabilities |= MAC_25000FD;
1235                 if (!max_speed || max_speed >= 40000)
1236                         priv->phylink_config.mac_capabilities |= MAC_40000FD;
1237                 if (!max_speed || max_speed >= 50000)
1238                         priv->phylink_config.mac_capabilities |= MAC_50000FD;
1239                 if (!max_speed || max_speed >= 100000)
1240                         priv->phylink_config.mac_capabilities |= MAC_100000FD;
1241         }
1242
1243         /* Half-Duplex can only work with single queue */
1244         if (priv->plat->tx_queues_to_use > 1)
1245                 priv->phylink_config.mac_capabilities &=
1246                         ~(MAC_10HD | MAC_100HD | MAC_1000HD);
1247         priv->phylink_config.mac_managed_pm = true;
1248
1249         phylink = phylink_create(&priv->phylink_config, fwnode,
1250                                  mode, &stmmac_phylink_mac_ops);
1251         if (IS_ERR(phylink))
1252                 return PTR_ERR(phylink);
1253
1254         priv->phylink = phylink;
1255         return 0;
1256 }
1257
1258 static void stmmac_display_rx_rings(struct stmmac_priv *priv,
1259                                     struct stmmac_dma_conf *dma_conf)
1260 {
1261         u32 rx_cnt = priv->plat->rx_queues_to_use;
1262         unsigned int desc_size;
1263         void *head_rx;
1264         u32 queue;
1265
1266         /* Display RX rings */
1267         for (queue = 0; queue < rx_cnt; queue++) {
1268                 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1269
1270                 pr_info("\tRX Queue %u rings\n", queue);
1271
1272                 if (priv->extend_desc) {
1273                         head_rx = (void *)rx_q->dma_erx;
1274                         desc_size = sizeof(struct dma_extended_desc);
1275                 } else {
1276                         head_rx = (void *)rx_q->dma_rx;
1277                         desc_size = sizeof(struct dma_desc);
1278                 }
1279
1280                 /* Display RX ring */
1281                 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true,
1282                                     rx_q->dma_rx_phy, desc_size);
1283         }
1284 }
1285
1286 static void stmmac_display_tx_rings(struct stmmac_priv *priv,
1287                                     struct stmmac_dma_conf *dma_conf)
1288 {
1289         u32 tx_cnt = priv->plat->tx_queues_to_use;
1290         unsigned int desc_size;
1291         void *head_tx;
1292         u32 queue;
1293
1294         /* Display TX rings */
1295         for (queue = 0; queue < tx_cnt; queue++) {
1296                 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1297
1298                 pr_info("\tTX Queue %d rings\n", queue);
1299
1300                 if (priv->extend_desc) {
1301                         head_tx = (void *)tx_q->dma_etx;
1302                         desc_size = sizeof(struct dma_extended_desc);
1303                 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1304                         head_tx = (void *)tx_q->dma_entx;
1305                         desc_size = sizeof(struct dma_edesc);
1306                 } else {
1307                         head_tx = (void *)tx_q->dma_tx;
1308                         desc_size = sizeof(struct dma_desc);
1309                 }
1310
1311                 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false,
1312                                     tx_q->dma_tx_phy, desc_size);
1313         }
1314 }
1315
1316 static void stmmac_display_rings(struct stmmac_priv *priv,
1317                                  struct stmmac_dma_conf *dma_conf)
1318 {
1319         /* Display RX ring */
1320         stmmac_display_rx_rings(priv, dma_conf);
1321
1322         /* Display TX ring */
1323         stmmac_display_tx_rings(priv, dma_conf);
1324 }
1325
1326 static int stmmac_set_bfsize(int mtu, int bufsize)
1327 {
1328         int ret = bufsize;
1329
1330         if (mtu >= BUF_SIZE_8KiB)
1331                 ret = BUF_SIZE_16KiB;
1332         else if (mtu >= BUF_SIZE_4KiB)
1333                 ret = BUF_SIZE_8KiB;
1334         else if (mtu >= BUF_SIZE_2KiB)
1335                 ret = BUF_SIZE_4KiB;
1336         else if (mtu > DEFAULT_BUFSIZE)
1337                 ret = BUF_SIZE_2KiB;
1338         else
1339                 ret = DEFAULT_BUFSIZE;
1340
1341         return ret;
1342 }
1343
1344 /**
1345  * stmmac_clear_rx_descriptors - clear RX descriptors
1346  * @priv: driver private structure
1347  * @dma_conf: structure to take the dma data
1348  * @queue: RX queue index
1349  * Description: this function is called to clear the RX descriptors
1350  * in case of both basic and extended descriptors are used.
1351  */
1352 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv,
1353                                         struct stmmac_dma_conf *dma_conf,
1354                                         u32 queue)
1355 {
1356         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1357         int i;
1358
1359         /* Clear the RX descriptors */
1360         for (i = 0; i < dma_conf->dma_rx_size; i++)
1361                 if (priv->extend_desc)
1362                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1363                                         priv->use_riwt, priv->mode,
1364                                         (i == dma_conf->dma_rx_size - 1),
1365                                         dma_conf->dma_buf_sz);
1366                 else
1367                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1368                                         priv->use_riwt, priv->mode,
1369                                         (i == dma_conf->dma_rx_size - 1),
1370                                         dma_conf->dma_buf_sz);
1371 }
1372
1373 /**
1374  * stmmac_clear_tx_descriptors - clear tx descriptors
1375  * @priv: driver private structure
1376  * @dma_conf: structure to take the dma data
1377  * @queue: TX queue index.
1378  * Description: this function is called to clear the TX descriptors
1379  * in case of both basic and extended descriptors are used.
1380  */
1381 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv,
1382                                         struct stmmac_dma_conf *dma_conf,
1383                                         u32 queue)
1384 {
1385         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1386         int i;
1387
1388         /* Clear the TX descriptors */
1389         for (i = 0; i < dma_conf->dma_tx_size; i++) {
1390                 int last = (i == (dma_conf->dma_tx_size - 1));
1391                 struct dma_desc *p;
1392
1393                 if (priv->extend_desc)
1394                         p = &tx_q->dma_etx[i].basic;
1395                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1396                         p = &tx_q->dma_entx[i].basic;
1397                 else
1398                         p = &tx_q->dma_tx[i];
1399
1400                 stmmac_init_tx_desc(priv, p, priv->mode, last);
1401         }
1402 }
1403
1404 /**
1405  * stmmac_clear_descriptors - clear descriptors
1406  * @priv: driver private structure
1407  * @dma_conf: structure to take the dma data
1408  * Description: this function is called to clear the TX and RX descriptors
1409  * in case of both basic and extended descriptors are used.
1410  */
1411 static void stmmac_clear_descriptors(struct stmmac_priv *priv,
1412                                      struct stmmac_dma_conf *dma_conf)
1413 {
1414         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1415         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1416         u32 queue;
1417
1418         /* Clear the RX descriptors */
1419         for (queue = 0; queue < rx_queue_cnt; queue++)
1420                 stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1421
1422         /* Clear the TX descriptors */
1423         for (queue = 0; queue < tx_queue_cnt; queue++)
1424                 stmmac_clear_tx_descriptors(priv, dma_conf, queue);
1425 }
1426
1427 /**
1428  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1429  * @priv: driver private structure
1430  * @dma_conf: structure to take the dma data
1431  * @p: descriptor pointer
1432  * @i: descriptor index
1433  * @flags: gfp flag
1434  * @queue: RX queue index
1435  * Description: this function is called to allocate a receive buffer, perform
1436  * the DMA mapping and init the descriptor.
1437  */
1438 static int stmmac_init_rx_buffers(struct stmmac_priv *priv,
1439                                   struct stmmac_dma_conf *dma_conf,
1440                                   struct dma_desc *p,
1441                                   int i, gfp_t flags, u32 queue)
1442 {
1443         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1444         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1445         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
1446
1447         if (priv->dma_cap.host_dma_width <= 32)
1448                 gfp |= GFP_DMA32;
1449
1450         if (!buf->page) {
1451                 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1452                 if (!buf->page)
1453                         return -ENOMEM;
1454                 buf->page_offset = stmmac_rx_offset(priv);
1455         }
1456
1457         if (priv->sph && !buf->sec_page) {
1458                 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
1459                 if (!buf->sec_page)
1460                         return -ENOMEM;
1461
1462                 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1463                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
1464         } else {
1465                 buf->sec_page = NULL;
1466                 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
1467         }
1468
1469         buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
1470
1471         stmmac_set_desc_addr(priv, p, buf->addr);
1472         if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB)
1473                 stmmac_init_desc3(priv, p);
1474
1475         return 0;
1476 }
1477
1478 /**
1479  * stmmac_free_rx_buffer - free RX dma buffers
1480  * @priv: private structure
1481  * @rx_q: RX queue
1482  * @i: buffer index.
1483  */
1484 static void stmmac_free_rx_buffer(struct stmmac_priv *priv,
1485                                   struct stmmac_rx_queue *rx_q,
1486                                   int i)
1487 {
1488         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1489
1490         if (buf->page)
1491                 page_pool_put_full_page(rx_q->page_pool, buf->page, false);
1492         buf->page = NULL;
1493
1494         if (buf->sec_page)
1495                 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false);
1496         buf->sec_page = NULL;
1497 }
1498
1499 /**
1500  * stmmac_free_tx_buffer - free RX dma buffers
1501  * @priv: private structure
1502  * @dma_conf: structure to take the dma data
1503  * @queue: RX queue index
1504  * @i: buffer index.
1505  */
1506 static void stmmac_free_tx_buffer(struct stmmac_priv *priv,
1507                                   struct stmmac_dma_conf *dma_conf,
1508                                   u32 queue, int i)
1509 {
1510         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1511
1512         if (tx_q->tx_skbuff_dma[i].buf &&
1513             tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
1514                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1515                         dma_unmap_page(priv->device,
1516                                        tx_q->tx_skbuff_dma[i].buf,
1517                                        tx_q->tx_skbuff_dma[i].len,
1518                                        DMA_TO_DEVICE);
1519                 else
1520                         dma_unmap_single(priv->device,
1521                                          tx_q->tx_skbuff_dma[i].buf,
1522                                          tx_q->tx_skbuff_dma[i].len,
1523                                          DMA_TO_DEVICE);
1524         }
1525
1526         if (tx_q->xdpf[i] &&
1527             (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX ||
1528              tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) {
1529                 xdp_return_frame(tx_q->xdpf[i]);
1530                 tx_q->xdpf[i] = NULL;
1531         }
1532
1533         if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX)
1534                 tx_q->xsk_frames_done++;
1535
1536         if (tx_q->tx_skbuff[i] &&
1537             tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) {
1538                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1539                 tx_q->tx_skbuff[i] = NULL;
1540         }
1541
1542         tx_q->tx_skbuff_dma[i].buf = 0;
1543         tx_q->tx_skbuff_dma[i].map_as_page = false;
1544 }
1545
1546 /**
1547  * dma_free_rx_skbufs - free RX dma buffers
1548  * @priv: private structure
1549  * @dma_conf: structure to take the dma data
1550  * @queue: RX queue index
1551  */
1552 static void dma_free_rx_skbufs(struct stmmac_priv *priv,
1553                                struct stmmac_dma_conf *dma_conf,
1554                                u32 queue)
1555 {
1556         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1557         int i;
1558
1559         for (i = 0; i < dma_conf->dma_rx_size; i++)
1560                 stmmac_free_rx_buffer(priv, rx_q, i);
1561 }
1562
1563 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv,
1564                                    struct stmmac_dma_conf *dma_conf,
1565                                    u32 queue, gfp_t flags)
1566 {
1567         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1568         int i;
1569
1570         for (i = 0; i < dma_conf->dma_rx_size; i++) {
1571                 struct dma_desc *p;
1572                 int ret;
1573
1574                 if (priv->extend_desc)
1575                         p = &((rx_q->dma_erx + i)->basic);
1576                 else
1577                         p = rx_q->dma_rx + i;
1578
1579                 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags,
1580                                              queue);
1581                 if (ret)
1582                         return ret;
1583
1584                 rx_q->buf_alloc_num++;
1585         }
1586
1587         return 0;
1588 }
1589
1590 /**
1591  * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
1592  * @priv: private structure
1593  * @dma_conf: structure to take the dma data
1594  * @queue: RX queue index
1595  */
1596 static void dma_free_rx_xskbufs(struct stmmac_priv *priv,
1597                                 struct stmmac_dma_conf *dma_conf,
1598                                 u32 queue)
1599 {
1600         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1601         int i;
1602
1603         for (i = 0; i < dma_conf->dma_rx_size; i++) {
1604                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1605
1606                 if (!buf->xdp)
1607                         continue;
1608
1609                 xsk_buff_free(buf->xdp);
1610                 buf->xdp = NULL;
1611         }
1612 }
1613
1614 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv,
1615                                       struct stmmac_dma_conf *dma_conf,
1616                                       u32 queue)
1617 {
1618         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1619         int i;
1620
1621         /* struct stmmac_xdp_buff is using cb field (maximum size of 24 bytes)
1622          * in struct xdp_buff_xsk to stash driver specific information. Thus,
1623          * use this macro to make sure no size violations.
1624          */
1625         XSK_CHECK_PRIV_TYPE(struct stmmac_xdp_buff);
1626
1627         for (i = 0; i < dma_conf->dma_rx_size; i++) {
1628                 struct stmmac_rx_buffer *buf;
1629                 dma_addr_t dma_addr;
1630                 struct dma_desc *p;
1631
1632                 if (priv->extend_desc)
1633                         p = (struct dma_desc *)(rx_q->dma_erx + i);
1634                 else
1635                         p = rx_q->dma_rx + i;
1636
1637                 buf = &rx_q->buf_pool[i];
1638
1639                 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
1640                 if (!buf->xdp)
1641                         return -ENOMEM;
1642
1643                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
1644                 stmmac_set_desc_addr(priv, p, dma_addr);
1645                 rx_q->buf_alloc_num++;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue)
1652 {
1653         if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps))
1654                 return NULL;
1655
1656         return xsk_get_pool_from_qid(priv->dev, queue);
1657 }
1658
1659 /**
1660  * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
1661  * @priv: driver private structure
1662  * @dma_conf: structure to take the dma data
1663  * @queue: RX queue index
1664  * @flags: gfp flag.
1665  * Description: this function initializes the DMA RX descriptors
1666  * and allocates the socket buffers. It supports the chained and ring
1667  * modes.
1668  */
1669 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv,
1670                                     struct stmmac_dma_conf *dma_conf,
1671                                     u32 queue, gfp_t flags)
1672 {
1673         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1674         int ret;
1675
1676         netif_dbg(priv, probe, priv->dev,
1677                   "(%s) dma_rx_phy=0x%08x\n", __func__,
1678                   (u32)rx_q->dma_rx_phy);
1679
1680         stmmac_clear_rx_descriptors(priv, dma_conf, queue);
1681
1682         xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
1683
1684         rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1685
1686         if (rx_q->xsk_pool) {
1687                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1688                                                    MEM_TYPE_XSK_BUFF_POOL,
1689                                                    NULL));
1690                 netdev_info(priv->dev,
1691                             "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n",
1692                             rx_q->queue_index);
1693                 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq);
1694         } else {
1695                 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq,
1696                                                    MEM_TYPE_PAGE_POOL,
1697                                                    rx_q->page_pool));
1698                 netdev_info(priv->dev,
1699                             "Register MEM_TYPE_PAGE_POOL RxQ-%d\n",
1700                             rx_q->queue_index);
1701         }
1702
1703         if (rx_q->xsk_pool) {
1704                 /* RX XDP ZC buffer pool may not be populated, e.g.
1705                  * xdpsock TX-only.
1706                  */
1707                 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue);
1708         } else {
1709                 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags);
1710                 if (ret < 0)
1711                         return -ENOMEM;
1712         }
1713
1714         /* Setup the chained descriptor addresses */
1715         if (priv->mode == STMMAC_CHAIN_MODE) {
1716                 if (priv->extend_desc)
1717                         stmmac_mode_init(priv, rx_q->dma_erx,
1718                                          rx_q->dma_rx_phy,
1719                                          dma_conf->dma_rx_size, 1);
1720                 else
1721                         stmmac_mode_init(priv, rx_q->dma_rx,
1722                                          rx_q->dma_rx_phy,
1723                                          dma_conf->dma_rx_size, 0);
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int init_dma_rx_desc_rings(struct net_device *dev,
1730                                   struct stmmac_dma_conf *dma_conf,
1731                                   gfp_t flags)
1732 {
1733         struct stmmac_priv *priv = netdev_priv(dev);
1734         u32 rx_count = priv->plat->rx_queues_to_use;
1735         int queue;
1736         int ret;
1737
1738         /* RX INITIALIZATION */
1739         netif_dbg(priv, probe, priv->dev,
1740                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1741
1742         for (queue = 0; queue < rx_count; queue++) {
1743                 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags);
1744                 if (ret)
1745                         goto err_init_rx_buffers;
1746         }
1747
1748         return 0;
1749
1750 err_init_rx_buffers:
1751         while (queue >= 0) {
1752                 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1753
1754                 if (rx_q->xsk_pool)
1755                         dma_free_rx_xskbufs(priv, dma_conf, queue);
1756                 else
1757                         dma_free_rx_skbufs(priv, dma_conf, queue);
1758
1759                 rx_q->buf_alloc_num = 0;
1760                 rx_q->xsk_pool = NULL;
1761
1762                 queue--;
1763         }
1764
1765         return ret;
1766 }
1767
1768 /**
1769  * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
1770  * @priv: driver private structure
1771  * @dma_conf: structure to take the dma data
1772  * @queue: TX queue index
1773  * Description: this function initializes the DMA TX descriptors
1774  * and allocates the socket buffers. It supports the chained and ring
1775  * modes.
1776  */
1777 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv,
1778                                     struct stmmac_dma_conf *dma_conf,
1779                                     u32 queue)
1780 {
1781         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1782         int i;
1783
1784         netif_dbg(priv, probe, priv->dev,
1785                   "(%s) dma_tx_phy=0x%08x\n", __func__,
1786                   (u32)tx_q->dma_tx_phy);
1787
1788         /* Setup the chained descriptor addresses */
1789         if (priv->mode == STMMAC_CHAIN_MODE) {
1790                 if (priv->extend_desc)
1791                         stmmac_mode_init(priv, tx_q->dma_etx,
1792                                          tx_q->dma_tx_phy,
1793                                          dma_conf->dma_tx_size, 1);
1794                 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL))
1795                         stmmac_mode_init(priv, tx_q->dma_tx,
1796                                          tx_q->dma_tx_phy,
1797                                          dma_conf->dma_tx_size, 0);
1798         }
1799
1800         tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue);
1801
1802         for (i = 0; i < dma_conf->dma_tx_size; i++) {
1803                 struct dma_desc *p;
1804
1805                 if (priv->extend_desc)
1806                         p = &((tx_q->dma_etx + i)->basic);
1807                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
1808                         p = &((tx_q->dma_entx + i)->basic);
1809                 else
1810                         p = tx_q->dma_tx + i;
1811
1812                 stmmac_clear_desc(priv, p);
1813
1814                 tx_q->tx_skbuff_dma[i].buf = 0;
1815                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1816                 tx_q->tx_skbuff_dma[i].len = 0;
1817                 tx_q->tx_skbuff_dma[i].last_segment = false;
1818                 tx_q->tx_skbuff[i] = NULL;
1819         }
1820
1821         return 0;
1822 }
1823
1824 static int init_dma_tx_desc_rings(struct net_device *dev,
1825                                   struct stmmac_dma_conf *dma_conf)
1826 {
1827         struct stmmac_priv *priv = netdev_priv(dev);
1828         u32 tx_queue_cnt;
1829         u32 queue;
1830
1831         tx_queue_cnt = priv->plat->tx_queues_to_use;
1832
1833         for (queue = 0; queue < tx_queue_cnt; queue++)
1834                 __init_dma_tx_desc_rings(priv, dma_conf, queue);
1835
1836         return 0;
1837 }
1838
1839 /**
1840  * init_dma_desc_rings - init the RX/TX descriptor rings
1841  * @dev: net device structure
1842  * @dma_conf: structure to take the dma data
1843  * @flags: gfp flag.
1844  * Description: this function initializes the DMA RX/TX descriptors
1845  * and allocates the socket buffers. It supports the chained and ring
1846  * modes.
1847  */
1848 static int init_dma_desc_rings(struct net_device *dev,
1849                                struct stmmac_dma_conf *dma_conf,
1850                                gfp_t flags)
1851 {
1852         struct stmmac_priv *priv = netdev_priv(dev);
1853         int ret;
1854
1855         ret = init_dma_rx_desc_rings(dev, dma_conf, flags);
1856         if (ret)
1857                 return ret;
1858
1859         ret = init_dma_tx_desc_rings(dev, dma_conf);
1860
1861         stmmac_clear_descriptors(priv, dma_conf);
1862
1863         if (netif_msg_hw(priv))
1864                 stmmac_display_rings(priv, dma_conf);
1865
1866         return ret;
1867 }
1868
1869 /**
1870  * dma_free_tx_skbufs - free TX dma buffers
1871  * @priv: private structure
1872  * @dma_conf: structure to take the dma data
1873  * @queue: TX queue index
1874  */
1875 static void dma_free_tx_skbufs(struct stmmac_priv *priv,
1876                                struct stmmac_dma_conf *dma_conf,
1877                                u32 queue)
1878 {
1879         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1880         int i;
1881
1882         tx_q->xsk_frames_done = 0;
1883
1884         for (i = 0; i < dma_conf->dma_tx_size; i++)
1885                 stmmac_free_tx_buffer(priv, dma_conf, queue, i);
1886
1887         if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
1888                 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
1889                 tx_q->xsk_frames_done = 0;
1890                 tx_q->xsk_pool = NULL;
1891         }
1892 }
1893
1894 /**
1895  * stmmac_free_tx_skbufs - free TX skb buffers
1896  * @priv: private structure
1897  */
1898 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
1899 {
1900         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1901         u32 queue;
1902
1903         for (queue = 0; queue < tx_queue_cnt; queue++)
1904                 dma_free_tx_skbufs(priv, &priv->dma_conf, queue);
1905 }
1906
1907 /**
1908  * __free_dma_rx_desc_resources - free RX dma desc resources (per queue)
1909  * @priv: private structure
1910  * @dma_conf: structure to take the dma data
1911  * @queue: RX queue index
1912  */
1913 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv,
1914                                          struct stmmac_dma_conf *dma_conf,
1915                                          u32 queue)
1916 {
1917         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
1918
1919         /* Release the DMA RX socket buffers */
1920         if (rx_q->xsk_pool)
1921                 dma_free_rx_xskbufs(priv, dma_conf, queue);
1922         else
1923                 dma_free_rx_skbufs(priv, dma_conf, queue);
1924
1925         rx_q->buf_alloc_num = 0;
1926         rx_q->xsk_pool = NULL;
1927
1928         /* Free DMA regions of consistent memory previously allocated */
1929         if (!priv->extend_desc)
1930                 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1931                                   sizeof(struct dma_desc),
1932                                   rx_q->dma_rx, rx_q->dma_rx_phy);
1933         else
1934                 dma_free_coherent(priv->device, dma_conf->dma_rx_size *
1935                                   sizeof(struct dma_extended_desc),
1936                                   rx_q->dma_erx, rx_q->dma_rx_phy);
1937
1938         if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq))
1939                 xdp_rxq_info_unreg(&rx_q->xdp_rxq);
1940
1941         kfree(rx_q->buf_pool);
1942         if (rx_q->page_pool)
1943                 page_pool_destroy(rx_q->page_pool);
1944 }
1945
1946 static void free_dma_rx_desc_resources(struct stmmac_priv *priv,
1947                                        struct stmmac_dma_conf *dma_conf)
1948 {
1949         u32 rx_count = priv->plat->rx_queues_to_use;
1950         u32 queue;
1951
1952         /* Free RX queue resources */
1953         for (queue = 0; queue < rx_count; queue++)
1954                 __free_dma_rx_desc_resources(priv, dma_conf, queue);
1955 }
1956
1957 /**
1958  * __free_dma_tx_desc_resources - free TX dma desc resources (per queue)
1959  * @priv: private structure
1960  * @dma_conf: structure to take the dma data
1961  * @queue: TX queue index
1962  */
1963 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv,
1964                                          struct stmmac_dma_conf *dma_conf,
1965                                          u32 queue)
1966 {
1967         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
1968         size_t size;
1969         void *addr;
1970
1971         /* Release the DMA TX socket buffers */
1972         dma_free_tx_skbufs(priv, dma_conf, queue);
1973
1974         if (priv->extend_desc) {
1975                 size = sizeof(struct dma_extended_desc);
1976                 addr = tx_q->dma_etx;
1977         } else if (tx_q->tbs & STMMAC_TBS_AVAIL) {
1978                 size = sizeof(struct dma_edesc);
1979                 addr = tx_q->dma_entx;
1980         } else {
1981                 size = sizeof(struct dma_desc);
1982                 addr = tx_q->dma_tx;
1983         }
1984
1985         size *= dma_conf->dma_tx_size;
1986
1987         dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
1988
1989         kfree(tx_q->tx_skbuff_dma);
1990         kfree(tx_q->tx_skbuff);
1991 }
1992
1993 static void free_dma_tx_desc_resources(struct stmmac_priv *priv,
1994                                        struct stmmac_dma_conf *dma_conf)
1995 {
1996         u32 tx_count = priv->plat->tx_queues_to_use;
1997         u32 queue;
1998
1999         /* Free TX queue resources */
2000         for (queue = 0; queue < tx_count; queue++)
2001                 __free_dma_tx_desc_resources(priv, dma_conf, queue);
2002 }
2003
2004 /**
2005  * __alloc_dma_rx_desc_resources - alloc RX resources (per queue).
2006  * @priv: private structure
2007  * @dma_conf: structure to take the dma data
2008  * @queue: RX queue index
2009  * Description: according to which descriptor can be used (extend or basic)
2010  * this function allocates the resources for TX and RX paths. In case of
2011  * reception, for example, it pre-allocated the RX socket buffer in order to
2012  * allow zero-copy mechanism.
2013  */
2014 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2015                                          struct stmmac_dma_conf *dma_conf,
2016                                          u32 queue)
2017 {
2018         struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
2019         struct stmmac_channel *ch = &priv->channel[queue];
2020         bool xdp_prog = stmmac_xdp_is_enabled(priv);
2021         struct page_pool_params pp_params = { 0 };
2022         unsigned int num_pages;
2023         unsigned int napi_id;
2024         int ret;
2025
2026         rx_q->queue_index = queue;
2027         rx_q->priv_data = priv;
2028
2029         pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
2030         pp_params.pool_size = dma_conf->dma_rx_size;
2031         num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE);
2032         pp_params.order = ilog2(num_pages);
2033         pp_params.nid = dev_to_node(priv->device);
2034         pp_params.dev = priv->device;
2035         pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
2036         pp_params.offset = stmmac_rx_offset(priv);
2037         pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages);
2038
2039         rx_q->page_pool = page_pool_create(&pp_params);
2040         if (IS_ERR(rx_q->page_pool)) {
2041                 ret = PTR_ERR(rx_q->page_pool);
2042                 rx_q->page_pool = NULL;
2043                 return ret;
2044         }
2045
2046         rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size,
2047                                  sizeof(*rx_q->buf_pool),
2048                                  GFP_KERNEL);
2049         if (!rx_q->buf_pool)
2050                 return -ENOMEM;
2051
2052         if (priv->extend_desc) {
2053                 rx_q->dma_erx = dma_alloc_coherent(priv->device,
2054                                                    dma_conf->dma_rx_size *
2055                                                    sizeof(struct dma_extended_desc),
2056                                                    &rx_q->dma_rx_phy,
2057                                                    GFP_KERNEL);
2058                 if (!rx_q->dma_erx)
2059                         return -ENOMEM;
2060
2061         } else {
2062                 rx_q->dma_rx = dma_alloc_coherent(priv->device,
2063                                                   dma_conf->dma_rx_size *
2064                                                   sizeof(struct dma_desc),
2065                                                   &rx_q->dma_rx_phy,
2066                                                   GFP_KERNEL);
2067                 if (!rx_q->dma_rx)
2068                         return -ENOMEM;
2069         }
2070
2071         if (stmmac_xdp_is_enabled(priv) &&
2072             test_bit(queue, priv->af_xdp_zc_qps))
2073                 napi_id = ch->rxtx_napi.napi_id;
2074         else
2075                 napi_id = ch->rx_napi.napi_id;
2076
2077         ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev,
2078                                rx_q->queue_index,
2079                                napi_id);
2080         if (ret) {
2081                 netdev_err(priv->dev, "Failed to register xdp rxq info\n");
2082                 return -EINVAL;
2083         }
2084
2085         return 0;
2086 }
2087
2088 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
2089                                        struct stmmac_dma_conf *dma_conf)
2090 {
2091         u32 rx_count = priv->plat->rx_queues_to_use;
2092         u32 queue;
2093         int ret;
2094
2095         /* RX queues buffers and DMA */
2096         for (queue = 0; queue < rx_count; queue++) {
2097                 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue);
2098                 if (ret)
2099                         goto err_dma;
2100         }
2101
2102         return 0;
2103
2104 err_dma:
2105         free_dma_rx_desc_resources(priv, dma_conf);
2106
2107         return ret;
2108 }
2109
2110 /**
2111  * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
2112  * @priv: private structure
2113  * @dma_conf: structure to take the dma data
2114  * @queue: TX queue index
2115  * Description: according to which descriptor can be used (extend or basic)
2116  * this function allocates the resources for TX and RX paths. In case of
2117  * reception, for example, it pre-allocated the RX socket buffer in order to
2118  * allow zero-copy mechanism.
2119  */
2120 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2121                                          struct stmmac_dma_conf *dma_conf,
2122                                          u32 queue)
2123 {
2124         struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue];
2125         size_t size;
2126         void *addr;
2127
2128         tx_q->queue_index = queue;
2129         tx_q->priv_data = priv;
2130
2131         tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size,
2132                                       sizeof(*tx_q->tx_skbuff_dma),
2133                                       GFP_KERNEL);
2134         if (!tx_q->tx_skbuff_dma)
2135                 return -ENOMEM;
2136
2137         tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size,
2138                                   sizeof(struct sk_buff *),
2139                                   GFP_KERNEL);
2140         if (!tx_q->tx_skbuff)
2141                 return -ENOMEM;
2142
2143         if (priv->extend_desc)
2144                 size = sizeof(struct dma_extended_desc);
2145         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2146                 size = sizeof(struct dma_edesc);
2147         else
2148                 size = sizeof(struct dma_desc);
2149
2150         size *= dma_conf->dma_tx_size;
2151
2152         addr = dma_alloc_coherent(priv->device, size,
2153                                   &tx_q->dma_tx_phy, GFP_KERNEL);
2154         if (!addr)
2155                 return -ENOMEM;
2156
2157         if (priv->extend_desc)
2158                 tx_q->dma_etx = addr;
2159         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2160                 tx_q->dma_entx = addr;
2161         else
2162                 tx_q->dma_tx = addr;
2163
2164         return 0;
2165 }
2166
2167 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
2168                                        struct stmmac_dma_conf *dma_conf)
2169 {
2170         u32 tx_count = priv->plat->tx_queues_to_use;
2171         u32 queue;
2172         int ret;
2173
2174         /* TX queues buffers and DMA */
2175         for (queue = 0; queue < tx_count; queue++) {
2176                 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue);
2177                 if (ret)
2178                         goto err_dma;
2179         }
2180
2181         return 0;
2182
2183 err_dma:
2184         free_dma_tx_desc_resources(priv, dma_conf);
2185         return ret;
2186 }
2187
2188 /**
2189  * alloc_dma_desc_resources - alloc TX/RX resources.
2190  * @priv: private structure
2191  * @dma_conf: structure to take the dma data
2192  * Description: according to which descriptor can be used (extend or basic)
2193  * this function allocates the resources for TX and RX paths. In case of
2194  * reception, for example, it pre-allocated the RX socket buffer in order to
2195  * allow zero-copy mechanism.
2196  */
2197 static int alloc_dma_desc_resources(struct stmmac_priv *priv,
2198                                     struct stmmac_dma_conf *dma_conf)
2199 {
2200         /* RX Allocation */
2201         int ret = alloc_dma_rx_desc_resources(priv, dma_conf);
2202
2203         if (ret)
2204                 return ret;
2205
2206         ret = alloc_dma_tx_desc_resources(priv, dma_conf);
2207
2208         return ret;
2209 }
2210
2211 /**
2212  * free_dma_desc_resources - free dma desc resources
2213  * @priv: private structure
2214  * @dma_conf: structure to take the dma data
2215  */
2216 static void free_dma_desc_resources(struct stmmac_priv *priv,
2217                                     struct stmmac_dma_conf *dma_conf)
2218 {
2219         /* Release the DMA TX socket buffers */
2220         free_dma_tx_desc_resources(priv, dma_conf);
2221
2222         /* Release the DMA RX socket buffers later
2223          * to ensure all pending XDP_TX buffers are returned.
2224          */
2225         free_dma_rx_desc_resources(priv, dma_conf);
2226 }
2227
2228 /**
2229  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
2230  *  @priv: driver private structure
2231  *  Description: It is used for enabling the rx queues in the MAC
2232  */
2233 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
2234 {
2235         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2236         int queue;
2237         u8 mode;
2238
2239         for (queue = 0; queue < rx_queues_count; queue++) {
2240                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
2241                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
2242         }
2243 }
2244
2245 /**
2246  * stmmac_start_rx_dma - start RX DMA channel
2247  * @priv: driver private structure
2248  * @chan: RX channel index
2249  * Description:
2250  * This starts a RX DMA channel
2251  */
2252 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
2253 {
2254         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
2255         stmmac_start_rx(priv, priv->ioaddr, chan);
2256 }
2257
2258 /**
2259  * stmmac_start_tx_dma - start TX DMA channel
2260  * @priv: driver private structure
2261  * @chan: TX channel index
2262  * Description:
2263  * This starts a TX DMA channel
2264  */
2265 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
2266 {
2267         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
2268         stmmac_start_tx(priv, priv->ioaddr, chan);
2269 }
2270
2271 /**
2272  * stmmac_stop_rx_dma - stop RX DMA channel
2273  * @priv: driver private structure
2274  * @chan: RX channel index
2275  * Description:
2276  * This stops a RX DMA channel
2277  */
2278 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
2279 {
2280         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
2281         stmmac_stop_rx(priv, priv->ioaddr, chan);
2282 }
2283
2284 /**
2285  * stmmac_stop_tx_dma - stop TX DMA channel
2286  * @priv: driver private structure
2287  * @chan: TX channel index
2288  * Description:
2289  * This stops a TX DMA channel
2290  */
2291 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
2292 {
2293         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
2294         stmmac_stop_tx(priv, priv->ioaddr, chan);
2295 }
2296
2297 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
2298 {
2299         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2300         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2301         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2302         u32 chan;
2303
2304         for (chan = 0; chan < dma_csr_ch; chan++) {
2305                 struct stmmac_channel *ch = &priv->channel[chan];
2306                 unsigned long flags;
2307
2308                 spin_lock_irqsave(&ch->lock, flags);
2309                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2310                 spin_unlock_irqrestore(&ch->lock, flags);
2311         }
2312 }
2313
2314 /**
2315  * stmmac_start_all_dma - start all RX and TX DMA channels
2316  * @priv: driver private structure
2317  * Description:
2318  * This starts all the RX and TX DMA channels
2319  */
2320 static void stmmac_start_all_dma(struct stmmac_priv *priv)
2321 {
2322         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2323         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2324         u32 chan = 0;
2325
2326         for (chan = 0; chan < rx_channels_count; chan++)
2327                 stmmac_start_rx_dma(priv, chan);
2328
2329         for (chan = 0; chan < tx_channels_count; chan++)
2330                 stmmac_start_tx_dma(priv, chan);
2331 }
2332
2333 /**
2334  * stmmac_stop_all_dma - stop all RX and TX DMA channels
2335  * @priv: driver private structure
2336  * Description:
2337  * This stops the RX and TX DMA channels
2338  */
2339 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
2340 {
2341         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2342         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2343         u32 chan = 0;
2344
2345         for (chan = 0; chan < rx_channels_count; chan++)
2346                 stmmac_stop_rx_dma(priv, chan);
2347
2348         for (chan = 0; chan < tx_channels_count; chan++)
2349                 stmmac_stop_tx_dma(priv, chan);
2350 }
2351
2352 /**
2353  *  stmmac_dma_operation_mode - HW DMA operation mode
2354  *  @priv: driver private structure
2355  *  Description: it is used for configuring the DMA operation mode register in
2356  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
2357  */
2358 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
2359 {
2360         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2361         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2362         int rxfifosz = priv->plat->rx_fifo_size;
2363         int txfifosz = priv->plat->tx_fifo_size;
2364         u32 txmode = 0;
2365         u32 rxmode = 0;
2366         u32 chan = 0;
2367         u8 qmode = 0;
2368
2369         if (rxfifosz == 0)
2370                 rxfifosz = priv->dma_cap.rx_fifo_size;
2371         if (txfifosz == 0)
2372                 txfifosz = priv->dma_cap.tx_fifo_size;
2373
2374         /* Adjust for real per queue fifo size */
2375         rxfifosz /= rx_channels_count;
2376         txfifosz /= tx_channels_count;
2377
2378         if (priv->plat->force_thresh_dma_mode) {
2379                 txmode = tc;
2380                 rxmode = tc;
2381         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
2382                 /*
2383                  * In case of GMAC, SF mode can be enabled
2384                  * to perform the TX COE in HW. This depends on:
2385                  * 1) TX COE if actually supported
2386                  * 2) There is no bugged Jumbo frame support
2387                  *    that needs to not insert csum in the TDES.
2388                  */
2389                 txmode = SF_DMA_MODE;
2390                 rxmode = SF_DMA_MODE;
2391                 priv->xstats.threshold = SF_DMA_MODE;
2392         } else {
2393                 txmode = tc;
2394                 rxmode = SF_DMA_MODE;
2395         }
2396
2397         /* configure all channels */
2398         for (chan = 0; chan < rx_channels_count; chan++) {
2399                 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2400                 u32 buf_size;
2401
2402                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2403
2404                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
2405                                 rxfifosz, qmode);
2406
2407                 if (rx_q->xsk_pool) {
2408                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
2409                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2410                                               buf_size,
2411                                               chan);
2412                 } else {
2413                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
2414                                               priv->dma_conf.dma_buf_sz,
2415                                               chan);
2416                 }
2417         }
2418
2419         for (chan = 0; chan < tx_channels_count; chan++) {
2420                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2421
2422                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
2423                                 txfifosz, qmode);
2424         }
2425 }
2426
2427 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
2428 {
2429         struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
2430         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2431         struct xsk_buff_pool *pool = tx_q->xsk_pool;
2432         unsigned int entry = tx_q->cur_tx;
2433         struct dma_desc *tx_desc = NULL;
2434         struct xdp_desc xdp_desc;
2435         bool work_done = true;
2436
2437         /* Avoids TX time-out as we are sharing with slow path */
2438         txq_trans_cond_update(nq);
2439
2440         budget = min(budget, stmmac_tx_avail(priv, queue));
2441
2442         while (budget-- > 0) {
2443                 dma_addr_t dma_addr;
2444                 bool set_ic;
2445
2446                 /* We are sharing with slow path and stop XSK TX desc submission when
2447                  * available TX ring is less than threshold.
2448                  */
2449                 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) ||
2450                     !netif_carrier_ok(priv->dev)) {
2451                         work_done = false;
2452                         break;
2453                 }
2454
2455                 if (!xsk_tx_peek_desc(pool, &xdp_desc))
2456                         break;
2457
2458                 if (likely(priv->extend_desc))
2459                         tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
2460                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2461                         tx_desc = &tx_q->dma_entx[entry].basic;
2462                 else
2463                         tx_desc = tx_q->dma_tx + entry;
2464
2465                 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr);
2466                 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len);
2467
2468                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX;
2469
2470                 /* To return XDP buffer to XSK pool, we simple call
2471                  * xsk_tx_completed(), so we don't need to fill up
2472                  * 'buf' and 'xdpf'.
2473                  */
2474                 tx_q->tx_skbuff_dma[entry].buf = 0;
2475                 tx_q->xdpf[entry] = NULL;
2476
2477                 tx_q->tx_skbuff_dma[entry].map_as_page = false;
2478                 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len;
2479                 tx_q->tx_skbuff_dma[entry].last_segment = true;
2480                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2481
2482                 stmmac_set_desc_addr(priv, tx_desc, dma_addr);
2483
2484                 tx_q->tx_count_frames++;
2485
2486                 if (!priv->tx_coal_frames[queue])
2487                         set_ic = false;
2488                 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
2489                         set_ic = true;
2490                 else
2491                         set_ic = false;
2492
2493                 if (set_ic) {
2494                         tx_q->tx_count_frames = 0;
2495                         stmmac_set_tx_ic(priv, tx_desc);
2496                         priv->xstats.tx_set_ic_bit++;
2497                 }
2498
2499                 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len,
2500                                        true, priv->mode, true, true,
2501                                        xdp_desc.len);
2502
2503                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
2504
2505                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
2506                 entry = tx_q->cur_tx;
2507         }
2508
2509         if (tx_desc) {
2510                 stmmac_flush_tx_descriptors(priv, queue);
2511                 xsk_tx_release(pool);
2512         }
2513
2514         /* Return true if all of the 3 conditions are met
2515          *  a) TX Budget is still available
2516          *  b) work_done = true when XSK TX desc peek is empty (no more
2517          *     pending XSK TX for transmission)
2518          */
2519         return !!budget && work_done;
2520 }
2521
2522 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan)
2523 {
2524         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) {
2525                 tc += 64;
2526
2527                 if (priv->plat->force_thresh_dma_mode)
2528                         stmmac_set_dma_operation_mode(priv, tc, tc, chan);
2529                 else
2530                         stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE,
2531                                                       chan);
2532
2533                 priv->xstats.threshold = tc;
2534         }
2535 }
2536
2537 /**
2538  * stmmac_tx_clean - to manage the transmission completion
2539  * @priv: driver private structure
2540  * @budget: napi budget limiting this functions packet handling
2541  * @queue: TX queue index
2542  * Description: it reclaims the transmit resources after transmission completes.
2543  */
2544 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
2545 {
2546         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2547         unsigned int bytes_compl = 0, pkts_compl = 0;
2548         unsigned int entry, xmits = 0, count = 0;
2549
2550         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
2551
2552         priv->xstats.tx_clean++;
2553
2554         tx_q->xsk_frames_done = 0;
2555
2556         entry = tx_q->dirty_tx;
2557
2558         /* Try to clean all TX complete frame in 1 shot */
2559         while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) {
2560                 struct xdp_frame *xdpf;
2561                 struct sk_buff *skb;
2562                 struct dma_desc *p;
2563                 int status;
2564
2565                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX ||
2566                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2567                         xdpf = tx_q->xdpf[entry];
2568                         skb = NULL;
2569                 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2570                         xdpf = NULL;
2571                         skb = tx_q->tx_skbuff[entry];
2572                 } else {
2573                         xdpf = NULL;
2574                         skb = NULL;
2575                 }
2576
2577                 if (priv->extend_desc)
2578                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
2579                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
2580                         p = &tx_q->dma_entx[entry].basic;
2581                 else
2582                         p = tx_q->dma_tx + entry;
2583
2584                 status = stmmac_tx_status(priv, &priv->dev->stats,
2585                                 &priv->xstats, p, priv->ioaddr);
2586                 /* Check if the descriptor is owned by the DMA */
2587                 if (unlikely(status & tx_dma_own))
2588                         break;
2589
2590                 count++;
2591
2592                 /* Make sure descriptor fields are read after reading
2593                  * the own bit.
2594                  */
2595                 dma_rmb();
2596
2597                 /* Just consider the last segment and ...*/
2598                 if (likely(!(status & tx_not_ls))) {
2599                         /* ... verify the status error condition */
2600                         if (unlikely(status & tx_err)) {
2601                                 priv->dev->stats.tx_errors++;
2602                                 if (unlikely(status & tx_err_bump_tc))
2603                                         stmmac_bump_dma_threshold(priv, queue);
2604                         } else {
2605                                 priv->dev->stats.tx_packets++;
2606                                 priv->xstats.tx_pkt_n++;
2607                                 priv->xstats.txq_stats[queue].tx_pkt_n++;
2608                         }
2609                         if (skb)
2610                                 stmmac_get_tx_hwtstamp(priv, p, skb);
2611                 }
2612
2613                 if (likely(tx_q->tx_skbuff_dma[entry].buf &&
2614                            tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) {
2615                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
2616                                 dma_unmap_page(priv->device,
2617                                                tx_q->tx_skbuff_dma[entry].buf,
2618                                                tx_q->tx_skbuff_dma[entry].len,
2619                                                DMA_TO_DEVICE);
2620                         else
2621                                 dma_unmap_single(priv->device,
2622                                                  tx_q->tx_skbuff_dma[entry].buf,
2623                                                  tx_q->tx_skbuff_dma[entry].len,
2624                                                  DMA_TO_DEVICE);
2625                         tx_q->tx_skbuff_dma[entry].buf = 0;
2626                         tx_q->tx_skbuff_dma[entry].len = 0;
2627                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
2628                 }
2629
2630                 stmmac_clean_desc3(priv, tx_q, p);
2631
2632                 tx_q->tx_skbuff_dma[entry].last_segment = false;
2633                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
2634
2635                 if (xdpf &&
2636                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) {
2637                         xdp_return_frame_rx_napi(xdpf);
2638                         tx_q->xdpf[entry] = NULL;
2639                 }
2640
2641                 if (xdpf &&
2642                     tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) {
2643                         xdp_return_frame(xdpf);
2644                         tx_q->xdpf[entry] = NULL;
2645                 }
2646
2647                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX)
2648                         tx_q->xsk_frames_done++;
2649
2650                 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) {
2651                         if (likely(skb)) {
2652                                 pkts_compl++;
2653                                 bytes_compl += skb->len;
2654                                 dev_consume_skb_any(skb);
2655                                 tx_q->tx_skbuff[entry] = NULL;
2656                         }
2657                 }
2658
2659                 stmmac_release_tx_desc(priv, p, priv->mode);
2660
2661                 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
2662         }
2663         tx_q->dirty_tx = entry;
2664
2665         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
2666                                   pkts_compl, bytes_compl);
2667
2668         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
2669                                                                 queue))) &&
2670             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) {
2671
2672                 netif_dbg(priv, tx_done, priv->dev,
2673                           "%s: restart transmit\n", __func__);
2674                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
2675         }
2676
2677         if (tx_q->xsk_pool) {
2678                 bool work_done;
2679
2680                 if (tx_q->xsk_frames_done)
2681                         xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
2682
2683                 if (xsk_uses_need_wakeup(tx_q->xsk_pool))
2684                         xsk_set_tx_need_wakeup(tx_q->xsk_pool);
2685
2686                 /* For XSK TX, we try to send as many as possible.
2687                  * If XSK work done (XSK TX desc empty and budget still
2688                  * available), return "budget - 1" to reenable TX IRQ.
2689                  * Else, return "budget" to make NAPI continue polling.
2690                  */
2691                 work_done = stmmac_xdp_xmit_zc(priv, queue,
2692                                                STMMAC_XSK_TX_BUDGET_MAX);
2693                 if (work_done)
2694                         xmits = budget - 1;
2695                 else
2696                         xmits = budget;
2697         }
2698
2699         if (priv->eee_enabled && !priv->tx_path_in_lpi_mode &&
2700             priv->eee_sw_timer_en) {
2701                 if (stmmac_enable_eee_mode(priv))
2702                         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer));
2703         }
2704
2705         /* We still have pending packets, let's call for a new scheduling */
2706         if (tx_q->dirty_tx != tx_q->cur_tx)
2707                 hrtimer_start(&tx_q->txtimer,
2708                               STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2709                               HRTIMER_MODE_REL);
2710
2711         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
2712
2713         /* Combine decisions from TX clean and XSK TX */
2714         return max(count, xmits);
2715 }
2716
2717 /**
2718  * stmmac_tx_err - to manage the tx error
2719  * @priv: driver private structure
2720  * @chan: channel index
2721  * Description: it cleans the descriptors and restarts the transmission
2722  * in case of transmission errors.
2723  */
2724 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
2725 {
2726         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2727
2728         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2729
2730         stmmac_stop_tx_dma(priv, chan);
2731         dma_free_tx_skbufs(priv, &priv->dma_conf, chan);
2732         stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan);
2733         stmmac_reset_tx_queue(priv, chan);
2734         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2735                             tx_q->dma_tx_phy, chan);
2736         stmmac_start_tx_dma(priv, chan);
2737
2738         priv->dev->stats.tx_errors++;
2739         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2740 }
2741
2742 /**
2743  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2744  *  @priv: driver private structure
2745  *  @txmode: TX operating mode
2746  *  @rxmode: RX operating mode
2747  *  @chan: channel index
2748  *  Description: it is used for configuring of the DMA operation mode in
2749  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2750  *  mode.
2751  */
2752 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2753                                           u32 rxmode, u32 chan)
2754 {
2755         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2756         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2757         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2758         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2759         int rxfifosz = priv->plat->rx_fifo_size;
2760         int txfifosz = priv->plat->tx_fifo_size;
2761
2762         if (rxfifosz == 0)
2763                 rxfifosz = priv->dma_cap.rx_fifo_size;
2764         if (txfifosz == 0)
2765                 txfifosz = priv->dma_cap.tx_fifo_size;
2766
2767         /* Adjust for real per queue fifo size */
2768         rxfifosz /= rx_channels_count;
2769         txfifosz /= tx_channels_count;
2770
2771         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2772         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2773 }
2774
2775 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2776 {
2777         int ret;
2778
2779         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2780                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2781         if (ret && (ret != -EINVAL)) {
2782                 stmmac_global_err(priv);
2783                 return true;
2784         }
2785
2786         return false;
2787 }
2788
2789 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
2790 {
2791         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2792                                                  &priv->xstats, chan, dir);
2793         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan];
2794         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
2795         struct stmmac_channel *ch = &priv->channel[chan];
2796         struct napi_struct *rx_napi;
2797         struct napi_struct *tx_napi;
2798         unsigned long flags;
2799
2800         rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi;
2801         tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
2802
2803         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2804                 if (napi_schedule_prep(rx_napi)) {
2805                         spin_lock_irqsave(&ch->lock, flags);
2806                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
2807                         spin_unlock_irqrestore(&ch->lock, flags);
2808                         __napi_schedule(rx_napi);
2809                 }
2810         }
2811
2812         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) {
2813                 if (napi_schedule_prep(tx_napi)) {
2814                         spin_lock_irqsave(&ch->lock, flags);
2815                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
2816                         spin_unlock_irqrestore(&ch->lock, flags);
2817                         __napi_schedule(tx_napi);
2818                 }
2819         }
2820
2821         return status;
2822 }
2823
2824 /**
2825  * stmmac_dma_interrupt - DMA ISR
2826  * @priv: driver private structure
2827  * Description: this is the DMA ISR. It is called by the main ISR.
2828  * It calls the dwmac dma routine and schedule poll method in case of some
2829  * work can be done.
2830  */
2831 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2832 {
2833         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2834         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2835         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2836                                 tx_channel_count : rx_channel_count;
2837         u32 chan;
2838         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2839
2840         /* Make sure we never check beyond our status buffer. */
2841         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2842                 channels_to_check = ARRAY_SIZE(status);
2843
2844         for (chan = 0; chan < channels_to_check; chan++)
2845                 status[chan] = stmmac_napi_check(priv, chan,
2846                                                  DMA_DIR_RXTX);
2847
2848         for (chan = 0; chan < tx_channel_count; chan++) {
2849                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2850                         /* Try to bump up the dma threshold on this failure */
2851                         stmmac_bump_dma_threshold(priv, chan);
2852                 } else if (unlikely(status[chan] == tx_hard_error)) {
2853                         stmmac_tx_err(priv, chan);
2854                 }
2855         }
2856 }
2857
2858 /**
2859  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2860  * @priv: driver private structure
2861  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2862  */
2863 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2864 {
2865         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2866                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2867
2868         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2869
2870         if (priv->dma_cap.rmon) {
2871                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2872                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2873         } else
2874                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2875 }
2876
2877 /**
2878  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2879  * @priv: driver private structure
2880  * Description:
2881  *  new GMAC chip generations have a new register to indicate the
2882  *  presence of the optional feature/functions.
2883  *  This can be also used to override the value passed through the
2884  *  platform and necessary for old MAC10/100 and GMAC chips.
2885  */
2886 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2887 {
2888         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2889 }
2890
2891 /**
2892  * stmmac_check_ether_addr - check if the MAC addr is valid
2893  * @priv: driver private structure
2894  * Description:
2895  * it is to verify if the MAC address is valid, in case of failures it
2896  * generates a random MAC address
2897  */
2898 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2899 {
2900         u8 addr[ETH_ALEN];
2901
2902         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2903                 stmmac_get_umac_addr(priv, priv->hw, addr, 0);
2904                 if (is_valid_ether_addr(addr))
2905                         eth_hw_addr_set(priv->dev, addr);
2906                 else
2907                         eth_hw_addr_random(priv->dev);
2908                 dev_info(priv->device, "device MAC address %pM\n",
2909                          priv->dev->dev_addr);
2910         }
2911 }
2912
2913 /**
2914  * stmmac_init_dma_engine - DMA init.
2915  * @priv: driver private structure
2916  * Description:
2917  * It inits the DMA invoking the specific MAC/GMAC callback.
2918  * Some DMA parameters can be passed from the platform;
2919  * in case of these are not passed a default is kept for the MAC or GMAC.
2920  */
2921 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2922 {
2923         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2924         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2925         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2926         struct stmmac_rx_queue *rx_q;
2927         struct stmmac_tx_queue *tx_q;
2928         u32 chan = 0;
2929         int atds = 0;
2930         int ret = 0;
2931
2932         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2933                 dev_err(priv->device, "Invalid DMA configuration\n");
2934                 return -EINVAL;
2935         }
2936
2937         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2938                 atds = 1;
2939
2940         ret = stmmac_reset(priv, priv->ioaddr);
2941         if (ret) {
2942                 dev_err(priv->device, "Failed to reset the dma\n");
2943                 return ret;
2944         }
2945
2946         /* DMA Configuration */
2947         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2948
2949         if (priv->plat->axi)
2950                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2951
2952         /* DMA CSR Channel configuration */
2953         for (chan = 0; chan < dma_csr_ch; chan++) {
2954                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2955                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
2956         }
2957
2958         /* DMA RX Channel Configuration */
2959         for (chan = 0; chan < rx_channels_count; chan++) {
2960                 rx_q = &priv->dma_conf.rx_queue[chan];
2961
2962                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2963                                     rx_q->dma_rx_phy, chan);
2964
2965                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2966                                      (rx_q->buf_alloc_num *
2967                                       sizeof(struct dma_desc));
2968                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2969                                        rx_q->rx_tail_addr, chan);
2970         }
2971
2972         /* DMA TX Channel Configuration */
2973         for (chan = 0; chan < tx_channels_count; chan++) {
2974                 tx_q = &priv->dma_conf.tx_queue[chan];
2975
2976                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2977                                     tx_q->dma_tx_phy, chan);
2978
2979                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2980                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2981                                        tx_q->tx_tail_addr, chan);
2982         }
2983
2984         return ret;
2985 }
2986
2987 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2988 {
2989         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
2990
2991         hrtimer_start(&tx_q->txtimer,
2992                       STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
2993                       HRTIMER_MODE_REL);
2994 }
2995
2996 /**
2997  * stmmac_tx_timer - mitigation sw timer for tx.
2998  * @t: data pointer
2999  * Description:
3000  * This is the timer handler to directly invoke the stmmac_tx_clean.
3001  */
3002 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
3003 {
3004         struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer);
3005         struct stmmac_priv *priv = tx_q->priv_data;
3006         struct stmmac_channel *ch;
3007         struct napi_struct *napi;
3008
3009         ch = &priv->channel[tx_q->queue_index];
3010         napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
3011
3012         if (likely(napi_schedule_prep(napi))) {
3013                 unsigned long flags;
3014
3015                 spin_lock_irqsave(&ch->lock, flags);
3016                 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1);
3017                 spin_unlock_irqrestore(&ch->lock, flags);
3018                 __napi_schedule(napi);
3019         }
3020
3021         return HRTIMER_NORESTART;
3022 }
3023
3024 /**
3025  * stmmac_init_coalesce - init mitigation options.
3026  * @priv: driver private structure
3027  * Description:
3028  * This inits the coalesce parameters: i.e. timer rate,
3029  * timer handler and default threshold used for enabling the
3030  * interrupt on completion bit.
3031  */
3032 static void stmmac_init_coalesce(struct stmmac_priv *priv)
3033 {
3034         u32 tx_channel_count = priv->plat->tx_queues_to_use;
3035         u32 rx_channel_count = priv->plat->rx_queues_to_use;
3036         u32 chan;
3037
3038         for (chan = 0; chan < tx_channel_count; chan++) {
3039                 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3040
3041                 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
3042                 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
3043
3044                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
3045                 tx_q->txtimer.function = stmmac_tx_timer;
3046         }
3047
3048         for (chan = 0; chan < rx_channel_count; chan++)
3049                 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES;
3050 }
3051
3052 static void stmmac_set_rings_length(struct stmmac_priv *priv)
3053 {
3054         u32 rx_channels_count = priv->plat->rx_queues_to_use;
3055         u32 tx_channels_count = priv->plat->tx_queues_to_use;
3056         u32 chan;
3057
3058         /* set TX ring length */
3059         for (chan = 0; chan < tx_channels_count; chan++)
3060                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
3061                                        (priv->dma_conf.dma_tx_size - 1), chan);
3062
3063         /* set RX ring length */
3064         for (chan = 0; chan < rx_channels_count; chan++)
3065                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
3066                                        (priv->dma_conf.dma_rx_size - 1), chan);
3067 }
3068
3069 /**
3070  *  stmmac_set_tx_queue_weight - Set TX queue weight
3071  *  @priv: driver private structure
3072  *  Description: It is used for setting TX queues weight
3073  */
3074 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
3075 {
3076         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3077         u32 weight;
3078         u32 queue;
3079
3080         for (queue = 0; queue < tx_queues_count; queue++) {
3081                 weight = priv->plat->tx_queues_cfg[queue].weight;
3082                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
3083         }
3084 }
3085
3086 /**
3087  *  stmmac_configure_cbs - Configure CBS in TX queue
3088  *  @priv: driver private structure
3089  *  Description: It is used for configuring CBS in AVB TX queues
3090  */
3091 static void stmmac_configure_cbs(struct stmmac_priv *priv)
3092 {
3093         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3094         u32 mode_to_use;
3095         u32 queue;
3096
3097         /* queue 0 is reserved for legacy traffic */
3098         for (queue = 1; queue < tx_queues_count; queue++) {
3099                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
3100                 if (mode_to_use == MTL_QUEUE_DCB)
3101                         continue;
3102
3103                 stmmac_config_cbs(priv, priv->hw,
3104                                 priv->plat->tx_queues_cfg[queue].send_slope,
3105                                 priv->plat->tx_queues_cfg[queue].idle_slope,
3106                                 priv->plat->tx_queues_cfg[queue].high_credit,
3107                                 priv->plat->tx_queues_cfg[queue].low_credit,
3108                                 queue);
3109         }
3110 }
3111
3112 /**
3113  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
3114  *  @priv: driver private structure
3115  *  Description: It is used for mapping RX queues to RX dma channels
3116  */
3117 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
3118 {
3119         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3120         u32 queue;
3121         u32 chan;
3122
3123         for (queue = 0; queue < rx_queues_count; queue++) {
3124                 chan = priv->plat->rx_queues_cfg[queue].chan;
3125                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
3126         }
3127 }
3128
3129 /**
3130  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
3131  *  @priv: driver private structure
3132  *  Description: It is used for configuring the RX Queue Priority
3133  */
3134 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
3135 {
3136         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3137         u32 queue;
3138         u32 prio;
3139
3140         for (queue = 0; queue < rx_queues_count; queue++) {
3141                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
3142                         continue;
3143
3144                 prio = priv->plat->rx_queues_cfg[queue].prio;
3145                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
3146         }
3147 }
3148
3149 /**
3150  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
3151  *  @priv: driver private structure
3152  *  Description: It is used for configuring the TX Queue Priority
3153  */
3154 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
3155 {
3156         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3157         u32 queue;
3158         u32 prio;
3159
3160         for (queue = 0; queue < tx_queues_count; queue++) {
3161                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
3162                         continue;
3163
3164                 prio = priv->plat->tx_queues_cfg[queue].prio;
3165                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
3166         }
3167 }
3168
3169 /**
3170  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
3171  *  @priv: driver private structure
3172  *  Description: It is used for configuring the RX queue routing
3173  */
3174 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
3175 {
3176         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3177         u32 queue;
3178         u8 packet;
3179
3180         for (queue = 0; queue < rx_queues_count; queue++) {
3181                 /* no specific packet type routing specified for the queue */
3182                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
3183                         continue;
3184
3185                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
3186                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
3187         }
3188 }
3189
3190 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
3191 {
3192         if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
3193                 priv->rss.enable = false;
3194                 return;
3195         }
3196
3197         if (priv->dev->features & NETIF_F_RXHASH)
3198                 priv->rss.enable = true;
3199         else
3200                 priv->rss.enable = false;
3201
3202         stmmac_rss_configure(priv, priv->hw, &priv->rss,
3203                              priv->plat->rx_queues_to_use);
3204 }
3205
3206 /**
3207  *  stmmac_mtl_configuration - Configure MTL
3208  *  @priv: driver private structure
3209  *  Description: It is used for configurring MTL
3210  */
3211 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
3212 {
3213         u32 rx_queues_count = priv->plat->rx_queues_to_use;
3214         u32 tx_queues_count = priv->plat->tx_queues_to_use;
3215
3216         if (tx_queues_count > 1)
3217                 stmmac_set_tx_queue_weight(priv);
3218
3219         /* Configure MTL RX algorithms */
3220         if (rx_queues_count > 1)
3221                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
3222                                 priv->plat->rx_sched_algorithm);
3223
3224         /* Configure MTL TX algorithms */
3225         if (tx_queues_count > 1)
3226                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
3227                                 priv->plat->tx_sched_algorithm);
3228
3229         /* Configure CBS in AVB TX queues */
3230         if (tx_queues_count > 1)
3231                 stmmac_configure_cbs(priv);
3232
3233         /* Map RX MTL to DMA channels */
3234         stmmac_rx_queue_dma_chan_map(priv);
3235
3236         /* Enable MAC RX Queues */
3237         stmmac_mac_enable_rx_queues(priv);
3238
3239         /* Set RX priorities */
3240         if (rx_queues_count > 1)
3241                 stmmac_mac_config_rx_queues_prio(priv);
3242
3243         /* Set TX priorities */
3244         if (tx_queues_count > 1)
3245                 stmmac_mac_config_tx_queues_prio(priv);
3246
3247         /* Set RX routing */
3248         if (rx_queues_count > 1)
3249                 stmmac_mac_config_rx_queues_routing(priv);
3250
3251         /* Receive Side Scaling */
3252         if (rx_queues_count > 1)
3253                 stmmac_mac_config_rss(priv);
3254 }
3255
3256 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
3257 {
3258         if (priv->dma_cap.asp) {
3259                 netdev_info(priv->dev, "Enabling Safety Features\n");
3260                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp,
3261                                           priv->plat->safety_feat_cfg);
3262         } else {
3263                 netdev_info(priv->dev, "No Safety Features support found\n");
3264         }
3265 }
3266
3267 static int stmmac_fpe_start_wq(struct stmmac_priv *priv)
3268 {
3269         char *name;
3270
3271         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
3272         clear_bit(__FPE_REMOVING,  &priv->fpe_task_state);
3273
3274         name = priv->wq_name;
3275         sprintf(name, "%s-fpe", priv->dev->name);
3276
3277         priv->fpe_wq = create_singlethread_workqueue(name);
3278         if (!priv->fpe_wq) {
3279                 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name);
3280
3281                 return -ENOMEM;
3282         }
3283         netdev_info(priv->dev, "FPE workqueue start");
3284
3285         return 0;
3286 }
3287
3288 /**
3289  * stmmac_hw_setup - setup mac in a usable state.
3290  *  @dev : pointer to the device structure.
3291  *  @ptp_register: register PTP if set
3292  *  Description:
3293  *  this is the main function to setup the HW in a usable state because the
3294  *  dma engine is reset, the core registers are configured (e.g. AXI,
3295  *  Checksum features, timers). The DMA is ready to start receiving and
3296  *  transmitting.
3297  *  Return value:
3298  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3299  *  file on failure.
3300  */
3301 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register)
3302 {
3303         struct stmmac_priv *priv = netdev_priv(dev);
3304         u32 rx_cnt = priv->plat->rx_queues_to_use;
3305         u32 tx_cnt = priv->plat->tx_queues_to_use;
3306         bool sph_en;
3307         u32 chan;
3308         int ret;
3309
3310         /* DMA initialization and SW reset */
3311         ret = stmmac_init_dma_engine(priv);
3312         if (ret < 0) {
3313                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
3314                            __func__);
3315                 return ret;
3316         }
3317
3318         /* Copy the MAC addr into the HW  */
3319         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
3320
3321         /* PS and related bits will be programmed according to the speed */
3322         if (priv->hw->pcs) {
3323                 int speed = priv->plat->mac_port_sel_speed;
3324
3325                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
3326                     (speed == SPEED_1000)) {
3327                         priv->hw->ps = speed;
3328                 } else {
3329                         dev_warn(priv->device, "invalid port speed\n");
3330                         priv->hw->ps = 0;
3331                 }
3332         }
3333
3334         /* Initialize the MAC Core */
3335         stmmac_core_init(priv, priv->hw, dev);
3336
3337         /* Initialize MTL*/
3338         stmmac_mtl_configuration(priv);
3339
3340         /* Initialize Safety Features */
3341         stmmac_safety_feat_configuration(priv);
3342
3343         ret = stmmac_rx_ipc(priv, priv->hw);
3344         if (!ret) {
3345                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
3346                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
3347                 priv->hw->rx_csum = 0;
3348         }
3349
3350         /* Enable the MAC Rx/Tx */
3351         stmmac_mac_set(priv, priv->ioaddr, true);
3352
3353         /* Set the HW DMA mode and the COE */
3354         stmmac_dma_operation_mode(priv);
3355
3356         stmmac_mmc_setup(priv);
3357
3358         if (ptp_register) {
3359                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
3360                 if (ret < 0)
3361                         netdev_warn(priv->dev,
3362                                     "failed to enable PTP reference clock: %pe\n",
3363                                     ERR_PTR(ret));
3364         }
3365
3366         ret = stmmac_init_ptp(priv);
3367         if (ret == -EOPNOTSUPP)
3368                 netdev_info(priv->dev, "PTP not supported by HW\n");
3369         else if (ret)
3370                 netdev_warn(priv->dev, "PTP init failed\n");
3371         else if (ptp_register)
3372                 stmmac_ptp_register(priv);
3373
3374         priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS;
3375
3376         /* Convert the timer from msec to usec */
3377         if (!priv->tx_lpi_timer)
3378                 priv->tx_lpi_timer = eee_timer * 1000;
3379
3380         if (priv->use_riwt) {
3381                 u32 queue;
3382
3383                 for (queue = 0; queue < rx_cnt; queue++) {
3384                         if (!priv->rx_riwt[queue])
3385                                 priv->rx_riwt[queue] = DEF_DMA_RIWT;
3386
3387                         stmmac_rx_watchdog(priv, priv->ioaddr,
3388                                            priv->rx_riwt[queue], queue);
3389                 }
3390         }
3391
3392         if (priv->hw->pcs)
3393                 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
3394
3395         /* set TX and RX rings length */
3396         stmmac_set_rings_length(priv);
3397
3398         /* Enable TSO */
3399         if (priv->tso) {
3400                 for (chan = 0; chan < tx_cnt; chan++) {
3401                         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3402
3403                         /* TSO and TBS cannot co-exist */
3404                         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3405                                 continue;
3406
3407                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
3408                 }
3409         }
3410
3411         /* Enable Split Header */
3412         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3413         for (chan = 0; chan < rx_cnt; chan++)
3414                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3415
3416
3417         /* VLAN Tag Insertion */
3418         if (priv->dma_cap.vlins)
3419                 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
3420
3421         /* TBS */
3422         for (chan = 0; chan < tx_cnt; chan++) {
3423                 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
3424                 int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
3425
3426                 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
3427         }
3428
3429         /* Configure real RX and TX queues */
3430         netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
3431         netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
3432
3433         /* Start the ball rolling... */
3434         stmmac_start_all_dma(priv);
3435
3436         if (priv->dma_cap.fpesel) {
3437                 stmmac_fpe_start_wq(priv);
3438
3439                 if (priv->plat->fpe_cfg->enable)
3440                         stmmac_fpe_handshake(priv, true);
3441         }
3442
3443         return 0;
3444 }
3445
3446 static void stmmac_hw_teardown(struct net_device *dev)
3447 {
3448         struct stmmac_priv *priv = netdev_priv(dev);
3449
3450         clk_disable_unprepare(priv->plat->clk_ptp_ref);
3451 }
3452
3453 static void stmmac_free_irq(struct net_device *dev,
3454                             enum request_irq_err irq_err, int irq_idx)
3455 {
3456         struct stmmac_priv *priv = netdev_priv(dev);
3457         int j;
3458
3459         switch (irq_err) {
3460         case REQ_IRQ_ERR_ALL:
3461                 irq_idx = priv->plat->tx_queues_to_use;
3462                 fallthrough;
3463         case REQ_IRQ_ERR_TX:
3464                 for (j = irq_idx - 1; j >= 0; j--) {
3465                         if (priv->tx_irq[j] > 0) {
3466                                 irq_set_affinity_hint(priv->tx_irq[j], NULL);
3467                                 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]);
3468                         }
3469                 }
3470                 irq_idx = priv->plat->rx_queues_to_use;
3471                 fallthrough;
3472         case REQ_IRQ_ERR_RX:
3473                 for (j = irq_idx - 1; j >= 0; j--) {
3474                         if (priv->rx_irq[j] > 0) {
3475                                 irq_set_affinity_hint(priv->rx_irq[j], NULL);
3476                                 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]);
3477                         }
3478                 }
3479
3480                 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq)
3481                         free_irq(priv->sfty_ue_irq, dev);
3482                 fallthrough;
3483         case REQ_IRQ_ERR_SFTY_UE:
3484                 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq)
3485                         free_irq(priv->sfty_ce_irq, dev);
3486                 fallthrough;
3487         case REQ_IRQ_ERR_SFTY_CE:
3488                 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq)
3489                         free_irq(priv->lpi_irq, dev);
3490                 fallthrough;
3491         case REQ_IRQ_ERR_LPI:
3492                 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq)
3493                         free_irq(priv->wol_irq, dev);
3494                 fallthrough;
3495         case REQ_IRQ_ERR_WOL:
3496                 free_irq(dev->irq, dev);
3497                 fallthrough;
3498         case REQ_IRQ_ERR_MAC:
3499         case REQ_IRQ_ERR_NO:
3500                 /* If MAC IRQ request error, no more IRQ to free */
3501                 break;
3502         }
3503 }
3504
3505 static int stmmac_request_irq_multi_msi(struct net_device *dev)
3506 {
3507         struct stmmac_priv *priv = netdev_priv(dev);
3508         enum request_irq_err irq_err;
3509         cpumask_t cpu_mask;
3510         int irq_idx = 0;
3511         char *int_name;
3512         int ret;
3513         int i;
3514
3515         /* For common interrupt */
3516         int_name = priv->int_name_mac;
3517         sprintf(int_name, "%s:%s", dev->name, "mac");
3518         ret = request_irq(dev->irq, stmmac_mac_interrupt,
3519                           0, int_name, dev);
3520         if (unlikely(ret < 0)) {
3521                 netdev_err(priv->dev,
3522                            "%s: alloc mac MSI %d (error: %d)\n",
3523                            __func__, dev->irq, ret);
3524                 irq_err = REQ_IRQ_ERR_MAC;
3525                 goto irq_error;
3526         }
3527
3528         /* Request the Wake IRQ in case of another line
3529          * is used for WoL
3530          */
3531         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3532                 int_name = priv->int_name_wol;
3533                 sprintf(int_name, "%s:%s", dev->name, "wol");
3534                 ret = request_irq(priv->wol_irq,
3535                                   stmmac_mac_interrupt,
3536                                   0, int_name, dev);
3537                 if (unlikely(ret < 0)) {
3538                         netdev_err(priv->dev,
3539                                    "%s: alloc wol MSI %d (error: %d)\n",
3540                                    __func__, priv->wol_irq, ret);
3541                         irq_err = REQ_IRQ_ERR_WOL;
3542                         goto irq_error;
3543                 }
3544         }
3545
3546         /* Request the LPI IRQ in case of another line
3547          * is used for LPI
3548          */
3549         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3550                 int_name = priv->int_name_lpi;
3551                 sprintf(int_name, "%s:%s", dev->name, "lpi");
3552                 ret = request_irq(priv->lpi_irq,
3553                                   stmmac_mac_interrupt,
3554                                   0, int_name, dev);
3555                 if (unlikely(ret < 0)) {
3556                         netdev_err(priv->dev,
3557                                    "%s: alloc lpi MSI %d (error: %d)\n",
3558                                    __func__, priv->lpi_irq, ret);
3559                         irq_err = REQ_IRQ_ERR_LPI;
3560                         goto irq_error;
3561                 }
3562         }
3563
3564         /* Request the Safety Feature Correctible Error line in
3565          * case of another line is used
3566          */
3567         if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) {
3568                 int_name = priv->int_name_sfty_ce;
3569                 sprintf(int_name, "%s:%s", dev->name, "safety-ce");
3570                 ret = request_irq(priv->sfty_ce_irq,
3571                                   stmmac_safety_interrupt,
3572                                   0, int_name, dev);
3573                 if (unlikely(ret < 0)) {
3574                         netdev_err(priv->dev,
3575                                    "%s: alloc sfty ce MSI %d (error: %d)\n",
3576                                    __func__, priv->sfty_ce_irq, ret);
3577                         irq_err = REQ_IRQ_ERR_SFTY_CE;
3578                         goto irq_error;
3579                 }
3580         }
3581
3582         /* Request the Safety Feature Uncorrectible Error line in
3583          * case of another line is used
3584          */
3585         if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) {
3586                 int_name = priv->int_name_sfty_ue;
3587                 sprintf(int_name, "%s:%s", dev->name, "safety-ue");
3588                 ret = request_irq(priv->sfty_ue_irq,
3589                                   stmmac_safety_interrupt,
3590                                   0, int_name, dev);
3591                 if (unlikely(ret < 0)) {
3592                         netdev_err(priv->dev,
3593                                    "%s: alloc sfty ue MSI %d (error: %d)\n",
3594                                    __func__, priv->sfty_ue_irq, ret);
3595                         irq_err = REQ_IRQ_ERR_SFTY_UE;
3596                         goto irq_error;
3597                 }
3598         }
3599
3600         /* Request Rx MSI irq */
3601         for (i = 0; i < priv->plat->rx_queues_to_use; i++) {
3602                 if (i >= MTL_MAX_RX_QUEUES)
3603                         break;
3604                 if (priv->rx_irq[i] == 0)
3605                         continue;
3606
3607                 int_name = priv->int_name_rx_irq[i];
3608                 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
3609                 ret = request_irq(priv->rx_irq[i],
3610                                   stmmac_msi_intr_rx,
3611                                   0, int_name, &priv->dma_conf.rx_queue[i]);
3612                 if (unlikely(ret < 0)) {
3613                         netdev_err(priv->dev,
3614                                    "%s: alloc rx-%d  MSI %d (error: %d)\n",
3615                                    __func__, i, priv->rx_irq[i], ret);
3616                         irq_err = REQ_IRQ_ERR_RX;
3617                         irq_idx = i;
3618                         goto irq_error;
3619                 }
3620                 cpumask_clear(&cpu_mask);
3621                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3622                 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask);
3623         }
3624
3625         /* Request Tx MSI irq */
3626         for (i = 0; i < priv->plat->tx_queues_to_use; i++) {
3627                 if (i >= MTL_MAX_TX_QUEUES)
3628                         break;
3629                 if (priv->tx_irq[i] == 0)
3630                         continue;
3631
3632                 int_name = priv->int_name_tx_irq[i];
3633                 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
3634                 ret = request_irq(priv->tx_irq[i],
3635                                   stmmac_msi_intr_tx,
3636                                   0, int_name, &priv->dma_conf.tx_queue[i]);
3637                 if (unlikely(ret < 0)) {
3638                         netdev_err(priv->dev,
3639                                    "%s: alloc tx-%d  MSI %d (error: %d)\n",
3640                                    __func__, i, priv->tx_irq[i], ret);
3641                         irq_err = REQ_IRQ_ERR_TX;
3642                         irq_idx = i;
3643                         goto irq_error;
3644                 }
3645                 cpumask_clear(&cpu_mask);
3646                 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask);
3647                 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask);
3648         }
3649
3650         return 0;
3651
3652 irq_error:
3653         stmmac_free_irq(dev, irq_err, irq_idx);
3654         return ret;
3655 }
3656
3657 static int stmmac_request_irq_single(struct net_device *dev)
3658 {
3659         struct stmmac_priv *priv = netdev_priv(dev);
3660         enum request_irq_err irq_err;
3661         int ret;
3662
3663         ret = request_irq(dev->irq, stmmac_interrupt,
3664                           IRQF_SHARED, dev->name, dev);
3665         if (unlikely(ret < 0)) {
3666                 netdev_err(priv->dev,
3667                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
3668                            __func__, dev->irq, ret);
3669                 irq_err = REQ_IRQ_ERR_MAC;
3670                 goto irq_error;
3671         }
3672
3673         /* Request the Wake IRQ in case of another line
3674          * is used for WoL
3675          */
3676         if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) {
3677                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
3678                                   IRQF_SHARED, dev->name, dev);
3679                 if (unlikely(ret < 0)) {
3680                         netdev_err(priv->dev,
3681                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
3682                                    __func__, priv->wol_irq, ret);
3683                         irq_err = REQ_IRQ_ERR_WOL;
3684                         goto irq_error;
3685                 }
3686         }
3687
3688         /* Request the IRQ lines */
3689         if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) {
3690                 ret = request_irq(priv->lpi_irq, stmmac_interrupt,
3691                                   IRQF_SHARED, dev->name, dev);
3692                 if (unlikely(ret < 0)) {
3693                         netdev_err(priv->dev,
3694                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
3695                                    __func__, priv->lpi_irq, ret);
3696                         irq_err = REQ_IRQ_ERR_LPI;
3697                         goto irq_error;
3698                 }
3699         }
3700
3701         return 0;
3702
3703 irq_error:
3704         stmmac_free_irq(dev, irq_err, 0);
3705         return ret;
3706 }
3707
3708 static int stmmac_request_irq(struct net_device *dev)
3709 {
3710         struct stmmac_priv *priv = netdev_priv(dev);
3711         int ret;
3712
3713         /* Request the IRQ lines */
3714         if (priv->plat->multi_msi_en)
3715                 ret = stmmac_request_irq_multi_msi(dev);
3716         else
3717                 ret = stmmac_request_irq_single(dev);
3718
3719         return ret;
3720 }
3721
3722 /**
3723  *  stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue
3724  *  @priv: driver private structure
3725  *  @mtu: MTU to setup the dma queue and buf with
3726  *  Description: Allocate and generate a dma_conf based on the provided MTU.
3727  *  Allocate the Tx/Rx DMA queue and init them.
3728  *  Return value:
3729  *  the dma_conf allocated struct on success and an appropriate ERR_PTR on failure.
3730  */
3731 static struct stmmac_dma_conf *
3732 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu)
3733 {
3734         struct stmmac_dma_conf *dma_conf;
3735         int chan, bfsize, ret;
3736
3737         dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL);
3738         if (!dma_conf) {
3739                 netdev_err(priv->dev, "%s: DMA conf allocation failed\n",
3740                            __func__);
3741                 return ERR_PTR(-ENOMEM);
3742         }
3743
3744         bfsize = stmmac_set_16kib_bfsize(priv, mtu);
3745         if (bfsize < 0)
3746                 bfsize = 0;
3747
3748         if (bfsize < BUF_SIZE_16KiB)
3749                 bfsize = stmmac_set_bfsize(mtu, 0);
3750
3751         dma_conf->dma_buf_sz = bfsize;
3752         /* Chose the tx/rx size from the already defined one in the
3753          * priv struct. (if defined)
3754          */
3755         dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size;
3756         dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size;
3757
3758         if (!dma_conf->dma_tx_size)
3759                 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE;
3760         if (!dma_conf->dma_rx_size)
3761                 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE;
3762
3763         /* Earlier check for TBS */
3764         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
3765                 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan];
3766                 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
3767
3768                 /* Setup per-TXQ tbs flag before TX descriptor alloc */
3769                 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
3770         }
3771
3772         ret = alloc_dma_desc_resources(priv, dma_conf);
3773         if (ret < 0) {
3774                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
3775                            __func__);
3776                 goto alloc_error;
3777         }
3778
3779         ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL);
3780         if (ret < 0) {
3781                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
3782                            __func__);
3783                 goto init_error;
3784         }
3785
3786         return dma_conf;
3787
3788 init_error:
3789         free_dma_desc_resources(priv, dma_conf);
3790 alloc_error:
3791         kfree(dma_conf);
3792         return ERR_PTR(ret);
3793 }
3794
3795 /**
3796  *  __stmmac_open - open entry point of the driver
3797  *  @dev : pointer to the device structure.
3798  *  @dma_conf :  structure to take the dma data
3799  *  Description:
3800  *  This function is the open entry point of the driver.
3801  *  Return value:
3802  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3803  *  file on failure.
3804  */
3805 static int __stmmac_open(struct net_device *dev,
3806                          struct stmmac_dma_conf *dma_conf)
3807 {
3808         struct stmmac_priv *priv = netdev_priv(dev);
3809         int mode = priv->plat->phy_interface;
3810         u32 chan;
3811         int ret;
3812
3813         ret = pm_runtime_resume_and_get(priv->device);
3814         if (ret < 0)
3815                 return ret;
3816
3817         if (priv->hw->pcs != STMMAC_PCS_TBI &&
3818             priv->hw->pcs != STMMAC_PCS_RTBI &&
3819             (!priv->hw->xpcs ||
3820              xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) &&
3821             !priv->hw->lynx_pcs) {
3822                 ret = stmmac_init_phy(dev);
3823                 if (ret) {
3824                         netdev_err(priv->dev,
3825                                    "%s: Cannot attach to PHY (error: %d)\n",
3826                                    __func__, ret);
3827                         goto init_phy_error;
3828                 }
3829         }
3830
3831         /* Extra statistics */
3832         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
3833         priv->xstats.threshold = tc;
3834
3835         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
3836
3837         buf_sz = dma_conf->dma_buf_sz;
3838         memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf));
3839
3840         stmmac_reset_queues_param(priv);
3841
3842         if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
3843             priv->plat->serdes_powerup) {
3844                 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
3845                 if (ret < 0) {
3846                         netdev_err(priv->dev, "%s: Serdes powerup failed\n",
3847                                    __func__);
3848                         goto init_error;
3849                 }
3850         }
3851
3852         ret = stmmac_hw_setup(dev, true);
3853         if (ret < 0) {
3854                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
3855                 goto init_error;
3856         }
3857
3858         stmmac_init_coalesce(priv);
3859
3860         phylink_start(priv->phylink);
3861         /* We may have called phylink_speed_down before */
3862         phylink_speed_up(priv->phylink);
3863
3864         ret = stmmac_request_irq(dev);
3865         if (ret)
3866                 goto irq_error;
3867
3868         stmmac_enable_all_queues(priv);
3869         netif_tx_start_all_queues(priv->dev);
3870         stmmac_enable_all_dma_irq(priv);
3871
3872         return 0;
3873
3874 irq_error:
3875         phylink_stop(priv->phylink);
3876
3877         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3878                 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
3879
3880         stmmac_hw_teardown(dev);
3881 init_error:
3882         phylink_disconnect_phy(priv->phylink);
3883 init_phy_error:
3884         pm_runtime_put(priv->device);
3885         return ret;
3886 }
3887
3888 static int stmmac_open(struct net_device *dev)
3889 {
3890         struct stmmac_priv *priv = netdev_priv(dev);
3891         struct stmmac_dma_conf *dma_conf;
3892         int ret;
3893
3894         dma_conf = stmmac_setup_dma_desc(priv, dev->mtu);
3895         if (IS_ERR(dma_conf))
3896                 return PTR_ERR(dma_conf);
3897
3898         ret = __stmmac_open(dev, dma_conf);
3899         if (ret)
3900                 free_dma_desc_resources(priv, dma_conf);
3901
3902         kfree(dma_conf);
3903         return ret;
3904 }
3905
3906 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
3907 {
3908         set_bit(__FPE_REMOVING, &priv->fpe_task_state);
3909
3910         if (priv->fpe_wq)
3911                 destroy_workqueue(priv->fpe_wq);
3912
3913         netdev_info(priv->dev, "FPE workqueue stop");
3914 }
3915
3916 /**
3917  *  stmmac_release - close entry point of the driver
3918  *  @dev : device pointer.
3919  *  Description:
3920  *  This is the stop entry point of the driver.
3921  */
3922 static int stmmac_release(struct net_device *dev)
3923 {
3924         struct stmmac_priv *priv = netdev_priv(dev);
3925         u32 chan;
3926
3927         if (device_may_wakeup(priv->device))
3928                 phylink_speed_down(priv->phylink, false);
3929         /* Stop and disconnect the PHY */
3930         phylink_stop(priv->phylink);
3931         phylink_disconnect_phy(priv->phylink);
3932
3933         stmmac_disable_all_queues(priv);
3934
3935         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
3936                 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
3937
3938         netif_tx_disable(dev);
3939
3940         /* Free the IRQ lines */
3941         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
3942
3943         if (priv->eee_enabled) {
3944                 priv->tx_path_in_lpi_mode = false;
3945                 del_timer_sync(&priv->eee_ctrl_timer);
3946         }
3947
3948         /* Stop TX/RX DMA and clear the descriptors */
3949         stmmac_stop_all_dma(priv);
3950
3951         /* Release and free the Rx/Tx resources */
3952         free_dma_desc_resources(priv, &priv->dma_conf);
3953
3954         /* Disable the MAC Rx/Tx */
3955         stmmac_mac_set(priv, priv->ioaddr, false);
3956
3957         /* Powerdown Serdes if there is */
3958         if (priv->plat->serdes_powerdown)
3959                 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv);
3960
3961         netif_carrier_off(dev);
3962
3963         stmmac_release_ptp(priv);
3964
3965         pm_runtime_put(priv->device);
3966
3967         if (priv->dma_cap.fpesel)
3968                 stmmac_fpe_stop_wq(priv);
3969
3970         return 0;
3971 }
3972
3973 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
3974                                struct stmmac_tx_queue *tx_q)
3975 {
3976         u16 tag = 0x0, inner_tag = 0x0;
3977         u32 inner_type = 0x0;
3978         struct dma_desc *p;
3979
3980         if (!priv->dma_cap.vlins)
3981                 return false;
3982         if (!skb_vlan_tag_present(skb))
3983                 return false;
3984         if (skb->vlan_proto == htons(ETH_P_8021AD)) {
3985                 inner_tag = skb_vlan_tag_get(skb);
3986                 inner_type = STMMAC_VLAN_INSERT;
3987         }
3988
3989         tag = skb_vlan_tag_get(skb);
3990
3991         if (tx_q->tbs & STMMAC_TBS_AVAIL)
3992                 p = &tx_q->dma_entx[tx_q->cur_tx].basic;
3993         else
3994                 p = &tx_q->dma_tx[tx_q->cur_tx];
3995
3996         if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
3997                 return false;
3998
3999         stmmac_set_tx_owner(priv, p);
4000         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4001         return true;
4002 }
4003
4004 /**
4005  *  stmmac_tso_allocator - close entry point of the driver
4006  *  @priv: driver private structure
4007  *  @des: buffer start address
4008  *  @total_len: total length to fill in descriptors
4009  *  @last_segment: condition for the last descriptor
4010  *  @queue: TX queue index
4011  *  Description:
4012  *  This function fills descriptor and request new descriptors according to
4013  *  buffer length to fill
4014  */
4015 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
4016                                  int total_len, bool last_segment, u32 queue)
4017 {
4018         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4019         struct dma_desc *desc;
4020         u32 buff_size;
4021         int tmp_len;
4022
4023         tmp_len = total_len;
4024
4025         while (tmp_len > 0) {
4026                 dma_addr_t curr_addr;
4027
4028                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4029                                                 priv->dma_conf.dma_tx_size);
4030                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4031
4032                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4033                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4034                 else
4035                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4036
4037                 curr_addr = des + (total_len - tmp_len);
4038                 if (priv->dma_cap.addr64 <= 32)
4039                         desc->des0 = cpu_to_le32(curr_addr);
4040                 else
4041                         stmmac_set_desc_addr(priv, desc, curr_addr);
4042
4043                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
4044                             TSO_MAX_BUFF_SIZE : tmp_len;
4045
4046                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
4047                                 0, 1,
4048                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
4049                                 0, 0);
4050
4051                 tmp_len -= TSO_MAX_BUFF_SIZE;
4052         }
4053 }
4054
4055 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
4056 {
4057         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4058         int desc_size;
4059
4060         if (likely(priv->extend_desc))
4061                 desc_size = sizeof(struct dma_extended_desc);
4062         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4063                 desc_size = sizeof(struct dma_edesc);
4064         else
4065                 desc_size = sizeof(struct dma_desc);
4066
4067         /* The own bit must be the latest setting done when prepare the
4068          * descriptor and then barrier is needed to make sure that
4069          * all is coherent before granting the DMA engine.
4070          */
4071         wmb();
4072
4073         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size);
4074         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
4075 }
4076
4077 /**
4078  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
4079  *  @skb : the socket buffer
4080  *  @dev : device pointer
4081  *  Description: this is the transmit function that is called on TSO frames
4082  *  (support available on GMAC4 and newer chips).
4083  *  Diagram below show the ring programming in case of TSO frames:
4084  *
4085  *  First Descriptor
4086  *   --------
4087  *   | DES0 |---> buffer1 = L2/L3/L4 header
4088  *   | DES1 |---> TCP Payload (can continue on next descr...)
4089  *   | DES2 |---> buffer 1 and 2 len
4090  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
4091  *   --------
4092  *      |
4093  *     ...
4094  *      |
4095  *   --------
4096  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
4097  *   | DES1 | --|
4098  *   | DES2 | --> buffer 1 and 2 len
4099  *   | DES3 |
4100  *   --------
4101  *
4102  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
4103  */
4104 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
4105 {
4106         struct dma_desc *desc, *first, *mss_desc = NULL;
4107         struct stmmac_priv *priv = netdev_priv(dev);
4108         int nfrags = skb_shinfo(skb)->nr_frags;
4109         u32 queue = skb_get_queue_mapping(skb);
4110         unsigned int first_entry, tx_packets;
4111         int tmp_pay_len = 0, first_tx;
4112         struct stmmac_tx_queue *tx_q;
4113         bool has_vlan, set_ic;
4114         u8 proto_hdr_len, hdr;
4115         u32 pay_len, mss;
4116         dma_addr_t des;
4117         int i;
4118
4119         tx_q = &priv->dma_conf.tx_queue[queue];
4120         first_tx = tx_q->cur_tx;
4121
4122         /* Compute header lengths */
4123         if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
4124                 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr);
4125                 hdr = sizeof(struct udphdr);
4126         } else {
4127                 proto_hdr_len = skb_tcp_all_headers(skb);
4128                 hdr = tcp_hdrlen(skb);
4129         }
4130
4131         /* Desc availability based on threshold should be enough safe */
4132         if (unlikely(stmmac_tx_avail(priv, queue) <
4133                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
4134                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4135                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4136                                                                 queue));
4137                         /* This is a hard error, log it. */
4138                         netdev_err(priv->dev,
4139                                    "%s: Tx Ring full when queue awake\n",
4140                                    __func__);
4141                 }
4142                 return NETDEV_TX_BUSY;
4143         }
4144
4145         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
4146
4147         mss = skb_shinfo(skb)->gso_size;
4148
4149         /* set new MSS value if needed */
4150         if (mss != tx_q->mss) {
4151                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4152                         mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4153                 else
4154                         mss_desc = &tx_q->dma_tx[tx_q->cur_tx];
4155
4156                 stmmac_set_mss(priv, mss_desc, mss);
4157                 tx_q->mss = mss;
4158                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
4159                                                 priv->dma_conf.dma_tx_size);
4160                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
4161         }
4162
4163         if (netif_msg_tx_queued(priv)) {
4164                 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
4165                         __func__, hdr, proto_hdr_len, pay_len, mss);
4166                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
4167                         skb->data_len);
4168         }
4169
4170         /* Check if VLAN can be inserted by HW */
4171         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4172
4173         first_entry = tx_q->cur_tx;
4174         WARN_ON(tx_q->tx_skbuff[first_entry]);
4175
4176         if (tx_q->tbs & STMMAC_TBS_AVAIL)
4177                 desc = &tx_q->dma_entx[first_entry].basic;
4178         else
4179                 desc = &tx_q->dma_tx[first_entry];
4180         first = desc;
4181
4182         if (has_vlan)
4183                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4184
4185         /* first descriptor: fill Headers on Buf1 */
4186         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
4187                              DMA_TO_DEVICE);
4188         if (dma_mapping_error(priv->device, des))
4189                 goto dma_map_err;
4190
4191         tx_q->tx_skbuff_dma[first_entry].buf = des;
4192         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
4193         tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4194         tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4195
4196         if (priv->dma_cap.addr64 <= 32) {
4197                 first->des0 = cpu_to_le32(des);
4198
4199                 /* Fill start of payload in buff2 of first descriptor */
4200                 if (pay_len)
4201                         first->des1 = cpu_to_le32(des + proto_hdr_len);
4202
4203                 /* If needed take extra descriptors to fill the remaining payload */
4204                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
4205         } else {
4206                 stmmac_set_desc_addr(priv, first, des);
4207                 tmp_pay_len = pay_len;
4208                 des += proto_hdr_len;
4209                 pay_len = 0;
4210         }
4211
4212         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
4213
4214         /* Prepare fragments */
4215         for (i = 0; i < nfrags; i++) {
4216                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4217
4218                 des = skb_frag_dma_map(priv->device, frag, 0,
4219                                        skb_frag_size(frag),
4220                                        DMA_TO_DEVICE);
4221                 if (dma_mapping_error(priv->device, des))
4222                         goto dma_map_err;
4223
4224                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
4225                                      (i == nfrags - 1), queue);
4226
4227                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
4228                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
4229                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
4230                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4231         }
4232
4233         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
4234
4235         /* Only the last descriptor gets to point to the skb. */
4236         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
4237         tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB;
4238
4239         /* Manage tx mitigation */
4240         tx_packets = (tx_q->cur_tx + 1) - first_tx;
4241         tx_q->tx_count_frames += tx_packets;
4242
4243         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4244                 set_ic = true;
4245         else if (!priv->tx_coal_frames[queue])
4246                 set_ic = false;
4247         else if (tx_packets > priv->tx_coal_frames[queue])
4248                 set_ic = true;
4249         else if ((tx_q->tx_count_frames %
4250                   priv->tx_coal_frames[queue]) < tx_packets)
4251                 set_ic = true;
4252         else
4253                 set_ic = false;
4254
4255         if (set_ic) {
4256                 if (tx_q->tbs & STMMAC_TBS_AVAIL)
4257                         desc = &tx_q->dma_entx[tx_q->cur_tx].basic;
4258                 else
4259                         desc = &tx_q->dma_tx[tx_q->cur_tx];
4260
4261                 tx_q->tx_count_frames = 0;
4262                 stmmac_set_tx_ic(priv, desc);
4263                 priv->xstats.tx_set_ic_bit++;
4264         }
4265
4266         /* We've used all descriptors we need for this skb, however,
4267          * advance cur_tx so that it references a fresh descriptor.
4268          * ndo_start_xmit will fill this descriptor the next time it's
4269          * called and stmmac_tx_clean may clean up to this descriptor.
4270          */
4271         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size);
4272
4273         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4274                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4275                           __func__);
4276                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4277         }
4278
4279         dev->stats.tx_bytes += skb->len;
4280         priv->xstats.tx_tso_frames++;
4281         priv->xstats.tx_tso_nfrags += nfrags;
4282
4283         if (priv->sarc_type)
4284                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4285
4286         skb_tx_timestamp(skb);
4287
4288         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4289                      priv->hwts_tx_en)) {
4290                 /* declare that device is doing timestamping */
4291                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4292                 stmmac_enable_tx_timestamp(priv, first);
4293         }
4294
4295         /* Complete the first descriptor before granting the DMA */
4296         stmmac_prepare_tso_tx_desc(priv, first, 1,
4297                         proto_hdr_len,
4298                         pay_len,
4299                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
4300                         hdr / 4, (skb->len - proto_hdr_len));
4301
4302         /* If context desc is used to change MSS */
4303         if (mss_desc) {
4304                 /* Make sure that first descriptor has been completely
4305                  * written, including its own bit. This is because MSS is
4306                  * actually before first descriptor, so we need to make
4307                  * sure that MSS's own bit is the last thing written.
4308                  */
4309                 dma_wmb();
4310                 stmmac_set_tx_owner(priv, mss_desc);
4311         }
4312
4313         if (netif_msg_pktdata(priv)) {
4314                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
4315                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4316                         tx_q->cur_tx, first, nfrags);
4317                 pr_info(">>> frame to be transmitted: ");
4318                 print_pkt(skb->data, skb_headlen(skb));
4319         }
4320
4321         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4322
4323         stmmac_flush_tx_descriptors(priv, queue);
4324         stmmac_tx_timer_arm(priv, queue);
4325
4326         return NETDEV_TX_OK;
4327
4328 dma_map_err:
4329         dev_err(priv->device, "Tx dma map failed\n");
4330         dev_kfree_skb(skb);
4331         priv->dev->stats.tx_dropped++;
4332         return NETDEV_TX_OK;
4333 }
4334
4335 /**
4336  *  stmmac_xmit - Tx entry point of the driver
4337  *  @skb : the socket buffer
4338  *  @dev : device pointer
4339  *  Description : this is the tx entry point of the driver.
4340  *  It programs the chain or the ring and supports oversized frames
4341  *  and SG feature.
4342  */
4343 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
4344 {
4345         unsigned int first_entry, tx_packets, enh_desc;
4346         struct stmmac_priv *priv = netdev_priv(dev);
4347         unsigned int nopaged_len = skb_headlen(skb);
4348         int i, csum_insertion = 0, is_jumbo = 0;
4349         u32 queue = skb_get_queue_mapping(skb);
4350         int nfrags = skb_shinfo(skb)->nr_frags;
4351         int gso = skb_shinfo(skb)->gso_type;
4352         struct dma_edesc *tbs_desc = NULL;
4353         struct dma_desc *desc, *first;
4354         struct stmmac_tx_queue *tx_q;
4355         bool has_vlan, set_ic;
4356         int entry, first_tx;
4357         dma_addr_t des;
4358
4359         tx_q = &priv->dma_conf.tx_queue[queue];
4360         first_tx = tx_q->cur_tx;
4361
4362         if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
4363                 stmmac_disable_eee_mode(priv);
4364
4365         /* Manage oversized TCP frames for GMAC4 device */
4366         if (skb_is_gso(skb) && priv->tso) {
4367                 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
4368                         return stmmac_tso_xmit(skb, dev);
4369                 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4))
4370                         return stmmac_tso_xmit(skb, dev);
4371         }
4372
4373         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
4374                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
4375                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
4376                                                                 queue));
4377                         /* This is a hard error, log it. */
4378                         netdev_err(priv->dev,
4379                                    "%s: Tx Ring full when queue awake\n",
4380                                    __func__);
4381                 }
4382                 return NETDEV_TX_BUSY;
4383         }
4384
4385         /* Check if VLAN can be inserted by HW */
4386         has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
4387
4388         entry = tx_q->cur_tx;
4389         first_entry = entry;
4390         WARN_ON(tx_q->tx_skbuff[first_entry]);
4391
4392         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
4393
4394         if (likely(priv->extend_desc))
4395                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4396         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4397                 desc = &tx_q->dma_entx[entry].basic;
4398         else
4399                 desc = tx_q->dma_tx + entry;
4400
4401         first = desc;
4402
4403         if (has_vlan)
4404                 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
4405
4406         enh_desc = priv->plat->enh_desc;
4407         /* To program the descriptors according to the size of the frame */
4408         if (enh_desc)
4409                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
4410
4411         if (unlikely(is_jumbo)) {
4412                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
4413                 if (unlikely(entry < 0) && (entry != -EINVAL))
4414                         goto dma_map_err;
4415         }
4416
4417         for (i = 0; i < nfrags; i++) {
4418                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4419                 int len = skb_frag_size(frag);
4420                 bool last_segment = (i == (nfrags - 1));
4421
4422                 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4423                 WARN_ON(tx_q->tx_skbuff[entry]);
4424
4425                 if (likely(priv->extend_desc))
4426                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4427                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4428                         desc = &tx_q->dma_entx[entry].basic;
4429                 else
4430                         desc = tx_q->dma_tx + entry;
4431
4432                 des = skb_frag_dma_map(priv->device, frag, 0, len,
4433                                        DMA_TO_DEVICE);
4434                 if (dma_mapping_error(priv->device, des))
4435                         goto dma_map_err; /* should reuse desc w/o issues */
4436
4437                 tx_q->tx_skbuff_dma[entry].buf = des;
4438
4439                 stmmac_set_desc_addr(priv, desc, des);
4440
4441                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
4442                 tx_q->tx_skbuff_dma[entry].len = len;
4443                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
4444                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4445
4446                 /* Prepare the descriptor and set the own bit too */
4447                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
4448                                 priv->mode, 1, last_segment, skb->len);
4449         }
4450
4451         /* Only the last descriptor gets to point to the skb. */
4452         tx_q->tx_skbuff[entry] = skb;
4453         tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB;
4454
4455         /* According to the coalesce parameter the IC bit for the latest
4456          * segment is reset and the timer re-started to clean the tx status.
4457          * This approach takes care about the fragments: desc is the first
4458          * element in case of no SG.
4459          */
4460         tx_packets = (entry + 1) - first_tx;
4461         tx_q->tx_count_frames += tx_packets;
4462
4463         if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en)
4464                 set_ic = true;
4465         else if (!priv->tx_coal_frames[queue])
4466                 set_ic = false;
4467         else if (tx_packets > priv->tx_coal_frames[queue])
4468                 set_ic = true;
4469         else if ((tx_q->tx_count_frames %
4470                   priv->tx_coal_frames[queue]) < tx_packets)
4471                 set_ic = true;
4472         else
4473                 set_ic = false;
4474
4475         if (set_ic) {
4476                 if (likely(priv->extend_desc))
4477                         desc = &tx_q->dma_etx[entry].basic;
4478                 else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4479                         desc = &tx_q->dma_entx[entry].basic;
4480                 else
4481                         desc = &tx_q->dma_tx[entry];
4482
4483                 tx_q->tx_count_frames = 0;
4484                 stmmac_set_tx_ic(priv, desc);
4485                 priv->xstats.tx_set_ic_bit++;
4486         }
4487
4488         /* We've used all descriptors we need for this skb, however,
4489          * advance cur_tx so that it references a fresh descriptor.
4490          * ndo_start_xmit will fill this descriptor the next time it's
4491          * called and stmmac_tx_clean may clean up to this descriptor.
4492          */
4493         entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4494         tx_q->cur_tx = entry;
4495
4496         if (netif_msg_pktdata(priv)) {
4497                 netdev_dbg(priv->dev,
4498                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
4499                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
4500                            entry, first, nfrags);
4501
4502                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
4503                 print_pkt(skb->data, skb->len);
4504         }
4505
4506         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
4507                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
4508                           __func__);
4509                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
4510         }
4511
4512         dev->stats.tx_bytes += skb->len;
4513
4514         if (priv->sarc_type)
4515                 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
4516
4517         skb_tx_timestamp(skb);
4518
4519         /* Ready to fill the first descriptor and set the OWN bit w/o any
4520          * problems because all the descriptors are actually ready to be
4521          * passed to the DMA engine.
4522          */
4523         if (likely(!is_jumbo)) {
4524                 bool last_segment = (nfrags == 0);
4525
4526                 des = dma_map_single(priv->device, skb->data,
4527                                      nopaged_len, DMA_TO_DEVICE);
4528                 if (dma_mapping_error(priv->device, des))
4529                         goto dma_map_err;
4530
4531                 tx_q->tx_skbuff_dma[first_entry].buf = des;
4532                 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB;
4533                 tx_q->tx_skbuff_dma[first_entry].map_as_page = false;
4534
4535                 stmmac_set_desc_addr(priv, first, des);
4536
4537                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
4538                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
4539
4540                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4541                              priv->hwts_tx_en)) {
4542                         /* declare that device is doing timestamping */
4543                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4544                         stmmac_enable_tx_timestamp(priv, first);
4545                 }
4546
4547                 /* Prepare the first descriptor setting the OWN bit too */
4548                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
4549                                 csum_insertion, priv->mode, 0, last_segment,
4550                                 skb->len);
4551         }
4552
4553         if (tx_q->tbs & STMMAC_TBS_EN) {
4554                 struct timespec64 ts = ns_to_timespec64(skb->tstamp);
4555
4556                 tbs_desc = &tx_q->dma_entx[first_entry];
4557                 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec);
4558         }
4559
4560         stmmac_set_tx_owner(priv, first);
4561
4562         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
4563
4564         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4565
4566         stmmac_flush_tx_descriptors(priv, queue);
4567         stmmac_tx_timer_arm(priv, queue);
4568
4569         return NETDEV_TX_OK;
4570
4571 dma_map_err:
4572         netdev_err(priv->dev, "Tx DMA map failed\n");
4573         dev_kfree_skb(skb);
4574         priv->dev->stats.tx_dropped++;
4575         return NETDEV_TX_OK;
4576 }
4577
4578 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
4579 {
4580         struct vlan_ethhdr *veth = skb_vlan_eth_hdr(skb);
4581         __be16 vlan_proto = veth->h_vlan_proto;
4582         u16 vlanid;
4583
4584         if ((vlan_proto == htons(ETH_P_8021Q) &&
4585              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
4586             (vlan_proto == htons(ETH_P_8021AD) &&
4587              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
4588                 /* pop the vlan tag */
4589                 vlanid = ntohs(veth->h_vlan_TCI);
4590                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
4591                 skb_pull(skb, VLAN_HLEN);
4592                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
4593         }
4594 }
4595
4596 /**
4597  * stmmac_rx_refill - refill used skb preallocated buffers
4598  * @priv: driver private structure
4599  * @queue: RX queue index
4600  * Description : this is to reallocate the skb for the reception process
4601  * that is based on zero-copy.
4602  */
4603 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
4604 {
4605         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
4606         int dirty = stmmac_rx_dirty(priv, queue);
4607         unsigned int entry = rx_q->dirty_rx;
4608         gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
4609
4610         if (priv->dma_cap.host_dma_width <= 32)
4611                 gfp |= GFP_DMA32;
4612
4613         while (dirty-- > 0) {
4614                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4615                 struct dma_desc *p;
4616                 bool use_rx_wd;
4617
4618                 if (priv->extend_desc)
4619                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
4620                 else
4621                         p = rx_q->dma_rx + entry;
4622
4623                 if (!buf->page) {
4624                         buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4625                         if (!buf->page)
4626                                 break;
4627                 }
4628
4629                 if (priv->sph && !buf->sec_page) {
4630                         buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
4631                         if (!buf->sec_page)
4632                                 break;
4633
4634                         buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
4635                 }
4636
4637                 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
4638
4639                 stmmac_set_desc_addr(priv, p, buf->addr);
4640                 if (priv->sph)
4641                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true);
4642                 else
4643                         stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false);
4644                 stmmac_refill_desc3(priv, rx_q, p);
4645
4646                 rx_q->rx_count_frames++;
4647                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4648                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4649                         rx_q->rx_count_frames = 0;
4650
4651                 use_rx_wd = !priv->rx_coal_frames[queue];
4652                 use_rx_wd |= rx_q->rx_count_frames > 0;
4653                 if (!priv->use_riwt)
4654                         use_rx_wd = false;
4655
4656                 dma_wmb();
4657                 stmmac_set_rx_owner(priv, p, use_rx_wd);
4658
4659                 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
4660         }
4661         rx_q->dirty_rx = entry;
4662         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
4663                             (rx_q->dirty_rx * sizeof(struct dma_desc));
4664         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
4665 }
4666
4667 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv,
4668                                        struct dma_desc *p,
4669                                        int status, unsigned int len)
4670 {
4671         unsigned int plen = 0, hlen = 0;
4672         int coe = priv->hw->rx_csum;
4673
4674         /* Not first descriptor, buffer is always zero */
4675         if (priv->sph && len)
4676                 return 0;
4677
4678         /* First descriptor, get split header length */
4679         stmmac_get_rx_header_len(priv, p, &hlen);
4680         if (priv->sph && hlen) {
4681                 priv->xstats.rx_split_hdr_pkt_n++;
4682                 return hlen;
4683         }
4684
4685         /* First descriptor, not last descriptor and not split header */
4686         if (status & rx_not_ls)
4687                 return priv->dma_conf.dma_buf_sz;
4688
4689         plen = stmmac_get_rx_frame_len(priv, p, coe);
4690
4691         /* First descriptor and last descriptor and not split header */
4692         return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen);
4693 }
4694
4695 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
4696                                        struct dma_desc *p,
4697                                        int status, unsigned int len)
4698 {
4699         int coe = priv->hw->rx_csum;
4700         unsigned int plen = 0;
4701
4702         /* Not split header, buffer is not available */
4703         if (!priv->sph)
4704                 return 0;
4705
4706         /* Not last descriptor */
4707         if (status & rx_not_ls)
4708                 return priv->dma_conf.dma_buf_sz;
4709
4710         plen = stmmac_get_rx_frame_len(priv, p, coe);
4711
4712         /* Last descriptor */
4713         return plen - len;
4714 }
4715
4716 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
4717                                 struct xdp_frame *xdpf, bool dma_map)
4718 {
4719         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
4720         unsigned int entry = tx_q->cur_tx;
4721         struct dma_desc *tx_desc;
4722         dma_addr_t dma_addr;
4723         bool set_ic;
4724
4725         if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv))
4726                 return STMMAC_XDP_CONSUMED;
4727
4728         if (likely(priv->extend_desc))
4729                 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry);
4730         else if (tx_q->tbs & STMMAC_TBS_AVAIL)
4731                 tx_desc = &tx_q->dma_entx[entry].basic;
4732         else
4733                 tx_desc = tx_q->dma_tx + entry;
4734
4735         if (dma_map) {
4736                 dma_addr = dma_map_single(priv->device, xdpf->data,
4737                                           xdpf->len, DMA_TO_DEVICE);
4738                 if (dma_mapping_error(priv->device, dma_addr))
4739                         return STMMAC_XDP_CONSUMED;
4740
4741                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO;
4742         } else {
4743                 struct page *page = virt_to_page(xdpf->data);
4744
4745                 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) +
4746                            xdpf->headroom;
4747                 dma_sync_single_for_device(priv->device, dma_addr,
4748                                            xdpf->len, DMA_BIDIRECTIONAL);
4749
4750                 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX;
4751         }
4752
4753         tx_q->tx_skbuff_dma[entry].buf = dma_addr;
4754         tx_q->tx_skbuff_dma[entry].map_as_page = false;
4755         tx_q->tx_skbuff_dma[entry].len = xdpf->len;
4756         tx_q->tx_skbuff_dma[entry].last_segment = true;
4757         tx_q->tx_skbuff_dma[entry].is_jumbo = false;
4758
4759         tx_q->xdpf[entry] = xdpf;
4760
4761         stmmac_set_desc_addr(priv, tx_desc, dma_addr);
4762
4763         stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len,
4764                                true, priv->mode, true, true,
4765                                xdpf->len);
4766
4767         tx_q->tx_count_frames++;
4768
4769         if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0)
4770                 set_ic = true;
4771         else
4772                 set_ic = false;
4773
4774         if (set_ic) {
4775                 tx_q->tx_count_frames = 0;
4776                 stmmac_set_tx_ic(priv, tx_desc);
4777                 priv->xstats.tx_set_ic_bit++;
4778         }
4779
4780         stmmac_enable_dma_transmission(priv, priv->ioaddr);
4781
4782         entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size);
4783         tx_q->cur_tx = entry;
4784
4785         return STMMAC_XDP_TX;
4786 }
4787
4788 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv,
4789                                    int cpu)
4790 {
4791         int index = cpu;
4792
4793         if (unlikely(index < 0))
4794                 index = 0;
4795
4796         while (index >= priv->plat->tx_queues_to_use)
4797                 index -= priv->plat->tx_queues_to_use;
4798
4799         return index;
4800 }
4801
4802 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv,
4803                                 struct xdp_buff *xdp)
4804 {
4805         struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp);
4806         int cpu = smp_processor_id();
4807         struct netdev_queue *nq;
4808         int queue;
4809         int res;
4810
4811         if (unlikely(!xdpf))
4812                 return STMMAC_XDP_CONSUMED;
4813
4814         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4815         nq = netdev_get_tx_queue(priv->dev, queue);
4816
4817         __netif_tx_lock(nq, cpu);
4818         /* Avoids TX time-out as we are sharing with slow path */
4819         txq_trans_cond_update(nq);
4820
4821         res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false);
4822         if (res == STMMAC_XDP_TX)
4823                 stmmac_flush_tx_descriptors(priv, queue);
4824
4825         __netif_tx_unlock(nq);
4826
4827         return res;
4828 }
4829
4830 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv,
4831                                  struct bpf_prog *prog,
4832                                  struct xdp_buff *xdp)
4833 {
4834         u32 act;
4835         int res;
4836
4837         act = bpf_prog_run_xdp(prog, xdp);
4838         switch (act) {
4839         case XDP_PASS:
4840                 res = STMMAC_XDP_PASS;
4841                 break;
4842         case XDP_TX:
4843                 res = stmmac_xdp_xmit_back(priv, xdp);
4844                 break;
4845         case XDP_REDIRECT:
4846                 if (xdp_do_redirect(priv->dev, xdp, prog) < 0)
4847                         res = STMMAC_XDP_CONSUMED;
4848                 else
4849                         res = STMMAC_XDP_REDIRECT;
4850                 break;
4851         default:
4852                 bpf_warn_invalid_xdp_action(priv->dev, prog, act);
4853                 fallthrough;
4854         case XDP_ABORTED:
4855                 trace_xdp_exception(priv->dev, prog, act);
4856                 fallthrough;
4857         case XDP_DROP:
4858                 res = STMMAC_XDP_CONSUMED;
4859                 break;
4860         }
4861
4862         return res;
4863 }
4864
4865 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv,
4866                                            struct xdp_buff *xdp)
4867 {
4868         struct bpf_prog *prog;
4869         int res;
4870
4871         prog = READ_ONCE(priv->xdp_prog);
4872         if (!prog) {
4873                 res = STMMAC_XDP_PASS;
4874                 goto out;
4875         }
4876
4877         res = __stmmac_xdp_run_prog(priv, prog, xdp);
4878 out:
4879         return ERR_PTR(-res);
4880 }
4881
4882 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv,
4883                                    int xdp_status)
4884 {
4885         int cpu = smp_processor_id();
4886         int queue;
4887
4888         queue = stmmac_xdp_get_tx_queue(priv, cpu);
4889
4890         if (xdp_status & STMMAC_XDP_TX)
4891                 stmmac_tx_timer_arm(priv, queue);
4892
4893         if (xdp_status & STMMAC_XDP_REDIRECT)
4894                 xdp_do_flush();
4895 }
4896
4897 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch,
4898                                                struct xdp_buff *xdp)
4899 {
4900         unsigned int metasize = xdp->data - xdp->data_meta;
4901         unsigned int datasize = xdp->data_end - xdp->data;
4902         struct sk_buff *skb;
4903
4904         skb = __napi_alloc_skb(&ch->rxtx_napi,
4905                                xdp->data_end - xdp->data_hard_start,
4906                                GFP_ATOMIC | __GFP_NOWARN);
4907         if (unlikely(!skb))
4908                 return NULL;
4909
4910         skb_reserve(skb, xdp->data - xdp->data_hard_start);
4911         memcpy(__skb_put(skb, datasize), xdp->data, datasize);
4912         if (metasize)
4913                 skb_metadata_set(skb, metasize);
4914
4915         return skb;
4916 }
4917
4918 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue,
4919                                    struct dma_desc *p, struct dma_desc *np,
4920                                    struct xdp_buff *xdp)
4921 {
4922         struct stmmac_channel *ch = &priv->channel[queue];
4923         unsigned int len = xdp->data_end - xdp->data;
4924         enum pkt_hash_types hash_type;
4925         int coe = priv->hw->rx_csum;
4926         struct sk_buff *skb;
4927         u32 hash;
4928
4929         skb = stmmac_construct_skb_zc(ch, xdp);
4930         if (!skb) {
4931                 priv->dev->stats.rx_dropped++;
4932                 return;
4933         }
4934
4935         stmmac_get_rx_hwtstamp(priv, p, np, skb);
4936         stmmac_rx_vlan(priv->dev, skb);
4937         skb->protocol = eth_type_trans(skb, priv->dev);
4938
4939         if (unlikely(!coe))
4940                 skb_checksum_none_assert(skb);
4941         else
4942                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4943
4944         if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
4945                 skb_set_hash(skb, hash, hash_type);
4946
4947         skb_record_rx_queue(skb, queue);
4948         napi_gro_receive(&ch->rxtx_napi, skb);
4949
4950         priv->dev->stats.rx_packets++;
4951         priv->dev->stats.rx_bytes += len;
4952 }
4953
4954 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
4955 {
4956         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
4957         unsigned int entry = rx_q->dirty_rx;
4958         struct dma_desc *rx_desc = NULL;
4959         bool ret = true;
4960
4961         budget = min(budget, stmmac_rx_dirty(priv, queue));
4962
4963         while (budget-- > 0 && entry != rx_q->cur_rx) {
4964                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
4965                 dma_addr_t dma_addr;
4966                 bool use_rx_wd;
4967
4968                 if (!buf->xdp) {
4969                         buf->xdp = xsk_buff_alloc(rx_q->xsk_pool);
4970                         if (!buf->xdp) {
4971                                 ret = false;
4972                                 break;
4973                         }
4974                 }
4975
4976                 if (priv->extend_desc)
4977                         rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry);
4978                 else
4979                         rx_desc = rx_q->dma_rx + entry;
4980
4981                 dma_addr = xsk_buff_xdp_get_dma(buf->xdp);
4982                 stmmac_set_desc_addr(priv, rx_desc, dma_addr);
4983                 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false);
4984                 stmmac_refill_desc3(priv, rx_q, rx_desc);
4985
4986                 rx_q->rx_count_frames++;
4987                 rx_q->rx_count_frames += priv->rx_coal_frames[queue];
4988                 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue])
4989                         rx_q->rx_count_frames = 0;
4990
4991                 use_rx_wd = !priv->rx_coal_frames[queue];
4992                 use_rx_wd |= rx_q->rx_count_frames > 0;
4993                 if (!priv->use_riwt)
4994                         use_rx_wd = false;
4995
4996                 dma_wmb();
4997                 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
4998
4999                 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size);
5000         }
5001
5002         if (rx_desc) {
5003                 rx_q->dirty_rx = entry;
5004                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
5005                                      (rx_q->dirty_rx * sizeof(struct dma_desc));
5006                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
5007         }
5008
5009         return ret;
5010 }
5011
5012 static struct stmmac_xdp_buff *xsk_buff_to_stmmac_ctx(struct xdp_buff *xdp)
5013 {
5014         /* In XDP zero copy data path, xdp field in struct xdp_buff_xsk is used
5015          * to represent incoming packet, whereas cb field in the same structure
5016          * is used to store driver specific info. Thus, struct stmmac_xdp_buff
5017          * is laid on top of xdp and cb fields of struct xdp_buff_xsk.
5018          */
5019         return (struct stmmac_xdp_buff *)xdp;
5020 }
5021
5022 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
5023 {
5024         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5025         unsigned int count = 0, error = 0, len = 0;
5026         int dirty = stmmac_rx_dirty(priv, queue);
5027         unsigned int next_entry = rx_q->cur_rx;
5028         unsigned int desc_size;
5029         struct bpf_prog *prog;
5030         bool failure = false;
5031         int xdp_status = 0;
5032         int status = 0;
5033
5034         if (netif_msg_rx_status(priv)) {
5035                 void *rx_head;
5036
5037                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5038                 if (priv->extend_desc) {
5039                         rx_head = (void *)rx_q->dma_erx;
5040                         desc_size = sizeof(struct dma_extended_desc);
5041                 } else {
5042                         rx_head = (void *)rx_q->dma_rx;
5043                         desc_size = sizeof(struct dma_desc);
5044                 }
5045
5046                 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5047                                     rx_q->dma_rx_phy, desc_size);
5048         }
5049         while (count < limit) {
5050                 struct stmmac_rx_buffer *buf;
5051                 struct stmmac_xdp_buff *ctx;
5052                 unsigned int buf1_len = 0;
5053                 struct dma_desc *np, *p;
5054                 int entry;
5055                 int res;
5056
5057                 if (!count && rx_q->state_saved) {
5058                         error = rx_q->state.error;
5059                         len = rx_q->state.len;
5060                 } else {
5061                         rx_q->state_saved = false;
5062                         error = 0;
5063                         len = 0;
5064                 }
5065
5066                 if (count >= limit)
5067                         break;
5068
5069 read_again:
5070                 buf1_len = 0;
5071                 entry = next_entry;
5072                 buf = &rx_q->buf_pool[entry];
5073
5074                 if (dirty >= STMMAC_RX_FILL_BATCH) {
5075                         failure = failure ||
5076                                   !stmmac_rx_refill_zc(priv, queue, dirty);
5077                         dirty = 0;
5078                 }
5079
5080                 if (priv->extend_desc)
5081                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5082                 else
5083                         p = rx_q->dma_rx + entry;
5084
5085                 /* read the status of the incoming frame */
5086                 status = stmmac_rx_status(priv, &priv->dev->stats,
5087                                           &priv->xstats, p);
5088                 /* check if managed by the DMA otherwise go ahead */
5089                 if (unlikely(status & dma_own))
5090                         break;
5091
5092                 /* Prefetch the next RX descriptor */
5093                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5094                                                 priv->dma_conf.dma_rx_size);
5095                 next_entry = rx_q->cur_rx;
5096
5097                 if (priv->extend_desc)
5098                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5099                 else
5100                         np = rx_q->dma_rx + next_entry;
5101
5102                 prefetch(np);
5103
5104                 /* Ensure a valid XSK buffer before proceed */
5105                 if (!buf->xdp)
5106                         break;
5107
5108                 if (priv->extend_desc)
5109                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5110                                                   &priv->xstats,
5111                                                   rx_q->dma_erx + entry);
5112                 if (unlikely(status == discard_frame)) {
5113                         xsk_buff_free(buf->xdp);
5114                         buf->xdp = NULL;
5115                         dirty++;
5116                         error = 1;
5117                         if (!priv->hwts_rx_en)
5118                                 priv->dev->stats.rx_errors++;
5119                 }
5120
5121                 if (unlikely(error && (status & rx_not_ls)))
5122                         goto read_again;
5123                 if (unlikely(error)) {
5124                         count++;
5125                         continue;
5126                 }
5127
5128                 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */
5129                 if (likely(status & rx_not_ls)) {
5130                         xsk_buff_free(buf->xdp);
5131                         buf->xdp = NULL;
5132                         dirty++;
5133                         count++;
5134                         goto read_again;
5135                 }
5136
5137                 ctx = xsk_buff_to_stmmac_ctx(buf->xdp);
5138                 ctx->priv = priv;
5139                 ctx->desc = p;
5140                 ctx->ndesc = np;
5141
5142                 /* XDP ZC Frame only support primary buffers for now */
5143                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5144                 len += buf1_len;
5145
5146                 /* ACS is disabled; strip manually. */
5147                 if (likely(!(status & rx_not_ls))) {
5148                         buf1_len -= ETH_FCS_LEN;
5149                         len -= ETH_FCS_LEN;
5150                 }
5151
5152                 /* RX buffer is good and fit into a XSK pool buffer */
5153                 buf->xdp->data_end = buf->xdp->data + buf1_len;
5154                 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool);
5155
5156                 prog = READ_ONCE(priv->xdp_prog);
5157                 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp);
5158
5159                 switch (res) {
5160                 case STMMAC_XDP_PASS:
5161                         stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp);
5162                         xsk_buff_free(buf->xdp);
5163                         break;
5164                 case STMMAC_XDP_CONSUMED:
5165                         xsk_buff_free(buf->xdp);
5166                         priv->dev->stats.rx_dropped++;
5167                         break;
5168                 case STMMAC_XDP_TX:
5169                 case STMMAC_XDP_REDIRECT:
5170                         xdp_status |= res;
5171                         break;
5172                 }
5173
5174                 buf->xdp = NULL;
5175                 dirty++;
5176                 count++;
5177         }
5178
5179         if (status & rx_not_ls) {
5180                 rx_q->state_saved = true;
5181                 rx_q->state.error = error;
5182                 rx_q->state.len = len;
5183         }
5184
5185         stmmac_finalize_xdp_rx(priv, xdp_status);
5186
5187         priv->xstats.rx_pkt_n += count;
5188         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5189
5190         if (xsk_uses_need_wakeup(rx_q->xsk_pool)) {
5191                 if (failure || stmmac_rx_dirty(priv, queue) > 0)
5192                         xsk_set_rx_need_wakeup(rx_q->xsk_pool);
5193                 else
5194                         xsk_clear_rx_need_wakeup(rx_q->xsk_pool);
5195
5196                 return (int)count;
5197         }
5198
5199         return failure ? limit : (int)count;
5200 }
5201
5202 /**
5203  * stmmac_rx - manage the receive process
5204  * @priv: driver private structure
5205  * @limit: napi bugget
5206  * @queue: RX queue index.
5207  * Description :  this the function called by the napi poll method.
5208  * It gets all the frames inside the ring.
5209  */
5210 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
5211 {
5212         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
5213         struct stmmac_channel *ch = &priv->channel[queue];
5214         unsigned int count = 0, error = 0, len = 0;
5215         int status = 0, coe = priv->hw->rx_csum;
5216         unsigned int next_entry = rx_q->cur_rx;
5217         enum dma_data_direction dma_dir;
5218         unsigned int desc_size;
5219         struct sk_buff *skb = NULL;
5220         struct stmmac_xdp_buff ctx;
5221         int xdp_status = 0;
5222         int buf_sz;
5223
5224         dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
5225         buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
5226
5227         if (netif_msg_rx_status(priv)) {
5228                 void *rx_head;
5229
5230                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
5231                 if (priv->extend_desc) {
5232                         rx_head = (void *)rx_q->dma_erx;
5233                         desc_size = sizeof(struct dma_extended_desc);
5234                 } else {
5235                         rx_head = (void *)rx_q->dma_rx;
5236                         desc_size = sizeof(struct dma_desc);
5237                 }
5238
5239                 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true,
5240                                     rx_q->dma_rx_phy, desc_size);
5241         }
5242         while (count < limit) {
5243                 unsigned int buf1_len = 0, buf2_len = 0;
5244                 enum pkt_hash_types hash_type;
5245                 struct stmmac_rx_buffer *buf;
5246                 struct dma_desc *np, *p;
5247                 int entry;
5248                 u32 hash;
5249
5250                 if (!count && rx_q->state_saved) {
5251                         skb = rx_q->state.skb;
5252                         error = rx_q->state.error;
5253                         len = rx_q->state.len;
5254                 } else {
5255                         rx_q->state_saved = false;
5256                         skb = NULL;
5257                         error = 0;
5258                         len = 0;
5259                 }
5260
5261                 if (count >= limit)
5262                         break;
5263
5264 read_again:
5265                 buf1_len = 0;
5266                 buf2_len = 0;
5267                 entry = next_entry;
5268                 buf = &rx_q->buf_pool[entry];
5269
5270                 if (priv->extend_desc)
5271                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
5272                 else
5273                         p = rx_q->dma_rx + entry;
5274
5275                 /* read the status of the incoming frame */
5276                 status = stmmac_rx_status(priv, &priv->dev->stats,
5277                                 &priv->xstats, p);
5278                 /* check if managed by the DMA otherwise go ahead */
5279                 if (unlikely(status & dma_own))
5280                         break;
5281
5282                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
5283                                                 priv->dma_conf.dma_rx_size);
5284                 next_entry = rx_q->cur_rx;
5285
5286                 if (priv->extend_desc)
5287                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
5288                 else
5289                         np = rx_q->dma_rx + next_entry;
5290
5291                 prefetch(np);
5292
5293                 if (priv->extend_desc)
5294                         stmmac_rx_extended_status(priv, &priv->dev->stats,
5295                                         &priv->xstats, rx_q->dma_erx + entry);
5296                 if (unlikely(status == discard_frame)) {
5297                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5298                         buf->page = NULL;
5299                         error = 1;
5300                         if (!priv->hwts_rx_en)
5301                                 priv->dev->stats.rx_errors++;
5302                 }
5303
5304                 if (unlikely(error && (status & rx_not_ls)))
5305                         goto read_again;
5306                 if (unlikely(error)) {
5307                         dev_kfree_skb(skb);
5308                         skb = NULL;
5309                         count++;
5310                         continue;
5311                 }
5312
5313                 /* Buffer is good. Go on. */
5314
5315                 prefetch(page_address(buf->page) + buf->page_offset);
5316                 if (buf->sec_page)
5317                         prefetch(page_address(buf->sec_page));
5318
5319                 buf1_len = stmmac_rx_buf1_len(priv, p, status, len);
5320                 len += buf1_len;
5321                 buf2_len = stmmac_rx_buf2_len(priv, p, status, len);
5322                 len += buf2_len;
5323
5324                 /* ACS is disabled; strip manually. */
5325                 if (likely(!(status & rx_not_ls))) {
5326                         if (buf2_len) {
5327                                 buf2_len -= ETH_FCS_LEN;
5328                                 len -= ETH_FCS_LEN;
5329                         } else if (buf1_len) {
5330                                 buf1_len -= ETH_FCS_LEN;
5331                                 len -= ETH_FCS_LEN;
5332                         }
5333                 }
5334
5335                 if (!skb) {
5336                         unsigned int pre_len, sync_len;
5337
5338                         dma_sync_single_for_cpu(priv->device, buf->addr,
5339                                                 buf1_len, dma_dir);
5340
5341                         xdp_init_buff(&ctx.xdp, buf_sz, &rx_q->xdp_rxq);
5342                         xdp_prepare_buff(&ctx.xdp, page_address(buf->page),
5343                                          buf->page_offset, buf1_len, true);
5344
5345                         pre_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5346                                   buf->page_offset;
5347
5348                         ctx.priv = priv;
5349                         ctx.desc = p;
5350                         ctx.ndesc = np;
5351
5352                         skb = stmmac_xdp_run_prog(priv, &ctx.xdp);
5353                         /* Due xdp_adjust_tail: DMA sync for_device
5354                          * cover max len CPU touch
5355                          */
5356                         sync_len = ctx.xdp.data_end - ctx.xdp.data_hard_start -
5357                                    buf->page_offset;
5358                         sync_len = max(sync_len, pre_len);
5359
5360                         /* For Not XDP_PASS verdict */
5361                         if (IS_ERR(skb)) {
5362                                 unsigned int xdp_res = -PTR_ERR(skb);
5363
5364                                 if (xdp_res & STMMAC_XDP_CONSUMED) {
5365                                         page_pool_put_page(rx_q->page_pool,
5366                                                            virt_to_head_page(ctx.xdp.data),
5367                                                            sync_len, true);
5368                                         buf->page = NULL;
5369                                         priv->dev->stats.rx_dropped++;
5370
5371                                         /* Clear skb as it was set as
5372                                          * status by XDP program.
5373                                          */
5374                                         skb = NULL;
5375
5376                                         if (unlikely((status & rx_not_ls)))
5377                                                 goto read_again;
5378
5379                                         count++;
5380                                         continue;
5381                                 } else if (xdp_res & (STMMAC_XDP_TX |
5382                                                       STMMAC_XDP_REDIRECT)) {
5383                                         xdp_status |= xdp_res;
5384                                         buf->page = NULL;
5385                                         skb = NULL;
5386                                         count++;
5387                                         continue;
5388                                 }
5389                         }
5390                 }
5391
5392                 if (!skb) {
5393                         /* XDP program may expand or reduce tail */
5394                         buf1_len = ctx.xdp.data_end - ctx.xdp.data;
5395
5396                         skb = napi_alloc_skb(&ch->rx_napi, buf1_len);
5397                         if (!skb) {
5398                                 priv->dev->stats.rx_dropped++;
5399                                 count++;
5400                                 goto drain_data;
5401                         }
5402
5403                         /* XDP program may adjust header */
5404                         skb_copy_to_linear_data(skb, ctx.xdp.data, buf1_len);
5405                         skb_put(skb, buf1_len);
5406
5407                         /* Data payload copied into SKB, page ready for recycle */
5408                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
5409                         buf->page = NULL;
5410                 } else if (buf1_len) {
5411                         dma_sync_single_for_cpu(priv->device, buf->addr,
5412                                                 buf1_len, dma_dir);
5413                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5414                                         buf->page, buf->page_offset, buf1_len,
5415                                         priv->dma_conf.dma_buf_sz);
5416
5417                         /* Data payload appended into SKB */
5418                         page_pool_release_page(rx_q->page_pool, buf->page);
5419                         buf->page = NULL;
5420                 }
5421
5422                 if (buf2_len) {
5423                         dma_sync_single_for_cpu(priv->device, buf->sec_addr,
5424                                                 buf2_len, dma_dir);
5425                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
5426                                         buf->sec_page, 0, buf2_len,
5427                                         priv->dma_conf.dma_buf_sz);
5428
5429                         /* Data payload appended into SKB */
5430                         page_pool_release_page(rx_q->page_pool, buf->sec_page);
5431                         buf->sec_page = NULL;
5432                 }
5433
5434 drain_data:
5435                 if (likely(status & rx_not_ls))
5436                         goto read_again;
5437                 if (!skb)
5438                         continue;
5439
5440                 /* Got entire packet into SKB. Finish it. */
5441
5442                 stmmac_get_rx_hwtstamp(priv, p, np, skb);
5443                 stmmac_rx_vlan(priv->dev, skb);
5444                 skb->protocol = eth_type_trans(skb, priv->dev);
5445
5446                 if (unlikely(!coe))
5447                         skb_checksum_none_assert(skb);
5448                 else
5449                         skb->ip_summed = CHECKSUM_UNNECESSARY;
5450
5451                 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
5452                         skb_set_hash(skb, hash, hash_type);
5453
5454                 skb_record_rx_queue(skb, queue);
5455                 napi_gro_receive(&ch->rx_napi, skb);
5456                 skb = NULL;
5457
5458                 priv->dev->stats.rx_packets++;
5459                 priv->dev->stats.rx_bytes += len;
5460                 count++;
5461         }
5462
5463         if (status & rx_not_ls || skb) {
5464                 rx_q->state_saved = true;
5465                 rx_q->state.skb = skb;
5466                 rx_q->state.error = error;
5467                 rx_q->state.len = len;
5468         }
5469
5470         stmmac_finalize_xdp_rx(priv, xdp_status);
5471
5472         stmmac_rx_refill(priv, queue);
5473
5474         priv->xstats.rx_pkt_n += count;
5475         priv->xstats.rxq_stats[queue].rx_pkt_n += count;
5476
5477         return count;
5478 }
5479
5480 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
5481 {
5482         struct stmmac_channel *ch =
5483                 container_of(napi, struct stmmac_channel, rx_napi);
5484         struct stmmac_priv *priv = ch->priv_data;
5485         u32 chan = ch->index;
5486         int work_done;
5487
5488         priv->xstats.napi_poll++;
5489
5490         work_done = stmmac_rx(priv, budget, chan);
5491         if (work_done < budget && napi_complete_done(napi, work_done)) {
5492                 unsigned long flags;
5493
5494                 spin_lock_irqsave(&ch->lock, flags);
5495                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0);
5496                 spin_unlock_irqrestore(&ch->lock, flags);
5497         }
5498
5499         return work_done;
5500 }
5501
5502 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
5503 {
5504         struct stmmac_channel *ch =
5505                 container_of(napi, struct stmmac_channel, tx_napi);
5506         struct stmmac_priv *priv = ch->priv_data;
5507         u32 chan = ch->index;
5508         int work_done;
5509
5510         priv->xstats.napi_poll++;
5511
5512         work_done = stmmac_tx_clean(priv, budget, chan);
5513         work_done = min(work_done, budget);
5514
5515         if (work_done < budget && napi_complete_done(napi, work_done)) {
5516                 unsigned long flags;
5517
5518                 spin_lock_irqsave(&ch->lock, flags);
5519                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1);
5520                 spin_unlock_irqrestore(&ch->lock, flags);
5521         }
5522
5523         return work_done;
5524 }
5525
5526 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget)
5527 {
5528         struct stmmac_channel *ch =
5529                 container_of(napi, struct stmmac_channel, rxtx_napi);
5530         struct stmmac_priv *priv = ch->priv_data;
5531         int rx_done, tx_done, rxtx_done;
5532         u32 chan = ch->index;
5533
5534         priv->xstats.napi_poll++;
5535
5536         tx_done = stmmac_tx_clean(priv, budget, chan);
5537         tx_done = min(tx_done, budget);
5538
5539         rx_done = stmmac_rx_zc(priv, budget, chan);
5540
5541         rxtx_done = max(tx_done, rx_done);
5542
5543         /* If either TX or RX work is not complete, return budget
5544          * and keep pooling
5545          */
5546         if (rxtx_done >= budget)
5547                 return budget;
5548
5549         /* all work done, exit the polling mode */
5550         if (napi_complete_done(napi, rxtx_done)) {
5551                 unsigned long flags;
5552
5553                 spin_lock_irqsave(&ch->lock, flags);
5554                 /* Both RX and TX work done are compelte,
5555                  * so enable both RX & TX IRQs.
5556                  */
5557                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
5558                 spin_unlock_irqrestore(&ch->lock, flags);
5559         }
5560
5561         return min(rxtx_done, budget - 1);
5562 }
5563
5564 /**
5565  *  stmmac_tx_timeout
5566  *  @dev : Pointer to net device structure
5567  *  @txqueue: the index of the hanging transmit queue
5568  *  Description: this function is called when a packet transmission fails to
5569  *   complete within a reasonable time. The driver will mark the error in the
5570  *   netdev structure and arrange for the device to be reset to a sane state
5571  *   in order to transmit a new packet.
5572  */
5573 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue)
5574 {
5575         struct stmmac_priv *priv = netdev_priv(dev);
5576
5577         stmmac_global_err(priv);
5578 }
5579
5580 /**
5581  *  stmmac_set_rx_mode - entry point for multicast addressing
5582  *  @dev : pointer to the device structure
5583  *  Description:
5584  *  This function is a driver entry point which gets called by the kernel
5585  *  whenever multicast addresses must be enabled/disabled.
5586  *  Return value:
5587  *  void.
5588  */
5589 static void stmmac_set_rx_mode(struct net_device *dev)
5590 {
5591         struct stmmac_priv *priv = netdev_priv(dev);
5592
5593         stmmac_set_filter(priv, priv->hw, dev);
5594 }
5595
5596 /**
5597  *  stmmac_change_mtu - entry point to change MTU size for the device.
5598  *  @dev : device pointer.
5599  *  @new_mtu : the new MTU size for the device.
5600  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
5601  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
5602  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
5603  *  Return value:
5604  *  0 on success and an appropriate (-)ve integer as defined in errno.h
5605  *  file on failure.
5606  */
5607 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
5608 {
5609         struct stmmac_priv *priv = netdev_priv(dev);
5610         int txfifosz = priv->plat->tx_fifo_size;
5611         struct stmmac_dma_conf *dma_conf;
5612         const int mtu = new_mtu;
5613         int ret;
5614
5615         if (txfifosz == 0)
5616                 txfifosz = priv->dma_cap.tx_fifo_size;
5617
5618         txfifosz /= priv->plat->tx_queues_to_use;
5619
5620         if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
5621                 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
5622                 return -EINVAL;
5623         }
5624
5625         new_mtu = STMMAC_ALIGN(new_mtu);
5626
5627         /* If condition true, FIFO is too small or MTU too large */
5628         if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
5629                 return -EINVAL;
5630
5631         if (netif_running(dev)) {
5632                 netdev_dbg(priv->dev, "restarting interface to change its MTU\n");
5633                 /* Try to allocate the new DMA conf with the new mtu */
5634                 dma_conf = stmmac_setup_dma_desc(priv, mtu);
5635                 if (IS_ERR(dma_conf)) {
5636                         netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n",
5637                                    mtu);
5638                         return PTR_ERR(dma_conf);
5639                 }
5640
5641                 stmmac_release(dev);
5642
5643                 ret = __stmmac_open(dev, dma_conf);
5644                 if (ret) {
5645                         free_dma_desc_resources(priv, dma_conf);
5646                         kfree(dma_conf);
5647                         netdev_err(priv->dev, "failed reopening the interface after MTU change\n");
5648                         return ret;
5649                 }
5650
5651                 kfree(dma_conf);
5652
5653                 stmmac_set_rx_mode(dev);
5654         }
5655
5656         dev->mtu = mtu;
5657         netdev_update_features(dev);
5658
5659         return 0;
5660 }
5661
5662 static netdev_features_t stmmac_fix_features(struct net_device *dev,
5663                                              netdev_features_t features)
5664 {
5665         struct stmmac_priv *priv = netdev_priv(dev);
5666
5667         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
5668                 features &= ~NETIF_F_RXCSUM;
5669
5670         if (!priv->plat->tx_coe)
5671                 features &= ~NETIF_F_CSUM_MASK;
5672
5673         /* Some GMAC devices have a bugged Jumbo frame support that
5674          * needs to have the Tx COE disabled for oversized frames
5675          * (due to limited buffer sizes). In this case we disable
5676          * the TX csum insertion in the TDES and not use SF.
5677          */
5678         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
5679                 features &= ~NETIF_F_CSUM_MASK;
5680
5681         /* Disable tso if asked by ethtool */
5682         if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
5683                 if (features & NETIF_F_TSO)
5684                         priv->tso = true;
5685                 else
5686                         priv->tso = false;
5687         }
5688
5689         return features;
5690 }
5691
5692 static int stmmac_set_features(struct net_device *netdev,
5693                                netdev_features_t features)
5694 {
5695         struct stmmac_priv *priv = netdev_priv(netdev);
5696
5697         /* Keep the COE Type in case of csum is supporting */
5698         if (features & NETIF_F_RXCSUM)
5699                 priv->hw->rx_csum = priv->plat->rx_coe;
5700         else
5701                 priv->hw->rx_csum = 0;
5702         /* No check needed because rx_coe has been set before and it will be
5703          * fixed in case of issue.
5704          */
5705         stmmac_rx_ipc(priv, priv->hw);
5706
5707         if (priv->sph_cap) {
5708                 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph;
5709                 u32 chan;
5710
5711                 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
5712                         stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
5713         }
5714
5715         return 0;
5716 }
5717
5718 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status)
5719 {
5720         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
5721         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
5722         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
5723         bool *hs_enable = &fpe_cfg->hs_enable;
5724
5725         if (status == FPE_EVENT_UNKNOWN || !*hs_enable)
5726                 return;
5727
5728         /* If LP has sent verify mPacket, LP is FPE capable */
5729         if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) {
5730                 if (*lp_state < FPE_STATE_CAPABLE)
5731                         *lp_state = FPE_STATE_CAPABLE;
5732
5733                 /* If user has requested FPE enable, quickly response */
5734                 if (*hs_enable)
5735                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
5736                                                 MPACKET_RESPONSE);
5737         }
5738
5739         /* If Local has sent verify mPacket, Local is FPE capable */
5740         if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) {
5741                 if (*lo_state < FPE_STATE_CAPABLE)
5742                         *lo_state = FPE_STATE_CAPABLE;
5743         }
5744
5745         /* If LP has sent response mPacket, LP is entering FPE ON */
5746         if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP)
5747                 *lp_state = FPE_STATE_ENTERING_ON;
5748
5749         /* If Local has sent response mPacket, Local is entering FPE ON */
5750         if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP)
5751                 *lo_state = FPE_STATE_ENTERING_ON;
5752
5753         if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) &&
5754             !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) &&
5755             priv->fpe_wq) {
5756                 queue_work(priv->fpe_wq, &priv->fpe_task);
5757         }
5758 }
5759
5760 static void stmmac_common_interrupt(struct stmmac_priv *priv)
5761 {
5762         u32 rx_cnt = priv->plat->rx_queues_to_use;
5763         u32 tx_cnt = priv->plat->tx_queues_to_use;
5764         u32 queues_count;
5765         u32 queue;
5766         bool xmac;
5767
5768         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
5769         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
5770
5771         if (priv->irq_wake)
5772                 pm_wakeup_event(priv->device, 0);
5773
5774         if (priv->dma_cap.estsel)
5775                 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev,
5776                                       &priv->xstats, tx_cnt);
5777
5778         if (priv->dma_cap.fpesel) {
5779                 int status = stmmac_fpe_irq_status(priv, priv->ioaddr,
5780                                                    priv->dev);
5781
5782                 stmmac_fpe_event_status(priv, status);
5783         }
5784
5785         /* To handle GMAC own interrupts */
5786         if ((priv->plat->has_gmac) || xmac) {
5787                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
5788
5789                 if (unlikely(status)) {
5790                         /* For LPI we need to save the tx status */
5791                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
5792                                 priv->tx_path_in_lpi_mode = true;
5793                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
5794                                 priv->tx_path_in_lpi_mode = false;
5795                 }
5796
5797                 for (queue = 0; queue < queues_count; queue++) {
5798                         status = stmmac_host_mtl_irq_status(priv, priv->hw,
5799                                                             queue);
5800                 }
5801
5802                 /* PCS link status */
5803                 if (priv->hw->pcs &&
5804                     !(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS)) {
5805                         if (priv->xstats.pcs_link)
5806                                 netif_carrier_on(priv->dev);
5807                         else
5808                                 netif_carrier_off(priv->dev);
5809                 }
5810
5811                 stmmac_timestamp_interrupt(priv, priv);
5812         }
5813 }
5814
5815 /**
5816  *  stmmac_interrupt - main ISR
5817  *  @irq: interrupt number.
5818  *  @dev_id: to pass the net device pointer.
5819  *  Description: this is the main driver interrupt service routine.
5820  *  It can call:
5821  *  o DMA service routine (to manage incoming frame reception and transmission
5822  *    status)
5823  *  o Core interrupts to manage: remote wake-up, management counter, LPI
5824  *    interrupts.
5825  */
5826 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
5827 {
5828         struct net_device *dev = (struct net_device *)dev_id;
5829         struct stmmac_priv *priv = netdev_priv(dev);
5830
5831         /* Check if adapter is up */
5832         if (test_bit(STMMAC_DOWN, &priv->state))
5833                 return IRQ_HANDLED;
5834
5835         /* Check if a fatal error happened */
5836         if (stmmac_safety_feat_interrupt(priv))
5837                 return IRQ_HANDLED;
5838
5839         /* To handle Common interrupts */
5840         stmmac_common_interrupt(priv);
5841
5842         /* To handle DMA interrupts */
5843         stmmac_dma_interrupt(priv);
5844
5845         return IRQ_HANDLED;
5846 }
5847
5848 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id)
5849 {
5850         struct net_device *dev = (struct net_device *)dev_id;
5851         struct stmmac_priv *priv = netdev_priv(dev);
5852
5853         if (unlikely(!dev)) {
5854                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5855                 return IRQ_NONE;
5856         }
5857
5858         /* Check if adapter is up */
5859         if (test_bit(STMMAC_DOWN, &priv->state))
5860                 return IRQ_HANDLED;
5861
5862         /* To handle Common interrupts */
5863         stmmac_common_interrupt(priv);
5864
5865         return IRQ_HANDLED;
5866 }
5867
5868 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id)
5869 {
5870         struct net_device *dev = (struct net_device *)dev_id;
5871         struct stmmac_priv *priv = netdev_priv(dev);
5872
5873         if (unlikely(!dev)) {
5874                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5875                 return IRQ_NONE;
5876         }
5877
5878         /* Check if adapter is up */
5879         if (test_bit(STMMAC_DOWN, &priv->state))
5880                 return IRQ_HANDLED;
5881
5882         /* Check if a fatal error happened */
5883         stmmac_safety_feat_interrupt(priv);
5884
5885         return IRQ_HANDLED;
5886 }
5887
5888 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data)
5889 {
5890         struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data;
5891         struct stmmac_dma_conf *dma_conf;
5892         int chan = tx_q->queue_index;
5893         struct stmmac_priv *priv;
5894         int status;
5895
5896         dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]);
5897         priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
5898
5899         if (unlikely(!data)) {
5900                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5901                 return IRQ_NONE;
5902         }
5903
5904         /* Check if adapter is up */
5905         if (test_bit(STMMAC_DOWN, &priv->state))
5906                 return IRQ_HANDLED;
5907
5908         status = stmmac_napi_check(priv, chan, DMA_DIR_TX);
5909
5910         if (unlikely(status & tx_hard_error_bump_tc)) {
5911                 /* Try to bump up the dma threshold on this failure */
5912                 stmmac_bump_dma_threshold(priv, chan);
5913         } else if (unlikely(status == tx_hard_error)) {
5914                 stmmac_tx_err(priv, chan);
5915         }
5916
5917         return IRQ_HANDLED;
5918 }
5919
5920 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data)
5921 {
5922         struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data;
5923         struct stmmac_dma_conf *dma_conf;
5924         int chan = rx_q->queue_index;
5925         struct stmmac_priv *priv;
5926
5927         dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]);
5928         priv = container_of(dma_conf, struct stmmac_priv, dma_conf);
5929
5930         if (unlikely(!data)) {
5931                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
5932                 return IRQ_NONE;
5933         }
5934
5935         /* Check if adapter is up */
5936         if (test_bit(STMMAC_DOWN, &priv->state))
5937                 return IRQ_HANDLED;
5938
5939         stmmac_napi_check(priv, chan, DMA_DIR_RX);
5940
5941         return IRQ_HANDLED;
5942 }
5943
5944 #ifdef CONFIG_NET_POLL_CONTROLLER
5945 /* Polling receive - used by NETCONSOLE and other diagnostic tools
5946  * to allow network I/O with interrupts disabled.
5947  */
5948 static void stmmac_poll_controller(struct net_device *dev)
5949 {
5950         struct stmmac_priv *priv = netdev_priv(dev);
5951         int i;
5952
5953         /* If adapter is down, do nothing */
5954         if (test_bit(STMMAC_DOWN, &priv->state))
5955                 return;
5956
5957         if (priv->plat->multi_msi_en) {
5958                 for (i = 0; i < priv->plat->rx_queues_to_use; i++)
5959                         stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]);
5960
5961                 for (i = 0; i < priv->plat->tx_queues_to_use; i++)
5962                         stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]);
5963         } else {
5964                 disable_irq(dev->irq);
5965                 stmmac_interrupt(dev->irq, dev);
5966                 enable_irq(dev->irq);
5967         }
5968 }
5969 #endif
5970
5971 /**
5972  *  stmmac_ioctl - Entry point for the Ioctl
5973  *  @dev: Device pointer.
5974  *  @rq: An IOCTL specefic structure, that can contain a pointer to
5975  *  a proprietary structure used to pass information to the driver.
5976  *  @cmd: IOCTL command
5977  *  Description:
5978  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
5979  */
5980 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5981 {
5982         struct stmmac_priv *priv = netdev_priv (dev);
5983         int ret = -EOPNOTSUPP;
5984
5985         if (!netif_running(dev))
5986                 return -EINVAL;
5987
5988         switch (cmd) {
5989         case SIOCGMIIPHY:
5990         case SIOCGMIIREG:
5991         case SIOCSMIIREG:
5992                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
5993                 break;
5994         case SIOCSHWTSTAMP:
5995                 ret = stmmac_hwtstamp_set(dev, rq);
5996                 break;
5997         case SIOCGHWTSTAMP:
5998                 ret = stmmac_hwtstamp_get(dev, rq);
5999                 break;
6000         default:
6001                 break;
6002         }
6003
6004         return ret;
6005 }
6006
6007 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
6008                                     void *cb_priv)
6009 {
6010         struct stmmac_priv *priv = cb_priv;
6011         int ret = -EOPNOTSUPP;
6012
6013         if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
6014                 return ret;
6015
6016         __stmmac_disable_all_queues(priv);
6017
6018         switch (type) {
6019         case TC_SETUP_CLSU32:
6020                 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
6021                 break;
6022         case TC_SETUP_CLSFLOWER:
6023                 ret = stmmac_tc_setup_cls(priv, priv, type_data);
6024                 break;
6025         default:
6026                 break;
6027         }
6028
6029         stmmac_enable_all_queues(priv);
6030         return ret;
6031 }
6032
6033 static LIST_HEAD(stmmac_block_cb_list);
6034
6035 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
6036                            void *type_data)
6037 {
6038         struct stmmac_priv *priv = netdev_priv(ndev);
6039
6040         switch (type) {
6041         case TC_QUERY_CAPS:
6042                 return stmmac_tc_query_caps(priv, priv, type_data);
6043         case TC_SETUP_BLOCK:
6044                 return flow_block_cb_setup_simple(type_data,
6045                                                   &stmmac_block_cb_list,
6046                                                   stmmac_setup_tc_block_cb,
6047                                                   priv, priv, true);
6048         case TC_SETUP_QDISC_CBS:
6049                 return stmmac_tc_setup_cbs(priv, priv, type_data);
6050         case TC_SETUP_QDISC_TAPRIO:
6051                 return stmmac_tc_setup_taprio(priv, priv, type_data);
6052         case TC_SETUP_QDISC_ETF:
6053                 return stmmac_tc_setup_etf(priv, priv, type_data);
6054         default:
6055                 return -EOPNOTSUPP;
6056         }
6057 }
6058
6059 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
6060                                struct net_device *sb_dev)
6061 {
6062         int gso = skb_shinfo(skb)->gso_type;
6063
6064         if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) {
6065                 /*
6066                  * There is no way to determine the number of TSO/USO
6067                  * capable Queues. Let's use always the Queue 0
6068                  * because if TSO/USO is supported then at least this
6069                  * one will be capable.
6070                  */
6071                 return 0;
6072         }
6073
6074         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
6075 }
6076
6077 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
6078 {
6079         struct stmmac_priv *priv = netdev_priv(ndev);
6080         int ret = 0;
6081
6082         ret = pm_runtime_resume_and_get(priv->device);
6083         if (ret < 0)
6084                 return ret;
6085
6086         ret = eth_mac_addr(ndev, addr);
6087         if (ret)
6088                 goto set_mac_error;
6089
6090         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
6091
6092 set_mac_error:
6093         pm_runtime_put(priv->device);
6094
6095         return ret;
6096 }
6097
6098 #ifdef CONFIG_DEBUG_FS
6099 static struct dentry *stmmac_fs_dir;
6100
6101 static void sysfs_display_ring(void *head, int size, int extend_desc,
6102                                struct seq_file *seq, dma_addr_t dma_phy_addr)
6103 {
6104         int i;
6105         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
6106         struct dma_desc *p = (struct dma_desc *)head;
6107         dma_addr_t dma_addr;
6108
6109         for (i = 0; i < size; i++) {
6110                 if (extend_desc) {
6111                         dma_addr = dma_phy_addr + i * sizeof(*ep);
6112                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
6113                                    i, &dma_addr,
6114                                    le32_to_cpu(ep->basic.des0),
6115                                    le32_to_cpu(ep->basic.des1),
6116                                    le32_to_cpu(ep->basic.des2),
6117                                    le32_to_cpu(ep->basic.des3));
6118                         ep++;
6119                 } else {
6120                         dma_addr = dma_phy_addr + i * sizeof(*p);
6121                         seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n",
6122                                    i, &dma_addr,
6123                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
6124                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
6125                         p++;
6126                 }
6127                 seq_printf(seq, "\n");
6128         }
6129 }
6130
6131 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
6132 {
6133         struct net_device *dev = seq->private;
6134         struct stmmac_priv *priv = netdev_priv(dev);
6135         u32 rx_count = priv->plat->rx_queues_to_use;
6136         u32 tx_count = priv->plat->tx_queues_to_use;
6137         u32 queue;
6138
6139         if ((dev->flags & IFF_UP) == 0)
6140                 return 0;
6141
6142         for (queue = 0; queue < rx_count; queue++) {
6143                 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6144
6145                 seq_printf(seq, "RX Queue %d:\n", queue);
6146
6147                 if (priv->extend_desc) {
6148                         seq_printf(seq, "Extended descriptor ring:\n");
6149                         sysfs_display_ring((void *)rx_q->dma_erx,
6150                                            priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy);
6151                 } else {
6152                         seq_printf(seq, "Descriptor ring:\n");
6153                         sysfs_display_ring((void *)rx_q->dma_rx,
6154                                            priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy);
6155                 }
6156         }
6157
6158         for (queue = 0; queue < tx_count; queue++) {
6159                 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6160
6161                 seq_printf(seq, "TX Queue %d:\n", queue);
6162
6163                 if (priv->extend_desc) {
6164                         seq_printf(seq, "Extended descriptor ring:\n");
6165                         sysfs_display_ring((void *)tx_q->dma_etx,
6166                                            priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy);
6167                 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) {
6168                         seq_printf(seq, "Descriptor ring:\n");
6169                         sysfs_display_ring((void *)tx_q->dma_tx,
6170                                            priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy);
6171                 }
6172         }
6173
6174         return 0;
6175 }
6176 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
6177
6178 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
6179 {
6180         struct net_device *dev = seq->private;
6181         struct stmmac_priv *priv = netdev_priv(dev);
6182
6183         if (!priv->hw_cap_support) {
6184                 seq_printf(seq, "DMA HW features not supported\n");
6185                 return 0;
6186         }
6187
6188         seq_printf(seq, "==============================\n");
6189         seq_printf(seq, "\tDMA HW features\n");
6190         seq_printf(seq, "==============================\n");
6191
6192         seq_printf(seq, "\t10/100 Mbps: %s\n",
6193                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
6194         seq_printf(seq, "\t1000 Mbps: %s\n",
6195                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
6196         seq_printf(seq, "\tHalf duplex: %s\n",
6197                    (priv->dma_cap.half_duplex) ? "Y" : "N");
6198         seq_printf(seq, "\tHash Filter: %s\n",
6199                    (priv->dma_cap.hash_filter) ? "Y" : "N");
6200         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
6201                    (priv->dma_cap.multi_addr) ? "Y" : "N");
6202         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
6203                    (priv->dma_cap.pcs) ? "Y" : "N");
6204         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
6205                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
6206         seq_printf(seq, "\tPMT Remote wake up: %s\n",
6207                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
6208         seq_printf(seq, "\tPMT Magic Frame: %s\n",
6209                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
6210         seq_printf(seq, "\tRMON module: %s\n",
6211                    (priv->dma_cap.rmon) ? "Y" : "N");
6212         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
6213                    (priv->dma_cap.time_stamp) ? "Y" : "N");
6214         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
6215                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
6216         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
6217                    (priv->dma_cap.eee) ? "Y" : "N");
6218         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
6219         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
6220                    (priv->dma_cap.tx_coe) ? "Y" : "N");
6221         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
6222                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
6223                            (priv->dma_cap.rx_coe) ? "Y" : "N");
6224         } else {
6225                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
6226                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
6227                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
6228                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
6229         }
6230         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
6231                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
6232         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
6233                    priv->dma_cap.number_rx_channel);
6234         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
6235                    priv->dma_cap.number_tx_channel);
6236         seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
6237                    priv->dma_cap.number_rx_queues);
6238         seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
6239                    priv->dma_cap.number_tx_queues);
6240         seq_printf(seq, "\tEnhanced descriptors: %s\n",
6241                    (priv->dma_cap.enh_desc) ? "Y" : "N");
6242         seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size);
6243         seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size);
6244         seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz);
6245         seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N");
6246         seq_printf(seq, "\tNumber of PPS Outputs: %d\n",
6247                    priv->dma_cap.pps_out_num);
6248         seq_printf(seq, "\tSafety Features: %s\n",
6249                    priv->dma_cap.asp ? "Y" : "N");
6250         seq_printf(seq, "\tFlexible RX Parser: %s\n",
6251                    priv->dma_cap.frpsel ? "Y" : "N");
6252         seq_printf(seq, "\tEnhanced Addressing: %d\n",
6253                    priv->dma_cap.host_dma_width);
6254         seq_printf(seq, "\tReceive Side Scaling: %s\n",
6255                    priv->dma_cap.rssen ? "Y" : "N");
6256         seq_printf(seq, "\tVLAN Hash Filtering: %s\n",
6257                    priv->dma_cap.vlhash ? "Y" : "N");
6258         seq_printf(seq, "\tSplit Header: %s\n",
6259                    priv->dma_cap.sphen ? "Y" : "N");
6260         seq_printf(seq, "\tVLAN TX Insertion: %s\n",
6261                    priv->dma_cap.vlins ? "Y" : "N");
6262         seq_printf(seq, "\tDouble VLAN: %s\n",
6263                    priv->dma_cap.dvlan ? "Y" : "N");
6264         seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n",
6265                    priv->dma_cap.l3l4fnum);
6266         seq_printf(seq, "\tARP Offloading: %s\n",
6267                    priv->dma_cap.arpoffsel ? "Y" : "N");
6268         seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n",
6269                    priv->dma_cap.estsel ? "Y" : "N");
6270         seq_printf(seq, "\tFrame Preemption (FPE): %s\n",
6271                    priv->dma_cap.fpesel ? "Y" : "N");
6272         seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n",
6273                    priv->dma_cap.tbssel ? "Y" : "N");
6274         return 0;
6275 }
6276 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
6277
6278 /* Use network device events to rename debugfs file entries.
6279  */
6280 static int stmmac_device_event(struct notifier_block *unused,
6281                                unsigned long event, void *ptr)
6282 {
6283         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6284         struct stmmac_priv *priv = netdev_priv(dev);
6285
6286         if (dev->netdev_ops != &stmmac_netdev_ops)
6287                 goto done;
6288
6289         switch (event) {
6290         case NETDEV_CHANGENAME:
6291                 if (priv->dbgfs_dir)
6292                         priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir,
6293                                                          priv->dbgfs_dir,
6294                                                          stmmac_fs_dir,
6295                                                          dev->name);
6296                 break;
6297         }
6298 done:
6299         return NOTIFY_DONE;
6300 }
6301
6302 static struct notifier_block stmmac_notifier = {
6303         .notifier_call = stmmac_device_event,
6304 };
6305
6306 static void stmmac_init_fs(struct net_device *dev)
6307 {
6308         struct stmmac_priv *priv = netdev_priv(dev);
6309
6310         rtnl_lock();
6311
6312         /* Create per netdev entries */
6313         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
6314
6315         /* Entry to report DMA RX/TX rings */
6316         debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
6317                             &stmmac_rings_status_fops);
6318
6319         /* Entry to report the DMA HW features */
6320         debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
6321                             &stmmac_dma_cap_fops);
6322
6323         rtnl_unlock();
6324 }
6325
6326 static void stmmac_exit_fs(struct net_device *dev)
6327 {
6328         struct stmmac_priv *priv = netdev_priv(dev);
6329
6330         debugfs_remove_recursive(priv->dbgfs_dir);
6331 }
6332 #endif /* CONFIG_DEBUG_FS */
6333
6334 static u32 stmmac_vid_crc32_le(__le16 vid_le)
6335 {
6336         unsigned char *data = (unsigned char *)&vid_le;
6337         unsigned char data_byte = 0;
6338         u32 crc = ~0x0;
6339         u32 temp = 0;
6340         int i, bits;
6341
6342         bits = get_bitmask_order(VLAN_VID_MASK);
6343         for (i = 0; i < bits; i++) {
6344                 if ((i % 8) == 0)
6345                         data_byte = data[i / 8];
6346
6347                 temp = ((crc & 1) ^ data_byte) & 1;
6348                 crc >>= 1;
6349                 data_byte >>= 1;
6350
6351                 if (temp)
6352                         crc ^= 0xedb88320;
6353         }
6354
6355         return crc;
6356 }
6357
6358 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
6359 {
6360         u32 crc, hash = 0;
6361         __le16 pmatch = 0;
6362         int count = 0;
6363         u16 vid = 0;
6364
6365         for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
6366                 __le16 vid_le = cpu_to_le16(vid);
6367                 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
6368                 hash |= (1 << crc);
6369                 count++;
6370         }
6371
6372         if (!priv->dma_cap.vlhash) {
6373                 if (count > 2) /* VID = 0 always passes filter */
6374                         return -EOPNOTSUPP;
6375
6376                 pmatch = cpu_to_le16(vid);
6377                 hash = 0;
6378         }
6379
6380         return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double);
6381 }
6382
6383 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
6384 {
6385         struct stmmac_priv *priv = netdev_priv(ndev);
6386         bool is_double = false;
6387         int ret;
6388
6389         ret = pm_runtime_resume_and_get(priv->device);
6390         if (ret < 0)
6391                 return ret;
6392
6393         if (be16_to_cpu(proto) == ETH_P_8021AD)
6394                 is_double = true;
6395
6396         set_bit(vid, priv->active_vlans);
6397         ret = stmmac_vlan_update(priv, is_double);
6398         if (ret) {
6399                 clear_bit(vid, priv->active_vlans);
6400                 goto err_pm_put;
6401         }
6402
6403         if (priv->hw->num_vlan) {
6404                 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6405                 if (ret)
6406                         goto err_pm_put;
6407         }
6408 err_pm_put:
6409         pm_runtime_put(priv->device);
6410
6411         return ret;
6412 }
6413
6414 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
6415 {
6416         struct stmmac_priv *priv = netdev_priv(ndev);
6417         bool is_double = false;
6418         int ret;
6419
6420         ret = pm_runtime_resume_and_get(priv->device);
6421         if (ret < 0)
6422                 return ret;
6423
6424         if (be16_to_cpu(proto) == ETH_P_8021AD)
6425                 is_double = true;
6426
6427         clear_bit(vid, priv->active_vlans);
6428
6429         if (priv->hw->num_vlan) {
6430                 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
6431                 if (ret)
6432                         goto del_vlan_error;
6433         }
6434
6435         ret = stmmac_vlan_update(priv, is_double);
6436
6437 del_vlan_error:
6438         pm_runtime_put(priv->device);
6439
6440         return ret;
6441 }
6442
6443 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf)
6444 {
6445         struct stmmac_priv *priv = netdev_priv(dev);
6446
6447         switch (bpf->command) {
6448         case XDP_SETUP_PROG:
6449                 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack);
6450         case XDP_SETUP_XSK_POOL:
6451                 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool,
6452                                              bpf->xsk.queue_id);
6453         default:
6454                 return -EOPNOTSUPP;
6455         }
6456 }
6457
6458 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames,
6459                            struct xdp_frame **frames, u32 flags)
6460 {
6461         struct stmmac_priv *priv = netdev_priv(dev);
6462         int cpu = smp_processor_id();
6463         struct netdev_queue *nq;
6464         int i, nxmit = 0;
6465         int queue;
6466
6467         if (unlikely(test_bit(STMMAC_DOWN, &priv->state)))
6468                 return -ENETDOWN;
6469
6470         if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
6471                 return -EINVAL;
6472
6473         queue = stmmac_xdp_get_tx_queue(priv, cpu);
6474         nq = netdev_get_tx_queue(priv->dev, queue);
6475
6476         __netif_tx_lock(nq, cpu);
6477         /* Avoids TX time-out as we are sharing with slow path */
6478         txq_trans_cond_update(nq);
6479
6480         for (i = 0; i < num_frames; i++) {
6481                 int res;
6482
6483                 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true);
6484                 if (res == STMMAC_XDP_CONSUMED)
6485                         break;
6486
6487                 nxmit++;
6488         }
6489
6490         if (flags & XDP_XMIT_FLUSH) {
6491                 stmmac_flush_tx_descriptors(priv, queue);
6492                 stmmac_tx_timer_arm(priv, queue);
6493         }
6494
6495         __netif_tx_unlock(nq);
6496
6497         return nxmit;
6498 }
6499
6500 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue)
6501 {
6502         struct stmmac_channel *ch = &priv->channel[queue];
6503         unsigned long flags;
6504
6505         spin_lock_irqsave(&ch->lock, flags);
6506         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6507         spin_unlock_irqrestore(&ch->lock, flags);
6508
6509         stmmac_stop_rx_dma(priv, queue);
6510         __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6511 }
6512
6513 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue)
6514 {
6515         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
6516         struct stmmac_channel *ch = &priv->channel[queue];
6517         unsigned long flags;
6518         u32 buf_size;
6519         int ret;
6520
6521         ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6522         if (ret) {
6523                 netdev_err(priv->dev, "Failed to alloc RX desc.\n");
6524                 return;
6525         }
6526
6527         ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL);
6528         if (ret) {
6529                 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue);
6530                 netdev_err(priv->dev, "Failed to init RX desc.\n");
6531                 return;
6532         }
6533
6534         stmmac_reset_rx_queue(priv, queue);
6535         stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue);
6536
6537         stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6538                             rx_q->dma_rx_phy, rx_q->queue_index);
6539
6540         rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num *
6541                              sizeof(struct dma_desc));
6542         stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6543                                rx_q->rx_tail_addr, rx_q->queue_index);
6544
6545         if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6546                 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6547                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6548                                       buf_size,
6549                                       rx_q->queue_index);
6550         } else {
6551                 stmmac_set_dma_bfsize(priv, priv->ioaddr,
6552                                       priv->dma_conf.dma_buf_sz,
6553                                       rx_q->queue_index);
6554         }
6555
6556         stmmac_start_rx_dma(priv, queue);
6557
6558         spin_lock_irqsave(&ch->lock, flags);
6559         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0);
6560         spin_unlock_irqrestore(&ch->lock, flags);
6561 }
6562
6563 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue)
6564 {
6565         struct stmmac_channel *ch = &priv->channel[queue];
6566         unsigned long flags;
6567
6568         spin_lock_irqsave(&ch->lock, flags);
6569         stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6570         spin_unlock_irqrestore(&ch->lock, flags);
6571
6572         stmmac_stop_tx_dma(priv, queue);
6573         __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6574 }
6575
6576 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
6577 {
6578         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
6579         struct stmmac_channel *ch = &priv->channel[queue];
6580         unsigned long flags;
6581         int ret;
6582
6583         ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6584         if (ret) {
6585                 netdev_err(priv->dev, "Failed to alloc TX desc.\n");
6586                 return;
6587         }
6588
6589         ret = __init_dma_tx_desc_rings(priv,  &priv->dma_conf, queue);
6590         if (ret) {
6591                 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue);
6592                 netdev_err(priv->dev, "Failed to init TX desc.\n");
6593                 return;
6594         }
6595
6596         stmmac_reset_tx_queue(priv, queue);
6597         stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue);
6598
6599         stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6600                             tx_q->dma_tx_phy, tx_q->queue_index);
6601
6602         if (tx_q->tbs & STMMAC_TBS_AVAIL)
6603                 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index);
6604
6605         tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6606         stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6607                                tx_q->tx_tail_addr, tx_q->queue_index);
6608
6609         stmmac_start_tx_dma(priv, queue);
6610
6611         spin_lock_irqsave(&ch->lock, flags);
6612         stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1);
6613         spin_unlock_irqrestore(&ch->lock, flags);
6614 }
6615
6616 void stmmac_xdp_release(struct net_device *dev)
6617 {
6618         struct stmmac_priv *priv = netdev_priv(dev);
6619         u32 chan;
6620
6621         /* Ensure tx function is not running */
6622         netif_tx_disable(dev);
6623
6624         /* Disable NAPI process */
6625         stmmac_disable_all_queues(priv);
6626
6627         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6628                 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
6629
6630         /* Free the IRQ lines */
6631         stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0);
6632
6633         /* Stop TX/RX DMA channels */
6634         stmmac_stop_all_dma(priv);
6635
6636         /* Release and free the Rx/Tx resources */
6637         free_dma_desc_resources(priv, &priv->dma_conf);
6638
6639         /* Disable the MAC Rx/Tx */
6640         stmmac_mac_set(priv, priv->ioaddr, false);
6641
6642         /* set trans_start so we don't get spurious
6643          * watchdogs during reset
6644          */
6645         netif_trans_update(dev);
6646         netif_carrier_off(dev);
6647 }
6648
6649 int stmmac_xdp_open(struct net_device *dev)
6650 {
6651         struct stmmac_priv *priv = netdev_priv(dev);
6652         u32 rx_cnt = priv->plat->rx_queues_to_use;
6653         u32 tx_cnt = priv->plat->tx_queues_to_use;
6654         u32 dma_csr_ch = max(rx_cnt, tx_cnt);
6655         struct stmmac_rx_queue *rx_q;
6656         struct stmmac_tx_queue *tx_q;
6657         u32 buf_size;
6658         bool sph_en;
6659         u32 chan;
6660         int ret;
6661
6662         ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
6663         if (ret < 0) {
6664                 netdev_err(dev, "%s: DMA descriptors allocation failed\n",
6665                            __func__);
6666                 goto dma_desc_error;
6667         }
6668
6669         ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL);
6670         if (ret < 0) {
6671                 netdev_err(dev, "%s: DMA descriptors initialization failed\n",
6672                            __func__);
6673                 goto init_error;
6674         }
6675
6676         stmmac_reset_queues_param(priv);
6677
6678         /* DMA CSR Channel configuration */
6679         for (chan = 0; chan < dma_csr_ch; chan++) {
6680                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
6681                 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1);
6682         }
6683
6684         /* Adjust Split header */
6685         sph_en = (priv->hw->rx_csum > 0) && priv->sph;
6686
6687         /* DMA RX Channel Configuration */
6688         for (chan = 0; chan < rx_cnt; chan++) {
6689                 rx_q = &priv->dma_conf.rx_queue[chan];
6690
6691                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6692                                     rx_q->dma_rx_phy, chan);
6693
6694                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
6695                                      (rx_q->buf_alloc_num *
6696                                       sizeof(struct dma_desc));
6697                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
6698                                        rx_q->rx_tail_addr, chan);
6699
6700                 if (rx_q->xsk_pool && rx_q->buf_alloc_num) {
6701                         buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool);
6702                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6703                                               buf_size,
6704                                               rx_q->queue_index);
6705                 } else {
6706                         stmmac_set_dma_bfsize(priv, priv->ioaddr,
6707                                               priv->dma_conf.dma_buf_sz,
6708                                               rx_q->queue_index);
6709                 }
6710
6711                 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
6712         }
6713
6714         /* DMA TX Channel Configuration */
6715         for (chan = 0; chan < tx_cnt; chan++) {
6716                 tx_q = &priv->dma_conf.tx_queue[chan];
6717
6718                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
6719                                     tx_q->dma_tx_phy, chan);
6720
6721                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
6722                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
6723                                        tx_q->tx_tail_addr, chan);
6724
6725                 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
6726                 tx_q->txtimer.function = stmmac_tx_timer;
6727         }
6728
6729         /* Enable the MAC Rx/Tx */
6730         stmmac_mac_set(priv, priv->ioaddr, true);
6731
6732         /* Start Rx & Tx DMA Channels */
6733         stmmac_start_all_dma(priv);
6734
6735         ret = stmmac_request_irq(dev);
6736         if (ret)
6737                 goto irq_error;
6738
6739         /* Enable NAPI process*/
6740         stmmac_enable_all_queues(priv);
6741         netif_carrier_on(dev);
6742         netif_tx_start_all_queues(dev);
6743         stmmac_enable_all_dma_irq(priv);
6744
6745         return 0;
6746
6747 irq_error:
6748         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
6749                 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
6750
6751         stmmac_hw_teardown(dev);
6752 init_error:
6753         free_dma_desc_resources(priv, &priv->dma_conf);
6754 dma_desc_error:
6755         return ret;
6756 }
6757
6758 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
6759 {
6760         struct stmmac_priv *priv = netdev_priv(dev);
6761         struct stmmac_rx_queue *rx_q;
6762         struct stmmac_tx_queue *tx_q;
6763         struct stmmac_channel *ch;
6764
6765         if (test_bit(STMMAC_DOWN, &priv->state) ||
6766             !netif_carrier_ok(priv->dev))
6767                 return -ENETDOWN;
6768
6769         if (!stmmac_xdp_is_enabled(priv))
6770                 return -EINVAL;
6771
6772         if (queue >= priv->plat->rx_queues_to_use ||
6773             queue >= priv->plat->tx_queues_to_use)
6774                 return -EINVAL;
6775
6776         rx_q = &priv->dma_conf.rx_queue[queue];
6777         tx_q = &priv->dma_conf.tx_queue[queue];
6778         ch = &priv->channel[queue];
6779
6780         if (!rx_q->xsk_pool && !tx_q->xsk_pool)
6781                 return -EINVAL;
6782
6783         if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) {
6784                 /* EQoS does not have per-DMA channel SW interrupt,
6785                  * so we schedule RX Napi straight-away.
6786                  */
6787                 if (likely(napi_schedule_prep(&ch->rxtx_napi)))
6788                         __napi_schedule(&ch->rxtx_napi);
6789         }
6790
6791         return 0;
6792 }
6793
6794 static const struct net_device_ops stmmac_netdev_ops = {
6795         .ndo_open = stmmac_open,
6796         .ndo_start_xmit = stmmac_xmit,
6797         .ndo_stop = stmmac_release,
6798         .ndo_change_mtu = stmmac_change_mtu,
6799         .ndo_fix_features = stmmac_fix_features,
6800         .ndo_set_features = stmmac_set_features,
6801         .ndo_set_rx_mode = stmmac_set_rx_mode,
6802         .ndo_tx_timeout = stmmac_tx_timeout,
6803         .ndo_eth_ioctl = stmmac_ioctl,
6804         .ndo_setup_tc = stmmac_setup_tc,
6805         .ndo_select_queue = stmmac_select_queue,
6806 #ifdef CONFIG_NET_POLL_CONTROLLER
6807         .ndo_poll_controller = stmmac_poll_controller,
6808 #endif
6809         .ndo_set_mac_address = stmmac_set_mac_address,
6810         .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
6811         .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
6812         .ndo_bpf = stmmac_bpf,
6813         .ndo_xdp_xmit = stmmac_xdp_xmit,
6814         .ndo_xsk_wakeup = stmmac_xsk_wakeup,
6815 };
6816
6817 static void stmmac_reset_subtask(struct stmmac_priv *priv)
6818 {
6819         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
6820                 return;
6821         if (test_bit(STMMAC_DOWN, &priv->state))
6822                 return;
6823
6824         netdev_err(priv->dev, "Reset adapter.\n");
6825
6826         rtnl_lock();
6827         netif_trans_update(priv->dev);
6828         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
6829                 usleep_range(1000, 2000);
6830
6831         set_bit(STMMAC_DOWN, &priv->state);
6832         dev_close(priv->dev);
6833         dev_open(priv->dev, NULL);
6834         clear_bit(STMMAC_DOWN, &priv->state);
6835         clear_bit(STMMAC_RESETING, &priv->state);
6836         rtnl_unlock();
6837 }
6838
6839 static void stmmac_service_task(struct work_struct *work)
6840 {
6841         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
6842                         service_task);
6843
6844         stmmac_reset_subtask(priv);
6845         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
6846 }
6847
6848 /**
6849  *  stmmac_hw_init - Init the MAC device
6850  *  @priv: driver private structure
6851  *  Description: this function is to configure the MAC device according to
6852  *  some platform parameters or the HW capability register. It prepares the
6853  *  driver to use either ring or chain modes and to setup either enhanced or
6854  *  normal descriptors.
6855  */
6856 static int stmmac_hw_init(struct stmmac_priv *priv)
6857 {
6858         int ret;
6859
6860         /* dwmac-sun8i only work in chain mode */
6861         if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I)
6862                 chain_mode = 1;
6863         priv->chain_mode = chain_mode;
6864
6865         /* Initialize HW Interface */
6866         ret = stmmac_hwif_init(priv);
6867         if (ret)
6868                 return ret;
6869
6870         /* Get the HW capability (new GMAC newer than 3.50a) */
6871         priv->hw_cap_support = stmmac_get_hw_features(priv);
6872         if (priv->hw_cap_support) {
6873                 dev_info(priv->device, "DMA HW capability register supported\n");
6874
6875                 /* We can override some gmac/dma configuration fields: e.g.
6876                  * enh_desc, tx_coe (e.g. that are passed through the
6877                  * platform) with the values from the HW capability
6878                  * register (if supported).
6879                  */
6880                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
6881                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up &&
6882                                 !(priv->plat->flags & STMMAC_FLAG_USE_PHY_WOL);
6883                 priv->hw->pmt = priv->plat->pmt;
6884                 if (priv->dma_cap.hash_tb_sz) {
6885                         priv->hw->multicast_filter_bins =
6886                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
6887                         priv->hw->mcast_bits_log2 =
6888                                         ilog2(priv->hw->multicast_filter_bins);
6889                 }
6890
6891                 /* TXCOE doesn't work in thresh DMA mode */
6892                 if (priv->plat->force_thresh_dma_mode)
6893                         priv->plat->tx_coe = 0;
6894                 else
6895                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
6896
6897                 /* In case of GMAC4 rx_coe is from HW cap register. */
6898                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
6899
6900                 if (priv->dma_cap.rx_coe_type2)
6901                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
6902                 else if (priv->dma_cap.rx_coe_type1)
6903                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
6904
6905         } else {
6906                 dev_info(priv->device, "No HW DMA feature register supported\n");
6907         }
6908
6909         if (priv->plat->rx_coe) {
6910                 priv->hw->rx_csum = priv->plat->rx_coe;
6911                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
6912                 if (priv->synopsys_id < DWMAC_CORE_4_00)
6913                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
6914         }
6915         if (priv->plat->tx_coe)
6916                 dev_info(priv->device, "TX Checksum insertion supported\n");
6917
6918         if (priv->plat->pmt) {
6919                 dev_info(priv->device, "Wake-Up On Lan supported\n");
6920                 device_set_wakeup_capable(priv->device, 1);
6921         }
6922
6923         if (priv->dma_cap.tsoen)
6924                 dev_info(priv->device, "TSO supported\n");
6925
6926         priv->hw->vlan_fail_q_en =
6927                 (priv->plat->flags & STMMAC_FLAG_VLAN_FAIL_Q_EN);
6928         priv->hw->vlan_fail_q = priv->plat->vlan_fail_q;
6929
6930         /* Run HW quirks, if any */
6931         if (priv->hwif_quirks) {
6932                 ret = priv->hwif_quirks(priv);
6933                 if (ret)
6934                         return ret;
6935         }
6936
6937         /* Rx Watchdog is available in the COREs newer than the 3.40.
6938          * In some case, for example on bugged HW this feature
6939          * has to be disable and this can be done by passing the
6940          * riwt_off field from the platform.
6941          */
6942         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
6943             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
6944                 priv->use_riwt = 1;
6945                 dev_info(priv->device,
6946                          "Enable RX Mitigation via HW Watchdog Timer\n");
6947         }
6948
6949         return 0;
6950 }
6951
6952 static void stmmac_napi_add(struct net_device *dev)
6953 {
6954         struct stmmac_priv *priv = netdev_priv(dev);
6955         u32 queue, maxq;
6956
6957         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6958
6959         for (queue = 0; queue < maxq; queue++) {
6960                 struct stmmac_channel *ch = &priv->channel[queue];
6961
6962                 ch->priv_data = priv;
6963                 ch->index = queue;
6964                 spin_lock_init(&ch->lock);
6965
6966                 if (queue < priv->plat->rx_queues_to_use) {
6967                         netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx);
6968                 }
6969                 if (queue < priv->plat->tx_queues_to_use) {
6970                         netif_napi_add_tx(dev, &ch->tx_napi,
6971                                           stmmac_napi_poll_tx);
6972                 }
6973                 if (queue < priv->plat->rx_queues_to_use &&
6974                     queue < priv->plat->tx_queues_to_use) {
6975                         netif_napi_add(dev, &ch->rxtx_napi,
6976                                        stmmac_napi_poll_rxtx);
6977                 }
6978         }
6979 }
6980
6981 static void stmmac_napi_del(struct net_device *dev)
6982 {
6983         struct stmmac_priv *priv = netdev_priv(dev);
6984         u32 queue, maxq;
6985
6986         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
6987
6988         for (queue = 0; queue < maxq; queue++) {
6989                 struct stmmac_channel *ch = &priv->channel[queue];
6990
6991                 if (queue < priv->plat->rx_queues_to_use)
6992                         netif_napi_del(&ch->rx_napi);
6993                 if (queue < priv->plat->tx_queues_to_use)
6994                         netif_napi_del(&ch->tx_napi);
6995                 if (queue < priv->plat->rx_queues_to_use &&
6996                     queue < priv->plat->tx_queues_to_use) {
6997                         netif_napi_del(&ch->rxtx_napi);
6998                 }
6999         }
7000 }
7001
7002 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
7003 {
7004         struct stmmac_priv *priv = netdev_priv(dev);
7005         int ret = 0, i;
7006
7007         if (netif_running(dev))
7008                 stmmac_release(dev);
7009
7010         stmmac_napi_del(dev);
7011
7012         priv->plat->rx_queues_to_use = rx_cnt;
7013         priv->plat->tx_queues_to_use = tx_cnt;
7014         if (!netif_is_rxfh_configured(dev))
7015                 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7016                         priv->rss.table[i] = ethtool_rxfh_indir_default(i,
7017                                                                         rx_cnt);
7018
7019         stmmac_napi_add(dev);
7020
7021         if (netif_running(dev))
7022                 ret = stmmac_open(dev);
7023
7024         return ret;
7025 }
7026
7027 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
7028 {
7029         struct stmmac_priv *priv = netdev_priv(dev);
7030         int ret = 0;
7031
7032         if (netif_running(dev))
7033                 stmmac_release(dev);
7034
7035         priv->dma_conf.dma_rx_size = rx_size;
7036         priv->dma_conf.dma_tx_size = tx_size;
7037
7038         if (netif_running(dev))
7039                 ret = stmmac_open(dev);
7040
7041         return ret;
7042 }
7043
7044 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n"
7045 static void stmmac_fpe_lp_task(struct work_struct *work)
7046 {
7047         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
7048                                                 fpe_task);
7049         struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg;
7050         enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state;
7051         enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state;
7052         bool *hs_enable = &fpe_cfg->hs_enable;
7053         bool *enable = &fpe_cfg->enable;
7054         int retries = 20;
7055
7056         while (retries-- > 0) {
7057                 /* Bail out immediately if FPE handshake is OFF */
7058                 if (*lo_state == FPE_STATE_OFF || !*hs_enable)
7059                         break;
7060
7061                 if (*lo_state == FPE_STATE_ENTERING_ON &&
7062                     *lp_state == FPE_STATE_ENTERING_ON) {
7063                         stmmac_fpe_configure(priv, priv->ioaddr,
7064                                              priv->plat->tx_queues_to_use,
7065                                              priv->plat->rx_queues_to_use,
7066                                              *enable);
7067
7068                         netdev_info(priv->dev, "configured FPE\n");
7069
7070                         *lo_state = FPE_STATE_ON;
7071                         *lp_state = FPE_STATE_ON;
7072                         netdev_info(priv->dev, "!!! BOTH FPE stations ON\n");
7073                         break;
7074                 }
7075
7076                 if ((*lo_state == FPE_STATE_CAPABLE ||
7077                      *lo_state == FPE_STATE_ENTERING_ON) &&
7078                      *lp_state != FPE_STATE_ON) {
7079                         netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT,
7080                                     *lo_state, *lp_state);
7081                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7082                                                 MPACKET_VERIFY);
7083                 }
7084                 /* Sleep then retry */
7085                 msleep(500);
7086         }
7087
7088         clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state);
7089 }
7090
7091 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable)
7092 {
7093         if (priv->plat->fpe_cfg->hs_enable != enable) {
7094                 if (enable) {
7095                         stmmac_fpe_send_mpacket(priv, priv->ioaddr,
7096                                                 MPACKET_VERIFY);
7097                 } else {
7098                         priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF;
7099                         priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF;
7100                 }
7101
7102                 priv->plat->fpe_cfg->hs_enable = enable;
7103         }
7104 }
7105
7106 static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp)
7107 {
7108         const struct stmmac_xdp_buff *ctx = (void *)_ctx;
7109         struct dma_desc *desc_contains_ts = ctx->desc;
7110         struct stmmac_priv *priv = ctx->priv;
7111         struct dma_desc *ndesc = ctx->ndesc;
7112         struct dma_desc *desc = ctx->desc;
7113         u64 ns = 0;
7114
7115         if (!priv->hwts_rx_en)
7116                 return -ENODATA;
7117
7118         /* For GMAC4, the valid timestamp is from CTX next desc. */
7119         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
7120                 desc_contains_ts = ndesc;
7121
7122         /* Check if timestamp is available */
7123         if (stmmac_get_rx_timestamp_status(priv, desc, ndesc, priv->adv_ts)) {
7124                 stmmac_get_timestamp(priv, desc_contains_ts, priv->adv_ts, &ns);
7125                 ns -= priv->plat->cdc_error_adj;
7126                 *timestamp = ns_to_ktime(ns);
7127                 return 0;
7128         }
7129
7130         return -ENODATA;
7131 }
7132
7133 static const struct xdp_metadata_ops stmmac_xdp_metadata_ops = {
7134         .xmo_rx_timestamp               = stmmac_xdp_rx_timestamp,
7135 };
7136
7137 /**
7138  * stmmac_dvr_probe
7139  * @device: device pointer
7140  * @plat_dat: platform data pointer
7141  * @res: stmmac resource pointer
7142  * Description: this is the main probe function used to
7143  * call the alloc_etherdev, allocate the priv structure.
7144  * Return:
7145  * returns 0 on success, otherwise errno.
7146  */
7147 int stmmac_dvr_probe(struct device *device,
7148                      struct plat_stmmacenet_data *plat_dat,
7149                      struct stmmac_resources *res)
7150 {
7151         struct net_device *ndev = NULL;
7152         struct stmmac_priv *priv;
7153         u32 rxq;
7154         int i, ret = 0;
7155
7156         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
7157                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
7158         if (!ndev)
7159                 return -ENOMEM;
7160
7161         SET_NETDEV_DEV(ndev, device);
7162
7163         priv = netdev_priv(ndev);
7164         priv->device = device;
7165         priv->dev = ndev;
7166
7167         stmmac_set_ethtool_ops(ndev);
7168         priv->pause = pause;
7169         priv->plat = plat_dat;
7170         priv->ioaddr = res->addr;
7171         priv->dev->base_addr = (unsigned long)res->addr;
7172         priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
7173
7174         priv->dev->irq = res->irq;
7175         priv->wol_irq = res->wol_irq;
7176         priv->lpi_irq = res->lpi_irq;
7177         priv->sfty_ce_irq = res->sfty_ce_irq;
7178         priv->sfty_ue_irq = res->sfty_ue_irq;
7179         for (i = 0; i < MTL_MAX_RX_QUEUES; i++)
7180                 priv->rx_irq[i] = res->rx_irq[i];
7181         for (i = 0; i < MTL_MAX_TX_QUEUES; i++)
7182                 priv->tx_irq[i] = res->tx_irq[i];
7183
7184         if (!is_zero_ether_addr(res->mac))
7185                 eth_hw_addr_set(priv->dev, res->mac);
7186
7187         dev_set_drvdata(device, priv->dev);
7188
7189         /* Verify driver arguments */
7190         stmmac_verify_args();
7191
7192         priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL);
7193         if (!priv->af_xdp_zc_qps)
7194                 return -ENOMEM;
7195
7196         /* Allocate workqueue */
7197         priv->wq = create_singlethread_workqueue("stmmac_wq");
7198         if (!priv->wq) {
7199                 dev_err(priv->device, "failed to create workqueue\n");
7200                 ret = -ENOMEM;
7201                 goto error_wq_init;
7202         }
7203
7204         INIT_WORK(&priv->service_task, stmmac_service_task);
7205
7206         /* Initialize Link Partner FPE workqueue */
7207         INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task);
7208
7209         /* Override with kernel parameters if supplied XXX CRS XXX
7210          * this needs to have multiple instances
7211          */
7212         if ((phyaddr >= 0) && (phyaddr <= 31))
7213                 priv->plat->phy_addr = phyaddr;
7214
7215         if (priv->plat->stmmac_rst) {
7216                 ret = reset_control_assert(priv->plat->stmmac_rst);
7217                 reset_control_deassert(priv->plat->stmmac_rst);
7218                 /* Some reset controllers have only reset callback instead of
7219                  * assert + deassert callbacks pair.
7220                  */
7221                 if (ret == -ENOTSUPP)
7222                         reset_control_reset(priv->plat->stmmac_rst);
7223         }
7224
7225         ret = reset_control_deassert(priv->plat->stmmac_ahb_rst);
7226         if (ret == -ENOTSUPP)
7227                 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n",
7228                         ERR_PTR(ret));
7229
7230         /* Init MAC and get the capabilities */
7231         ret = stmmac_hw_init(priv);
7232         if (ret)
7233                 goto error_hw_init;
7234
7235         /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch.
7236          */
7237         if (priv->synopsys_id < DWMAC_CORE_5_20)
7238                 priv->plat->dma_cfg->dche = false;
7239
7240         stmmac_check_ether_addr(priv);
7241
7242         ndev->netdev_ops = &stmmac_netdev_ops;
7243
7244         ndev->xdp_metadata_ops = &stmmac_xdp_metadata_ops;
7245
7246         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
7247                             NETIF_F_RXCSUM;
7248         ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
7249                              NETDEV_XDP_ACT_XSK_ZEROCOPY;
7250
7251         ret = stmmac_tc_init(priv, priv);
7252         if (!ret) {
7253                 ndev->hw_features |= NETIF_F_HW_TC;
7254         }
7255
7256         if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) {
7257                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
7258                 if (priv->plat->has_gmac4)
7259                         ndev->hw_features |= NETIF_F_GSO_UDP_L4;
7260                 priv->tso = true;
7261                 dev_info(priv->device, "TSO feature enabled\n");
7262         }
7263
7264         if (priv->dma_cap.sphen &&
7265             !(priv->plat->flags & STMMAC_FLAG_SPH_DISABLE)) {
7266                 ndev->hw_features |= NETIF_F_GRO;
7267                 priv->sph_cap = true;
7268                 priv->sph = priv->sph_cap;
7269                 dev_info(priv->device, "SPH feature enabled\n");
7270         }
7271
7272         /* Ideally our host DMA address width is the same as for the
7273          * device. However, it may differ and then we have to use our
7274          * host DMA width for allocation and the device DMA width for
7275          * register handling.
7276          */
7277         if (priv->plat->host_dma_width)
7278                 priv->dma_cap.host_dma_width = priv->plat->host_dma_width;
7279         else
7280                 priv->dma_cap.host_dma_width = priv->dma_cap.addr64;
7281
7282         if (priv->dma_cap.host_dma_width) {
7283                 ret = dma_set_mask_and_coherent(device,
7284                                 DMA_BIT_MASK(priv->dma_cap.host_dma_width));
7285                 if (!ret) {
7286                         dev_info(priv->device, "Using %d/%d bits DMA host/device width\n",
7287                                  priv->dma_cap.host_dma_width, priv->dma_cap.addr64);
7288
7289                         /*
7290                          * If more than 32 bits can be addressed, make sure to
7291                          * enable enhanced addressing mode.
7292                          */
7293                         if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
7294                                 priv->plat->dma_cfg->eame = true;
7295                 } else {
7296                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
7297                         if (ret) {
7298                                 dev_err(priv->device, "Failed to set DMA Mask\n");
7299                                 goto error_hw_init;
7300                         }
7301
7302                         priv->dma_cap.host_dma_width = 32;
7303                 }
7304         }
7305
7306         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
7307         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
7308 #ifdef STMMAC_VLAN_TAG_USED
7309         /* Both mac100 and gmac support receive VLAN tag detection */
7310         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
7311         if (priv->dma_cap.vlhash) {
7312                 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7313                 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
7314         }
7315         if (priv->dma_cap.vlins) {
7316                 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
7317                 if (priv->dma_cap.dvlan)
7318                         ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
7319         }
7320 #endif
7321         priv->msg_enable = netif_msg_init(debug, default_msg_level);
7322
7323         /* Initialize RSS */
7324         rxq = priv->plat->rx_queues_to_use;
7325         netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
7326         for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
7327                 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
7328
7329         if (priv->dma_cap.rssen && priv->plat->rss_en)
7330                 ndev->features |= NETIF_F_RXHASH;
7331
7332         ndev->vlan_features |= ndev->features;
7333         /* TSO doesn't work on VLANs yet */
7334         ndev->vlan_features &= ~NETIF_F_TSO;
7335
7336         /* MTU range: 46 - hw-specific max */
7337         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
7338         if (priv->plat->has_xgmac)
7339                 ndev->max_mtu = XGMAC_JUMBO_LEN;
7340         else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
7341                 ndev->max_mtu = JUMBO_LEN;
7342         else
7343                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
7344         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
7345          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
7346          */
7347         if ((priv->plat->maxmtu < ndev->max_mtu) &&
7348             (priv->plat->maxmtu >= ndev->min_mtu))
7349                 ndev->max_mtu = priv->plat->maxmtu;
7350         else if (priv->plat->maxmtu < ndev->min_mtu)
7351                 dev_warn(priv->device,
7352                          "%s: warning: maxmtu having invalid value (%d)\n",
7353                          __func__, priv->plat->maxmtu);
7354
7355         if (flow_ctrl)
7356                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
7357
7358         ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7359
7360         /* Setup channels NAPI */
7361         stmmac_napi_add(ndev);
7362
7363         mutex_init(&priv->lock);
7364
7365         /* If a specific clk_csr value is passed from the platform
7366          * this means that the CSR Clock Range selection cannot be
7367          * changed at run-time and it is fixed. Viceversa the driver'll try to
7368          * set the MDC clock dynamically according to the csr actual
7369          * clock input.
7370          */
7371         if (priv->plat->clk_csr >= 0)
7372                 priv->clk_csr = priv->plat->clk_csr;
7373         else
7374                 stmmac_clk_csr_set(priv);
7375
7376         stmmac_check_pcs_mode(priv);
7377
7378         pm_runtime_get_noresume(device);
7379         pm_runtime_set_active(device);
7380         if (!pm_runtime_enabled(device))
7381                 pm_runtime_enable(device);
7382
7383         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7384             priv->hw->pcs != STMMAC_PCS_RTBI) {
7385                 /* MDIO bus Registration */
7386                 ret = stmmac_mdio_register(ndev);
7387                 if (ret < 0) {
7388                         dev_err_probe(priv->device, ret,
7389                                       "%s: MDIO bus (id: %d) registration failed\n",
7390                                       __func__, priv->plat->bus_id);
7391                         goto error_mdio_register;
7392                 }
7393         }
7394
7395         if (priv->plat->speed_mode_2500)
7396                 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
7397
7398         if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) {
7399                 ret = stmmac_xpcs_setup(priv->mii);
7400                 if (ret)
7401                         goto error_xpcs_setup;
7402         }
7403
7404         ret = stmmac_phy_setup(priv);
7405         if (ret) {
7406                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
7407                 goto error_phy_setup;
7408         }
7409
7410         ret = register_netdev(ndev);
7411         if (ret) {
7412                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
7413                         __func__, ret);
7414                 goto error_netdev_register;
7415         }
7416
7417 #ifdef CONFIG_DEBUG_FS
7418         stmmac_init_fs(ndev);
7419 #endif
7420
7421         if (priv->plat->dump_debug_regs)
7422                 priv->plat->dump_debug_regs(priv->plat->bsp_priv);
7423
7424         /* Let pm_runtime_put() disable the clocks.
7425          * If CONFIG_PM is not enabled, the clocks will stay powered.
7426          */
7427         pm_runtime_put(device);
7428
7429         return ret;
7430
7431 error_netdev_register:
7432         phylink_destroy(priv->phylink);
7433 error_xpcs_setup:
7434 error_phy_setup:
7435         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7436             priv->hw->pcs != STMMAC_PCS_RTBI)
7437                 stmmac_mdio_unregister(ndev);
7438 error_mdio_register:
7439         stmmac_napi_del(ndev);
7440 error_hw_init:
7441         destroy_workqueue(priv->wq);
7442 error_wq_init:
7443         bitmap_free(priv->af_xdp_zc_qps);
7444
7445         return ret;
7446 }
7447 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
7448
7449 /**
7450  * stmmac_dvr_remove
7451  * @dev: device pointer
7452  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
7453  * changes the link status, releases the DMA descriptor rings.
7454  */
7455 void stmmac_dvr_remove(struct device *dev)
7456 {
7457         struct net_device *ndev = dev_get_drvdata(dev);
7458         struct stmmac_priv *priv = netdev_priv(ndev);
7459
7460         netdev_info(priv->dev, "%s: removing driver", __func__);
7461
7462         pm_runtime_get_sync(dev);
7463
7464         stmmac_stop_all_dma(priv);
7465         stmmac_mac_set(priv, priv->ioaddr, false);
7466         netif_carrier_off(ndev);
7467         unregister_netdev(ndev);
7468
7469 #ifdef CONFIG_DEBUG_FS
7470         stmmac_exit_fs(ndev);
7471 #endif
7472         phylink_destroy(priv->phylink);
7473         if (priv->plat->stmmac_rst)
7474                 reset_control_assert(priv->plat->stmmac_rst);
7475         reset_control_assert(priv->plat->stmmac_ahb_rst);
7476         if (priv->hw->pcs != STMMAC_PCS_TBI &&
7477             priv->hw->pcs != STMMAC_PCS_RTBI)
7478                 stmmac_mdio_unregister(ndev);
7479         destroy_workqueue(priv->wq);
7480         mutex_destroy(&priv->lock);
7481         bitmap_free(priv->af_xdp_zc_qps);
7482
7483         pm_runtime_disable(dev);
7484         pm_runtime_put_noidle(dev);
7485 }
7486 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
7487
7488 /**
7489  * stmmac_suspend - suspend callback
7490  * @dev: device pointer
7491  * Description: this is the function to suspend the device and it is called
7492  * by the platform driver to stop the network queue, release the resources,
7493  * program the PMT register (for WoL), clean and release driver resources.
7494  */
7495 int stmmac_suspend(struct device *dev)
7496 {
7497         struct net_device *ndev = dev_get_drvdata(dev);
7498         struct stmmac_priv *priv = netdev_priv(ndev);
7499         u32 chan;
7500
7501         if (!ndev || !netif_running(ndev))
7502                 return 0;
7503
7504         mutex_lock(&priv->lock);
7505
7506         netif_device_detach(ndev);
7507
7508         stmmac_disable_all_queues(priv);
7509
7510         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
7511                 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer);
7512
7513         if (priv->eee_enabled) {
7514                 priv->tx_path_in_lpi_mode = false;
7515                 del_timer_sync(&priv->eee_ctrl_timer);
7516         }
7517
7518         /* Stop TX/RX DMA */
7519         stmmac_stop_all_dma(priv);
7520
7521         if (priv->plat->serdes_powerdown)
7522                 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv);
7523
7524         /* Enable Power down mode by programming the PMT regs */
7525         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7526                 stmmac_pmt(priv, priv->hw, priv->wolopts);
7527                 priv->irq_wake = 1;
7528         } else {
7529                 stmmac_mac_set(priv, priv->ioaddr, false);
7530                 pinctrl_pm_select_sleep_state(priv->device);
7531         }
7532
7533         mutex_unlock(&priv->lock);
7534
7535         rtnl_lock();
7536         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7537                 phylink_suspend(priv->phylink, true);
7538         } else {
7539                 if (device_may_wakeup(priv->device))
7540                         phylink_speed_down(priv->phylink, false);
7541                 phylink_suspend(priv->phylink, false);
7542         }
7543         rtnl_unlock();
7544
7545         if (priv->dma_cap.fpesel) {
7546                 /* Disable FPE */
7547                 stmmac_fpe_configure(priv, priv->ioaddr,
7548                                      priv->plat->tx_queues_to_use,
7549                                      priv->plat->rx_queues_to_use, false);
7550
7551                 stmmac_fpe_handshake(priv, false);
7552                 stmmac_fpe_stop_wq(priv);
7553         }
7554
7555         priv->speed = SPEED_UNKNOWN;
7556         return 0;
7557 }
7558 EXPORT_SYMBOL_GPL(stmmac_suspend);
7559
7560 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
7561 {
7562         struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
7563
7564         rx_q->cur_rx = 0;
7565         rx_q->dirty_rx = 0;
7566 }
7567
7568 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
7569 {
7570         struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
7571
7572         tx_q->cur_tx = 0;
7573         tx_q->dirty_tx = 0;
7574         tx_q->mss = 0;
7575
7576         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
7577 }
7578
7579 /**
7580  * stmmac_reset_queues_param - reset queue parameters
7581  * @priv: device pointer
7582  */
7583 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
7584 {
7585         u32 rx_cnt = priv->plat->rx_queues_to_use;
7586         u32 tx_cnt = priv->plat->tx_queues_to_use;
7587         u32 queue;
7588
7589         for (queue = 0; queue < rx_cnt; queue++)
7590                 stmmac_reset_rx_queue(priv, queue);
7591
7592         for (queue = 0; queue < tx_cnt; queue++)
7593                 stmmac_reset_tx_queue(priv, queue);
7594 }
7595
7596 /**
7597  * stmmac_resume - resume callback
7598  * @dev: device pointer
7599  * Description: when resume this function is invoked to setup the DMA and CORE
7600  * in a usable state.
7601  */
7602 int stmmac_resume(struct device *dev)
7603 {
7604         struct net_device *ndev = dev_get_drvdata(dev);
7605         struct stmmac_priv *priv = netdev_priv(ndev);
7606         int ret;
7607
7608         if (!netif_running(ndev))
7609                 return 0;
7610
7611         /* Power Down bit, into the PM register, is cleared
7612          * automatically as soon as a magic packet or a Wake-up frame
7613          * is received. Anyway, it's better to manually clear
7614          * this bit because it can generate problems while resuming
7615          * from another devices (e.g. serial console).
7616          */
7617         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7618                 mutex_lock(&priv->lock);
7619                 stmmac_pmt(priv, priv->hw, 0);
7620                 mutex_unlock(&priv->lock);
7621                 priv->irq_wake = 0;
7622         } else {
7623                 pinctrl_pm_select_default_state(priv->device);
7624                 /* reset the phy so that it's ready */
7625                 if (priv->mii)
7626                         stmmac_mdio_reset(priv->mii);
7627         }
7628
7629         if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) &&
7630             priv->plat->serdes_powerup) {
7631                 ret = priv->plat->serdes_powerup(ndev,
7632                                                  priv->plat->bsp_priv);
7633
7634                 if (ret < 0)
7635                         return ret;
7636         }
7637
7638         rtnl_lock();
7639         if (device_may_wakeup(priv->device) && priv->plat->pmt) {
7640                 phylink_resume(priv->phylink);
7641         } else {
7642                 phylink_resume(priv->phylink);
7643                 if (device_may_wakeup(priv->device))
7644                         phylink_speed_up(priv->phylink);
7645         }
7646         rtnl_unlock();
7647
7648         rtnl_lock();
7649         mutex_lock(&priv->lock);
7650
7651         stmmac_reset_queues_param(priv);
7652
7653         stmmac_free_tx_skbufs(priv);
7654         stmmac_clear_descriptors(priv, &priv->dma_conf);
7655
7656         stmmac_hw_setup(ndev, false);
7657         stmmac_init_coalesce(priv);
7658         stmmac_set_rx_mode(ndev);
7659
7660         stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
7661
7662         stmmac_enable_all_queues(priv);
7663         stmmac_enable_all_dma_irq(priv);
7664
7665         mutex_unlock(&priv->lock);
7666         rtnl_unlock();
7667
7668         netif_device_attach(ndev);
7669
7670         return 0;
7671 }
7672 EXPORT_SYMBOL_GPL(stmmac_resume);
7673
7674 #ifndef MODULE
7675 static int __init stmmac_cmdline_opt(char *str)
7676 {
7677         char *opt;
7678
7679         if (!str || !*str)
7680                 return 1;
7681         while ((opt = strsep(&str, ",")) != NULL) {
7682                 if (!strncmp(opt, "debug:", 6)) {
7683                         if (kstrtoint(opt + 6, 0, &debug))
7684                                 goto err;
7685                 } else if (!strncmp(opt, "phyaddr:", 8)) {
7686                         if (kstrtoint(opt + 8, 0, &phyaddr))
7687                                 goto err;
7688                 } else if (!strncmp(opt, "buf_sz:", 7)) {
7689                         if (kstrtoint(opt + 7, 0, &buf_sz))
7690                                 goto err;
7691                 } else if (!strncmp(opt, "tc:", 3)) {
7692                         if (kstrtoint(opt + 3, 0, &tc))
7693                                 goto err;
7694                 } else if (!strncmp(opt, "watchdog:", 9)) {
7695                         if (kstrtoint(opt + 9, 0, &watchdog))
7696                                 goto err;
7697                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
7698                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
7699                                 goto err;
7700                 } else if (!strncmp(opt, "pause:", 6)) {
7701                         if (kstrtoint(opt + 6, 0, &pause))
7702                                 goto err;
7703                 } else if (!strncmp(opt, "eee_timer:", 10)) {
7704                         if (kstrtoint(opt + 10, 0, &eee_timer))
7705                                 goto err;
7706                 } else if (!strncmp(opt, "chain_mode:", 11)) {
7707                         if (kstrtoint(opt + 11, 0, &chain_mode))
7708                                 goto err;
7709                 }
7710         }
7711         return 1;
7712
7713 err:
7714         pr_err("%s: ERROR broken module parameter conversion", __func__);
7715         return 1;
7716 }
7717
7718 __setup("stmmaceth=", stmmac_cmdline_opt);
7719 #endif /* MODULE */
7720
7721 static int __init stmmac_init(void)
7722 {
7723 #ifdef CONFIG_DEBUG_FS
7724         /* Create debugfs main directory if it doesn't exist yet */
7725         if (!stmmac_fs_dir)
7726                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
7727         register_netdevice_notifier(&stmmac_notifier);
7728 #endif
7729
7730         return 0;
7731 }
7732
7733 static void __exit stmmac_exit(void)
7734 {
7735 #ifdef CONFIG_DEBUG_FS
7736         unregister_netdevice_notifier(&stmmac_notifier);
7737         debugfs_remove_recursive(stmmac_fs_dir);
7738 #endif
7739 }
7740
7741 module_init(stmmac_init)
7742 module_exit(stmmac_exit)
7743
7744 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
7745 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
7746 MODULE_LICENSE("GPL");