drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55 #include <linux/of_mdio.h>
  56 #include "dwmac1000.h"
  57
  58 #define STMMAC_ALIGN(x)         ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16)
  59 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  60
  61 /* Module parameters */
  62 #define TX_TIMEO        5000
  63 static int watchdog = TX_TIMEO;
  64 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  65 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  66
  67 static int debug = -1;
  68 module_param(debug, int, S_IRUGO | S_IWUSR);
  69 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  70
  71 static int phyaddr = -1;
  72 module_param(phyaddr, int, S_IRUGO);
  73 MODULE_PARM_DESC(phyaddr, "Physical device address");
  74
  75 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  76 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  77
  78 static int flow_ctrl = FLOW_OFF;
  79 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  81
  82 static int pause = PAUSE_TIME;
  83 module_param(pause, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  85
  86 #define TC_DEFAULT 64
  87 static int tc = TC_DEFAULT;
  88 module_param(tc, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(tc, "DMA threshold control value");
  90
  91 #define DEFAULT_BUFSIZE 1536
  92 static int buf_sz = DEFAULT_BUFSIZE;
  93 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  94 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  95
  96 #define STMMAC_RX_COPYBREAK     256
  97
  98 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  99                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 100                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 101
 102 #define STMMAC_DEFAULT_LPI_TIMER        1000
 103 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 104 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 107
 108 /* By default the driver will use the ring mode to manage tx and rx descriptors
 109  * but passing this value so user can force to use the chain instead of the ring
 110  */
 111 static unsigned int chain_mode;
 112 module_param(chain_mode, int, S_IRUGO);
 113 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 114
 115 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 116
 117 #ifdef CONFIG_DEBUG_FS
 118 static int stmmac_init_fs(struct net_device *dev);
 119 static void stmmac_exit_fs(struct net_device *dev);
 120 #endif
 121
 122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 123
 124 /**
 125  * stmmac_verify_args - verify the driver parameters.
 126  * Description: it checks the driver parameters and set a default in case of
 127  * errors.
 128  */
 129 static void stmmac_verify_args(void)
 130 {
 131         if (unlikely(watchdog < 0))
 132                 watchdog = TX_TIMEO;
 133         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 134                 buf_sz = DEFAULT_BUFSIZE;
 135         if (unlikely(flow_ctrl > 1))
 136                 flow_ctrl = FLOW_AUTO;
 137         else if (likely(flow_ctrl < 0))
 138                 flow_ctrl = FLOW_OFF;
 139         if (unlikely((pause < 0) || (pause > 0xffff)))
 140                 pause = PAUSE_TIME;
 141         if (eee_timer < 0)
 142                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 143 }
 144
 145 /**
 146  * stmmac_clk_csr_set - dynamically set the MDC clock
 147  * @priv: driver private structure
 148  * Description: this is to dynamically set the MDC clock according to the csr
 149  * clock input.
 150  * Note:
 151  *      If a specific clk_csr value is passed from the platform
 152  *      this means that the CSR Clock Range selection cannot be
 153  *      changed at run-time and it is fixed (as reported in the driver
 154  *      documentation). Viceversa the driver will try to set the MDC
 155  *      clock dynamically according to the actual clock input.
 156  */
 157 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 158 {
 159         u32 clk_rate;
 160
 161         clk_rate = clk_get_rate(priv->stmmac_clk);
 162
 163         /* Platform provided default clk_csr would be assumed valid
 164          * for all other cases except for the below mentioned ones.
 165          * For values higher than the IEEE 802.3 specified frequency
 166          * we can not estimate the proper divider as it is not known
 167          * the frequency of clk_csr_i. So we do not change the default
 168          * divider.
 169          */
 170         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 171                 if (clk_rate < CSR_F_35M)
 172                         priv->clk_csr = STMMAC_CSR_20_35M;
 173                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 174                         priv->clk_csr = STMMAC_CSR_35_60M;
 175                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 176                         priv->clk_csr = STMMAC_CSR_60_100M;
 177                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 178                         priv->clk_csr = STMMAC_CSR_100_150M;
 179                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 180                         priv->clk_csr = STMMAC_CSR_150_250M;
 181                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 182                         priv->clk_csr = STMMAC_CSR_250_300M;
 183         }
 184 }
 185
 186 static void print_pkt(unsigned char *buf, int len)
 187 {
 188         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 189         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 190 }
 191
 192 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 193 {
 194         unsigned avail;
 195
 196         if (priv->dirty_tx > priv->cur_tx)
 197                 avail = priv->dirty_tx - priv->cur_tx - 1;
 198         else
 199                 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
 200
 201         return avail;
 202 }
 203
 204 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
 205 {
 206         unsigned dirty;
 207
 208         if (priv->dirty_rx <= priv->cur_rx)
 209                 dirty = priv->cur_rx - priv->dirty_rx;
 210         else
 211                 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
 212
 213         return dirty;
 214 }
 215
 216 /**
 217  * stmmac_hw_fix_mac_speed - callback for speed selection
 218  * @priv: driver private structure
 219  * Description: on some platforms (e.g. ST), some HW system configuraton
 220  * registers have to be set according to the link speed negotiated.
 221  */
 222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 223 {
 224         struct phy_device *phydev = priv->phydev;
 225
 226         if (likely(priv->plat->fix_mac_speed))
 227                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 228 }
 229
 230 /**
 231  * stmmac_enable_eee_mode - check and enter in LPI mode
 232  * @priv: driver private structure
 233  * Description: this function is to verify and enter in LPI mode in case of
 234  * EEE.
 235  */
 236 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 237 {
 238         /* Check and enter in LPI mode */
 239         if ((priv->dirty_tx == priv->cur_tx) &&
 240             (priv->tx_path_in_lpi_mode == false))
 241                 priv->hw->mac->set_eee_mode(priv->hw);
 242 }
 243
 244 /**
 245  * stmmac_disable_eee_mode - disable and exit from LPI mode
 246  * @priv: driver private structure
 247  * Description: this function is to exit and disable EEE in case of
 248  * LPI state is true. This is called by the xmit.
 249  */
 250 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 251 {
 252         priv->hw->mac->reset_eee_mode(priv->hw);
 253         del_timer_sync(&priv->eee_ctrl_timer);
 254         priv->tx_path_in_lpi_mode = false;
 255 }
 256
 257 /**
 258  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 259  * @arg : data hook
 260  * Description:
 261  *  if there is no data transfer and if we are not in LPI state,
 262  *  then MAC Transmitter can be moved to LPI state.
 263  */
 264 static void stmmac_eee_ctrl_timer(unsigned long arg)
 265 {
 266         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 267
 268         stmmac_enable_eee_mode(priv);
 269         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 270 }
 271
 272 /**
 273  * stmmac_eee_init - init EEE
 274  * @priv: driver private structure
 275  * Description:
 276  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 277  *  can also manage EEE, this function enable the LPI state and start related
 278  *  timer.
 279  */
 280 bool stmmac_eee_init(struct stmmac_priv *priv)
 281 {
 282         unsigned long flags;
 283         int interface = priv->plat->interface;
 284         bool ret = false;
 285
 286         if ((interface != PHY_INTERFACE_MODE_MII) &&
 287             (interface != PHY_INTERFACE_MODE_GMII) &&
 288             !phy_interface_mode_is_rgmii(interface))
 289                 goto out;
 290
 291         /* Using PCS we cannot dial with the phy registers at this stage
 292          * so we do not support extra feature like EEE.
 293          */
 294         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 295             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 296             (priv->hw->pcs == STMMAC_PCS_RTBI))
 297                 goto out;
 298
 299         /* MAC core supports the EEE feature. */
 300         if (priv->dma_cap.eee) {
 301                 int tx_lpi_timer = priv->tx_lpi_timer;
 302
 303                 /* Check if the PHY supports EEE */
 304                 if (phy_init_eee(priv->phydev, 1)) {
 305                         /* To manage at run-time if the EEE cannot be supported
 306                          * anymore (for example because the lp caps have been
 307                          * changed).
 308                          * In that case the driver disable own timers.
 309                          */
 310                         spin_lock_irqsave(&priv->lock, flags);
 311                         if (priv->eee_active) {
 312                                 pr_debug("stmmac: disable EEE\n");
 313                                 del_timer_sync(&priv->eee_ctrl_timer);
 314                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 315                                                              tx_lpi_timer);
 316                         }
 317                         priv->eee_active = 0;
 318                         spin_unlock_irqrestore(&priv->lock, flags);
 319                         goto out;
 320                 }
 321                 /* Activate the EEE and start timers */
 322                 spin_lock_irqsave(&priv->lock, flags);
 323                 if (!priv->eee_active) {
 324                         priv->eee_active = 1;
 325                         setup_timer(&priv->eee_ctrl_timer,
 326                                     stmmac_eee_ctrl_timer,
 327                                     (unsigned long)priv);
 328                         mod_timer(&priv->eee_ctrl_timer,
 329                                   STMMAC_LPI_T(eee_timer));
 330
 331                         priv->hw->mac->set_eee_timer(priv->hw,
 332                                                      STMMAC_DEFAULT_LIT_LS,
 333                                                      tx_lpi_timer);
 334                 }
 335                 /* Set HW EEE according to the speed */
 336                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 337
 338                 ret = true;
 339                 spin_unlock_irqrestore(&priv->lock, flags);
 340
 341                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 342         }
 343 out:
 344         return ret;
 345 }
 346
 347 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 348  * @priv: driver private structure
 349  * @p : descriptor pointer
 350  * @skb : the socket buffer
 351  * Description :
 352  * This function will read timestamp from the descriptor & pass it to stack.
 353  * and also perform some sanity checks.
 354  */
 355 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 356                                    struct dma_desc *p, struct sk_buff *skb)
 357 {
 358         struct skb_shared_hwtstamps shhwtstamp;
 359         u64 ns;
 360
 361         if (!priv->hwts_tx_en)
 362                 return;
 363
 364         /* exit if skb doesn't support hw tstamp */
 365         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 366                 return;
 367
 368         /* check tx tstamp status */
 369         if (!priv->hw->desc->get_tx_timestamp_status(p)) {
 370                 /* get the valid tstamp */
 371                 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 372
 373                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 374                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 375
 376                 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 377                 /* pass tstamp to stack */
 378                 skb_tstamp_tx(skb, &shhwtstamp);
 379         }
 380
 381         return;
 382 }
 383
 384 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 385  * @priv: driver private structure
 386  * @p : descriptor pointer
 387  * @np : next descriptor pointer
 388  * @skb : the socket buffer
 389  * Description :
 390  * This function will read received packet's timestamp from the descriptor
 391  * and pass it to stack. It also perform some sanity checks.
 392  */
 393 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 394                                    struct dma_desc *np, struct sk_buff *skb)
 395 {
 396         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 397         u64 ns;
 398
 399         if (!priv->hwts_rx_en)
 400                 return;
 401
 402         /* Check if timestamp is available */
 403         if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
 404                 /* For GMAC4, the valid timestamp is from CTX next desc. */
 405                 if (priv->plat->has_gmac4)
 406                         ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
 407                 else
 408                         ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
 409
 410                 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 411                 shhwtstamp = skb_hwtstamps(skb);
 412                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 413                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 414         } else  {
 415                 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
 416         }
 417 }
 418
 419 /**
 420  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 421  *  @dev: device pointer.
 422  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 423  *  a proprietary structure used to pass information to the driver.
 424  *  Description:
 425  *  This function configures the MAC to enable/disable both outgoing(TX)
 426  *  and incoming(RX) packets time stamping based on user input.
 427  *  Return Value:
 428  *  0 on success and an appropriate -ve integer on failure.
 429  */
 430 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 431 {
 432         struct stmmac_priv *priv = netdev_priv(dev);
 433         struct hwtstamp_config config;
 434         struct timespec64 now;
 435         u64 temp = 0;
 436         u32 ptp_v2 = 0;
 437         u32 tstamp_all = 0;
 438         u32 ptp_over_ipv4_udp = 0;
 439         u32 ptp_over_ipv6_udp = 0;
 440         u32 ptp_over_ethernet = 0;
 441         u32 snap_type_sel = 0;
 442         u32 ts_master_en = 0;
 443         u32 ts_event_en = 0;
 444         u32 value = 0;
 445         u32 sec_inc;
 446
 447         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 448                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 449                 priv->hwts_tx_en = 0;
 450                 priv->hwts_rx_en = 0;
 451
 452                 return -EOPNOTSUPP;
 453         }
 454
 455         if (copy_from_user(&config, ifr->ifr_data,
 456                            sizeof(struct hwtstamp_config)))
 457                 return -EFAULT;
 458
 459         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 460                  __func__, config.flags, config.tx_type, config.rx_filter);
 461
 462         /* reserved for future extensions */
 463         if (config.flags)
 464                 return -EINVAL;
 465
 466         if (config.tx_type != HWTSTAMP_TX_OFF &&
 467             config.tx_type != HWTSTAMP_TX_ON)
 468                 return -ERANGE;
 469
 470         if (priv->adv_ts) {
 471                 switch (config.rx_filter) {
 472                 case HWTSTAMP_FILTER_NONE:
 473                         /* time stamp no incoming packet at all */
 474                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 475                         break;
 476
 477                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 478                         /* PTP v1, UDP, any kind of event packet */
 479                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 480                         /* take time stamp for all event messages */
 481                         if (priv->plat->has_gmac4)
 482                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 483                         else
 484                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 485
 486                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 487                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 488                         break;
 489
 490                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 491                         /* PTP v1, UDP, Sync packet */
 492                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 493                         /* take time stamp for SYNC messages only */
 494                         ts_event_en = PTP_TCR_TSEVNTENA;
 495
 496                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 497                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 498                         break;
 499
 500                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 501                         /* PTP v1, UDP, Delay_req packet */
 502                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 503                         /* take time stamp for Delay_Req messages only */
 504                         ts_master_en = PTP_TCR_TSMSTRENA;
 505                         ts_event_en = PTP_TCR_TSEVNTENA;
 506
 507                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 508                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 509                         break;
 510
 511                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 512                         /* PTP v2, UDP, any kind of event packet */
 513                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 514                         ptp_v2 = PTP_TCR_TSVER2ENA;
 515                         /* take time stamp for all event messages */
 516                         if (priv->plat->has_gmac4)
 517                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 518                         else
 519                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 520
 521                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 522                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 523                         break;
 524
 525                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 526                         /* PTP v2, UDP, Sync packet */
 527                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 528                         ptp_v2 = PTP_TCR_TSVER2ENA;
 529                         /* take time stamp for SYNC messages only */
 530                         ts_event_en = PTP_TCR_TSEVNTENA;
 531
 532                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 533                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 534                         break;
 535
 536                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 537                         /* PTP v2, UDP, Delay_req packet */
 538                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 539                         ptp_v2 = PTP_TCR_TSVER2ENA;
 540                         /* take time stamp for Delay_Req messages only */
 541                         ts_master_en = PTP_TCR_TSMSTRENA;
 542                         ts_event_en = PTP_TCR_TSEVNTENA;
 543
 544                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 545                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 546                         break;
 547
 548                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 549                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 550                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 551                         ptp_v2 = PTP_TCR_TSVER2ENA;
 552                         /* take time stamp for all event messages */
 553                         if (priv->plat->has_gmac4)
 554                                 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
 555                         else
 556                                 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 557
 558                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 559                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 560                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 561                         break;
 562
 563                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 564                         /* PTP v2/802.AS1, any layer, Sync packet */
 565                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 566                         ptp_v2 = PTP_TCR_TSVER2ENA;
 567                         /* take time stamp for SYNC messages only */
 568                         ts_event_en = PTP_TCR_TSEVNTENA;
 569
 570                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 571                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 572                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 573                         break;
 574
 575                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 576                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 577                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 578                         ptp_v2 = PTP_TCR_TSVER2ENA;
 579                         /* take time stamp for Delay_Req messages only */
 580                         ts_master_en = PTP_TCR_TSMSTRENA;
 581                         ts_event_en = PTP_TCR_TSEVNTENA;
 582
 583                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 584                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 585                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 586                         break;
 587
 588                 case HWTSTAMP_FILTER_ALL:
 589                         /* time stamp any incoming packet */
 590                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 591                         tstamp_all = PTP_TCR_TSENALL;
 592                         break;
 593
 594                 default:
 595                         return -ERANGE;
 596                 }
 597         } else {
 598                 switch (config.rx_filter) {
 599                 case HWTSTAMP_FILTER_NONE:
 600                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 601                         break;
 602                 default:
 603                         /* PTP v1, UDP, any kind of event packet */
 604                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 605                         break;
 606                 }
 607         }
 608         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 609         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 610
 611         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 612                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
 613         else {
 614                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 615                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 616                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 617                          ts_master_en | snap_type_sel);
 618                 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
 619
 620                 /* program Sub Second Increment reg */
 621                 sec_inc = priv->hw->ptp->config_sub_second_increment(
 622                         priv->ptpaddr, priv->clk_ptp_rate,
 623                         priv->plat->has_gmac4);
 624                 temp = div_u64(1000000000ULL, sec_inc);
 625
 626                 /* calculate default added value:
 627                  * formula is :
 628                  * addend = (2^32)/freq_div_ratio;
 629                  * where, freq_div_ratio = 1e9ns/sec_inc
 630                  */
 631                 temp = (u64)(temp << 32);
 632                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 633                 priv->hw->ptp->config_addend(priv->ptpaddr,
 634                                              priv->default_addend);
 635
 636                 /* initialize system time */
 637                 ktime_get_real_ts64(&now);
 638
 639                 /* lower 32 bits of tv_sec are safe until y2106 */
 640                 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
 641                                             now.tv_nsec);
 642         }
 643
 644         return copy_to_user(ifr->ifr_data, &config,
 645                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 646 }
 647
 648 /**
 649  * stmmac_init_ptp - init PTP
 650  * @priv: driver private structure
 651  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 652  * This is done by looking at the HW cap. register.
 653  * This function also registers the ptp driver.
 654  */
 655 static int stmmac_init_ptp(struct stmmac_priv *priv)
 656 {
 657         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 658                 return -EOPNOTSUPP;
 659
 660         /* Fall-back to main clock in case of no PTP ref is passed */
 661         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 662         if (IS_ERR(priv->clk_ptp_ref)) {
 663                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 664                 priv->clk_ptp_ref = NULL;
 665                 netdev_dbg(priv->dev, "PTP uses main clock\n");
 666         } else {
 667                 clk_prepare_enable(priv->clk_ptp_ref);
 668                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 669                 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
 670         }
 671
 672         priv->adv_ts = 0;
 673         /* Check if adv_ts can be enabled for dwmac 4.x core */
 674         if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
 675                 priv->adv_ts = 1;
 676         /* Dwmac 3.x core with extend_desc can support adv_ts */
 677         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 678                 priv->adv_ts = 1;
 679
 680         if (priv->dma_cap.time_stamp)
 681                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 682
 683         if (priv->adv_ts)
 684                 netdev_info(priv->dev,
 685                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 686
 687         priv->hw->ptp = &stmmac_ptp;
 688         priv->hwts_tx_en = 0;
 689         priv->hwts_rx_en = 0;
 690
 691         stmmac_ptp_register(priv);
 692
 693         return 0;
 694 }
 695
 696 static void stmmac_release_ptp(struct stmmac_priv *priv)
 697 {
 698         if (priv->clk_ptp_ref)
 699                 clk_disable_unprepare(priv->clk_ptp_ref);
 700         stmmac_ptp_unregister(priv);
 701 }
 702
 703 /**
 704  * stmmac_adjust_link - adjusts the link parameters
 705  * @dev: net device structure
 706  * Description: this is the helper called by the physical abstraction layer
 707  * drivers to communicate the phy link status. According the speed and duplex
 708  * this driver can invoke registered glue-logic as well.
 709  * It also invoke the eee initialization because it could happen when switch
 710  * on different networks (that are eee capable).
 711  */
 712 static void stmmac_adjust_link(struct net_device *dev)
 713 {
 714         struct stmmac_priv *priv = netdev_priv(dev);
 715         struct phy_device *phydev = priv->phydev;
 716         unsigned long flags;
 717         int new_state = 0;
 718         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 719
 720         if (phydev == NULL)
 721                 return;
 722
 723         spin_lock_irqsave(&priv->lock, flags);
 724
 725         if (phydev->link) {
 726                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 727
 728                 /* Now we make sure that we can be in full duplex mode.
 729                  * If not, we operate in half-duplex mode. */
 730                 if (phydev->duplex != priv->oldduplex) {
 731                         new_state = 1;
 732                         if (!(phydev->duplex))
 733                                 ctrl &= ~priv->hw->link.duplex;
 734                         else
 735                                 ctrl |= priv->hw->link.duplex;
 736                         priv->oldduplex = phydev->duplex;
 737                 }
 738                 /* Flow Control operation */
 739                 if (phydev->pause)
 740                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 741                                                  fc, pause_time);
 742
 743                 if (phydev->speed != priv->speed) {
 744                         new_state = 1;
 745                         switch (phydev->speed) {
 746                         case 1000:
 747                                 if (likely((priv->plat->has_gmac) ||
 748                                            (priv->plat->has_gmac4)))
 749                                         ctrl &= ~priv->hw->link.port;
 750                                 stmmac_hw_fix_mac_speed(priv);
 751                                 break;
 752                         case 100:
 753                         case 10:
 754                                 if (likely((priv->plat->has_gmac) ||
 755                                            (priv->plat->has_gmac4))) {
 756                                         ctrl |= priv->hw->link.port;
 757                                         if (phydev->speed == SPEED_100) {
 758                                                 ctrl |= priv->hw->link.speed;
 759                                         } else {
 760                                                 ctrl &= ~(priv->hw->link.speed);
 761                                         }
 762                                 } else {
 763                                         ctrl &= ~priv->hw->link.port;
 764                                 }
 765                                 stmmac_hw_fix_mac_speed(priv);
 766                                 break;
 767                         default:
 768                                 if (netif_msg_link(priv))
 769                                         pr_warn("%s: Speed (%d) not 10/100\n",
 770                                                 dev->name, phydev->speed);
 771                                 break;
 772                         }
 773
 774                         priv->speed = phydev->speed;
 775                 }
 776
 777                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 778
 779                 if (!priv->oldlink) {
 780                         new_state = 1;
 781                         priv->oldlink = 1;
 782                 }
 783         } else if (priv->oldlink) {
 784                 new_state = 1;
 785                 priv->oldlink = 0;
 786                 priv->speed = 0;
 787                 priv->oldduplex = -1;
 788         }
 789
 790         if (new_state && netif_msg_link(priv))
 791                 phy_print_status(phydev);
 792
 793         spin_unlock_irqrestore(&priv->lock, flags);
 794
 795         if (phydev->is_pseudo_fixed_link)
 796                 /* Stop PHY layer to call the hook to adjust the link in case
 797                  * of a switch is attached to the stmmac driver.
 798                  */
 799                 phydev->irq = PHY_IGNORE_INTERRUPT;
 800         else
 801                 /* At this stage, init the EEE if supported.
 802                  * Never called in case of fixed_link.
 803                  */
 804                 priv->eee_enabled = stmmac_eee_init(priv);
 805 }
 806
 807 /**
 808  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 809  * @priv: driver private structure
 810  * Description: this is to verify if the HW supports the PCS.
 811  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 812  * configured for the TBI, RTBI, or SGMII PHY interface.
 813  */
 814 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 815 {
 816         int interface = priv->plat->interface;
 817
 818         if (priv->dma_cap.pcs) {
 819                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 820                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 821                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 822                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 823                         pr_debug("STMMAC: PCS RGMII support enable\n");
 824                         priv->hw->pcs = STMMAC_PCS_RGMII;
 825                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 826                         pr_debug("STMMAC: PCS SGMII support enable\n");
 827                         priv->hw->pcs = STMMAC_PCS_SGMII;
 828                 }
 829         }
 830 }
 831
 832 /**
 833  * stmmac_init_phy - PHY initialization
 834  * @dev: net device structure
 835  * Description: it initializes the driver's PHY state, and attaches the PHY
 836  * to the mac driver.
 837  *  Return value:
 838  *  0 on success
 839  */
 840 static int stmmac_init_phy(struct net_device *dev)
 841 {
 842         struct stmmac_priv *priv = netdev_priv(dev);
 843         struct phy_device *phydev;
 844         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 845         char bus_id[MII_BUS_ID_SIZE];
 846         int interface = priv->plat->interface;
 847         int max_speed = priv->plat->max_speed;
 848         priv->oldlink = 0;
 849         priv->speed = 0;
 850         priv->oldduplex = -1;
 851
 852         if (priv->plat->phy_node) {
 853                 phydev = of_phy_connect(dev, priv->plat->phy_node,
 854                                         &stmmac_adjust_link, 0, interface);
 855         } else {
 856                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 857                          priv->plat->bus_id);
 858
 859                 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 860                          priv->plat->phy_addr);
 861                 pr_debug("stmmac_init_phy:  trying to attach to %s\n",
 862                          phy_id_fmt);
 863
 864                 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
 865                                      interface);
 866         }
 867
 868         if (IS_ERR_OR_NULL(phydev)) {
 869                 pr_err("%s: Could not attach to PHY\n", dev->name);
 870                 if (!phydev)
 871                         return -ENODEV;
 872
 873                 return PTR_ERR(phydev);
 874         }
 875
 876         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 877         if ((interface == PHY_INTERFACE_MODE_MII) ||
 878             (interface == PHY_INTERFACE_MODE_RMII) ||
 879                 (max_speed < 1000 && max_speed > 0))
 880                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 881                                          SUPPORTED_1000baseT_Full);
 882
 883         /*
 884          * Broken HW is sometimes missing the pull-up resistor on the
 885          * MDIO line, which results in reads to non-existent devices returning
 886          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 887          * device as well.
 888          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 889          */
 890         if (!priv->plat->phy_node && phydev->phy_id == 0) {
 891                 phy_disconnect(phydev);
 892                 return -ENODEV;
 893         }
 894
 895         /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
 896          * subsequent PHY polling, make sure we force a link transition if
 897          * we have a UP/DOWN/UP transition
 898          */
 899         if (phydev->is_pseudo_fixed_link)
 900                 phydev->irq = PHY_POLL;
 901
 902         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 903                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 904
 905         priv->phydev = phydev;
 906
 907         return 0;
 908 }
 909
 910 static void stmmac_display_rings(struct stmmac_priv *priv)
 911 {
 912         void *head_rx, *head_tx;
 913
 914         if (priv->extend_desc) {
 915                 head_rx = (void *)priv->dma_erx;
 916                 head_tx = (void *)priv->dma_etx;
 917         } else {
 918                 head_rx = (void *)priv->dma_rx;
 919                 head_tx = (void *)priv->dma_tx;
 920         }
 921
 922         /* Display Rx ring */
 923         priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
 924         /* Display Tx ring */
 925         priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
 926 }
 927
 928 static int stmmac_set_bfsize(int mtu, int bufsize)
 929 {
 930         int ret = bufsize;
 931
 932         if (mtu >= BUF_SIZE_4KiB)
 933                 ret = BUF_SIZE_8KiB;
 934         else if (mtu >= BUF_SIZE_2KiB)
 935                 ret = BUF_SIZE_4KiB;
 936         else if (mtu > DEFAULT_BUFSIZE)
 937                 ret = BUF_SIZE_2KiB;
 938         else
 939                 ret = DEFAULT_BUFSIZE;
 940
 941         return ret;
 942 }
 943
 944 /**
 945  * stmmac_clear_descriptors - clear descriptors
 946  * @priv: driver private structure
 947  * Description: this function is called to clear the tx and rx descriptors
 948  * in case of both basic and extended descriptors are used.
 949  */
 950 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 951 {
 952         int i;
 953
 954         /* Clear the Rx/Tx descriptors */
 955         for (i = 0; i < DMA_RX_SIZE; i++)
 956                 if (priv->extend_desc)
 957                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 958                                                      priv->use_riwt, priv->mode,
 959                                                      (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
 960                 else
 961                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 962                                                      priv->use_riwt, priv->mode,
 963                                                      (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
 964         for (i = 0; i < DMA_TX_SIZE; i++)
 965                 if (priv->extend_desc)
 966                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 967                                                      priv->mode,
 968                                                      (i == DMA_TX_SIZE - 1));
 969                 else
 970                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 971                                                      priv->mode,
 972                                                      (i == DMA_TX_SIZE - 1));
 973 }
 974
 975 /**
 976  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 977  * @priv: driver private structure
 978  * @p: descriptor pointer
 979  * @i: descriptor index
 980  * @flags: gfp flag.
 981  * Description: this function is called to allocate a receive buffer, perform
 982  * the DMA mapping and init the descriptor.
 983  */
 984 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 985                                   int i, gfp_t flags)
 986 {
 987         struct sk_buff *skb;
 988
 989         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 990         if (!skb) {
 991                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 992                 return -ENOMEM;
 993         }
 994         priv->rx_skbuff[i] = skb;
 995         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 996                                                 priv->dma_buf_sz,
 997                                                 DMA_FROM_DEVICE);
 998         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 999                 pr_err("%s: DMA mapping error\n", __func__);
1000                 dev_kfree_skb_any(skb);
1001                 return -EINVAL;
1002         }
1003
1004         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1005                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1006         else
1007                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1008
1009         if ((priv->hw->mode->init_desc3) &&
1010             (priv->dma_buf_sz == BUF_SIZE_16KiB))
1011                 priv->hw->mode->init_desc3(p);
1012
1013         return 0;
1014 }
1015
1016 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1017 {
1018         if (priv->rx_skbuff[i]) {
1019                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1020                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1021                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1022         }
1023         priv->rx_skbuff[i] = NULL;
1024 }
1025
1026 /**
1027  * init_dma_desc_rings - init the RX/TX descriptor rings
1028  * @dev: net device structure
1029  * @flags: gfp flag.
1030  * Description: this function initializes the DMA RX/TX descriptors
1031  * and allocates the socket buffers. It suppors the chained and ring
1032  * modes.
1033  */
1034 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1035 {
1036         int i;
1037         struct stmmac_priv *priv = netdev_priv(dev);
1038         unsigned int bfsize = 0;
1039         int ret = -ENOMEM;
1040
1041         if (priv->hw->mode->set_16kib_bfsize)
1042                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1043
1044         if (bfsize < BUF_SIZE_16KiB)
1045                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1046
1047         priv->dma_buf_sz = bfsize;
1048
1049         if (netif_msg_probe(priv)) {
1050                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1051                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1052
1053                 /* RX INITIALIZATION */
1054                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1055         }
1056         for (i = 0; i < DMA_RX_SIZE; i++) {
1057                 struct dma_desc *p;
1058                 if (priv->extend_desc)
1059                         p = &((priv->dma_erx + i)->basic);
1060                 else
1061                         p = priv->dma_rx + i;
1062
1063                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1064                 if (ret)
1065                         goto err_init_rx_buffers;
1066
1067                 if (netif_msg_probe(priv))
1068                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1069                                  priv->rx_skbuff[i]->data,
1070                                  (unsigned int)priv->rx_skbuff_dma[i]);
1071         }
1072         priv->cur_rx = 0;
1073         priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1074         buf_sz = bfsize;
1075
1076         /* Setup the chained descriptor addresses */
1077         if (priv->mode == STMMAC_CHAIN_MODE) {
1078                 if (priv->extend_desc) {
1079                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1080                                              DMA_RX_SIZE, 1);
1081                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1082                                              DMA_TX_SIZE, 1);
1083                 } else {
1084                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1085                                              DMA_RX_SIZE, 0);
1086                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1087                                              DMA_TX_SIZE, 0);
1088                 }
1089         }
1090
1091         /* TX INITIALIZATION */
1092         for (i = 0; i < DMA_TX_SIZE; i++) {
1093                 struct dma_desc *p;
1094                 if (priv->extend_desc)
1095                         p = &((priv->dma_etx + i)->basic);
1096                 else
1097                         p = priv->dma_tx + i;
1098
1099                 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1100                         p->des0 = 0;
1101                         p->des1 = 0;
1102                         p->des2 = 0;
1103                         p->des3 = 0;
1104                 } else {
1105                         p->des2 = 0;
1106                 }
1107
1108                 priv->tx_skbuff_dma[i].buf = 0;
1109                 priv->tx_skbuff_dma[i].map_as_page = false;
1110                 priv->tx_skbuff_dma[i].len = 0;
1111                 priv->tx_skbuff_dma[i].last_segment = false;
1112                 priv->tx_skbuff[i] = NULL;
1113         }
1114
1115         priv->dirty_tx = 0;
1116         priv->cur_tx = 0;
1117         netdev_reset_queue(priv->dev);
1118
1119         stmmac_clear_descriptors(priv);
1120
1121         if (netif_msg_hw(priv))
1122                 stmmac_display_rings(priv);
1123
1124         return 0;
1125 err_init_rx_buffers:
1126         while (--i >= 0)
1127                 stmmac_free_rx_buffers(priv, i);
1128         return ret;
1129 }
1130
1131 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1132 {
1133         int i;
1134
1135         for (i = 0; i < DMA_RX_SIZE; i++)
1136                 stmmac_free_rx_buffers(priv, i);
1137 }
1138
1139 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1140 {
1141         int i;
1142
1143         for (i = 0; i < DMA_TX_SIZE; i++) {
1144                 struct dma_desc *p;
1145
1146                 if (priv->extend_desc)
1147                         p = &((priv->dma_etx + i)->basic);
1148                 else
1149                         p = priv->dma_tx + i;
1150
1151                 if (priv->tx_skbuff_dma[i].buf) {
1152                         if (priv->tx_skbuff_dma[i].map_as_page)
1153                                 dma_unmap_page(priv->device,
1154                                                priv->tx_skbuff_dma[i].buf,
1155                                                priv->tx_skbuff_dma[i].len,
1156                                                DMA_TO_DEVICE);
1157                         else
1158                                 dma_unmap_single(priv->device,
1159                                                  priv->tx_skbuff_dma[i].buf,
1160                                                  priv->tx_skbuff_dma[i].len,
1161                                                  DMA_TO_DEVICE);
1162                 }
1163
1164                 if (priv->tx_skbuff[i] != NULL) {
1165                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1166                         priv->tx_skbuff[i] = NULL;
1167                         priv->tx_skbuff_dma[i].buf = 0;
1168                         priv->tx_skbuff_dma[i].map_as_page = false;
1169                 }
1170         }
1171 }
1172
1173 /**
1174  * alloc_dma_desc_resources - alloc TX/RX resources.
1175  * @priv: private structure
1176  * Description: according to which descriptor can be used (extend or basic)
1177  * this function allocates the resources for TX and RX paths. In case of
1178  * reception, for example, it pre-allocated the RX socket buffer in order to
1179  * allow zero-copy mechanism.
1180  */
1181 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1182 {
1183         int ret = -ENOMEM;
1184
1185         priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1186                                             GFP_KERNEL);
1187         if (!priv->rx_skbuff_dma)
1188                 return -ENOMEM;
1189
1190         priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1191                                         GFP_KERNEL);
1192         if (!priv->rx_skbuff)
1193                 goto err_rx_skbuff;
1194
1195         priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1196                                             sizeof(*priv->tx_skbuff_dma),
1197                                             GFP_KERNEL);
1198         if (!priv->tx_skbuff_dma)
1199                 goto err_tx_skbuff_dma;
1200
1201         priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1202                                         GFP_KERNEL);
1203         if (!priv->tx_skbuff)
1204                 goto err_tx_skbuff;
1205
1206         if (priv->extend_desc) {
1207                 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1208                                                     sizeof(struct
1209                                                            dma_extended_desc),
1210                                                     &priv->dma_rx_phy,
1211                                                     GFP_KERNEL);
1212                 if (!priv->dma_erx)
1213                         goto err_dma;
1214
1215                 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1216                                                     sizeof(struct
1217                                                            dma_extended_desc),
1218                                                     &priv->dma_tx_phy,
1219                                                     GFP_KERNEL);
1220                 if (!priv->dma_etx) {
1221                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1222                                           sizeof(struct dma_extended_desc),
1223                                           priv->dma_erx, priv->dma_rx_phy);
1224                         goto err_dma;
1225                 }
1226         } else {
1227                 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1228                                                    sizeof(struct dma_desc),
1229                                                    &priv->dma_rx_phy,
1230                                                    GFP_KERNEL);
1231                 if (!priv->dma_rx)
1232                         goto err_dma;
1233
1234                 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1235                                                    sizeof(struct dma_desc),
1236                                                    &priv->dma_tx_phy,
1237                                                    GFP_KERNEL);
1238                 if (!priv->dma_tx) {
1239                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1240                                           sizeof(struct dma_desc),
1241                                           priv->dma_rx, priv->dma_rx_phy);
1242                         goto err_dma;
1243                 }
1244         }
1245
1246         return 0;
1247
1248 err_dma:
1249         kfree(priv->tx_skbuff);
1250 err_tx_skbuff:
1251         kfree(priv->tx_skbuff_dma);
1252 err_tx_skbuff_dma:
1253         kfree(priv->rx_skbuff);
1254 err_rx_skbuff:
1255         kfree(priv->rx_skbuff_dma);
1256         return ret;
1257 }
1258
1259 static void free_dma_desc_resources(struct stmmac_priv *priv)
1260 {
1261         /* Release the DMA TX/RX socket buffers */
1262         dma_free_rx_skbufs(priv);
1263         dma_free_tx_skbufs(priv);
1264
1265         /* Free DMA regions of consistent memory previously allocated */
1266         if (!priv->extend_desc) {
1267                 dma_free_coherent(priv->device,
1268                                   DMA_TX_SIZE * sizeof(struct dma_desc),
1269                                   priv->dma_tx, priv->dma_tx_phy);
1270                 dma_free_coherent(priv->device,
1271                                   DMA_RX_SIZE * sizeof(struct dma_desc),
1272                                   priv->dma_rx, priv->dma_rx_phy);
1273         } else {
1274                 dma_free_coherent(priv->device, DMA_TX_SIZE *
1275                                   sizeof(struct dma_extended_desc),
1276                                   priv->dma_etx, priv->dma_tx_phy);
1277                 dma_free_coherent(priv->device, DMA_RX_SIZE *
1278                                   sizeof(struct dma_extended_desc),
1279                                   priv->dma_erx, priv->dma_rx_phy);
1280         }
1281         kfree(priv->rx_skbuff_dma);
1282         kfree(priv->rx_skbuff);
1283         kfree(priv->tx_skbuff_dma);
1284         kfree(priv->tx_skbuff);
1285 }
1286
1287 /**
1288  *  stmmac_dma_operation_mode - HW DMA operation mode
1289  *  @priv: driver private structure
1290  *  Description: it is used for configuring the DMA operation mode register in
1291  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1292  */
1293 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1294 {
1295         int rxfifosz = priv->plat->rx_fifo_size;
1296
1297         if (priv->plat->force_thresh_dma_mode)
1298                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1299         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1300                 /*
1301                  * In case of GMAC, SF mode can be enabled
1302                  * to perform the TX COE in HW. This depends on:
1303                  * 1) TX COE if actually supported
1304                  * 2) There is no bugged Jumbo frame support
1305                  *    that needs to not insert csum in the TDES.
1306                  */
1307                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1308                                         rxfifosz);
1309                 priv->xstats.threshold = SF_DMA_MODE;
1310         } else
1311                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1312                                         rxfifosz);
1313 }
1314
1315 /**
1316  * stmmac_tx_clean - to manage the transmission completion
1317  * @priv: driver private structure
1318  * Description: it reclaims the transmit resources after transmission completes.
1319  */
1320 static void stmmac_tx_clean(struct stmmac_priv *priv)
1321 {
1322         unsigned int bytes_compl = 0, pkts_compl = 0;
1323         unsigned int entry = priv->dirty_tx;
1324
1325         spin_lock(&priv->tx_lock);
1326
1327         priv->xstats.tx_clean++;
1328
1329         while (entry != priv->cur_tx) {
1330                 struct sk_buff *skb = priv->tx_skbuff[entry];
1331                 struct dma_desc *p;
1332                 int status;
1333
1334                 if (priv->extend_desc)
1335                         p = (struct dma_desc *)(priv->dma_etx + entry);
1336                 else
1337                         p = priv->dma_tx + entry;
1338
1339                 status = priv->hw->desc->tx_status(&priv->dev->stats,
1340                                                       &priv->xstats, p,
1341                                                       priv->ioaddr);
1342                 /* Check if the descriptor is owned by the DMA */
1343                 if (unlikely(status & tx_dma_own))
1344                         break;
1345
1346                 /* Make sure descriptor fields are read after reading
1347                  * the own bit.
1348                  */
1349                 dma_rmb();
1350
1351                 /* Just consider the last segment and ...*/
1352                 if (likely(!(status & tx_not_ls))) {
1353                         /* ... verify the status error condition */
1354                         if (unlikely(status & tx_err)) {
1355                                 priv->dev->stats.tx_errors++;
1356                         } else {
1357                                 priv->dev->stats.tx_packets++;
1358                                 priv->xstats.tx_pkt_n++;
1359                         }
1360                         stmmac_get_tx_hwtstamp(priv, p, skb);
1361                 }
1362
1363                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1364                         if (priv->tx_skbuff_dma[entry].map_as_page)
1365                                 dma_unmap_page(priv->device,
1366                                                priv->tx_skbuff_dma[entry].buf,
1367                                                priv->tx_skbuff_dma[entry].len,
1368                                                DMA_TO_DEVICE);
1369                         else
1370                                 dma_unmap_single(priv->device,
1371                                                  priv->tx_skbuff_dma[entry].buf,
1372                                                  priv->tx_skbuff_dma[entry].len,
1373                                                  DMA_TO_DEVICE);
1374                         priv->tx_skbuff_dma[entry].buf = 0;
1375                         priv->tx_skbuff_dma[entry].len = 0;
1376                         priv->tx_skbuff_dma[entry].map_as_page = false;
1377                 }
1378
1379                 if (priv->hw->mode->clean_desc3)
1380                         priv->hw->mode->clean_desc3(priv, p);
1381
1382                 priv->tx_skbuff_dma[entry].last_segment = false;
1383                 priv->tx_skbuff_dma[entry].is_jumbo = false;
1384
1385                 if (likely(skb != NULL)) {
1386                         pkts_compl++;
1387                         bytes_compl += skb->len;
1388                         dev_consume_skb_any(skb);
1389                         priv->tx_skbuff[entry] = NULL;
1390                 }
1391
1392                 priv->hw->desc->release_tx_desc(p, priv->mode);
1393
1394                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1395         }
1396         priv->dirty_tx = entry;
1397
1398         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1399
1400         if (unlikely(netif_queue_stopped(priv->dev) &&
1401                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1402                 netif_tx_lock(priv->dev);
1403                 if (netif_queue_stopped(priv->dev) &&
1404                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1405                         if (netif_msg_tx_done(priv))
1406                                 pr_debug("%s: restart transmit\n", __func__);
1407                         netif_wake_queue(priv->dev);
1408                 }
1409                 netif_tx_unlock(priv->dev);
1410         }
1411
1412         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1413                 stmmac_enable_eee_mode(priv);
1414                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1415         }
1416         spin_unlock(&priv->tx_lock);
1417 }
1418
1419 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1420 {
1421         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1422 }
1423
1424 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1425 {
1426         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1427 }
1428
1429 /**
1430  * stmmac_tx_err - to manage the tx error
1431  * @priv: driver private structure
1432  * Description: it cleans the descriptors and restarts the transmission
1433  * in case of transmission errors.
1434  */
1435 static void stmmac_tx_err(struct stmmac_priv *priv)
1436 {
1437         int i;
1438         netif_stop_queue(priv->dev);
1439
1440         priv->hw->dma->stop_tx(priv->ioaddr);
1441         dma_free_tx_skbufs(priv);
1442         for (i = 0; i < DMA_TX_SIZE; i++)
1443                 if (priv->extend_desc)
1444                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1445                                                      priv->mode,
1446                                                      (i == DMA_TX_SIZE - 1));
1447                 else
1448                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1449                                                      priv->mode,
1450                                                      (i == DMA_TX_SIZE - 1));
1451         priv->dirty_tx = 0;
1452         priv->cur_tx = 0;
1453         netdev_reset_queue(priv->dev);
1454         priv->hw->dma->start_tx(priv->ioaddr);
1455
1456         priv->dev->stats.tx_errors++;
1457         netif_wake_queue(priv->dev);
1458 }
1459
1460 /**
1461  * stmmac_dma_interrupt - DMA ISR
1462  * @priv: driver private structure
1463  * Description: this is the DMA ISR. It is called by the main ISR.
1464  * It calls the dwmac dma routine and schedule poll method in case of some
1465  * work can be done.
1466  */
1467 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1468 {
1469         int status;
1470         int rxfifosz = priv->plat->rx_fifo_size;
1471
1472         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1473         if (likely((status & handle_rx)) || (status & handle_tx)) {
1474                 if (likely(napi_schedule_prep(&priv->napi))) {
1475                         stmmac_disable_dma_irq(priv);
1476                         __napi_schedule(&priv->napi);
1477                 }
1478         }
1479         if (unlikely(status & tx_hard_error_bump_tc)) {
1480                 /* Try to bump up the dma threshold on this failure */
1481                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1482                     (tc <= 256)) {
1483                         tc += 64;
1484                         if (priv->plat->force_thresh_dma_mode)
1485                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1486                                                         rxfifosz);
1487                         else
1488                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1489                                                         SF_DMA_MODE, rxfifosz);
1490                         priv->xstats.threshold = tc;
1491                 }
1492         } else if (unlikely(status == tx_hard_error))
1493                 stmmac_tx_err(priv);
1494 }
1495
1496 /**
1497  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1498  * @priv: driver private structure
1499  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1500  */
1501 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1502 {
1503         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1504                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1505
1506         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1507                 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1508                 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1509         } else {
1510                 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1511                 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1512         }
1513
1514         dwmac_mmc_intr_all_mask(priv->mmcaddr);
1515
1516         if (priv->dma_cap.rmon) {
1517                 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1518                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1519         } else
1520                 pr_info(" No MAC Management Counters available\n");
1521 }
1522
1523 /**
1524  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1525  * @priv: driver private structure
1526  * Description: select the Enhanced/Alternate or Normal descriptors.
1527  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1528  * supported by the HW capability register.
1529  */
1530 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1531 {
1532         if (priv->plat->enh_desc) {
1533                 pr_info(" Enhanced/Alternate descriptors\n");
1534
1535                 /* GMAC older than 3.50 has no extended descriptors */
1536                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1537                         pr_info("\tEnabled extended descriptors\n");
1538                         priv->extend_desc = 1;
1539                 } else
1540                         pr_warn("Extended descriptors not supported\n");
1541
1542                 priv->hw->desc = &enh_desc_ops;
1543         } else {
1544                 pr_info(" Normal descriptors\n");
1545                 priv->hw->desc = &ndesc_ops;
1546         }
1547 }
1548
1549 /**
1550  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1551  * @priv: driver private structure
1552  * Description:
1553  *  new GMAC chip generations have a new register to indicate the
1554  *  presence of the optional feature/functions.
1555  *  This can be also used to override the value passed through the
1556  *  platform and necessary for old MAC10/100 and GMAC chips.
1557  */
1558 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1559 {
1560         u32 ret = 0;
1561
1562         if (priv->hw->dma->get_hw_feature) {
1563                 priv->hw->dma->get_hw_feature(priv->ioaddr,
1564                                               &priv->dma_cap);
1565                 ret = 1;
1566         }
1567
1568         return ret;
1569 }
1570
1571 /**
1572  * stmmac_check_ether_addr - check if the MAC addr is valid
1573  * @priv: driver private structure
1574  * Description:
1575  * it is to verify if the MAC address is valid, in case of failures it
1576  * generates a random MAC address
1577  */
1578 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1579 {
1580         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1581                 priv->hw->mac->get_umac_addr(priv->hw,
1582                                              priv->dev->dev_addr, 0);
1583                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1584                         eth_hw_addr_random(priv->dev);
1585                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1586                         priv->dev->dev_addr);
1587         }
1588 }
1589
1590 /**
1591  * stmmac_init_dma_engine - DMA init.
1592  * @priv: driver private structure
1593  * Description:
1594  * It inits the DMA invoking the specific MAC/GMAC callback.
1595  * Some DMA parameters can be passed from the platform;
1596  * in case of these are not passed a default is kept for the MAC or GMAC.
1597  */
1598 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1599 {
1600         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1601         int mixed_burst = 0;
1602         int atds = 0;
1603         int ret = 0;
1604
1605         if (priv->plat->dma_cfg) {
1606                 pbl = priv->plat->dma_cfg->pbl;
1607                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1608                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1609                 aal = priv->plat->dma_cfg->aal;
1610         }
1611
1612         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1613                 atds = 1;
1614
1615         ret = priv->hw->dma->reset(priv->ioaddr);
1616         if (ret) {
1617                 dev_err(priv->device, "Failed to reset the dma\n");
1618                 return ret;
1619         }
1620
1621         priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1622                             aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1623
1624         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1625                 priv->rx_tail_addr = priv->dma_rx_phy +
1626                             (DMA_RX_SIZE * sizeof(struct dma_desc));
1627                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1628                                                STMMAC_CHAN0);
1629
1630                 priv->tx_tail_addr = priv->dma_tx_phy +
1631                             (DMA_TX_SIZE * sizeof(struct dma_desc));
1632                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1633                                                STMMAC_CHAN0);
1634         }
1635
1636         if (priv->plat->axi && priv->hw->dma->axi)
1637                 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1638
1639         return ret;
1640 }
1641
1642 /**
1643  * stmmac_tx_timer - mitigation sw timer for tx.
1644  * @data: data pointer
1645  * Description:
1646  * This is the timer handler to directly invoke the stmmac_tx_clean.
1647  */
1648 static void stmmac_tx_timer(unsigned long data)
1649 {
1650         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1651
1652         stmmac_tx_clean(priv);
1653 }
1654
1655 /**
1656  * stmmac_init_tx_coalesce - init tx mitigation options.
1657  * @priv: driver private structure
1658  * Description:
1659  * This inits the transmit coalesce parameters: i.e. timer rate,
1660  * timer handler and default threshold used for enabling the
1661  * interrupt on completion bit.
1662  */
1663 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1664 {
1665         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1666         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1667         init_timer(&priv->txtimer);
1668         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1669         priv->txtimer.data = (unsigned long)priv;
1670         priv->txtimer.function = stmmac_tx_timer;
1671         add_timer(&priv->txtimer);
1672 }
1673
1674 /**
1675  * stmmac_hw_setup - setup mac in a usable state.
1676  *  @dev : pointer to the device structure.
1677  *  Description:
1678  *  this is the main function to setup the HW in a usable state because the
1679  *  dma engine is reset, the core registers are configured (e.g. AXI,
1680  *  Checksum features, timers). The DMA is ready to start receiving and
1681  *  transmitting.
1682  *  Return value:
1683  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1684  *  file on failure.
1685  */
1686 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1687 {
1688         struct stmmac_priv *priv = netdev_priv(dev);
1689         int ret;
1690
1691         /* DMA initialization and SW reset */
1692         ret = stmmac_init_dma_engine(priv);
1693         if (ret < 0) {
1694                 pr_err("%s: DMA engine initialization failed\n", __func__);
1695                 return ret;
1696         }
1697
1698         /* Copy the MAC addr into the HW  */
1699         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1700
1701         /* If required, perform hw setup of the bus. */
1702         if (priv->plat->bus_setup)
1703                 priv->plat->bus_setup(priv->ioaddr);
1704
1705         /* PS and related bits will be programmed according to the speed */
1706         if (priv->hw->pcs) {
1707                 int speed = priv->plat->mac_port_sel_speed;
1708
1709                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1710                     (speed == SPEED_1000)) {
1711                         priv->hw->ps = speed;
1712                 } else {
1713                         dev_warn(priv->device, "invalid port speed\n");
1714                         priv->hw->ps = 0;
1715                 }
1716         }
1717
1718         /* Initialize the MAC Core */
1719         priv->hw->mac->core_init(priv->hw, dev->mtu);
1720
1721         ret = priv->hw->mac->rx_ipc(priv->hw);
1722         if (!ret) {
1723                 pr_warn(" RX IPC Checksum Offload disabled\n");
1724                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1725                 priv->hw->rx_csum = 0;
1726         }
1727
1728         /* Enable the MAC Rx/Tx */
1729         if (priv->synopsys_id >= DWMAC_CORE_4_00)
1730                 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1731         else
1732                 stmmac_set_mac(priv->ioaddr, true);
1733
1734         /* Set the HW DMA mode and the COE */
1735         stmmac_dma_operation_mode(priv);
1736
1737         stmmac_mmc_setup(priv);
1738
1739         if (init_ptp) {
1740                 ret = stmmac_init_ptp(priv);
1741                 if (ret)
1742                         netdev_warn(priv->dev, "fail to init PTP.\n");
1743         }
1744
1745 #ifdef CONFIG_DEBUG_FS
1746         ret = stmmac_init_fs(dev);
1747         if (ret < 0)
1748                 pr_warn("%s: failed debugFS registration\n", __func__);
1749 #endif
1750         /* Dump DMA/MAC registers */
1751         if (netif_msg_hw(priv)) {
1752                 priv->hw->mac->dump_regs(priv->hw);
1753                 priv->hw->dma->dump_regs(priv->ioaddr);
1754         }
1755         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1756
1757         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1758                 priv->rx_riwt = MAX_DMA_RIWT;
1759                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1760         }
1761
1762         if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1763                 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1764
1765         /*  set TX ring length */
1766         if (priv->hw->dma->set_tx_ring_len)
1767                 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1768                                                (DMA_TX_SIZE - 1));
1769         /*  set RX ring length */
1770         if (priv->hw->dma->set_rx_ring_len)
1771                 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1772                                                (DMA_RX_SIZE - 1));
1773         /* Enable TSO */
1774         if (priv->tso)
1775                 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1776
1777         /* Start the ball rolling... */
1778         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1779         priv->hw->dma->start_tx(priv->ioaddr);
1780         priv->hw->dma->start_rx(priv->ioaddr);
1781
1782         return 0;
1783 }
1784
1785 /**
1786  *  stmmac_open - open entry point of the driver
1787  *  @dev : pointer to the device structure.
1788  *  Description:
1789  *  This function is the open entry point of the driver.
1790  *  Return value:
1791  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1792  *  file on failure.
1793  */
1794 static int stmmac_open(struct net_device *dev)
1795 {
1796         struct stmmac_priv *priv = netdev_priv(dev);
1797         int ret;
1798
1799         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1800             priv->hw->pcs != STMMAC_PCS_TBI &&
1801             priv->hw->pcs != STMMAC_PCS_RTBI) {
1802                 ret = stmmac_init_phy(dev);
1803                 if (ret) {
1804                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1805                                __func__, ret);
1806                         return ret;
1807                 }
1808         }
1809
1810         /* Extra statistics */
1811         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1812         priv->xstats.threshold = tc;
1813
1814         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1815         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1816         priv->mss = 0;
1817
1818         ret = alloc_dma_desc_resources(priv);
1819         if (ret < 0) {
1820                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1821                 goto dma_desc_error;
1822         }
1823
1824         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1825         if (ret < 0) {
1826                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1827                 goto init_error;
1828         }
1829
1830         ret = stmmac_hw_setup(dev, true);
1831         if (ret < 0) {
1832                 pr_err("%s: Hw setup failed\n", __func__);
1833                 goto init_error;
1834         }
1835
1836         stmmac_init_tx_coalesce(priv);
1837
1838         if (priv->phydev)
1839                 phy_start(priv->phydev);
1840
1841         /* Request the IRQ lines */
1842         ret = request_irq(dev->irq, stmmac_interrupt,
1843                           IRQF_SHARED, dev->name, dev);
1844         if (unlikely(ret < 0)) {
1845                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1846                        __func__, dev->irq, ret);
1847                 goto init_error;
1848         }
1849
1850         /* Request the Wake IRQ in case of another line is used for WoL */
1851         if (priv->wol_irq != dev->irq) {
1852                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1853                                   IRQF_SHARED, dev->name, dev);
1854                 if (unlikely(ret < 0)) {
1855                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1856                                __func__, priv->wol_irq, ret);
1857                         goto wolirq_error;
1858                 }
1859         }
1860
1861         /* Request the IRQ lines */
1862         if (priv->lpi_irq > 0) {
1863                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1864                                   dev->name, dev);
1865                 if (unlikely(ret < 0)) {
1866                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1867                                __func__, priv->lpi_irq, ret);
1868                         goto lpiirq_error;
1869                 }
1870         }
1871
1872         napi_enable(&priv->napi);
1873         netif_start_queue(dev);
1874
1875         return 0;
1876
1877 lpiirq_error:
1878         if (priv->wol_irq != dev->irq)
1879                 free_irq(priv->wol_irq, dev);
1880 wolirq_error:
1881         free_irq(dev->irq, dev);
1882
1883 init_error:
1884         free_dma_desc_resources(priv);
1885 dma_desc_error:
1886         if (priv->phydev)
1887                 phy_disconnect(priv->phydev);
1888
1889         return ret;
1890 }
1891
1892 /**
1893  *  stmmac_release - close entry point of the driver
1894  *  @dev : device pointer.
1895  *  Description:
1896  *  This is the stop entry point of the driver.
1897  */
1898 static int stmmac_release(struct net_device *dev)
1899 {
1900         struct stmmac_priv *priv = netdev_priv(dev);
1901
1902         if (priv->eee_enabled)
1903                 del_timer_sync(&priv->eee_ctrl_timer);
1904
1905         /* Stop and disconnect the PHY */
1906         if (priv->phydev) {
1907                 phy_stop(priv->phydev);
1908                 phy_disconnect(priv->phydev);
1909                 priv->phydev = NULL;
1910         }
1911
1912         netif_stop_queue(dev);
1913
1914         napi_disable(&priv->napi);
1915
1916         del_timer_sync(&priv->txtimer);
1917
1918         /* Free the IRQ lines */
1919         free_irq(dev->irq, dev);
1920         if (priv->wol_irq != dev->irq)
1921                 free_irq(priv->wol_irq, dev);
1922         if (priv->lpi_irq > 0)
1923                 free_irq(priv->lpi_irq, dev);
1924
1925         /* Stop TX/RX DMA and clear the descriptors */
1926         priv->hw->dma->stop_tx(priv->ioaddr);
1927         priv->hw->dma->stop_rx(priv->ioaddr);
1928
1929         /* Release and free the Rx/Tx resources */
1930         free_dma_desc_resources(priv);
1931
1932         /* Disable the MAC Rx/Tx */
1933         stmmac_set_mac(priv->ioaddr, false);
1934
1935         netif_carrier_off(dev);
1936
1937 #ifdef CONFIG_DEBUG_FS
1938         stmmac_exit_fs(dev);
1939 #endif
1940
1941         stmmac_release_ptp(priv);
1942
1943         return 0;
1944 }
1945
1946 /**
1947  *  stmmac_tso_allocator - close entry point of the driver
1948  *  @priv: driver private structure
1949  *  @des: buffer start address
1950  *  @total_len: total length to fill in descriptors
1951  *  @last_segmant: condition for the last descriptor
1952  *  Description:
1953  *  This function fills descriptor and request new descriptors according to
1954  *  buffer length to fill
1955  */
1956 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1957                                  int total_len, bool last_segment)
1958 {
1959         struct dma_desc *desc;
1960         int tmp_len;
1961         u32 buff_size;
1962
1963         tmp_len = total_len;
1964
1965         while (tmp_len > 0) {
1966                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
1967                 desc = priv->dma_tx + priv->cur_tx;
1968
1969                 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
1970                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
1971                             TSO_MAX_BUFF_SIZE : tmp_len;
1972
1973                 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
1974                         0, 1,
1975                         (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
1976                         0, 0);
1977
1978                 tmp_len -= TSO_MAX_BUFF_SIZE;
1979         }
1980 }
1981
1982 /**
1983  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1984  *  @skb : the socket buffer
1985  *  @dev : device pointer
1986  *  Description: this is the transmit function that is called on TSO frames
1987  *  (support available on GMAC4 and newer chips).
1988  *  Diagram below show the ring programming in case of TSO frames:
1989  *
1990  *  First Descriptor
1991  *   --------
1992  *   | DES0 |---> buffer1 = L2/L3/L4 header
1993  *   | DES1 |---> TCP Payload (can continue on next descr...)
1994  *   | DES2 |---> buffer 1 and 2 len
1995  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1996  *   --------
1997  *      |
1998  *     ...
1999  *      |
2000  *   --------
2001  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2002  *   | DES1 | --|
2003  *   | DES2 | --> buffer 1 and 2 len
2004  *   | DES3 |
2005  *   --------
2006  *
2007  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2008  */
2009 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2010 {
2011         u32 pay_len, mss;
2012         int tmp_pay_len = 0;
2013         struct stmmac_priv *priv = netdev_priv(dev);
2014         int nfrags = skb_shinfo(skb)->nr_frags;
2015         unsigned int first_entry, des;
2016         struct dma_desc *desc, *first, *mss_desc = NULL;
2017         u8 proto_hdr_len;
2018         int i;
2019
2020         spin_lock(&priv->tx_lock);
2021
2022         /* Compute header lengths */
2023         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2024
2025         /* Desc availability based on threshold should be enough safe */
2026         if (unlikely(stmmac_tx_avail(priv) <
2027                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2028                 if (!netif_queue_stopped(dev)) {
2029                         netif_stop_queue(dev);
2030                         /* This is a hard error, log it. */
2031                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2032                 }
2033                 spin_unlock(&priv->tx_lock);
2034                 return NETDEV_TX_BUSY;
2035         }
2036
2037         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2038
2039         mss = skb_shinfo(skb)->gso_size;
2040
2041         /* set new MSS value if needed */
2042         if (mss != priv->mss) {
2043                 mss_desc = priv->dma_tx + priv->cur_tx;
2044                 priv->hw->desc->set_mss(mss_desc, mss);
2045                 priv->mss = mss;
2046                 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2047         }
2048
2049         if (netif_msg_tx_queued(priv)) {
2050                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2051                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2052                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2053                         skb->data_len);
2054         }
2055
2056         first_entry = priv->cur_tx;
2057
2058         desc = priv->dma_tx + first_entry;
2059         first = desc;
2060
2061         /* first descriptor: fill Headers on Buf1 */
2062         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2063                              DMA_TO_DEVICE);
2064         if (dma_mapping_error(priv->device, des))
2065                 goto dma_map_err;
2066
2067         priv->tx_skbuff_dma[first_entry].buf = des;
2068         priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2069         priv->tx_skbuff[first_entry] = skb;
2070
2071         first->des0 = cpu_to_le32(des);
2072
2073         /* Fill start of payload in buff2 of first descriptor */
2074         if (pay_len)
2075                 first->des1 = cpu_to_le32(des + proto_hdr_len);
2076
2077         /* If needed take extra descriptors to fill the remaining payload */
2078         tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2079
2080         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2081
2082         /* Prepare fragments */
2083         for (i = 0; i < nfrags; i++) {
2084                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2085
2086                 des = skb_frag_dma_map(priv->device, frag, 0,
2087                                        skb_frag_size(frag),
2088                                        DMA_TO_DEVICE);
2089
2090                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2091                                      (i == nfrags - 1));
2092
2093                 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2094                 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2095                 priv->tx_skbuff[priv->cur_tx] = NULL;
2096                 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2097         }
2098
2099         priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2100
2101         priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2102
2103         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2104                 if (netif_msg_hw(priv))
2105                         pr_debug("%s: stop transmitted packets\n", __func__);
2106                 netif_stop_queue(dev);
2107         }
2108
2109         dev->stats.tx_bytes += skb->len;
2110         priv->xstats.tx_tso_frames++;
2111         priv->xstats.tx_tso_nfrags += nfrags;
2112
2113         /* Manage tx mitigation */
2114         priv->tx_count_frames += nfrags + 1;
2115         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2116                 mod_timer(&priv->txtimer,
2117                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2118         } else {
2119                 priv->tx_count_frames = 0;
2120                 priv->hw->desc->set_tx_ic(desc);
2121                 priv->xstats.tx_set_ic_bit++;
2122         }
2123
2124         if (!priv->hwts_tx_en)
2125                 skb_tx_timestamp(skb);
2126
2127         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2128                      priv->hwts_tx_en)) {
2129                 /* declare that device is doing timestamping */
2130                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2131                 priv->hw->desc->enable_tx_timestamp(first);
2132         }
2133
2134         /* Complete the first descriptor before granting the DMA */
2135         priv->hw->desc->prepare_tso_tx_desc(first, 1,
2136                         proto_hdr_len,
2137                         pay_len,
2138                         1, priv->tx_skbuff_dma[first_entry].last_segment,
2139                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2140
2141         /* If context desc is used to change MSS */
2142         if (mss_desc) {
2143                 /* Make sure that first descriptor has been completely
2144                  * written, including its own bit. This is because MSS is
2145                  * actually before first descriptor, so we need to make
2146                  * sure that MSS's own bit is the last thing written.
2147                  */
2148                 dma_wmb();
2149                 priv->hw->desc->set_tx_owner(mss_desc);
2150         }
2151
2152         /* The own bit must be the latest setting done when prepare the
2153          * descriptor and then barrier is needed to make sure that
2154          * all is coherent before granting the DMA engine.
2155          */
2156         smp_wmb();
2157
2158         if (netif_msg_pktdata(priv)) {
2159                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2160                         __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2161                         priv->cur_tx, first, nfrags);
2162
2163                 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2164                                              0);
2165
2166                 pr_info(">>> frame to be transmitted: ");
2167                 print_pkt(skb->data, skb_headlen(skb));
2168         }
2169
2170         netdev_sent_queue(dev, skb->len);
2171
2172         priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2173                                        STMMAC_CHAN0);
2174
2175         spin_unlock(&priv->tx_lock);
2176         return NETDEV_TX_OK;
2177
2178 dma_map_err:
2179         spin_unlock(&priv->tx_lock);
2180         dev_err(priv->device, "Tx dma map failed\n");
2181         dev_kfree_skb(skb);
2182         priv->dev->stats.tx_dropped++;
2183         return NETDEV_TX_OK;
2184 }
2185
2186 /**
2187  *  stmmac_xmit - Tx entry point of the driver
2188  *  @skb : the socket buffer
2189  *  @dev : device pointer
2190  *  Description : this is the tx entry point of the driver.
2191  *  It programs the chain or the ring and supports oversized frames
2192  *  and SG feature.
2193  */
2194 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2195 {
2196         struct stmmac_priv *priv = netdev_priv(dev);
2197         unsigned int nopaged_len = skb_headlen(skb);
2198         int i, csum_insertion = 0, is_jumbo = 0;
2199         int nfrags = skb_shinfo(skb)->nr_frags;
2200         int entry;
2201         unsigned int first_entry;
2202         struct dma_desc *desc, *first;
2203         unsigned int enh_desc;
2204         unsigned int des;
2205
2206         /* Manage oversized TCP frames for GMAC4 device */
2207         if (skb_is_gso(skb) && priv->tso) {
2208                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2209                         return stmmac_tso_xmit(skb, dev);
2210         }
2211
2212         spin_lock(&priv->tx_lock);
2213
2214         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2215                 spin_unlock(&priv->tx_lock);
2216                 if (!netif_queue_stopped(dev)) {
2217                         netif_stop_queue(dev);
2218                         /* This is a hard error, log it. */
2219                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
2220                 }
2221                 return NETDEV_TX_BUSY;
2222         }
2223
2224         if (priv->tx_path_in_lpi_mode)
2225                 stmmac_disable_eee_mode(priv);
2226
2227         entry = priv->cur_tx;
2228         first_entry = entry;
2229
2230         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2231
2232         if (likely(priv->extend_desc))
2233                 desc = (struct dma_desc *)(priv->dma_etx + entry);
2234         else
2235                 desc = priv->dma_tx + entry;
2236
2237         first = desc;
2238
2239         priv->tx_skbuff[first_entry] = skb;
2240
2241         enh_desc = priv->plat->enh_desc;
2242         /* To program the descriptors according to the size of the frame */
2243         if (enh_desc)
2244                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2245
2246         if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2247                                          DWMAC_CORE_4_00)) {
2248                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2249                 if (unlikely(entry < 0))
2250                         goto dma_map_err;
2251         }
2252
2253         for (i = 0; i < nfrags; i++) {
2254                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2255                 int len = skb_frag_size(frag);
2256                 bool last_segment = (i == (nfrags - 1));
2257
2258                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2259
2260                 if (likely(priv->extend_desc))
2261                         desc = (struct dma_desc *)(priv->dma_etx + entry);
2262                 else
2263                         desc = priv->dma_tx + entry;
2264
2265                 des = skb_frag_dma_map(priv->device, frag, 0, len,
2266                                        DMA_TO_DEVICE);
2267                 if (dma_mapping_error(priv->device, des))
2268                         goto dma_map_err; /* should reuse desc w/o issues */
2269
2270                 priv->tx_skbuff[entry] = NULL;
2271
2272                 priv->tx_skbuff_dma[entry].buf = des;
2273                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2274                         desc->des0 = cpu_to_le32(des);
2275                 else
2276                         desc->des2 = cpu_to_le32(des);
2277
2278                 priv->tx_skbuff_dma[entry].map_as_page = true;
2279                 priv->tx_skbuff_dma[entry].len = len;
2280                 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2281
2282                 /* Prepare the descriptor and set the own bit too */
2283                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2284                                                 priv->mode, 1, last_segment);
2285         }
2286
2287         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2288
2289         priv->cur_tx = entry;
2290
2291         if (netif_msg_pktdata(priv)) {
2292                 void *tx_head;
2293
2294                 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2295                          __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2296                          entry, first, nfrags);
2297
2298                 if (priv->extend_desc)
2299                         tx_head = (void *)priv->dma_etx;
2300                 else
2301                         tx_head = (void *)priv->dma_tx;
2302
2303                 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2304
2305                 pr_debug(">>> frame to be transmitted: ");
2306                 print_pkt(skb->data, skb->len);
2307         }
2308
2309         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2310                 if (netif_msg_hw(priv))
2311                         pr_debug("%s: stop transmitted packets\n", __func__);
2312                 netif_stop_queue(dev);
2313         }
2314
2315         dev->stats.tx_bytes += skb->len;
2316
2317         /* According to the coalesce parameter the IC bit for the latest
2318          * segment is reset and the timer re-started to clean the tx status.
2319          * This approach takes care about the fragments: desc is the first
2320          * element in case of no SG.
2321          */
2322         priv->tx_count_frames += nfrags + 1;
2323         if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2324                 mod_timer(&priv->txtimer,
2325                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2326         } else {
2327                 priv->tx_count_frames = 0;
2328                 priv->hw->desc->set_tx_ic(desc);
2329                 priv->xstats.tx_set_ic_bit++;
2330         }
2331
2332         if (!priv->hwts_tx_en)
2333                 skb_tx_timestamp(skb);
2334
2335         /* Ready to fill the first descriptor and set the OWN bit w/o any
2336          * problems because all the descriptors are actually ready to be
2337          * passed to the DMA engine.
2338          */
2339         if (likely(!is_jumbo)) {
2340                 bool last_segment = (nfrags == 0);
2341
2342                 des = dma_map_single(priv->device, skb->data,
2343                                      nopaged_len, DMA_TO_DEVICE);
2344                 if (dma_mapping_error(priv->device, des))
2345                         goto dma_map_err;
2346
2347                 priv->tx_skbuff_dma[first_entry].buf = des;
2348                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2349                         first->des0 = cpu_to_le32(des);
2350                 else
2351                         first->des2 = cpu_to_le32(des);
2352
2353                 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2354                 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2355
2356                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2357                              priv->hwts_tx_en)) {
2358                         /* declare that device is doing timestamping */
2359                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2360                         priv->hw->desc->enable_tx_timestamp(first);
2361                 }
2362
2363                 /* Prepare the first descriptor setting the OWN bit too */
2364                 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2365                                                 csum_insertion, priv->mode, 1,
2366                                                 last_segment);
2367
2368                 /* The own bit must be the latest setting done when prepare the
2369                  * descriptor and then barrier is needed to make sure that
2370                  * all is coherent before granting the DMA engine.
2371                  */
2372                 smp_wmb();
2373         }
2374
2375         netdev_sent_queue(dev, skb->len);
2376
2377         if (priv->synopsys_id < DWMAC_CORE_4_00)
2378                 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2379         else
2380                 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2381                                                STMMAC_CHAN0);
2382
2383         spin_unlock(&priv->tx_lock);
2384         return NETDEV_TX_OK;
2385
2386 dma_map_err:
2387         spin_unlock(&priv->tx_lock);
2388         dev_err(priv->device, "Tx dma map failed\n");
2389         dev_kfree_skb(skb);
2390         priv->dev->stats.tx_dropped++;
2391         return NETDEV_TX_OK;
2392 }
2393
2394 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2395 {
2396         struct ethhdr *ehdr;
2397         u16 vlanid;
2398
2399         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2400             NETIF_F_HW_VLAN_CTAG_RX &&
2401             !__vlan_get_tag(skb, &vlanid)) {
2402                 /* pop the vlan tag */
2403                 ehdr = (struct ethhdr *)skb->data;
2404                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2405                 skb_pull(skb, VLAN_HLEN);
2406                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2407         }
2408 }
2409
2410
2411 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2412 {
2413         if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2414                 return 0;
2415
2416         return 1;
2417 }
2418
2419 /**
2420  * stmmac_rx_refill - refill used skb preallocated buffers
2421  * @priv: driver private structure
2422  * Description : this is to reallocate the skb for the reception process
2423  * that is based on zero-copy.
2424  */
2425 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2426 {
2427         int bfsize = priv->dma_buf_sz;
2428         unsigned int entry = priv->dirty_rx;
2429         int dirty = stmmac_rx_dirty(priv);
2430
2431         while (dirty-- > 0) {
2432                 struct dma_desc *p;
2433
2434                 if (priv->extend_desc)
2435                         p = (struct dma_desc *)(priv->dma_erx + entry);
2436                 else
2437                         p = priv->dma_rx + entry;
2438
2439                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2440                         struct sk_buff *skb;
2441
2442                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2443                         if (unlikely(!skb)) {
2444                                 /* so for a while no zero-copy! */
2445                                 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2446                                 if (unlikely(net_ratelimit()))
2447                                         dev_err(priv->device,
2448                                                 "fail to alloc skb entry %d\n",
2449                                                 entry);
2450                                 break;
2451                         }
2452
2453                         priv->rx_skbuff[entry] = skb;
2454                         priv->rx_skbuff_dma[entry] =
2455                             dma_map_single(priv->device, skb->data, bfsize,
2456                                            DMA_FROM_DEVICE);
2457                         if (dma_mapping_error(priv->device,
2458                                               priv->rx_skbuff_dma[entry])) {
2459                                 dev_err(priv->device, "Rx dma map failed\n");
2460                                 dev_kfree_skb(skb);
2461                                 break;
2462                         }
2463
2464                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2465                                 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2466                                 p->des1 = 0;
2467                         } else {
2468                                 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2469                         }
2470                         if (priv->hw->mode->refill_desc3)
2471                                 priv->hw->mode->refill_desc3(priv, p);
2472
2473                         if (priv->rx_zeroc_thresh > 0)
2474                                 priv->rx_zeroc_thresh--;
2475
2476                         if (netif_msg_rx_status(priv))
2477                                 pr_debug("\trefill entry #%d\n", entry);
2478                 }
2479                 wmb();
2480
2481                 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2482                         priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0, priv->dma_buf_sz);
2483                 else
2484                         priv->hw->desc->set_rx_owner(p);
2485
2486                 wmb();
2487
2488                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2489         }
2490         priv->dirty_rx = entry;
2491 }
2492
2493 /**
2494  * stmmac_rx - manage the receive process
2495  * @priv: driver private structure
2496  * @limit: napi bugget.
2497  * Description :  this the function called by the napi poll method.
2498  * It gets all the frames inside the ring.
2499  */
2500 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2501 {
2502         unsigned int next_entry = priv->cur_rx;
2503         unsigned int count = 0;
2504         int coe = priv->hw->rx_csum;
2505
2506         if (netif_msg_rx_status(priv)) {
2507                 void *rx_head;
2508
2509                 pr_info(">>>>>> %s: descriptor ring:\n", __func__);
2510                 if (priv->extend_desc)
2511                         rx_head = (void *)priv->dma_erx;
2512                 else
2513                         rx_head = (void *)priv->dma_rx;
2514
2515                 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2516         }
2517         while (count < limit) {
2518                 int entry, status;
2519                 struct dma_desc *p;
2520                 struct dma_desc *np;
2521
2522                 entry = next_entry;
2523
2524                 if (priv->extend_desc)
2525                         p = (struct dma_desc *)(priv->dma_erx + entry);
2526                 else
2527                         p = priv->dma_rx + entry;
2528
2529                 /* read the status of the incoming frame */
2530                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2531                                                    &priv->xstats, p);
2532                 /* check if managed by the DMA otherwise go ahead */
2533                 if (unlikely(status & dma_own))
2534                         break;
2535
2536                 count++;
2537
2538                 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2539                 next_entry = priv->cur_rx;
2540
2541                 if (priv->extend_desc)
2542                         np = (struct dma_desc *)(priv->dma_erx + next_entry);
2543                 else
2544                         np = priv->dma_rx + next_entry;
2545
2546                 prefetch(np);
2547
2548                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2549                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2550                                                            &priv->xstats,
2551                                                            priv->dma_erx +
2552                                                            entry);
2553                 if (unlikely(status == discard_frame)) {
2554                         priv->dev->stats.rx_errors++;
2555                         if (priv->hwts_rx_en && !priv->extend_desc) {
2556                                 /* DESC2 & DESC3 will be overwitten by device
2557                                  * with timestamp value, hence reinitialize
2558                                  * them in stmmac_rx_refill() function so that
2559                                  * device can reuse it.
2560                                  */
2561                                 priv->rx_skbuff[entry] = NULL;
2562                                 dma_unmap_single(priv->device,
2563                                                  priv->rx_skbuff_dma[entry],
2564                                                  priv->dma_buf_sz,
2565                                                  DMA_FROM_DEVICE);
2566                         }
2567                 } else {
2568                         struct sk_buff *skb;
2569                         int frame_len;
2570                         unsigned int des;
2571
2572                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2573                                 des = le32_to_cpu(p->des0);
2574                         else
2575                                 des = le32_to_cpu(p->des2);
2576
2577                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2578
2579                         /*  If frame length is greather than skb buffer size
2580                          *  (preallocated during init) then the packet is
2581                          *  ignored
2582                          */
2583                         if (frame_len > priv->dma_buf_sz) {
2584                                 pr_err("%s: len %d larger than size (%d)\n",
2585                                        priv->dev->name, frame_len,
2586                                        priv->dma_buf_sz);
2587                                 priv->dev->stats.rx_length_errors++;
2588                                 continue;
2589                         }
2590
2591                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2592                          * Type frames (LLC/LLC-SNAP)
2593                          */
2594                         if (unlikely(status != llc_snap))
2595                                 frame_len -= ETH_FCS_LEN;
2596
2597                         if (netif_msg_rx_status(priv)) {
2598                                 pr_info("\tdesc: %p [entry %d] buff=0x%x\n",
2599                                         p, entry, des);
2600                                 if (frame_len > ETH_FRAME_LEN)
2601                                         pr_debug("\tframe size %d, COE: %d\n",
2602                                                  frame_len, status);
2603                         }
2604
2605                         /* The zero-copy is always used for all the sizes
2606                          * in case of GMAC4 because it needs
2607                          * to refill the used descriptors, always.
2608                          */
2609                         if (unlikely(!priv->plat->has_gmac4 &&
2610                                      ((frame_len < priv->rx_copybreak) ||
2611                                      stmmac_rx_threshold_count(priv)))) {
2612                                 skb = netdev_alloc_skb_ip_align(priv->dev,
2613                                                                 frame_len);
2614                                 if (unlikely(!skb)) {
2615                                         if (net_ratelimit())
2616                                                 dev_warn(priv->device,
2617                                                          "packet dropped\n");
2618                                         priv->dev->stats.rx_dropped++;
2619                                         continue;
2620                                 }
2621
2622                                 dma_sync_single_for_cpu(priv->device,
2623                                                         priv->rx_skbuff_dma
2624                                                         [entry], frame_len,
2625                                                         DMA_FROM_DEVICE);
2626                                 skb_copy_to_linear_data(skb,
2627                                                         priv->
2628                                                         rx_skbuff[entry]->data,
2629                                                         frame_len);
2630
2631                                 skb_put(skb, frame_len);
2632                                 dma_sync_single_for_device(priv->device,
2633                                                            priv->rx_skbuff_dma
2634                                                            [entry], frame_len,
2635                                                            DMA_FROM_DEVICE);
2636                         } else {
2637                                 skb = priv->rx_skbuff[entry];
2638                                 if (unlikely(!skb)) {
2639                                         pr_err("%s: Inconsistent Rx chain\n",
2640                                                priv->dev->name);
2641                                         priv->dev->stats.rx_dropped++;
2642                                         continue;
2643                                 }
2644                                 prefetch(skb->data - NET_IP_ALIGN);
2645                                 priv->rx_skbuff[entry] = NULL;
2646                                 priv->rx_zeroc_thresh++;
2647
2648                                 skb_put(skb, frame_len);
2649                                 dma_unmap_single(priv->device,
2650                                                  priv->rx_skbuff_dma[entry],
2651                                                  priv->dma_buf_sz,
2652                                                  DMA_FROM_DEVICE);
2653                         }
2654
2655                         if (netif_msg_pktdata(priv)) {
2656                                 pr_debug("frame received (%dbytes)", frame_len);
2657                                 print_pkt(skb->data, frame_len);
2658                         }
2659
2660                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
2661
2662                         stmmac_rx_vlan(priv->dev, skb);
2663
2664                         skb->protocol = eth_type_trans(skb, priv->dev);
2665
2666                         if (unlikely(!coe))
2667                                 skb_checksum_none_assert(skb);
2668                         else
2669                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2670
2671                         napi_gro_receive(&priv->napi, skb);
2672
2673                         priv->dev->stats.rx_packets++;
2674                         priv->dev->stats.rx_bytes += frame_len;
2675                 }
2676         }
2677
2678         stmmac_rx_refill(priv);
2679
2680         priv->xstats.rx_pkt_n += count;
2681
2682         return count;
2683 }
2684
2685 /**
2686  *  stmmac_poll - stmmac poll method (NAPI)
2687  *  @napi : pointer to the napi structure.
2688  *  @budget : maximum number of packets that the current CPU can receive from
2689  *            all interfaces.
2690  *  Description :
2691  *  To look at the incoming frames and clear the tx resources.
2692  */
2693 static int stmmac_poll(struct napi_struct *napi, int budget)
2694 {
2695         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2696         int work_done = 0;
2697
2698         priv->xstats.napi_poll++;
2699         stmmac_tx_clean(priv);
2700
2701         work_done = stmmac_rx(priv, budget);
2702         if (work_done < budget) {
2703                 napi_complete(napi);
2704                 stmmac_enable_dma_irq(priv);
2705         }
2706         return work_done;
2707 }
2708
2709 /**
2710  *  stmmac_tx_timeout
2711  *  @dev : Pointer to net device structure
2712  *  Description: this function is called when a packet transmission fails to
2713  *   complete within a reasonable time. The driver will mark the error in the
2714  *   netdev structure and arrange for the device to be reset to a sane state
2715  *   in order to transmit a new packet.
2716  */
2717 static void stmmac_tx_timeout(struct net_device *dev)
2718 {
2719         struct stmmac_priv *priv = netdev_priv(dev);
2720
2721         /* Clear Tx resources and restart transmitting again */
2722         stmmac_tx_err(priv);
2723 }
2724
2725 /**
2726  *  stmmac_set_rx_mode - entry point for multicast addressing
2727  *  @dev : pointer to the device structure
2728  *  Description:
2729  *  This function is a driver entry point which gets called by the kernel
2730  *  whenever multicast addresses must be enabled/disabled.
2731  *  Return value:
2732  *  void.
2733  */
2734 static void stmmac_set_rx_mode(struct net_device *dev)
2735 {
2736         struct stmmac_priv *priv = netdev_priv(dev);
2737
2738         priv->hw->mac->set_filter(priv->hw, dev);
2739 }
2740
2741 /**
2742  *  stmmac_change_mtu - entry point to change MTU size for the device.
2743  *  @dev : device pointer.
2744  *  @new_mtu : the new MTU size for the device.
2745  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2746  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2747  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2748  *  Return value:
2749  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2750  *  file on failure.
2751  */
2752 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2753 {
2754         struct stmmac_priv *priv = netdev_priv(dev);
2755         int max_mtu;
2756
2757         if (netif_running(dev)) {
2758                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2759                 return -EBUSY;
2760         }
2761
2762         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2763                 max_mtu = JUMBO_LEN;
2764         else
2765                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2766
2767         if (priv->plat->maxmtu < max_mtu)
2768                 max_mtu = priv->plat->maxmtu;
2769
2770         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2771                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2772                 return -EINVAL;
2773         }
2774
2775         dev->mtu = new_mtu;
2776
2777         netdev_update_features(dev);
2778
2779         return 0;
2780 }
2781
2782 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2783                                              netdev_features_t features)
2784 {
2785         struct stmmac_priv *priv = netdev_priv(dev);
2786
2787         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2788                 features &= ~NETIF_F_RXCSUM;
2789
2790         if (!priv->plat->tx_coe)
2791                 features &= ~NETIF_F_CSUM_MASK;
2792
2793         /* Some GMAC devices have a bugged Jumbo frame support that
2794          * needs to have the Tx COE disabled for oversized frames
2795          * (due to limited buffer sizes). In this case we disable
2796          * the TX csum insertionin the TDES and not use SF.
2797          */
2798         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2799                 features &= ~NETIF_F_CSUM_MASK;
2800
2801         /* Disable tso if asked by ethtool */
2802         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2803                 if (features & NETIF_F_TSO)
2804                         priv->tso = true;
2805                 else
2806                         priv->tso = false;
2807         }
2808
2809         return features;
2810 }
2811
2812 static int stmmac_set_features(struct net_device *netdev,
2813                                netdev_features_t features)
2814 {
2815         struct stmmac_priv *priv = netdev_priv(netdev);
2816
2817         /* Keep the COE Type in case of csum is supporting */
2818         if (features & NETIF_F_RXCSUM)
2819                 priv->hw->rx_csum = priv->plat->rx_coe;
2820         else
2821                 priv->hw->rx_csum = 0;
2822         /* No check needed because rx_coe has been set before and it will be
2823          * fixed in case of issue.
2824          */
2825         priv->hw->mac->rx_ipc(priv->hw);
2826
2827         return 0;
2828 }
2829
2830 /**
2831  *  stmmac_interrupt - main ISR
2832  *  @irq: interrupt number.
2833  *  @dev_id: to pass the net device pointer.
2834  *  Description: this is the main driver interrupt service routine.
2835  *  It can call:
2836  *  o DMA service routine (to manage incoming frame reception and transmission
2837  *    status)
2838  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2839  *    interrupts.
2840  */
2841 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2842 {
2843         struct net_device *dev = (struct net_device *)dev_id;
2844         struct stmmac_priv *priv = netdev_priv(dev);
2845
2846         if (priv->irq_wake)
2847                 pm_wakeup_event(priv->device, 0);
2848
2849         if (unlikely(!dev)) {
2850                 pr_err("%s: invalid dev pointer\n", __func__);
2851                 return IRQ_NONE;
2852         }
2853
2854         /* To handle GMAC own interrupts */
2855         if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2856                 int status = priv->hw->mac->host_irq_status(priv->hw,
2857                                                             &priv->xstats);
2858                 if (unlikely(status)) {
2859                         /* For LPI we need to save the tx status */
2860                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2861                                 priv->tx_path_in_lpi_mode = true;
2862                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2863                                 priv->tx_path_in_lpi_mode = false;
2864                         if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2865                                 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2866                                                         priv->rx_tail_addr,
2867                                                         STMMAC_CHAN0);
2868                 }
2869
2870                 /* PCS link status */
2871                 if (priv->hw->pcs) {
2872                         if (priv->xstats.pcs_link)
2873                                 netif_carrier_on(dev);
2874                         else
2875                                 netif_carrier_off(dev);
2876                 }
2877         }
2878
2879         /* To handle DMA interrupts */
2880         stmmac_dma_interrupt(priv);
2881
2882         return IRQ_HANDLED;
2883 }
2884
2885 #ifdef CONFIG_NET_POLL_CONTROLLER
2886 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2887  * to allow network I/O with interrupts disabled.
2888  */
2889 static void stmmac_poll_controller(struct net_device *dev)
2890 {
2891         disable_irq(dev->irq);
2892         stmmac_interrupt(dev->irq, dev);
2893         enable_irq(dev->irq);
2894 }
2895 #endif
2896
2897 /**
2898  *  stmmac_ioctl - Entry point for the Ioctl
2899  *  @dev: Device pointer.
2900  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2901  *  a proprietary structure used to pass information to the driver.
2902  *  @cmd: IOCTL command
2903  *  Description:
2904  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2905  */
2906 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2907 {
2908         struct stmmac_priv *priv = netdev_priv(dev);
2909         int ret = -EOPNOTSUPP;
2910
2911         if (!netif_running(dev))
2912                 return -EINVAL;
2913
2914         switch (cmd) {
2915         case SIOCGMIIPHY:
2916         case SIOCGMIIREG:
2917         case SIOCSMIIREG:
2918                 if (!priv->phydev)
2919                         return -EINVAL;
2920                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2921                 break;
2922         case SIOCSHWTSTAMP:
2923                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2924                 break;
2925         default:
2926                 break;
2927         }
2928
2929         return ret;
2930 }
2931
2932 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
2933 {
2934         struct stmmac_priv *priv = netdev_priv(ndev);
2935         int ret = 0;
2936
2937         ret = eth_mac_addr(ndev, addr);
2938         if (ret)
2939                 return ret;
2940
2941         priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);
2942
2943         return ret;
2944 }
2945
2946 #ifdef CONFIG_DEBUG_FS
2947 static struct dentry *stmmac_fs_dir;
2948
2949 static void sysfs_display_ring(void *head, int size, int extend_desc,
2950                                struct seq_file *seq)
2951 {
2952         int i;
2953         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2954         struct dma_desc *p = (struct dma_desc *)head;
2955
2956         for (i = 0; i < size; i++) {
2957                 u64 x;
2958                 if (extend_desc) {
2959                         x = *(u64 *) ep;
2960                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2961                                    i, (unsigned int)virt_to_phys(ep),
2962                                    le32_to_cpu(ep->basic.des0),
2963                                    le32_to_cpu(ep->basic.des1),
2964                                    le32_to_cpu(ep->basic.des2),
2965                                    le32_to_cpu(ep->basic.des3));
2966                         ep++;
2967                 } else {
2968                         x = *(u64 *) p;
2969                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2970                                    i, (unsigned int)virt_to_phys(ep),
2971                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
2972                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
2973                         p++;
2974                 }
2975                 seq_printf(seq, "\n");
2976         }
2977 }
2978
2979 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2980 {
2981         struct net_device *dev = seq->private;
2982         struct stmmac_priv *priv = netdev_priv(dev);
2983
2984         if (priv->extend_desc) {
2985                 seq_printf(seq, "Extended RX descriptor ring:\n");
2986                 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
2987                 seq_printf(seq, "Extended TX descriptor ring:\n");
2988                 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
2989         } else {
2990                 seq_printf(seq, "RX descriptor ring:\n");
2991                 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
2992                 seq_printf(seq, "TX descriptor ring:\n");
2993                 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
2994         }
2995
2996         return 0;
2997 }
2998
2999 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3000 {
3001         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3002 }
3003
3004 static const struct file_operations stmmac_rings_status_fops = {
3005         .owner = THIS_MODULE,
3006         .open = stmmac_sysfs_ring_open,
3007         .read = seq_read,
3008         .llseek = seq_lseek,
3009         .release = single_release,
3010 };
3011
3012 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3013 {
3014         struct net_device *dev = seq->private;
3015         struct stmmac_priv *priv = netdev_priv(dev);
3016
3017         if (!priv->hw_cap_support) {
3018                 seq_printf(seq, "DMA HW features not supported\n");
3019                 return 0;
3020         }
3021
3022         seq_printf(seq, "==============================\n");
3023         seq_printf(seq, "\tDMA HW features\n");
3024         seq_printf(seq, "==============================\n");
3025
3026         seq_printf(seq, "\t10/100 Mbps %s\n",
3027                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3028         seq_printf(seq, "\t1000 Mbps %s\n",
3029                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3030         seq_printf(seq, "\tHalf duple %s\n",
3031                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3032         seq_printf(seq, "\tHash Filter: %s\n",
3033                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3034         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3035                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3036         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
3037                    (priv->dma_cap.pcs) ? "Y" : "N");
3038         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3039                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3040         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3041                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3042         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3043                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3044         seq_printf(seq, "\tRMON module: %s\n",
3045                    (priv->dma_cap.rmon) ? "Y" : "N");
3046         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3047                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3048         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
3049                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3050         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3051                    (priv->dma_cap.eee) ? "Y" : "N");
3052         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3053         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3054                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3055         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3056                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3057                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3058         } else {
3059                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3060                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3061                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3062                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3063         }
3064         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3065                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3066         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3067                    priv->dma_cap.number_rx_channel);
3068         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3069                    priv->dma_cap.number_tx_channel);
3070         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3071                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3072
3073         return 0;
3074 }
3075
3076 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3077 {
3078         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3079 }
3080
3081 static const struct file_operations stmmac_dma_cap_fops = {
3082         .owner = THIS_MODULE,
3083         .open = stmmac_sysfs_dma_cap_open,
3084         .read = seq_read,
3085         .llseek = seq_lseek,
3086         .release = single_release,
3087 };
3088
3089 static int stmmac_init_fs(struct net_device *dev)
3090 {
3091         struct stmmac_priv *priv = netdev_priv(dev);
3092
3093         /* Create per netdev entries */
3094         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3095
3096         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3097                 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3098                        STMMAC_RESOURCE_NAME, dev->name);
3099
3100                 return -ENOMEM;
3101         }
3102
3103         /* Entry to report DMA RX/TX rings */
3104         priv->dbgfs_rings_status =
3105                 debugfs_create_file("descriptors_status", S_IRUGO,
3106                                     priv->dbgfs_dir, dev,
3107                                     &stmmac_rings_status_fops);
3108
3109         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3110                 pr_info("ERROR creating stmmac ring debugfs file\n");
3111                 debugfs_remove_recursive(priv->dbgfs_dir);
3112
3113                 return -ENOMEM;
3114         }
3115
3116         /* Entry to report the DMA HW features */
3117         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3118                                             priv->dbgfs_dir,
3119                                             dev, &stmmac_dma_cap_fops);
3120
3121         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3122                 pr_info("ERROR creating stmmac MMC debugfs file\n");
3123                 debugfs_remove_recursive(priv->dbgfs_dir);
3124
3125                 return -ENOMEM;
3126         }
3127
3128         return 0;
3129 }
3130
3131 static void stmmac_exit_fs(struct net_device *dev)
3132 {
3133         struct stmmac_priv *priv = netdev_priv(dev);
3134
3135         debugfs_remove_recursive(priv->dbgfs_dir);
3136 }
3137 #endif /* CONFIG_DEBUG_FS */
3138
3139 static const struct net_device_ops stmmac_netdev_ops = {
3140         .ndo_open = stmmac_open,
3141         .ndo_start_xmit = stmmac_xmit,
3142         .ndo_stop = stmmac_release,
3143         .ndo_change_mtu = stmmac_change_mtu,
3144         .ndo_fix_features = stmmac_fix_features,
3145         .ndo_set_features = stmmac_set_features,
3146         .ndo_set_rx_mode = stmmac_set_rx_mode,
3147         .ndo_tx_timeout = stmmac_tx_timeout,
3148         .ndo_do_ioctl = stmmac_ioctl,
3149 #ifdef CONFIG_NET_POLL_CONTROLLER
3150         .ndo_poll_controller = stmmac_poll_controller,
3151 #endif
3152         .ndo_set_mac_address = stmmac_set_mac_address,
3153 };
3154
3155 /**
3156  *  stmmac_hw_init - Init the MAC device
3157  *  @priv: driver private structure
3158  *  Description: this function is to configure the MAC device according to
3159  *  some platform parameters or the HW capability register. It prepares the
3160  *  driver to use either ring or chain modes and to setup either enhanced or
3161  *  normal descriptors.
3162  */
3163 static int stmmac_hw_init(struct stmmac_priv *priv)
3164 {
3165         struct mac_device_info *mac;
3166
3167         /* Identify the MAC HW device */
3168         if (priv->plat->has_gmac) {
3169                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3170                 mac = dwmac1000_setup(priv->ioaddr,
3171                                       priv->plat->multicast_filter_bins,
3172                                       priv->plat->unicast_filter_entries,
3173                                       &priv->synopsys_id);
3174         } else if (priv->plat->has_gmac4) {
3175                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3176                 mac = dwmac4_setup(priv->ioaddr,
3177                                    priv->plat->multicast_filter_bins,
3178                                    priv->plat->unicast_filter_entries,
3179                                    &priv->synopsys_id);
3180         } else {
3181                 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3182         }
3183         if (!mac)
3184                 return -ENOMEM;
3185
3186         priv->hw = mac;
3187
3188         /* To use the chained or ring mode */
3189         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3190                 priv->hw->mode = &dwmac4_ring_mode_ops;
3191         } else {
3192                 if (chain_mode) {
3193                         priv->hw->mode = &chain_mode_ops;
3194                         pr_info(" Chain mode enabled\n");
3195                         priv->mode = STMMAC_CHAIN_MODE;
3196                 } else {
3197                         priv->hw->mode = &ring_mode_ops;
3198                         pr_info(" Ring mode enabled\n");
3199                         priv->mode = STMMAC_RING_MODE;
3200                 }
3201         }
3202
3203         /* Get the HW capability (new GMAC newer than 3.50a) */
3204         priv->hw_cap_support = stmmac_get_hw_features(priv);
3205         if (priv->hw_cap_support) {
3206                 pr_info(" DMA HW capability register supported");
3207
3208                 /* We can override some gmac/dma configuration fields: e.g.
3209                  * enh_desc, tx_coe (e.g. that are passed through the
3210                  * platform) with the values from the HW capability
3211                  * register (if supported).
3212                  */
3213                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3214                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3215                 priv->hw->pmt = priv->plat->pmt;
3216
3217                 /* TXCOE doesn't work in thresh DMA mode */
3218                 if (priv->plat->force_thresh_dma_mode)
3219                         priv->plat->tx_coe = 0;
3220                 else
3221                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
3222
3223                 /* In case of GMAC4 rx_coe is from HW cap register. */
3224                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3225
3226                 if (priv->dma_cap.rx_coe_type2)
3227                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3228                 else if (priv->dma_cap.rx_coe_type1)
3229                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3230
3231         } else
3232                 pr_info(" No HW DMA feature register supported");
3233
3234         /* To use alternate (extended), normal or GMAC4 descriptor structures */
3235         if (priv->synopsys_id >= DWMAC_CORE_4_00)
3236                 priv->hw->desc = &dwmac4_desc_ops;
3237         else
3238                 stmmac_selec_desc_mode(priv);
3239
3240         if (priv->plat->rx_coe) {
3241                 priv->hw->rx_csum = priv->plat->rx_coe;
3242                 pr_info(" RX Checksum Offload Engine supported\n");
3243                 if (priv->synopsys_id < DWMAC_CORE_4_00)
3244                         pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3245         }
3246         if (priv->plat->tx_coe)
3247                 pr_info(" TX Checksum insertion supported\n");
3248
3249         if (priv->plat->pmt) {
3250                 pr_info(" Wake-Up On Lan supported\n");
3251                 device_set_wakeup_capable(priv->device, 1);
3252         }
3253
3254         if (priv->dma_cap.tsoen)
3255                 pr_info(" TSO supported\n");
3256
3257         return 0;
3258 }
3259
3260 /**
3261  * stmmac_dvr_probe
3262  * @device: device pointer
3263  * @plat_dat: platform data pointer
3264  * @res: stmmac resource pointer
3265  * Description: this is the main probe function used to
3266  * call the alloc_etherdev, allocate the priv structure.
3267  * Return:
3268  * returns 0 on success, otherwise errno.
3269  */
3270 int stmmac_dvr_probe(struct device *device,
3271                      struct plat_stmmacenet_data *plat_dat,
3272                      struct stmmac_resources *res)
3273 {
3274         int ret = 0;
3275         struct net_device *ndev = NULL;
3276         struct stmmac_priv *priv;
3277
3278         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3279         if (!ndev)
3280                 return -ENOMEM;
3281
3282         SET_NETDEV_DEV(ndev, device);
3283
3284         priv = netdev_priv(ndev);
3285         priv->device = device;
3286         priv->dev = ndev;
3287
3288         stmmac_set_ethtool_ops(ndev);
3289         priv->pause = pause;
3290         priv->plat = plat_dat;
3291         priv->ioaddr = res->addr;
3292         priv->dev->base_addr = (unsigned long)res->addr;
3293
3294         priv->dev->irq = res->irq;
3295         priv->wol_irq = res->wol_irq;
3296         priv->lpi_irq = res->lpi_irq;
3297
3298         if (res->mac)
3299                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3300
3301         dev_set_drvdata(device, priv->dev);
3302
3303         /* Verify driver arguments */
3304         stmmac_verify_args();
3305
3306         /* Override with kernel parameters if supplied XXX CRS XXX
3307          * this needs to have multiple instances
3308          */
3309         if ((phyaddr >= 0) && (phyaddr <= 31))
3310                 priv->plat->phy_addr = phyaddr;
3311
3312         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3313         if (IS_ERR(priv->stmmac_clk)) {
3314                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3315                          __func__);
3316                 /* If failed to obtain stmmac_clk and specific clk_csr value
3317                  * is NOT passed from the platform, probe fail.
3318                  */
3319                 if (!priv->plat->clk_csr) {
3320                         ret = PTR_ERR(priv->stmmac_clk);
3321                         goto error_clk_get;
3322                 } else {
3323                         priv->stmmac_clk = NULL;
3324                 }
3325         }
3326         clk_prepare_enable(priv->stmmac_clk);
3327
3328         priv->pclk = devm_clk_get(priv->device, "pclk");
3329         if (IS_ERR(priv->pclk)) {
3330                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3331                         ret = -EPROBE_DEFER;
3332                         goto error_pclk_get;
3333                 }
3334                 priv->pclk = NULL;
3335         }
3336         clk_prepare_enable(priv->pclk);
3337
3338         priv->stmmac_rst = devm_reset_control_get(priv->device,
3339                                                   STMMAC_RESOURCE_NAME);
3340         if (IS_ERR(priv->stmmac_rst)) {
3341                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3342                         ret = -EPROBE_DEFER;
3343                         goto error_hw_init;
3344                 }
3345                 dev_info(priv->device, "no reset control found\n");
3346                 priv->stmmac_rst = NULL;
3347         }
3348         if (priv->stmmac_rst)
3349                 reset_control_deassert(priv->stmmac_rst);
3350
3351         /* Init MAC and get the capabilities */
3352         ret = stmmac_hw_init(priv);
3353         if (ret)
3354                 goto error_hw_init;
3355
3356         stmmac_check_ether_addr(priv);
3357
3358         ndev->netdev_ops = &stmmac_netdev_ops;
3359
3360         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3361                             NETIF_F_RXCSUM;
3362
3363         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3364                 ndev->hw_features |= NETIF_F_TSO;
3365                 priv->tso = true;
3366                 pr_info(" TSO feature enabled\n");
3367         }
3368         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3369         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3370 #ifdef STMMAC_VLAN_TAG_USED
3371         /* Both mac100 and gmac support receive VLAN tag detection */
3372         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3373 #endif
3374         priv->msg_enable = netif_msg_init(debug, default_msg_level);
3375
3376         if (flow_ctrl)
3377                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
3378
3379         /* Rx Watchdog is available in the COREs newer than the 3.40.
3380          * In some case, for example on bugged HW this feature
3381          * has to be disable and this can be done by passing the
3382          * riwt_off field from the platform.
3383          */
3384         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3385                 priv->use_riwt = 1;
3386                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3387         }
3388
3389         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3390
3391         spin_lock_init(&priv->lock);
3392         spin_lock_init(&priv->tx_lock);
3393
3394         /* If a specific clk_csr value is passed from the platform
3395          * this means that the CSR Clock Range selection cannot be
3396          * changed at run-time and it is fixed. Viceversa the driver'll try to
3397          * set the MDC clock dynamically according to the csr actual
3398          * clock input.
3399          */
3400         if (!priv->plat->clk_csr)
3401                 stmmac_clk_csr_set(priv);
3402         else
3403                 priv->clk_csr = priv->plat->clk_csr;
3404
3405         stmmac_check_pcs_mode(priv);
3406
3407         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
3408             priv->hw->pcs != STMMAC_PCS_TBI &&
3409             priv->hw->pcs != STMMAC_PCS_RTBI) {
3410                 /* MDIO bus Registration */
3411                 ret = stmmac_mdio_register(ndev);
3412                 if (ret < 0) {
3413                         pr_debug("%s: MDIO bus (id: %d) registration failed",
3414                                  __func__, priv->plat->bus_id);
3415                         goto error_napi_register;
3416                 }
3417         }
3418
3419         ret = register_netdev(ndev);
3420         if (ret) {
3421                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3422                 goto error_netdev_register;
3423         }
3424
3425         return ret;
3426
3427 error_netdev_register:
3428         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3429             priv->hw->pcs != STMMAC_PCS_TBI &&
3430             priv->hw->pcs != STMMAC_PCS_RTBI)
3431                 stmmac_mdio_unregister(ndev);
3432 error_napi_register:
3433         netif_napi_del(&priv->napi);
3434 error_hw_init:
3435         clk_disable_unprepare(priv->pclk);
3436 error_pclk_get:
3437         clk_disable_unprepare(priv->stmmac_clk);
3438 error_clk_get:
3439         free_netdev(ndev);
3440
3441         return ret;
3442 }
3443 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3444
3445 /**
3446  * stmmac_dvr_remove
3447  * @dev: device pointer
3448  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3449  * changes the link status, releases the DMA descriptor rings.
3450  */
3451 int stmmac_dvr_remove(struct device *dev)
3452 {
3453         struct net_device *ndev = dev_get_drvdata(dev);
3454         struct stmmac_priv *priv = netdev_priv(ndev);
3455
3456         pr_info("%s:\n\tremoving driver", __func__);
3457
3458         priv->hw->dma->stop_rx(priv->ioaddr);
3459         priv->hw->dma->stop_tx(priv->ioaddr);
3460
3461         stmmac_set_mac(priv->ioaddr, false);
3462         netif_carrier_off(ndev);
3463         unregister_netdev(ndev);
3464         if (priv->stmmac_rst)
3465                 reset_control_assert(priv->stmmac_rst);
3466         clk_disable_unprepare(priv->pclk);
3467         clk_disable_unprepare(priv->stmmac_clk);
3468         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3469             priv->hw->pcs != STMMAC_PCS_TBI &&
3470             priv->hw->pcs != STMMAC_PCS_RTBI)
3471                 stmmac_mdio_unregister(ndev);
3472         free_netdev(ndev);
3473
3474         return 0;
3475 }
3476 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3477
3478 /**
3479  * stmmac_suspend - suspend callback
3480  * @dev: device pointer
3481  * Description: this is the function to suspend the device and it is called
3482  * by the platform driver to stop the network queue, release the resources,
3483  * program the PMT register (for WoL), clean and release driver resources.
3484  */
3485 int stmmac_suspend(struct device *dev)
3486 {
3487         struct net_device *ndev = dev_get_drvdata(dev);
3488         struct stmmac_priv *priv = netdev_priv(ndev);
3489         unsigned long flags;
3490
3491         if (!ndev || !netif_running(ndev))
3492                 return 0;
3493
3494         if (priv->phydev)
3495                 phy_stop(priv->phydev);
3496
3497         spin_lock_irqsave(&priv->lock, flags);
3498
3499         netif_device_detach(ndev);
3500         netif_stop_queue(ndev);
3501
3502         napi_disable(&priv->napi);
3503
3504         /* Stop TX/RX DMA */
3505         priv->hw->dma->stop_tx(priv->ioaddr);
3506         priv->hw->dma->stop_rx(priv->ioaddr);
3507
3508         /* Enable Power down mode by programming the PMT regs */
3509         if (device_may_wakeup(priv->device)) {
3510                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3511                 priv->irq_wake = 1;
3512         } else {
3513                 stmmac_set_mac(priv->ioaddr, false);
3514                 pinctrl_pm_select_sleep_state(priv->device);
3515                 /* Disable clock in case of PWM is off */
3516                 clk_disable(priv->pclk);
3517                 clk_disable(priv->stmmac_clk);
3518         }
3519         spin_unlock_irqrestore(&priv->lock, flags);
3520
3521         priv->oldlink = 0;
3522         priv->speed = 0;
3523         priv->oldduplex = -1;
3524         return 0;
3525 }
3526 EXPORT_SYMBOL_GPL(stmmac_suspend);
3527
3528 /**
3529  * stmmac_resume - resume callback
3530  * @dev: device pointer
3531  * Description: when resume this function is invoked to setup the DMA and CORE
3532  * in a usable state.
3533  */
3534 int stmmac_resume(struct device *dev)
3535 {
3536         struct net_device *ndev = dev_get_drvdata(dev);
3537         struct stmmac_priv *priv = netdev_priv(ndev);
3538         unsigned long flags;
3539
3540         if (!netif_running(ndev))
3541                 return 0;
3542
3543         /* Power Down bit, into the PM register, is cleared
3544          * automatically as soon as a magic packet or a Wake-up frame
3545          * is received. Anyway, it's better to manually clear
3546          * this bit because it can generate problems while resuming
3547          * from another devices (e.g. serial console).
3548          */
3549         if (device_may_wakeup(priv->device)) {
3550                 spin_lock_irqsave(&priv->lock, flags);
3551                 priv->hw->mac->pmt(priv->hw, 0);
3552                 spin_unlock_irqrestore(&priv->lock, flags);
3553                 priv->irq_wake = 0;
3554         } else {
3555                 pinctrl_pm_select_default_state(priv->device);
3556                 /* enable the clk prevously disabled */
3557                 clk_enable(priv->stmmac_clk);
3558                 clk_enable(priv->pclk);
3559                 /* reset the phy so that it's ready */
3560                 if (priv->mii)
3561                         stmmac_mdio_reset(priv->mii);
3562         }
3563
3564         netif_device_attach(ndev);
3565
3566         spin_lock_irqsave(&priv->lock, flags);
3567
3568         priv->cur_rx = 0;
3569         priv->dirty_rx = 0;
3570         priv->dirty_tx = 0;
3571         priv->cur_tx = 0;
3572         /* reset private mss value to force mss context settings at
3573          * next tso xmit (only used for gmac4).
3574          */
3575         priv->mss = 0;
3576
3577         stmmac_clear_descriptors(priv);
3578
3579         stmmac_hw_setup(ndev, false);
3580         stmmac_init_tx_coalesce(priv);
3581         stmmac_set_rx_mode(ndev);
3582
3583         napi_enable(&priv->napi);
3584
3585         netif_start_queue(ndev);
3586
3587         spin_unlock_irqrestore(&priv->lock, flags);
3588
3589         if (priv->phydev)
3590                 phy_start(priv->phydev);
3591
3592         return 0;
3593 }
3594 EXPORT_SYMBOL_GPL(stmmac_resume);
3595
3596 #ifndef MODULE
3597 static int __init stmmac_cmdline_opt(char *str)
3598 {
3599         char *opt;
3600
3601         if (!str || !*str)
3602                 return -EINVAL;
3603         while ((opt = strsep(&str, ",")) != NULL) {
3604                 if (!strncmp(opt, "debug:", 6)) {
3605                         if (kstrtoint(opt + 6, 0, &debug))
3606                                 goto err;
3607                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3608                         if (kstrtoint(opt + 8, 0, &phyaddr))
3609                                 goto err;
3610                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3611                         if (kstrtoint(opt + 7, 0, &buf_sz))
3612                                 goto err;
3613                 } else if (!strncmp(opt, "tc:", 3)) {
3614                         if (kstrtoint(opt + 3, 0, &tc))
3615                                 goto err;
3616                 } else if (!strncmp(opt, "watchdog:", 9)) {
3617                         if (kstrtoint(opt + 9, 0, &watchdog))
3618                                 goto err;
3619                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3620                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3621                                 goto err;
3622                 } else if (!strncmp(opt, "pause:", 6)) {
3623                         if (kstrtoint(opt + 6, 0, &pause))
3624                                 goto err;
3625                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3626                         if (kstrtoint(opt + 10, 0, &eee_timer))
3627                                 goto err;
3628                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3629                         if (kstrtoint(opt + 11, 0, &chain_mode))
3630                                 goto err;
3631                 }
3632         }
3633         return 0;
3634
3635 err:
3636         pr_err("%s: ERROR broken module parameter conversion", __func__);
3637         return -EINVAL;
3638 }
3639
3640 __setup("stmmaceth=", stmmac_cmdline_opt);
3641 #endif /* MODULE */
3642
3643 static int __init stmmac_init(void)
3644 {
3645 #ifdef CONFIG_DEBUG_FS
3646         /* Create debugfs main directory if it doesn't exist yet */
3647         if (!stmmac_fs_dir) {
3648                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3649
3650                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3651                         pr_err("ERROR %s, debugfs create directory failed\n",
3652                                STMMAC_RESOURCE_NAME);
3653
3654                         return -ENOMEM;
3655                 }
3656         }
3657 #endif
3658
3659         return 0;
3660 }
3661
3662 static void __exit stmmac_exit(void)
3663 {
3664 #ifdef CONFIG_DEBUG_FS
3665         debugfs_remove_recursive(stmmac_fs_dir);
3666 #endif
3667 }
3668
3669 module_init(stmmac_init)
3670 module_exit(stmmac_exit)
3671
3672 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3673 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3674 MODULE_LICENSE("GPL");