1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
57 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
58 #include "stmmac_platform.h"
60 #ifdef CONFIG_DWMAC_MESON
61 #include <phy_debug.h>
64 #include <linux/suspend.h>
65 #define PM_SUSPEND_PREPARE 0x0003 /* Going to suspend the system */
67 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
68 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
70 /* Module parameters */
72 static int watchdog = TX_TIMEO;
73 module_param(watchdog, int, S_IRUGO | S_IWUSR);
74 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
76 static int debug = -1;
77 module_param(debug, int, S_IRUGO | S_IWUSR);
78 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
80 static int phyaddr = -1;
81 module_param(phyaddr, int, S_IRUGO);
82 MODULE_PARM_DESC(phyaddr, "Physical device address");
84 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
85 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
87 static int flow_ctrl = FLOW_OFF;
88 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
89 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
91 static int pause = PAUSE_TIME;
92 module_param(pause, int, S_IRUGO | S_IWUSR);
93 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
96 static int tc = TC_DEFAULT;
97 module_param(tc, int, S_IRUGO | S_IWUSR);
98 MODULE_PARM_DESC(tc, "DMA threshold control value");
100 #define DEFAULT_BUFSIZE 1536
101 static int buf_sz = DEFAULT_BUFSIZE;
102 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
103 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
105 #define STMMAC_RX_COPYBREAK 256
107 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
108 NETIF_MSG_LINK | NETIF_MSG_IFUP |
109 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
111 #define STMMAC_DEFAULT_LPI_TIMER 1000
112 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
113 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
114 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
115 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
117 /* By default the driver will use the ring mode to manage tx and rx descriptors
118 * but passing this value so user can force to use the chain instead of the ring
120 static unsigned int chain_mode;
121 module_param(chain_mode, int, S_IRUGO);
122 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
124 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
126 #ifdef CONFIG_DEBUG_FS
127 static int stmmac_init_fs(struct net_device *dev);
128 static void stmmac_exit_fs(struct net_device *dev);
131 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
133 /*won't be valid unless enable amlogic priv code*/
134 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
139 static struct workqueue_struct *moniter_tx_wq;
140 static struct delayed_work moniter_tx_worker;
143 * stmmac_verify_args - verify the driver parameters.
144 * Description: it checks the driver parameters and set a default in case of
147 static void stmmac_verify_args(void)
149 if (unlikely(watchdog < 0))
151 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
152 buf_sz = DEFAULT_BUFSIZE;
153 if (unlikely(flow_ctrl > 1))
154 flow_ctrl = FLOW_AUTO;
155 else if (likely(flow_ctrl < 0))
156 flow_ctrl = FLOW_OFF;
157 if (unlikely((pause < 0) || (pause > 0xffff)))
160 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
164 * stmmac_clk_csr_set - dynamically set the MDC clock
165 * @priv: driver private structure
166 * Description: this is to dynamically set the MDC clock according to the csr
169 * If a specific clk_csr value is passed from the platform
170 * this means that the CSR Clock Range selection cannot be
171 * changed at run-time and it is fixed (as reported in the driver
172 * documentation). Viceversa the driver will try to set the MDC
173 * clock dynamically according to the actual clock input.
175 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
179 clk_rate = clk_get_rate(priv->stmmac_clk);
181 /* Platform provided default clk_csr would be assumed valid
182 * for all other cases except for the below mentioned ones.
183 * For values higher than the IEEE 802.3 specified frequency
184 * we can not estimate the proper divider as it is not known
185 * the frequency of clk_csr_i. So we do not change the default
188 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
189 if (clk_rate < CSR_F_35M)
190 priv->clk_csr = STMMAC_CSR_20_35M;
191 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
192 priv->clk_csr = STMMAC_CSR_35_60M;
193 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
194 priv->clk_csr = STMMAC_CSR_60_100M;
195 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
196 priv->clk_csr = STMMAC_CSR_100_150M;
197 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
198 priv->clk_csr = STMMAC_CSR_150_250M;
199 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
200 priv->clk_csr = STMMAC_CSR_250_300M;
204 static void print_pkt(unsigned char *buf, int len)
206 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
207 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
210 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
214 if (priv->dirty_tx > priv->cur_tx)
215 avail = priv->dirty_tx - priv->cur_tx - 1;
217 avail = DMA_TX_SIZE - priv->cur_tx + priv->dirty_tx - 1;
222 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv)
226 if (priv->dirty_rx <= priv->cur_rx)
227 dirty = priv->cur_rx - priv->dirty_rx;
229 dirty = DMA_RX_SIZE - priv->dirty_rx + priv->cur_rx;
235 * stmmac_hw_fix_mac_speed - callback for speed selection
236 * @priv: driver private structure
237 * Description: on some platforms (e.g. ST), some HW system configuraton
238 * registers have to be set according to the link speed negotiated.
240 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
242 struct phy_device *phydev = priv->phydev;
244 if (likely(priv->plat->fix_mac_speed))
245 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
249 * stmmac_enable_eee_mode - check and enter in LPI mode
250 * @priv: driver private structure
251 * Description: this function is to verify and enter in LPI mode in case of
254 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
256 /* Check and enter in LPI mode */
257 if ((priv->dirty_tx == priv->cur_tx) &&
258 (priv->tx_path_in_lpi_mode == false))
259 priv->hw->mac->set_eee_mode(priv->hw);
263 * stmmac_disable_eee_mode - disable and exit from LPI mode
264 * @priv: driver private structure
265 * Description: this function is to exit and disable EEE in case of
266 * LPI state is true. This is called by the xmit.
268 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
270 priv->hw->mac->reset_eee_mode(priv->hw);
271 del_timer_sync(&priv->eee_ctrl_timer);
272 priv->tx_path_in_lpi_mode = false;
276 * stmmac_eee_ctrl_timer - EEE TX SW timer.
279 * if there is no data transfer and if we are not in LPI state,
280 * then MAC Transmitter can be moved to LPI state.
282 static void stmmac_eee_ctrl_timer(unsigned long arg)
284 struct stmmac_priv *priv = (struct stmmac_priv *)arg;
286 stmmac_enable_eee_mode(priv);
287 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
291 * stmmac_eee_init - init EEE
292 * @priv: driver private structure
294 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
295 * can also manage EEE, this function enable the LPI state and start related
298 bool stmmac_eee_init(struct stmmac_priv *priv)
301 int interface = priv->plat->interface;
304 if ((interface != PHY_INTERFACE_MODE_MII) &&
305 (interface != PHY_INTERFACE_MODE_GMII) &&
306 !phy_interface_mode_is_rgmii(interface))
309 /* Using PCS we cannot dial with the phy registers at this stage
310 * so we do not support extra feature like EEE.
312 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
313 (priv->hw->pcs == STMMAC_PCS_TBI) ||
314 (priv->hw->pcs == STMMAC_PCS_RTBI))
317 /* MAC core supports the EEE feature. */
318 if (priv->dma_cap.eee) {
319 int tx_lpi_timer = priv->tx_lpi_timer;
321 /* Check if the PHY supports EEE */
322 if (phy_init_eee(priv->phydev, 1)) {
323 /* To manage at run-time if the EEE cannot be supported
324 * anymore (for example because the lp caps have been
326 * In that case the driver disable own timers.
328 spin_lock_irqsave(&priv->lock, flags);
329 if (priv->eee_active) {
330 pr_debug("stmmac: disable EEE\n");
331 del_timer_sync(&priv->eee_ctrl_timer);
332 priv->hw->mac->set_eee_timer(priv->hw, 0,
335 priv->eee_active = 0;
336 spin_unlock_irqrestore(&priv->lock, flags);
339 /* Activate the EEE and start timers */
340 spin_lock_irqsave(&priv->lock, flags);
341 if (!priv->eee_active) {
342 priv->eee_active = 1;
343 setup_timer(&priv->eee_ctrl_timer,
344 stmmac_eee_ctrl_timer,
345 (unsigned long)priv);
346 mod_timer(&priv->eee_ctrl_timer,
347 STMMAC_LPI_T(eee_timer));
349 priv->hw->mac->set_eee_timer(priv->hw,
350 STMMAC_DEFAULT_LIT_LS,
353 /* Set HW EEE according to the speed */
354 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
357 spin_unlock_irqrestore(&priv->lock, flags);
359 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
365 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
366 * @priv: driver private structure
367 * @p : descriptor pointer
368 * @skb : the socket buffer
370 * This function will read timestamp from the descriptor & pass it to stack.
371 * and also perform some sanity checks.
373 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
374 struct dma_desc *p, struct sk_buff *skb)
376 struct skb_shared_hwtstamps shhwtstamp;
379 if (!priv->hwts_tx_en)
382 /* exit if skb doesn't support hw tstamp */
383 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
386 /* check tx tstamp status */
387 if (!priv->hw->desc->get_tx_timestamp_status(p)) {
388 /* get the valid tstamp */
389 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
391 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
392 shhwtstamp.hwtstamp = ns_to_ktime(ns);
394 netdev_info(priv->dev, "get valid TX hw timestamp %llu\n", ns);
395 /* pass tstamp to stack */
396 skb_tstamp_tx(skb, &shhwtstamp);
402 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
403 * @priv: driver private structure
404 * @p : descriptor pointer
405 * @np : next descriptor pointer
406 * @skb : the socket buffer
408 * This function will read received packet's timestamp from the descriptor
409 * and pass it to stack. It also perform some sanity checks.
411 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
412 struct dma_desc *np, struct sk_buff *skb)
414 struct skb_shared_hwtstamps *shhwtstamp = NULL;
417 if (!priv->hwts_rx_en)
420 /* Check if timestamp is available */
421 if (!priv->hw->desc->get_rx_timestamp_status(p, priv->adv_ts)) {
422 /* For GMAC4, the valid timestamp is from CTX next desc. */
423 if (priv->plat->has_gmac4)
424 ns = priv->hw->desc->get_timestamp(np, priv->adv_ts);
426 ns = priv->hw->desc->get_timestamp(p, priv->adv_ts);
428 netdev_info(priv->dev, "get valid RX hw timestamp %llu\n", ns);
429 shhwtstamp = skb_hwtstamps(skb);
430 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
431 shhwtstamp->hwtstamp = ns_to_ktime(ns);
433 netdev_err(priv->dev, "cannot get RX hw timestamp\n");
438 * stmmac_hwtstamp_ioctl - control hardware timestamping.
439 * @dev: device pointer.
440 * @ifr: An IOCTL specefic structure, that can contain a pointer to
441 * a proprietary structure used to pass information to the driver.
443 * This function configures the MAC to enable/disable both outgoing(TX)
444 * and incoming(RX) packets time stamping based on user input.
446 * 0 on success and an appropriate -ve integer on failure.
448 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
450 struct stmmac_priv *priv = netdev_priv(dev);
451 struct hwtstamp_config config;
452 struct timespec64 now;
456 u32 ptp_over_ipv4_udp = 0;
457 u32 ptp_over_ipv6_udp = 0;
458 u32 ptp_over_ethernet = 0;
459 u32 snap_type_sel = 0;
460 u32 ts_master_en = 0;
465 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
466 netdev_alert(priv->dev, "No support for HW time stamping\n");
467 priv->hwts_tx_en = 0;
468 priv->hwts_rx_en = 0;
473 if (copy_from_user(&config, ifr->ifr_data,
474 sizeof(struct hwtstamp_config)))
477 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
478 __func__, config.flags, config.tx_type, config.rx_filter);
480 /* reserved for future extensions */
484 if (config.tx_type != HWTSTAMP_TX_OFF &&
485 config.tx_type != HWTSTAMP_TX_ON)
489 switch (config.rx_filter) {
490 case HWTSTAMP_FILTER_NONE:
491 /* time stamp no incoming packet at all */
492 config.rx_filter = HWTSTAMP_FILTER_NONE;
495 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
496 /* PTP v1, UDP, any kind of event packet */
497 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
498 /* take time stamp for all event messages */
499 if (priv->plat->has_gmac4)
500 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
502 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
504 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
505 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
508 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
509 /* PTP v1, UDP, Sync packet */
510 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
511 /* take time stamp for SYNC messages only */
512 ts_event_en = PTP_TCR_TSEVNTENA;
514 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
515 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
518 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
519 /* PTP v1, UDP, Delay_req packet */
520 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
521 /* take time stamp for Delay_Req messages only */
522 ts_master_en = PTP_TCR_TSMSTRENA;
523 ts_event_en = PTP_TCR_TSEVNTENA;
525 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
526 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
529 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
530 /* PTP v2, UDP, any kind of event packet */
531 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
532 ptp_v2 = PTP_TCR_TSVER2ENA;
533 /* take time stamp for all event messages */
534 if (priv->plat->has_gmac4)
535 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
537 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
539 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
540 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
543 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
544 /* PTP v2, UDP, Sync packet */
545 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
546 ptp_v2 = PTP_TCR_TSVER2ENA;
547 /* take time stamp for SYNC messages only */
548 ts_event_en = PTP_TCR_TSEVNTENA;
550 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
551 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
554 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
555 /* PTP v2, UDP, Delay_req packet */
556 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
557 ptp_v2 = PTP_TCR_TSVER2ENA;
558 /* take time stamp for Delay_Req messages only */
559 ts_master_en = PTP_TCR_TSMSTRENA;
560 ts_event_en = PTP_TCR_TSEVNTENA;
562 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
563 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
566 case HWTSTAMP_FILTER_PTP_V2_EVENT:
567 /* PTP v2/802.AS1 any layer, any kind of event packet */
568 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
569 ptp_v2 = PTP_TCR_TSVER2ENA;
570 /* take time stamp for all event messages */
571 if (priv->plat->has_gmac4)
572 snap_type_sel = PTP_GMAC4_TCR_SNAPTYPSEL_1;
574 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
576 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
577 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
578 ptp_over_ethernet = PTP_TCR_TSIPENA;
581 case HWTSTAMP_FILTER_PTP_V2_SYNC:
582 /* PTP v2/802.AS1, any layer, Sync packet */
583 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
584 ptp_v2 = PTP_TCR_TSVER2ENA;
585 /* take time stamp for SYNC messages only */
586 ts_event_en = PTP_TCR_TSEVNTENA;
588 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
589 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
590 ptp_over_ethernet = PTP_TCR_TSIPENA;
593 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
594 /* PTP v2/802.AS1, any layer, Delay_req packet */
595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
596 ptp_v2 = PTP_TCR_TSVER2ENA;
597 /* take time stamp for Delay_Req messages only */
598 ts_master_en = PTP_TCR_TSMSTRENA;
599 ts_event_en = PTP_TCR_TSEVNTENA;
601 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
602 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
603 ptp_over_ethernet = PTP_TCR_TSIPENA;
606 case HWTSTAMP_FILTER_ALL:
607 /* time stamp any incoming packet */
608 config.rx_filter = HWTSTAMP_FILTER_ALL;
609 tstamp_all = PTP_TCR_TSENALL;
616 switch (config.rx_filter) {
617 case HWTSTAMP_FILTER_NONE:
618 config.rx_filter = HWTSTAMP_FILTER_NONE;
621 /* PTP v1, UDP, any kind of event packet */
622 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
626 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
627 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
629 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
630 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, 0);
632 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
633 tstamp_all | ptp_v2 | ptp_over_ethernet |
634 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
635 ts_master_en | snap_type_sel);
636 priv->hw->ptp->config_hw_tstamping(priv->ptpaddr, value);
638 /* program Sub Second Increment reg */
639 sec_inc = priv->hw->ptp->config_sub_second_increment(
640 priv->ptpaddr, priv->clk_ptp_rate,
641 priv->plat->has_gmac4);
642 temp = div_u64(1000000000ULL, sec_inc);
644 /* calculate default added value:
646 * addend = (2^32)/freq_div_ratio;
647 * where, freq_div_ratio = 1e9ns/sec_inc
649 temp = (u64)(temp << 32);
650 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
651 priv->hw->ptp->config_addend(priv->ptpaddr,
652 priv->default_addend);
654 /* initialize system time */
655 ktime_get_real_ts64(&now);
657 /* lower 32 bits of tv_sec are safe until y2106 */
658 priv->hw->ptp->init_systime(priv->ptpaddr, (u32)now.tv_sec,
662 return copy_to_user(ifr->ifr_data, &config,
663 sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
667 * stmmac_init_ptp - init PTP
668 * @priv: driver private structure
669 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
670 * This is done by looking at the HW cap. register.
671 * This function also registers the ptp driver.
673 static int stmmac_init_ptp(struct stmmac_priv *priv)
675 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
678 /* Fall-back to main clock in case of no PTP ref is passed */
679 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
680 if (IS_ERR(priv->clk_ptp_ref)) {
681 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
682 priv->clk_ptp_ref = NULL;
683 netdev_dbg(priv->dev, "PTP uses main clock\n");
685 clk_prepare_enable(priv->clk_ptp_ref);
686 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
687 netdev_dbg(priv->dev, "PTP rate %d\n", priv->clk_ptp_rate);
691 /* Check if adv_ts can be enabled for dwmac 4.x core */
692 if (priv->plat->has_gmac4 && priv->dma_cap.atime_stamp)
694 /* Dwmac 3.x core with extend_desc can support adv_ts */
695 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
698 if (priv->dma_cap.time_stamp)
699 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
702 netdev_info(priv->dev,
703 "IEEE 1588-2008 Advanced Timestamp supported\n");
705 priv->hw->ptp = &stmmac_ptp;
706 priv->hwts_tx_en = 0;
707 priv->hwts_rx_en = 0;
709 stmmac_ptp_register(priv);
714 static void stmmac_release_ptp(struct stmmac_priv *priv)
716 if (priv->clk_ptp_ref)
717 clk_disable_unprepare(priv->clk_ptp_ref);
718 stmmac_ptp_unregister(priv);
722 * stmmac_adjust_link - adjusts the link parameters
723 * @dev: net device structure
724 * Description: this is the helper called by the physical abstraction layer
725 * drivers to communicate the phy link status. According the speed and duplex
726 * this driver can invoke registered glue-logic as well.
727 * It also invoke the eee initialization because it could happen when switch
728 * on different networks (that are eee capable).
730 static void stmmac_adjust_link(struct net_device *dev)
732 struct stmmac_priv *priv = netdev_priv(dev);
733 struct phy_device *phydev = priv->phydev;
736 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
741 spin_lock_irqsave(&priv->lock, flags);
744 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
746 /* Now we make sure that we can be in full duplex mode.
747 * If not, we operate in half-duplex mode. */
748 if (phydev->duplex != priv->oldduplex) {
750 if (!(phydev->duplex))
751 ctrl &= ~priv->hw->link.duplex;
753 ctrl |= priv->hw->link.duplex;
754 priv->oldduplex = phydev->duplex;
756 /* Flow Control operation */
758 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
761 if (phydev->speed != priv->speed) {
763 switch (phydev->speed) {
765 if (likely((priv->plat->has_gmac) ||
766 (priv->plat->has_gmac4)))
767 ctrl &= ~priv->hw->link.port;
768 stmmac_hw_fix_mac_speed(priv);
772 if (likely((priv->plat->has_gmac) ||
773 (priv->plat->has_gmac4))) {
774 ctrl |= priv->hw->link.port;
775 if (phydev->speed == SPEED_100) {
776 ctrl |= priv->hw->link.speed;
778 ctrl &= ~(priv->hw->link.speed);
781 ctrl &= ~priv->hw->link.port;
783 stmmac_hw_fix_mac_speed(priv);
786 if (netif_msg_link(priv))
787 pr_warn("%s: Speed (%d) not 10/100\n",
788 dev->name, phydev->speed);
792 priv->speed = phydev->speed;
795 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
797 if (!priv->oldlink) {
801 } else if (priv->oldlink) {
805 priv->oldduplex = -1;
808 if (new_state && netif_msg_link(priv))
809 phy_print_status(phydev);
811 spin_unlock_irqrestore(&priv->lock, flags);
813 if (phydev->is_pseudo_fixed_link)
814 /* Stop PHY layer to call the hook to adjust the link in case
815 * of a switch is attached to the stmmac driver.
817 phydev->irq = PHY_IGNORE_INTERRUPT;
819 /* At this stage, init the EEE if supported.
820 * Never called in case of fixed_link.
822 priv->eee_enabled = stmmac_eee_init(priv);
826 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
827 * @priv: driver private structure
828 * Description: this is to verify if the HW supports the PCS.
829 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
830 * configured for the TBI, RTBI, or SGMII PHY interface.
832 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
834 int interface = priv->plat->interface;
836 if (priv->dma_cap.pcs) {
837 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
838 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
839 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
840 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
841 pr_debug("STMMAC: PCS RGMII support enable\n");
842 priv->hw->pcs = STMMAC_PCS_RGMII;
843 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
844 pr_debug("STMMAC: PCS SGMII support enable\n");
845 priv->hw->pcs = STMMAC_PCS_SGMII;
851 * stmmac_init_phy - PHY initialization
852 * @dev: net device structure
853 * Description: it initializes the driver's PHY state, and attaches the PHY
858 static int stmmac_init_phy(struct net_device *dev)
860 struct stmmac_priv *priv = netdev_priv(dev);
861 struct phy_device *phydev;
862 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
863 char bus_id[MII_BUS_ID_SIZE];
864 int interface = priv->plat->interface;
865 int max_speed = priv->plat->max_speed;
868 priv->oldduplex = -1;
870 if (priv->plat->phy_node) {
871 phydev = of_phy_connect(dev, priv->plat->phy_node,
872 &stmmac_adjust_link, 0, interface);
874 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
877 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
878 priv->plat->phy_addr);
879 pr_debug("stmmac_init_phy: trying to attach to %s\n",
882 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
886 if (IS_ERR_OR_NULL(phydev)) {
887 pr_err("%s: Could not attach to PHY\n", dev->name);
891 return PTR_ERR(phydev);
894 /* Stop Advertising 1000BASE Capability if interface is not GMII */
895 if ((interface == PHY_INTERFACE_MODE_MII) ||
896 (interface == PHY_INTERFACE_MODE_RMII) ||
897 (max_speed < 1000 && max_speed > 0))
898 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
899 SUPPORTED_1000baseT_Full);
902 * Broken HW is sometimes missing the pull-up resistor on the
903 * MDIO line, which results in reads to non-existent devices returning
904 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
906 * Note: phydev->phy_id is the result of reading the UID PHY registers.
908 if (!priv->plat->phy_node && phydev->phy_id == 0) {
909 phy_disconnect(phydev);
913 /* stmmac_adjust_link will change this to PHY_IGNORE_INTERRUPT to avoid
914 * subsequent PHY polling, make sure we force a link transition if
915 * we have a UP/DOWN/UP transition
917 if (phydev->is_pseudo_fixed_link)
918 phydev->irq = PHY_POLL;
920 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
921 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
923 priv->phydev = phydev;
928 static void stmmac_display_rings(struct stmmac_priv *priv)
930 void *head_rx, *head_tx;
932 if (priv->extend_desc) {
933 head_rx = (void *)priv->dma_erx;
934 head_tx = (void *)priv->dma_etx;
936 head_rx = (void *)priv->dma_rx;
937 head_tx = (void *)priv->dma_tx;
940 /* Display Rx ring */
941 priv->hw->desc->display_ring(head_rx, DMA_RX_SIZE, true);
942 /* Display Tx ring */
943 priv->hw->desc->display_ring(head_tx, DMA_TX_SIZE, false);
946 static int stmmac_set_bfsize(int mtu, int bufsize)
950 if (mtu >= BUF_SIZE_4KiB)
952 else if (mtu >= BUF_SIZE_2KiB)
954 else if (mtu > DEFAULT_BUFSIZE)
957 ret = DEFAULT_BUFSIZE;
963 * stmmac_clear_descriptors - clear descriptors
964 * @priv: driver private structure
965 * Description: this function is called to clear the tx and rx descriptors
966 * in case of both basic and extended descriptors are used.
968 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
972 /* Clear the Rx/Tx descriptors */
973 for (i = 0; i < DMA_RX_SIZE; i++)
974 if (priv->extend_desc)
975 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
976 priv->use_riwt, priv->mode,
977 (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
979 priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
980 priv->use_riwt, priv->mode,
981 (i == DMA_RX_SIZE - 1), priv->dma_buf_sz);
982 for (i = 0; i < DMA_TX_SIZE; i++)
983 if (priv->extend_desc)
984 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
986 (i == DMA_TX_SIZE - 1));
988 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
990 (i == DMA_TX_SIZE - 1));
994 * stmmac_init_rx_buffers - init the RX descriptor buffer.
995 * @priv: driver private structure
996 * @p: descriptor pointer
997 * @i: descriptor index
999 * Description: this function is called to allocate a receive buffer, perform
1000 * the DMA mapping and init the descriptor.
1002 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1005 struct sk_buff *skb;
1007 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1009 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
1012 priv->rx_skbuff[i] = skb;
1013 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1016 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
1017 pr_err("%s: DMA mapping error\n", __func__);
1018 dev_kfree_skb_any(skb);
1022 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1023 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1025 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[i]);
1027 if ((priv->hw->mode->init_desc3) &&
1028 (priv->dma_buf_sz == BUF_SIZE_16KiB))
1029 priv->hw->mode->init_desc3(p);
1034 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1036 if (priv->rx_skbuff[i]) {
1037 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1038 priv->dma_buf_sz, DMA_FROM_DEVICE);
1039 dev_kfree_skb_any(priv->rx_skbuff[i]);
1041 priv->rx_skbuff[i] = NULL;
1045 * init_dma_desc_rings - init the RX/TX descriptor rings
1046 * @dev: net device structure
1048 * Description: this function initializes the DMA RX/TX descriptors
1049 * and allocates the socket buffers. It suppors the chained and ring
1052 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1055 struct stmmac_priv *priv = netdev_priv(dev);
1056 unsigned int bfsize = 0;
1059 if (priv->hw->mode->set_16kib_bfsize)
1060 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1062 if (bfsize < BUF_SIZE_16KiB)
1063 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1065 priv->dma_buf_sz = bfsize;
1067 if (netif_msg_probe(priv)) {
1068 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1069 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1071 /* RX INITIALIZATION */
1072 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1074 for (i = 0; i < DMA_RX_SIZE; i++) {
1076 if (priv->extend_desc)
1077 p = &((priv->dma_erx + i)->basic);
1079 p = priv->dma_rx + i;
1081 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1083 goto err_init_rx_buffers;
1085 if (netif_msg_probe(priv))
1086 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1087 priv->rx_skbuff[i]->data,
1088 (unsigned int)priv->rx_skbuff_dma[i]);
1091 priv->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1094 /* Setup the chained descriptor addresses */
1095 if (priv->mode == STMMAC_CHAIN_MODE) {
1096 if (priv->extend_desc) {
1097 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1099 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1102 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1104 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1109 /* TX INITIALIZATION */
1110 for (i = 0; i < DMA_TX_SIZE; i++) {
1112 if (priv->extend_desc)
1113 p = &((priv->dma_etx + i)->basic);
1115 p = priv->dma_tx + i;
1117 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1126 priv->tx_skbuff_dma[i].buf = 0;
1127 priv->tx_skbuff_dma[i].map_as_page = false;
1128 priv->tx_skbuff_dma[i].len = 0;
1129 priv->tx_skbuff_dma[i].last_segment = false;
1130 priv->tx_skbuff[i] = NULL;
1135 netdev_reset_queue(priv->dev);
1137 stmmac_clear_descriptors(priv);
1139 if (netif_msg_hw(priv))
1140 stmmac_display_rings(priv);
1143 err_init_rx_buffers:
1145 stmmac_free_rx_buffers(priv, i);
1149 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1153 for (i = 0; i < DMA_RX_SIZE; i++)
1154 stmmac_free_rx_buffers(priv, i);
1157 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1161 for (i = 0; i < DMA_TX_SIZE; i++) {
1164 if (priv->extend_desc)
1165 p = &((priv->dma_etx + i)->basic);
1167 p = priv->dma_tx + i;
1169 if (priv->tx_skbuff_dma[i].buf) {
1170 if (priv->tx_skbuff_dma[i].map_as_page)
1171 dma_unmap_page(priv->device,
1172 priv->tx_skbuff_dma[i].buf,
1173 priv->tx_skbuff_dma[i].len,
1176 dma_unmap_single(priv->device,
1177 priv->tx_skbuff_dma[i].buf,
1178 priv->tx_skbuff_dma[i].len,
1182 if (priv->tx_skbuff[i] != NULL) {
1183 dev_kfree_skb_any(priv->tx_skbuff[i]);
1184 priv->tx_skbuff[i] = NULL;
1185 priv->tx_skbuff_dma[i].buf = 0;
1186 priv->tx_skbuff_dma[i].map_as_page = false;
1192 * alloc_dma_desc_resources - alloc TX/RX resources.
1193 * @priv: private structure
1194 * Description: according to which descriptor can be used (extend or basic)
1195 * this function allocates the resources for TX and RX paths. In case of
1196 * reception, for example, it pre-allocated the RX socket buffer in order to
1197 * allow zero-copy mechanism.
1199 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1203 priv->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE, sizeof(dma_addr_t),
1205 if (!priv->rx_skbuff_dma)
1208 priv->rx_skbuff = kmalloc_array(DMA_RX_SIZE, sizeof(struct sk_buff *),
1210 if (!priv->rx_skbuff)
1213 priv->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1214 sizeof(*priv->tx_skbuff_dma),
1216 if (!priv->tx_skbuff_dma)
1217 goto err_tx_skbuff_dma;
1219 priv->tx_skbuff = kmalloc_array(DMA_TX_SIZE, sizeof(struct sk_buff *),
1221 if (!priv->tx_skbuff)
1224 if (priv->extend_desc) {
1225 priv->dma_erx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1233 priv->dma_etx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1238 if (!priv->dma_etx) {
1239 dma_free_coherent(priv->device, DMA_RX_SIZE *
1240 sizeof(struct dma_extended_desc),
1241 priv->dma_erx, priv->dma_rx_phy);
1245 priv->dma_rx = dma_zalloc_coherent(priv->device, DMA_RX_SIZE *
1246 sizeof(struct dma_desc),
1252 priv->dma_tx = dma_zalloc_coherent(priv->device, DMA_TX_SIZE *
1253 sizeof(struct dma_desc),
1256 if (!priv->dma_tx) {
1257 dma_free_coherent(priv->device, DMA_RX_SIZE *
1258 sizeof(struct dma_desc),
1259 priv->dma_rx, priv->dma_rx_phy);
1267 kfree(priv->tx_skbuff);
1269 kfree(priv->tx_skbuff_dma);
1271 kfree(priv->rx_skbuff);
1273 kfree(priv->rx_skbuff_dma);
1277 static void free_dma_desc_resources(struct stmmac_priv *priv)
1279 /* Release the DMA TX/RX socket buffers */
1280 dma_free_rx_skbufs(priv);
1281 dma_free_tx_skbufs(priv);
1283 /* Free DMA regions of consistent memory previously allocated */
1284 if (!priv->extend_desc) {
1285 dma_free_coherent(priv->device,
1286 DMA_TX_SIZE * sizeof(struct dma_desc),
1287 priv->dma_tx, priv->dma_tx_phy);
1288 dma_free_coherent(priv->device,
1289 DMA_RX_SIZE * sizeof(struct dma_desc),
1290 priv->dma_rx, priv->dma_rx_phy);
1292 dma_free_coherent(priv->device, DMA_TX_SIZE *
1293 sizeof(struct dma_extended_desc),
1294 priv->dma_etx, priv->dma_tx_phy);
1295 dma_free_coherent(priv->device, DMA_RX_SIZE *
1296 sizeof(struct dma_extended_desc),
1297 priv->dma_erx, priv->dma_rx_phy);
1299 kfree(priv->rx_skbuff_dma);
1300 kfree(priv->rx_skbuff);
1301 kfree(priv->tx_skbuff_dma);
1302 kfree(priv->tx_skbuff);
1306 * stmmac_dma_operation_mode - HW DMA operation mode
1307 * @priv: driver private structure
1308 * Description: it is used for configuring the DMA operation mode register in
1309 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1311 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1313 int rxfifosz = priv->plat->rx_fifo_size;
1315 if (priv->plat->force_thresh_dma_mode)
1316 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1317 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1319 * In case of GMAC, SF mode can be enabled
1320 * to perform the TX COE in HW. This depends on:
1321 * 1) TX COE if actually supported
1322 * 2) There is no bugged Jumbo frame support
1323 * that needs to not insert csum in the TDES.
1325 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1327 priv->xstats.threshold = SF_DMA_MODE;
1329 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1334 * stmmac_tx_clean - to manage the transmission completion
1335 * @priv: driver private structure
1336 * Description: it reclaims the transmit resources after transmission completes.
1338 static void stmmac_tx_clean(struct stmmac_priv *priv)
1340 unsigned int bytes_compl = 0, pkts_compl = 0;
1341 unsigned int entry = priv->dirty_tx;
1343 spin_lock(&priv->tx_lock);
1345 priv->xstats.tx_clean++;
1347 while (entry != priv->cur_tx) {
1348 struct sk_buff *skb = priv->tx_skbuff[entry];
1352 if (priv->extend_desc)
1353 p = (struct dma_desc *)(priv->dma_etx + entry);
1355 p = priv->dma_tx + entry;
1357 status = priv->hw->desc->tx_status(&priv->dev->stats,
1360 /* Check if the descriptor is owned by the DMA */
1361 if (unlikely(status & tx_dma_own))
1364 /* Make sure descriptor fields are read after reading
1369 /* Just consider the last segment and ...*/
1370 if (likely(!(status & tx_not_ls))) {
1371 /* ... verify the status error condition */
1372 if (unlikely(status & tx_err)) {
1373 priv->dev->stats.tx_errors++;
1375 priv->dev->stats.tx_packets++;
1376 priv->xstats.tx_pkt_n++;
1378 stmmac_get_tx_hwtstamp(priv, p, skb);
1381 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1382 if (priv->tx_skbuff_dma[entry].map_as_page)
1383 dma_unmap_page(priv->device,
1384 priv->tx_skbuff_dma[entry].buf,
1385 priv->tx_skbuff_dma[entry].len,
1388 dma_unmap_single(priv->device,
1389 priv->tx_skbuff_dma[entry].buf,
1390 priv->tx_skbuff_dma[entry].len,
1392 priv->tx_skbuff_dma[entry].buf = 0;
1393 priv->tx_skbuff_dma[entry].len = 0;
1394 priv->tx_skbuff_dma[entry].map_as_page = false;
1397 if (priv->hw->mode->clean_desc3)
1398 priv->hw->mode->clean_desc3(priv, p);
1400 priv->tx_skbuff_dma[entry].last_segment = false;
1401 priv->tx_skbuff_dma[entry].is_jumbo = false;
1403 if (likely(skb != NULL)) {
1405 bytes_compl += skb->len;
1406 dev_consume_skb_any(skb);
1407 priv->tx_skbuff[entry] = NULL;
1410 priv->hw->desc->release_tx_desc(p, priv->mode);
1412 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1414 priv->dirty_tx = entry;
1416 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1418 if (unlikely(netif_queue_stopped(priv->dev) &&
1419 stmmac_tx_avail(priv) > STMMAC_TX_THRESH)) {
1420 netif_tx_lock(priv->dev);
1421 if (netif_queue_stopped(priv->dev) &&
1422 stmmac_tx_avail(priv) > STMMAC_TX_THRESH) {
1423 if (netif_msg_tx_done(priv))
1424 pr_debug("%s: restart transmit\n", __func__);
1425 netif_wake_queue(priv->dev);
1427 netif_tx_unlock(priv->dev);
1430 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1431 stmmac_enable_eee_mode(priv);
1432 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1434 spin_unlock(&priv->tx_lock);
1437 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1439 priv->hw->dma->enable_dma_irq(priv->ioaddr);
1442 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1444 priv->hw->dma->disable_dma_irq(priv->ioaddr);
1448 * stmmac_tx_err - to manage the tx error
1449 * @priv: driver private structure
1450 * Description: it cleans the descriptors and restarts the transmission
1451 * in case of transmission errors.
1453 static void stmmac_tx_err(struct stmmac_priv *priv)
1456 netif_stop_queue(priv->dev);
1458 priv->hw->dma->stop_tx(priv->ioaddr);
1459 dma_free_tx_skbufs(priv);
1460 for (i = 0; i < DMA_TX_SIZE; i++)
1461 if (priv->extend_desc)
1462 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1464 (i == DMA_TX_SIZE - 1));
1466 priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1468 (i == DMA_TX_SIZE - 1));
1471 netdev_reset_queue(priv->dev);
1472 priv->hw->dma->start_tx(priv->ioaddr);
1474 priv->dev->stats.tx_errors++;
1475 netif_wake_queue(priv->dev);
1479 * stmmac_dma_interrupt - DMA ISR
1480 * @priv: driver private structure
1481 * Description: this is the DMA ISR. It is called by the main ISR.
1482 * It calls the dwmac dma routine and schedule poll method in case of some
1485 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1488 int rxfifosz = priv->plat->rx_fifo_size;
1490 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1491 if (likely((status & handle_rx)) || (status & handle_tx)) {
1492 if (likely(napi_schedule_prep(&priv->napi))) {
1493 stmmac_disable_dma_irq(priv);
1494 __napi_schedule(&priv->napi);
1497 if (unlikely(status & tx_hard_error_bump_tc)) {
1498 /* Try to bump up the dma threshold on this failure */
1499 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1502 if (priv->plat->force_thresh_dma_mode)
1503 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1506 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1507 SF_DMA_MODE, rxfifosz);
1508 priv->xstats.threshold = tc;
1510 } else if (unlikely(status == tx_hard_error))
1511 stmmac_tx_err(priv);
1515 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1516 * @priv: driver private structure
1517 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1519 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1521 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1522 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1524 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1525 priv->ptpaddr = priv->ioaddr + PTP_GMAC4_OFFSET;
1526 priv->mmcaddr = priv->ioaddr + MMC_GMAC4_OFFSET;
1528 priv->ptpaddr = priv->ioaddr + PTP_GMAC3_X_OFFSET;
1529 priv->mmcaddr = priv->ioaddr + MMC_GMAC3_X_OFFSET;
1532 dwmac_mmc_intr_all_mask(priv->mmcaddr);
1534 if (priv->dma_cap.rmon) {
1535 dwmac_mmc_ctrl(priv->mmcaddr, mode);
1536 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1538 pr_info(" No MAC Management Counters available\n");
1542 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1543 * @priv: driver private structure
1544 * Description: select the Enhanced/Alternate or Normal descriptors.
1545 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1546 * supported by the HW capability register.
1548 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1550 if (priv->plat->enh_desc) {
1551 pr_info(" Enhanced/Alternate descriptors\n");
1553 /* GMAC older than 3.50 has no extended descriptors */
1554 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1555 pr_info("\tEnabled extended descriptors\n");
1556 priv->extend_desc = 1;
1558 pr_warn("Extended descriptors not supported\n");
1560 priv->hw->desc = &enh_desc_ops;
1562 pr_info(" Normal descriptors\n");
1563 priv->hw->desc = &ndesc_ops;
1568 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1569 * @priv: driver private structure
1571 * new GMAC chip generations have a new register to indicate the
1572 * presence of the optional feature/functions.
1573 * This can be also used to override the value passed through the
1574 * platform and necessary for old MAC10/100 and GMAC chips.
1576 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1580 if (priv->hw->dma->get_hw_feature) {
1581 priv->hw->dma->get_hw_feature(priv->ioaddr,
1590 * stmmac_check_ether_addr - check if the MAC addr is valid
1591 * @priv: driver private structure
1593 * it is to verify if the MAC address is valid, in case of failures it
1594 * generates a random MAC address
1596 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1598 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1599 priv->hw->mac->get_umac_addr(priv->hw,
1600 priv->dev->dev_addr, 0);
1601 if (!is_valid_ether_addr(priv->dev->dev_addr))
1602 eth_hw_addr_random(priv->dev);
1603 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1604 priv->dev->dev_addr);
1609 * stmmac_init_dma_engine - DMA init.
1610 * @priv: driver private structure
1612 * It inits the DMA invoking the specific MAC/GMAC callback.
1613 * Some DMA parameters can be passed from the platform;
1614 * in case of these are not passed a default is kept for the MAC or GMAC.
1616 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1618 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, aal = 0;
1619 int mixed_burst = 0;
1623 if (priv->plat->dma_cfg) {
1624 pbl = priv->plat->dma_cfg->pbl;
1625 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1626 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1627 aal = priv->plat->dma_cfg->aal;
1630 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1633 ret = priv->hw->dma->reset(priv->ioaddr);
1635 dev_err(priv->device, "Failed to reset the dma\n");
1639 priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1640 aal, priv->dma_tx_phy, priv->dma_rx_phy, atds);
1642 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
1643 priv->rx_tail_addr = priv->dma_rx_phy +
1644 (DMA_RX_SIZE * sizeof(struct dma_desc));
1645 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr, priv->rx_tail_addr,
1648 priv->tx_tail_addr = priv->dma_tx_phy +
1649 (DMA_TX_SIZE * sizeof(struct dma_desc));
1650 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
1654 if (priv->plat->axi && priv->hw->dma->axi)
1655 priv->hw->dma->axi(priv->ioaddr, priv->plat->axi);
1661 * stmmac_tx_timer - mitigation sw timer for tx.
1662 * @data: data pointer
1664 * This is the timer handler to directly invoke the stmmac_tx_clean.
1666 static void stmmac_tx_timer(unsigned long data)
1668 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1670 stmmac_tx_clean(priv);
1674 * stmmac_init_tx_coalesce - init tx mitigation options.
1675 * @priv: driver private structure
1677 * This inits the transmit coalesce parameters: i.e. timer rate,
1678 * timer handler and default threshold used for enabling the
1679 * interrupt on completion bit.
1681 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1683 priv->tx_coal_frames = STMMAC_TX_FRAMES;
1684 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1685 init_timer(&priv->txtimer);
1686 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1687 priv->txtimer.data = (unsigned long)priv;
1688 priv->txtimer.function = stmmac_tx_timer;
1689 add_timer(&priv->txtimer);
1693 * stmmac_hw_setup - setup mac in a usable state.
1694 * @dev : pointer to the device structure.
1696 * this is the main function to setup the HW in a usable state because the
1697 * dma engine is reset, the core registers are configured (e.g. AXI,
1698 * Checksum features, timers). The DMA is ready to start receiving and
1701 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1704 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1706 struct stmmac_priv *priv = netdev_priv(dev);
1709 /* DMA initialization and SW reset */
1710 ret = stmmac_init_dma_engine(priv);
1712 pr_err("%s: DMA engine initialization failed\n", __func__);
1716 /* Copy the MAC addr into the HW */
1717 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1719 /* If required, perform hw setup of the bus. */
1720 if (priv->plat->bus_setup)
1721 priv->plat->bus_setup(priv->ioaddr);
1723 /* PS and related bits will be programmed according to the speed */
1724 if (priv->hw->pcs) {
1725 int speed = priv->plat->mac_port_sel_speed;
1727 if ((speed == SPEED_10) || (speed == SPEED_100) ||
1728 (speed == SPEED_1000)) {
1729 priv->hw->ps = speed;
1731 dev_warn(priv->device, "invalid port speed\n");
1736 /* Initialize the MAC Core */
1737 priv->hw->mac->core_init(priv->hw, dev->mtu);
1739 ret = priv->hw->mac->rx_ipc(priv->hw);
1741 pr_warn(" RX IPC Checksum Offload disabled\n");
1742 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1743 priv->hw->rx_csum = 0;
1746 /* Enable the MAC Rx/Tx */
1747 if (priv->synopsys_id >= DWMAC_CORE_4_00)
1748 stmmac_dwmac4_set_mac(priv->ioaddr, true);
1750 stmmac_set_mac(priv->ioaddr, true);
1752 /* Set the HW DMA mode and the COE */
1753 stmmac_dma_operation_mode(priv);
1755 stmmac_mmc_setup(priv);
1758 ret = stmmac_init_ptp(priv);
1760 netdev_warn(priv->dev, "fail to init PTP.\n");
1763 #ifdef CONFIG_DEBUG_FS
1764 ret = stmmac_init_fs(dev);
1766 pr_warn("%s: failed debugFS registration\n", __func__);
1768 /* Dump DMA/MAC registers */
1769 if (netif_msg_hw(priv)) {
1770 priv->hw->mac->dump_regs(priv->hw);
1771 priv->hw->dma->dump_regs(priv->ioaddr);
1773 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1775 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1776 priv->rx_riwt = MAX_DMA_RIWT;
1777 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1780 if (priv->hw->pcs && priv->hw->mac->pcs_ctrl_ane)
1781 priv->hw->mac->pcs_ctrl_ane(priv->hw, 1, priv->hw->ps, 0);
1783 /* set TX ring length */
1784 if (priv->hw->dma->set_tx_ring_len)
1785 priv->hw->dma->set_tx_ring_len(priv->ioaddr,
1787 /* set RX ring length */
1788 if (priv->hw->dma->set_rx_ring_len)
1789 priv->hw->dma->set_rx_ring_len(priv->ioaddr,
1793 priv->hw->dma->enable_tso(priv->ioaddr, 1, STMMAC_CHAN0);
1795 /* Start the ball rolling... */
1796 pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1797 priv->hw->dma->start_tx(priv->ioaddr);
1798 priv->hw->dma->start_rx(priv->ioaddr);
1804 static int suspend_pm_notify(struct notifier_block *nb,
1805 unsigned long mode, void *_unused)
1808 case PM_SUSPEND_PREPARE:
1809 cancel_delayed_work_sync(&moniter_tx_worker);
1810 flush_scheduled_work();
1811 pr_info("receive suspend notify\n");
1819 static struct notifier_block suspend_pm_nb = {
1820 .notifier_call = suspend_pm_notify,
1824 * stmmac_open - open entry point of the driver
1825 * @dev : pointer to the device structure.
1827 * This function is the open entry point of the driver.
1829 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1832 static int stmmac_open(struct net_device *dev)
1834 struct stmmac_priv *priv = netdev_priv(dev);
1837 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
1838 priv->hw->pcs != STMMAC_PCS_TBI &&
1839 priv->hw->pcs != STMMAC_PCS_RTBI) {
1840 ret = stmmac_init_phy(dev);
1842 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1848 /* Extra statistics */
1849 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1850 priv->xstats.threshold = tc;
1852 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1853 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
1856 ret = alloc_dma_desc_resources(priv);
1858 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1859 goto dma_desc_error;
1862 ret = init_dma_desc_rings(dev, GFP_KERNEL);
1864 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1868 ret = stmmac_hw_setup(dev, true);
1870 pr_err("%s: Hw setup failed\n", __func__);
1874 stmmac_init_tx_coalesce(priv);
1877 phy_start(priv->phydev);
1879 /* Request the IRQ lines */
1880 ret = request_irq(dev->irq, stmmac_interrupt,
1881 IRQF_SHARED, dev->name, dev);
1882 if (unlikely(ret < 0)) {
1883 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1884 __func__, dev->irq, ret);
1888 /* Request the Wake IRQ in case of another line is used for WoL */
1889 if (priv->wol_irq != dev->irq) {
1890 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1891 IRQF_SHARED, dev->name, dev);
1892 if (unlikely(ret < 0)) {
1893 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1894 __func__, priv->wol_irq, ret);
1899 /* Request the IRQ lines */
1900 if (priv->lpi_irq > 0) {
1901 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1903 if (unlikely(ret < 0)) {
1904 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1905 __func__, priv->lpi_irq, ret);
1910 napi_enable(&priv->napi);
1911 netif_start_queue(dev);
1913 queue_delayed_work(moniter_tx_wq, &moniter_tx_worker, HZ);
1918 if (priv->wol_irq != dev->irq)
1919 free_irq(priv->wol_irq, dev);
1921 free_irq(dev->irq, dev);
1924 free_dma_desc_resources(priv);
1927 phy_disconnect(priv->phydev);
1933 * stmmac_release - close entry point of the driver
1934 * @dev : device pointer.
1936 * This is the stop entry point of the driver.
1938 static int stmmac_release(struct net_device *dev)
1940 struct stmmac_priv *priv = netdev_priv(dev);
1942 if (priv->eee_enabled)
1943 del_timer_sync(&priv->eee_ctrl_timer);
1945 /* Stop and disconnect the PHY */
1947 phy_stop(priv->phydev);
1948 phy_disconnect(priv->phydev);
1949 priv->phydev = NULL;
1952 netif_stop_queue(dev);
1954 napi_disable(&priv->napi);
1956 del_timer_sync(&priv->txtimer);
1958 /* Free the IRQ lines */
1959 free_irq(dev->irq, dev);
1960 if (priv->wol_irq != dev->irq)
1961 free_irq(priv->wol_irq, dev);
1962 if (priv->lpi_irq > 0)
1963 free_irq(priv->lpi_irq, dev);
1965 /* Stop TX/RX DMA and clear the descriptors */
1966 priv->hw->dma->stop_tx(priv->ioaddr);
1967 priv->hw->dma->stop_rx(priv->ioaddr);
1969 /* Release and free the Rx/Tx resources */
1970 free_dma_desc_resources(priv);
1972 /* Disable the MAC Rx/Tx */
1973 stmmac_set_mac(priv->ioaddr, false);
1975 netif_carrier_off(dev);
1977 #ifdef CONFIG_DEBUG_FS
1978 stmmac_exit_fs(dev);
1981 stmmac_release_ptp(priv);
1987 * stmmac_tso_allocator - close entry point of the driver
1988 * @priv: driver private structure
1989 * @des: buffer start address
1990 * @total_len: total length to fill in descriptors
1991 * @last_segmant: condition for the last descriptor
1993 * This function fills descriptor and request new descriptors according to
1994 * buffer length to fill
1996 static void stmmac_tso_allocator(struct stmmac_priv *priv, unsigned int des,
1997 int total_len, bool last_segment)
1999 struct dma_desc *desc;
2003 tmp_len = total_len;
2005 while (tmp_len > 0) {
2006 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2007 desc = priv->dma_tx + priv->cur_tx;
2009 desc->des0 = cpu_to_le32(des + (total_len - tmp_len));
2010 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2011 TSO_MAX_BUFF_SIZE : tmp_len;
2013 priv->hw->desc->prepare_tso_tx_desc(desc, 0, buff_size,
2015 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2018 tmp_len -= TSO_MAX_BUFF_SIZE;
2023 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2024 * @skb : the socket buffer
2025 * @dev : device pointer
2026 * Description: this is the transmit function that is called on TSO frames
2027 * (support available on GMAC4 and newer chips).
2028 * Diagram below show the ring programming in case of TSO frames:
2032 * | DES0 |---> buffer1 = L2/L3/L4 header
2033 * | DES1 |---> TCP Payload (can continue on next descr...)
2034 * | DES2 |---> buffer 1 and 2 len
2035 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2041 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2043 * | DES2 | --> buffer 1 and 2 len
2047 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2049 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2052 int tmp_pay_len = 0;
2053 struct stmmac_priv *priv = netdev_priv(dev);
2054 int nfrags = skb_shinfo(skb)->nr_frags;
2055 unsigned int first_entry, des;
2056 struct dma_desc *desc, *first, *mss_desc = NULL;
2060 spin_lock(&priv->tx_lock);
2062 /* Compute header lengths */
2063 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2065 /* Desc availability based on threshold should be enough safe */
2066 if (unlikely(stmmac_tx_avail(priv) <
2067 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2068 if (!netif_queue_stopped(dev)) {
2069 netif_stop_queue(dev);
2070 /* This is a hard error, log it. */
2071 pr_err("%s: Tx Ring full when queue awake\n", __func__);
2073 spin_unlock(&priv->tx_lock);
2074 return NETDEV_TX_BUSY;
2077 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2079 mss = skb_shinfo(skb)->gso_size;
2081 /* set new MSS value if needed */
2082 if (mss != priv->mss) {
2083 mss_desc = priv->dma_tx + priv->cur_tx;
2084 priv->hw->desc->set_mss(mss_desc, mss);
2086 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2089 if (netif_msg_tx_queued(priv)) {
2090 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2091 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2092 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2096 first_entry = priv->cur_tx;
2098 desc = priv->dma_tx + first_entry;
2101 /* first descriptor: fill Headers on Buf1 */
2102 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2104 if (dma_mapping_error(priv->device, des))
2107 priv->tx_skbuff_dma[first_entry].buf = des;
2108 priv->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2109 priv->tx_skbuff[first_entry] = skb;
2111 first->des0 = cpu_to_le32(des);
2113 /* Fill start of payload in buff2 of first descriptor */
2115 first->des1 = cpu_to_le32(des + proto_hdr_len);
2117 /* If needed take extra descriptors to fill the remaining payload */
2118 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2120 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0));
2122 /* Prepare fragments */
2123 for (i = 0; i < nfrags; i++) {
2124 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2126 des = skb_frag_dma_map(priv->device, frag, 0,
2127 skb_frag_size(frag),
2130 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2133 priv->tx_skbuff_dma[priv->cur_tx].buf = des;
2134 priv->tx_skbuff_dma[priv->cur_tx].len = skb_frag_size(frag);
2135 priv->tx_skbuff[priv->cur_tx] = NULL;
2136 priv->tx_skbuff_dma[priv->cur_tx].map_as_page = true;
2139 priv->tx_skbuff_dma[priv->cur_tx].last_segment = true;
2141 priv->cur_tx = STMMAC_GET_ENTRY(priv->cur_tx, DMA_TX_SIZE);
2143 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2144 if (netif_msg_hw(priv))
2145 pr_debug("%s: stop transmitted packets\n", __func__);
2146 netif_stop_queue(dev);
2149 dev->stats.tx_bytes += skb->len;
2150 priv->xstats.tx_tso_frames++;
2151 priv->xstats.tx_tso_nfrags += nfrags;
2153 /* Manage tx mitigation */
2154 priv->tx_count_frames += nfrags + 1;
2155 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2156 mod_timer(&priv->txtimer,
2157 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2159 priv->tx_count_frames = 0;
2160 priv->hw->desc->set_tx_ic(desc);
2161 priv->xstats.tx_set_ic_bit++;
2164 if (!priv->hwts_tx_en)
2165 skb_tx_timestamp(skb);
2167 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2168 priv->hwts_tx_en)) {
2169 /* declare that device is doing timestamping */
2170 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2171 priv->hw->desc->enable_tx_timestamp(first);
2174 /* Complete the first descriptor before granting the DMA */
2175 priv->hw->desc->prepare_tso_tx_desc(first, 1,
2178 1, priv->tx_skbuff_dma[first_entry].last_segment,
2179 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2181 /* If context desc is used to change MSS */
2183 /* Make sure that first descriptor has been completely
2184 * written, including its own bit. This is because MSS is
2185 * actually before first descriptor, so we need to make
2186 * sure that MSS's own bit is the last thing written.
2189 priv->hw->desc->set_tx_owner(mss_desc);
2192 /* The own bit must be the latest setting done when prepare the
2193 * descriptor and then barrier is needed to make sure that
2194 * all is coherent before granting the DMA engine.
2198 if (netif_msg_pktdata(priv)) {
2199 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2200 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2201 priv->cur_tx, first, nfrags);
2203 priv->hw->desc->display_ring((void *)priv->dma_tx, DMA_TX_SIZE,
2206 pr_info(">>> frame to be transmitted: ");
2207 print_pkt(skb->data, skb_headlen(skb));
2210 netdev_sent_queue(dev, skb->len);
2212 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2215 spin_unlock(&priv->tx_lock);
2216 return NETDEV_TX_OK;
2219 spin_unlock(&priv->tx_lock);
2220 dev_err(priv->device, "Tx dma map failed\n");
2222 priv->dev->stats.tx_dropped++;
2223 return NETDEV_TX_OK;
2227 * stmmac_xmit - Tx entry point of the driver
2228 * @skb : the socket buffer
2229 * @dev : device pointer
2230 * Description : this is the tx entry point of the driver.
2231 * It programs the chain or the ring and supports oversized frames
2234 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
2236 struct stmmac_priv *priv = netdev_priv(dev);
2237 unsigned int nopaged_len = skb_headlen(skb);
2238 int i, csum_insertion = 0, is_jumbo = 0;
2239 int nfrags = skb_shinfo(skb)->nr_frags;
2241 unsigned int first_entry;
2242 struct dma_desc *desc, *first;
2243 unsigned int enh_desc;
2246 /* Manage oversized TCP frames for GMAC4 device */
2247 if (skb_is_gso(skb) && priv->tso) {
2248 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
2249 return stmmac_tso_xmit(skb, dev);
2252 spin_lock(&priv->tx_lock);
2254 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
2255 spin_unlock(&priv->tx_lock);
2256 if (!netif_queue_stopped(dev)) {
2257 netif_stop_queue(dev);
2258 /* This is a hard error, log it. */
2259 pr_err("%s: Tx Ring full when queue awake\n", __func__);
2261 return NETDEV_TX_BUSY;
2264 if (priv->tx_path_in_lpi_mode)
2265 stmmac_disable_eee_mode(priv);
2267 entry = priv->cur_tx;
2268 first_entry = entry;
2270 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
2272 if (likely(priv->extend_desc))
2273 desc = (struct dma_desc *)(priv->dma_etx + entry);
2275 desc = priv->dma_tx + entry;
2279 priv->tx_skbuff[first_entry] = skb;
2281 enh_desc = priv->plat->enh_desc;
2282 /* To program the descriptors according to the size of the frame */
2284 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
2286 if (unlikely(is_jumbo) && likely(priv->synopsys_id <
2288 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
2289 if (unlikely(entry < 0))
2293 for (i = 0; i < nfrags; i++) {
2294 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2295 int len = skb_frag_size(frag);
2296 bool last_segment = (i == (nfrags - 1));
2298 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2300 if (likely(priv->extend_desc))
2301 desc = (struct dma_desc *)(priv->dma_etx + entry);
2303 desc = priv->dma_tx + entry;
2305 des = skb_frag_dma_map(priv->device, frag, 0, len,
2307 if (dma_mapping_error(priv->device, des))
2308 goto dma_map_err; /* should reuse desc w/o issues */
2310 priv->tx_skbuff[entry] = NULL;
2312 priv->tx_skbuff_dma[entry].buf = des;
2313 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2314 desc->des0 = cpu_to_le32(des);
2316 desc->des2 = cpu_to_le32(des);
2318 priv->tx_skbuff_dma[entry].map_as_page = true;
2319 priv->tx_skbuff_dma[entry].len = len;
2320 priv->tx_skbuff_dma[entry].last_segment = last_segment;
2322 /* Prepare the descriptor and set the own bit too */
2323 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2324 priv->mode, 1, last_segment);
2327 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
2329 priv->cur_tx = entry;
2331 if (netif_msg_pktdata(priv)) {
2334 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2335 __func__, priv->cur_tx, priv->dirty_tx, first_entry,
2336 entry, first, nfrags);
2338 if (priv->extend_desc)
2339 tx_head = (void *)priv->dma_etx;
2341 tx_head = (void *)priv->dma_tx;
2343 priv->hw->desc->display_ring(tx_head, DMA_TX_SIZE, false);
2345 pr_debug(">>> frame to be transmitted: ");
2346 print_pkt(skb->data, skb->len);
2349 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2350 if (netif_msg_hw(priv))
2351 pr_debug("%s: stop transmitted packets\n", __func__);
2352 netif_stop_queue(dev);
2355 dev->stats.tx_bytes += skb->len;
2357 /* According to the coalesce parameter the IC bit for the latest
2358 * segment is reset and the timer re-started to clean the tx status.
2359 * This approach takes care about the fragments: desc is the first
2360 * element in case of no SG.
2362 priv->tx_count_frames += nfrags + 1;
2363 if (likely(priv->tx_coal_frames > priv->tx_count_frames)) {
2364 mod_timer(&priv->txtimer,
2365 STMMAC_COAL_TIMER(priv->tx_coal_timer));
2367 priv->tx_count_frames = 0;
2368 priv->hw->desc->set_tx_ic(desc);
2369 priv->xstats.tx_set_ic_bit++;
2372 if (!priv->hwts_tx_en)
2373 skb_tx_timestamp(skb);
2375 /* Ready to fill the first descriptor and set the OWN bit w/o any
2376 * problems because all the descriptors are actually ready to be
2377 * passed to the DMA engine.
2379 if (likely(!is_jumbo)) {
2380 bool last_segment = (nfrags == 0);
2382 des = dma_map_single(priv->device, skb->data,
2383 nopaged_len, DMA_TO_DEVICE);
2384 if (dma_mapping_error(priv->device, des))
2387 priv->tx_skbuff_dma[first_entry].buf = des;
2388 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2389 first->des0 = cpu_to_le32(des);
2391 first->des2 = cpu_to_le32(des);
2393 priv->tx_skbuff_dma[first_entry].len = nopaged_len;
2394 priv->tx_skbuff_dma[first_entry].last_segment = last_segment;
2396 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2397 priv->hwts_tx_en)) {
2398 /* declare that device is doing timestamping */
2399 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2400 priv->hw->desc->enable_tx_timestamp(first);
2403 /* Prepare the first descriptor setting the OWN bit too */
2404 priv->hw->desc->prepare_tx_desc(first, 1, nopaged_len,
2405 csum_insertion, priv->mode, 1,
2408 /* The own bit must be the latest setting done when prepare the
2409 * descriptor and then barrier is needed to make sure that
2410 * all is coherent before granting the DMA engine.
2415 netdev_sent_queue(dev, skb->len);
2417 if (priv->synopsys_id < DWMAC_CORE_4_00)
2418 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2420 priv->hw->dma->set_tx_tail_ptr(priv->ioaddr, priv->tx_tail_addr,
2423 spin_unlock(&priv->tx_lock);
2424 return NETDEV_TX_OK;
2427 spin_unlock(&priv->tx_lock);
2428 dev_err(priv->device, "Tx dma map failed\n");
2430 priv->dev->stats.tx_dropped++;
2431 return NETDEV_TX_OK;
2434 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2436 struct ethhdr *ehdr;
2439 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2440 NETIF_F_HW_VLAN_CTAG_RX &&
2441 !__vlan_get_tag(skb, &vlanid)) {
2442 /* pop the vlan tag */
2443 ehdr = (struct ethhdr *)skb->data;
2444 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2445 skb_pull(skb, VLAN_HLEN);
2446 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2451 static inline int stmmac_rx_threshold_count(struct stmmac_priv *priv)
2453 if (priv->rx_zeroc_thresh < STMMAC_RX_THRESH)
2460 * stmmac_rx_refill - refill used skb preallocated buffers
2461 * @priv: driver private structure
2462 * Description : this is to reallocate the skb for the reception process
2463 * that is based on zero-copy.
2465 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2467 int bfsize = priv->dma_buf_sz;
2468 unsigned int entry = priv->dirty_rx;
2469 int dirty = stmmac_rx_dirty(priv);
2471 while (dirty-- > 0) {
2474 if (priv->extend_desc)
2475 p = (struct dma_desc *)(priv->dma_erx + entry);
2477 p = priv->dma_rx + entry;
2479 if (likely(priv->rx_skbuff[entry] == NULL)) {
2480 struct sk_buff *skb;
2482 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2483 if (unlikely(!skb)) {
2484 /* so for a while no zero-copy! */
2485 priv->rx_zeroc_thresh = STMMAC_RX_THRESH;
2486 if (unlikely(net_ratelimit()))
2487 dev_err(priv->device,
2488 "fail to alloc skb entry %d\n",
2493 priv->rx_skbuff[entry] = skb;
2494 priv->rx_skbuff_dma[entry] =
2495 dma_map_single(priv->device, skb->data, bfsize,
2497 if (dma_mapping_error(priv->device,
2498 priv->rx_skbuff_dma[entry])) {
2499 dev_err(priv->device, "Rx dma map failed\n");
2504 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00)) {
2505 p->des0 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2508 p->des2 = cpu_to_le32(priv->rx_skbuff_dma[entry]);
2510 if (priv->hw->mode->refill_desc3)
2511 priv->hw->mode->refill_desc3(priv, p);
2513 if (priv->rx_zeroc_thresh > 0)
2514 priv->rx_zeroc_thresh--;
2516 if (netif_msg_rx_status(priv))
2517 pr_debug("\trefill entry #%d\n", entry);
2521 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2522 priv->hw->desc->init_rx_desc(p, priv->use_riwt, 0, 0, priv->dma_buf_sz);
2524 priv->hw->desc->set_rx_owner(p);
2528 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
2530 priv->dirty_rx = entry;
2534 * stmmac_rx - manage the receive process
2535 * @priv: driver private structure
2536 * @limit: napi bugget.
2537 * Description : this the function called by the napi poll method.
2538 * It gets all the frames inside the ring.
2540 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2542 unsigned int next_entry = priv->cur_rx;
2543 unsigned int count = 0;
2544 int coe = priv->hw->rx_csum;
2546 if (netif_msg_rx_status(priv)) {
2549 pr_info(">>>>>> %s: descriptor ring:\n", __func__);
2550 if (priv->extend_desc)
2551 rx_head = (void *)priv->dma_erx;
2553 rx_head = (void *)priv->dma_rx;
2555 priv->hw->desc->display_ring(rx_head, DMA_RX_SIZE, true);
2557 while (count < limit) {
2560 struct dma_desc *np;
2564 if (priv->extend_desc)
2565 p = (struct dma_desc *)(priv->dma_erx + entry);
2567 p = priv->dma_rx + entry;
2569 /* read the status of the incoming frame */
2570 status = priv->hw->desc->rx_status(&priv->dev->stats,
2572 /* check if managed by the DMA otherwise go ahead */
2573 if (unlikely(status & dma_own))
2578 priv->cur_rx = STMMAC_GET_ENTRY(priv->cur_rx, DMA_RX_SIZE);
2579 next_entry = priv->cur_rx;
2581 if (priv->extend_desc)
2582 np = (struct dma_desc *)(priv->dma_erx + next_entry);
2584 np = priv->dma_rx + next_entry;
2588 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2589 priv->hw->desc->rx_extended_status(&priv->dev->stats,
2593 if (unlikely(status == discard_frame)) {
2594 priv->dev->stats.rx_errors++;
2595 if (priv->hwts_rx_en && !priv->extend_desc) {
2596 /* DESC2 & DESC3 will be overwitten by device
2597 * with timestamp value, hence reinitialize
2598 * them in stmmac_rx_refill() function so that
2599 * device can reuse it.
2601 priv->rx_skbuff[entry] = NULL;
2602 dma_unmap_single(priv->device,
2603 priv->rx_skbuff_dma[entry],
2608 struct sk_buff *skb;
2612 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00))
2613 des = le32_to_cpu(p->des0);
2615 des = le32_to_cpu(p->des2);
2617 frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2619 /* If frame length is greather than skb buffer size
2620 * (preallocated during init) then the packet is
2623 if (frame_len > priv->dma_buf_sz) {
2624 pr_err("%s: len %d larger than size (%d)\n",
2625 priv->dev->name, frame_len,
2627 priv->dev->stats.rx_length_errors++;
2631 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2632 * Type frames (LLC/LLC-SNAP)
2634 if (unlikely(status != llc_snap))
2635 frame_len -= ETH_FCS_LEN;
2637 if (netif_msg_rx_status(priv)) {
2638 pr_info("\tdesc: %p [entry %d] buff=0x%x\n",
2640 if (frame_len > ETH_FRAME_LEN)
2641 pr_debug("\tframe size %d, COE: %d\n",
2645 /* The zero-copy is always used for all the sizes
2646 * in case of GMAC4 because it needs
2647 * to refill the used descriptors, always.
2649 if (unlikely(!priv->plat->has_gmac4 &&
2650 ((frame_len < priv->rx_copybreak) ||
2651 stmmac_rx_threshold_count(priv)))) {
2652 skb = netdev_alloc_skb_ip_align(priv->dev,
2654 if (unlikely(!skb)) {
2655 if (net_ratelimit())
2656 dev_warn(priv->device,
2657 "packet dropped\n");
2658 priv->dev->stats.rx_dropped++;
2662 dma_sync_single_for_cpu(priv->device,
2666 skb_copy_to_linear_data(skb,
2668 rx_skbuff[entry]->data,
2671 skb_put(skb, frame_len);
2672 dma_sync_single_for_device(priv->device,
2677 skb = priv->rx_skbuff[entry];
2678 if (unlikely(!skb)) {
2679 pr_err("%s: Inconsistent Rx chain\n",
2681 priv->dev->stats.rx_dropped++;
2684 prefetch(skb->data - NET_IP_ALIGN);
2685 priv->rx_skbuff[entry] = NULL;
2686 priv->rx_zeroc_thresh++;
2688 skb_put(skb, frame_len);
2689 dma_unmap_single(priv->device,
2690 priv->rx_skbuff_dma[entry],
2695 if (netif_msg_pktdata(priv)) {
2696 pr_debug("frame received (%dbytes)", frame_len);
2697 print_pkt(skb->data, frame_len);
2700 stmmac_get_rx_hwtstamp(priv, p, np, skb);
2702 stmmac_rx_vlan(priv->dev, skb);
2704 skb->protocol = eth_type_trans(skb, priv->dev);
2707 skb_checksum_none_assert(skb);
2709 skb->ip_summed = CHECKSUM_UNNECESSARY;
2711 napi_gro_receive(&priv->napi, skb);
2713 priv->dev->stats.rx_packets++;
2714 priv->dev->stats.rx_bytes += frame_len;
2718 stmmac_rx_refill(priv);
2720 priv->xstats.rx_pkt_n += count;
2726 * stmmac_poll - stmmac poll method (NAPI)
2727 * @napi : pointer to the napi structure.
2728 * @budget : maximum number of packets that the current CPU can receive from
2731 * To look at the incoming frames and clear the tx resources.
2733 static int stmmac_poll(struct napi_struct *napi, int budget)
2735 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2738 priv->xstats.napi_poll++;
2739 stmmac_tx_clean(priv);
2741 work_done = stmmac_rx(priv, budget);
2742 if (work_done < budget) {
2743 napi_complete(napi);
2744 stmmac_enable_dma_irq(priv);
2751 * @dev : Pointer to net device structure
2752 * Description: this function is called when a packet transmission fails to
2753 * complete within a reasonable time. The driver will mark the error in the
2754 * netdev structure and arrange for the device to be reset to a sane state
2755 * in order to transmit a new packet.
2758 unsigned int timeout_err;
2760 static void stmmac_tx_timeout(struct net_device *dev)
2762 struct stmmac_priv *priv = netdev_priv(dev);
2764 /* Clear Tx resources and restart transmitting again */
2765 stmmac_tx_err(priv);
2769 * stmmac_set_rx_mode - entry point for multicast addressing
2770 * @dev : pointer to the device structure
2772 * This function is a driver entry point which gets called by the kernel
2773 * whenever multicast addresses must be enabled/disabled.
2777 static void stmmac_set_rx_mode(struct net_device *dev)
2779 struct stmmac_priv *priv = netdev_priv(dev);
2781 priv->hw->mac->set_filter(priv->hw, dev);
2785 * stmmac_change_mtu - entry point to change MTU size for the device.
2786 * @dev : device pointer.
2787 * @new_mtu : the new MTU size for the device.
2788 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2789 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2790 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2792 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2795 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2797 struct stmmac_priv *priv = netdev_priv(dev);
2800 if (netif_running(dev)) {
2801 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2805 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
2806 max_mtu = JUMBO_LEN;
2808 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2810 if (priv->plat->maxmtu < max_mtu)
2811 max_mtu = priv->plat->maxmtu;
2813 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2814 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2820 netdev_update_features(dev);
2825 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2826 netdev_features_t features)
2828 struct stmmac_priv *priv = netdev_priv(dev);
2830 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2831 features &= ~NETIF_F_RXCSUM;
2833 if (!priv->plat->tx_coe)
2834 features &= ~NETIF_F_CSUM_MASK;
2836 /* Some GMAC devices have a bugged Jumbo frame support that
2837 * needs to have the Tx COE disabled for oversized frames
2838 * (due to limited buffer sizes). In this case we disable
2839 * the TX csum insertionin the TDES and not use SF.
2841 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2842 features &= ~NETIF_F_CSUM_MASK;
2844 /* Disable tso if asked by ethtool */
2845 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
2846 if (features & NETIF_F_TSO)
2855 static int stmmac_set_features(struct net_device *netdev,
2856 netdev_features_t features)
2858 struct stmmac_priv *priv = netdev_priv(netdev);
2860 /* Keep the COE Type in case of csum is supporting */
2861 if (features & NETIF_F_RXCSUM)
2862 priv->hw->rx_csum = priv->plat->rx_coe;
2864 priv->hw->rx_csum = 0;
2865 /* No check needed because rx_coe has been set before and it will be
2866 * fixed in case of issue.
2868 priv->hw->mac->rx_ipc(priv->hw);
2874 * stmmac_interrupt - main ISR
2875 * @irq: interrupt number.
2876 * @dev_id: to pass the net device pointer.
2877 * Description: this is the main driver interrupt service routine.
2879 * o DMA service routine (to manage incoming frame reception and transmission
2881 * o Core interrupts to manage: remote wake-up, management counter, LPI
2884 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2886 struct net_device *dev = (struct net_device *)dev_id;
2887 struct stmmac_priv *priv = netdev_priv(dev);
2890 pm_wakeup_event(priv->device, 0);
2892 if (unlikely(!dev)) {
2893 pr_err("%s: invalid dev pointer\n", __func__);
2897 /* To handle GMAC own interrupts */
2898 if ((priv->plat->has_gmac) || (priv->plat->has_gmac4)) {
2899 int status = priv->hw->mac->host_irq_status(priv->hw,
2901 if (unlikely(status)) {
2902 /* For LPI we need to save the tx status */
2903 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2904 priv->tx_path_in_lpi_mode = true;
2905 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2906 priv->tx_path_in_lpi_mode = false;
2907 if (status & CORE_IRQ_MTL_RX_OVERFLOW && priv->hw->dma->set_rx_tail_ptr)
2908 priv->hw->dma->set_rx_tail_ptr(priv->ioaddr,
2913 /* PCS link status */
2914 if (priv->hw->pcs) {
2915 if (priv->xstats.pcs_link)
2916 netif_carrier_on(dev);
2918 netif_carrier_off(dev);
2922 /* To handle DMA interrupts */
2923 stmmac_dma_interrupt(priv);
2928 #ifdef CONFIG_NET_POLL_CONTROLLER
2929 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2930 * to allow network I/O with interrupts disabled.
2932 static void stmmac_poll_controller(struct net_device *dev)
2934 disable_irq(dev->irq);
2935 stmmac_interrupt(dev->irq, dev);
2936 enable_irq(dev->irq);
2941 * stmmac_ioctl - Entry point for the Ioctl
2942 * @dev: Device pointer.
2943 * @rq: An IOCTL specefic structure, that can contain a pointer to
2944 * a proprietary structure used to pass information to the driver.
2945 * @cmd: IOCTL command
2947 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2949 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2951 struct stmmac_priv *priv = netdev_priv(dev);
2952 int ret = -EOPNOTSUPP;
2954 if (!netif_running(dev))
2963 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2966 ret = stmmac_hwtstamp_ioctl(dev, rq);
2975 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
2977 struct stmmac_priv *priv = netdev_priv(ndev);
2980 ret = eth_mac_addr(ndev, addr);
2984 priv->hw->mac->set_umac_addr(priv->hw, ndev->dev_addr, 0);
2989 #ifdef CONFIG_DEBUG_FS
2990 static struct dentry *stmmac_fs_dir;
2992 static void sysfs_display_ring(void *head, int size, int extend_desc,
2993 struct seq_file *seq)
2996 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2997 struct dma_desc *p = (struct dma_desc *)head;
2999 for (i = 0; i < size; i++) {
3003 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3004 i, (unsigned int)virt_to_phys(ep),
3005 le32_to_cpu(ep->basic.des0),
3006 le32_to_cpu(ep->basic.des1),
3007 le32_to_cpu(ep->basic.des2),
3008 le32_to_cpu(ep->basic.des3));
3012 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3013 i, (unsigned int)virt_to_phys(ep),
3014 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3015 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3018 seq_printf(seq, "\n");
3022 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
3024 struct net_device *dev = seq->private;
3025 struct stmmac_priv *priv = netdev_priv(dev);
3027 if (priv->extend_desc) {
3028 seq_printf(seq, "Extended RX descriptor ring:\n");
3029 sysfs_display_ring((void *)priv->dma_erx, DMA_RX_SIZE, 1, seq);
3030 seq_printf(seq, "Extended TX descriptor ring:\n");
3031 sysfs_display_ring((void *)priv->dma_etx, DMA_TX_SIZE, 1, seq);
3033 seq_printf(seq, "RX descriptor ring:\n");
3034 sysfs_display_ring((void *)priv->dma_rx, DMA_RX_SIZE, 0, seq);
3035 seq_printf(seq, "TX descriptor ring:\n");
3036 sysfs_display_ring((void *)priv->dma_tx, DMA_TX_SIZE, 0, seq);
3042 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
3044 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
3047 static const struct file_operations stmmac_rings_status_fops = {
3048 .owner = THIS_MODULE,
3049 .open = stmmac_sysfs_ring_open,
3051 .llseek = seq_lseek,
3052 .release = single_release,
3055 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
3057 struct net_device *dev = seq->private;
3058 struct stmmac_priv *priv = netdev_priv(dev);
3060 if (!priv->hw_cap_support) {
3061 seq_printf(seq, "DMA HW features not supported\n");
3065 seq_printf(seq, "==============================\n");
3066 seq_printf(seq, "\tDMA HW features\n");
3067 seq_printf(seq, "==============================\n");
3069 seq_printf(seq, "\t10/100 Mbps %s\n",
3070 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3071 seq_printf(seq, "\t1000 Mbps %s\n",
3072 (priv->dma_cap.mbps_1000) ? "Y" : "N");
3073 seq_printf(seq, "\tHalf duple %s\n",
3074 (priv->dma_cap.half_duplex) ? "Y" : "N");
3075 seq_printf(seq, "\tHash Filter: %s\n",
3076 (priv->dma_cap.hash_filter) ? "Y" : "N");
3077 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3078 (priv->dma_cap.multi_addr) ? "Y" : "N");
3079 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
3080 (priv->dma_cap.pcs) ? "Y" : "N");
3081 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3082 (priv->dma_cap.sma_mdio) ? "Y" : "N");
3083 seq_printf(seq, "\tPMT Remote wake up: %s\n",
3084 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3085 seq_printf(seq, "\tPMT Magic Frame: %s\n",
3086 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3087 seq_printf(seq, "\tRMON module: %s\n",
3088 (priv->dma_cap.rmon) ? "Y" : "N");
3089 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3090 (priv->dma_cap.time_stamp) ? "Y" : "N");
3091 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
3092 (priv->dma_cap.atime_stamp) ? "Y" : "N");
3093 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
3094 (priv->dma_cap.eee) ? "Y" : "N");
3095 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3096 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3097 (priv->dma_cap.tx_coe) ? "Y" : "N");
3098 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3099 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3100 (priv->dma_cap.rx_coe) ? "Y" : "N");
3102 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3103 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3104 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3105 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3107 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3108 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3109 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3110 priv->dma_cap.number_rx_channel);
3111 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3112 priv->dma_cap.number_tx_channel);
3113 seq_printf(seq, "\tEnhanced descriptors: %s\n",
3114 (priv->dma_cap.enh_desc) ? "Y" : "N");
3119 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
3121 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
3124 static const struct file_operations stmmac_dma_cap_fops = {
3125 .owner = THIS_MODULE,
3126 .open = stmmac_sysfs_dma_cap_open,
3128 .llseek = seq_lseek,
3129 .release = single_release,
3132 static int stmmac_init_fs(struct net_device *dev)
3134 struct stmmac_priv *priv = netdev_priv(dev);
3136 /* Create per netdev entries */
3137 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3139 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3140 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3141 STMMAC_RESOURCE_NAME, dev->name);
3146 /* Entry to report DMA RX/TX rings */
3147 priv->dbgfs_rings_status =
3148 debugfs_create_file("descriptors_status", S_IRUGO,
3149 priv->dbgfs_dir, dev,
3150 &stmmac_rings_status_fops);
3152 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3153 pr_info("ERROR creating stmmac ring debugfs file\n");
3154 debugfs_remove_recursive(priv->dbgfs_dir);
3159 /* Entry to report the DMA HW features */
3160 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
3162 dev, &stmmac_dma_cap_fops);
3164 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3165 pr_info("ERROR creating stmmac MMC debugfs file\n");
3166 debugfs_remove_recursive(priv->dbgfs_dir);
3174 static void stmmac_exit_fs(struct net_device *dev)
3176 struct stmmac_priv *priv = netdev_priv(dev);
3178 debugfs_remove_recursive(priv->dbgfs_dir);
3180 #endif /* CONFIG_DEBUG_FS */
3182 static const struct net_device_ops stmmac_netdev_ops = {
3183 .ndo_open = stmmac_open,
3184 .ndo_start_xmit = stmmac_xmit,
3185 .ndo_stop = stmmac_release,
3186 .ndo_change_mtu = stmmac_change_mtu,
3187 .ndo_fix_features = stmmac_fix_features,
3188 .ndo_set_features = stmmac_set_features,
3189 .ndo_set_rx_mode = stmmac_set_rx_mode,
3190 .ndo_tx_timeout = stmmac_tx_timeout,
3191 .ndo_do_ioctl = stmmac_ioctl,
3192 #ifdef CONFIG_NET_POLL_CONTROLLER
3193 .ndo_poll_controller = stmmac_poll_controller,
3195 .ndo_set_mac_address = stmmac_set_mac_address,
3199 * stmmac_hw_init - Init the MAC device
3200 * @priv: driver private structure
3201 * Description: this function is to configure the MAC device according to
3202 * some platform parameters or the HW capability register. It prepares the
3203 * driver to use either ring or chain modes and to setup either enhanced or
3204 * normal descriptors.
3206 static int stmmac_hw_init(struct stmmac_priv *priv)
3208 struct mac_device_info *mac;
3210 /* Identify the MAC HW device */
3211 if (priv->plat->has_gmac) {
3212 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3213 mac = dwmac1000_setup(priv->ioaddr,
3214 priv->plat->multicast_filter_bins,
3215 priv->plat->unicast_filter_entries,
3216 &priv->synopsys_id);
3217 } else if (priv->plat->has_gmac4) {
3218 priv->dev->priv_flags |= IFF_UNICAST_FLT;
3219 mac = dwmac4_setup(priv->ioaddr,
3220 priv->plat->multicast_filter_bins,
3221 priv->plat->unicast_filter_entries,
3222 &priv->synopsys_id);
3224 mac = dwmac100_setup(priv->ioaddr, &priv->synopsys_id);
3231 /* To use the chained or ring mode */
3232 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3233 priv->hw->mode = &dwmac4_ring_mode_ops;
3236 priv->hw->mode = &chain_mode_ops;
3237 pr_info(" Chain mode enabled\n");
3238 priv->mode = STMMAC_CHAIN_MODE;
3240 priv->hw->mode = &ring_mode_ops;
3241 pr_info(" Ring mode enabled\n");
3242 priv->mode = STMMAC_RING_MODE;
3246 /* Get the HW capability (new GMAC newer than 3.50a) */
3247 priv->hw_cap_support = stmmac_get_hw_features(priv);
3248 if (priv->hw_cap_support) {
3249 pr_info(" DMA HW capability register supported");
3251 /* We can override some gmac/dma configuration fields: e.g.
3252 * enh_desc, tx_coe (e.g. that are passed through the
3253 * platform) with the values from the HW capability
3254 * register (if supported).
3256 priv->plat->enh_desc = priv->dma_cap.enh_desc;
3257 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
3258 priv->hw->pmt = priv->plat->pmt;
3260 /* TXCOE doesn't work in thresh DMA mode */
3261 if (priv->plat->force_thresh_dma_mode)
3262 priv->plat->tx_coe = 0;
3264 priv->plat->tx_coe = priv->dma_cap.tx_coe;
3266 /* In case of GMAC4 rx_coe is from HW cap register. */
3267 priv->plat->rx_coe = priv->dma_cap.rx_coe;
3269 if (priv->dma_cap.rx_coe_type2)
3270 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
3271 else if (priv->dma_cap.rx_coe_type1)
3272 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
3275 pr_info(" No HW DMA feature register supported");
3277 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3278 if (priv->synopsys_id >= DWMAC_CORE_4_00)
3279 priv->hw->desc = &dwmac4_desc_ops;
3281 stmmac_selec_desc_mode(priv);
3283 if (priv->plat->rx_coe) {
3284 priv->hw->rx_csum = priv->plat->rx_coe;
3285 pr_info(" RX Checksum Offload Engine supported\n");
3286 if (priv->synopsys_id < DWMAC_CORE_4_00)
3287 pr_info("\tCOE Type %d\n", priv->hw->rx_csum);
3289 if (priv->plat->tx_coe)
3290 pr_info(" TX Checksum insertion supported\n");
3292 if (priv->plat->pmt) {
3293 pr_info(" Wake-Up On Lan supported\n");
3294 device_set_wakeup_capable(priv->device, 1);
3297 if (priv->dma_cap.tsoen)
3298 pr_info(" TSO supported\n");
3304 struct stmmac_priv *priv_monitor;
3305 static void moniter_tx_handler(struct work_struct *work)
3309 pr_info("reset eth\n");
3310 stmmac_release(priv_monitor->dev);
3311 stmmac_open(priv_monitor->dev);
3315 pr_info("device not init yet!\n");
3317 // queue_delayed_work(moniter_tx_wq, &moniter_tx_worker, HZ);
3322 * @device: device pointer
3323 * @plat_dat: platform data pointer
3324 * @res: stmmac resource pointer
3325 * Description: this is the main probe function used to
3326 * call the alloc_etherdev, allocate the priv structure.
3328 * returns 0 on success, otherwise errno.
3330 int stmmac_dvr_probe(struct device *device,
3331 struct plat_stmmacenet_data *plat_dat,
3332 struct stmmac_resources *res)
3335 struct net_device *ndev = NULL;
3336 struct stmmac_priv *priv;
3340 moniter_tx_wq = create_singlethread_workqueue("eth_moniter_tx_wq");
3341 INIT_DELAYED_WORK(&moniter_tx_worker, moniter_tx_handler);
3342 /*register pm notify callback*/
3343 result = register_pm_notifier(&suspend_pm_nb);
3345 unregister_pm_notifier(&suspend_pm_nb);
3346 pr_info("register suspend notifier failed return %d\n", result);
3349 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
3353 SET_NETDEV_DEV(ndev, device);
3355 priv = netdev_priv(ndev);
3356 priv->device = device;
3359 stmmac_set_ethtool_ops(ndev);
3360 priv->pause = pause;
3361 priv->plat = plat_dat;
3362 priv->ioaddr = res->addr;
3363 priv->dev->base_addr = (unsigned long)res->addr;
3365 priv->dev->irq = res->irq;
3366 priv->wol_irq = res->wol_irq;
3367 priv->lpi_irq = res->lpi_irq;
3370 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
3372 dev_set_drvdata(device, priv->dev);
3374 /* Verify driver arguments */
3375 stmmac_verify_args();
3377 /* Override with kernel parameters if supplied XXX CRS XXX
3378 * this needs to have multiple instances
3380 if ((phyaddr >= 0) && (phyaddr <= 31))
3381 priv->plat->phy_addr = phyaddr;
3383 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
3384 if (IS_ERR(priv->stmmac_clk)) {
3385 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
3387 /* If failed to obtain stmmac_clk and specific clk_csr value
3388 * is NOT passed from the platform, probe fail.
3390 if (!priv->plat->clk_csr) {
3391 ret = PTR_ERR(priv->stmmac_clk);
3394 priv->stmmac_clk = NULL;
3397 clk_prepare_enable(priv->stmmac_clk);
3399 priv->pclk = devm_clk_get(priv->device, "pclk");
3400 if (IS_ERR(priv->pclk)) {
3401 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
3402 ret = -EPROBE_DEFER;
3403 goto error_pclk_get;
3407 clk_prepare_enable(priv->pclk);
3409 priv->stmmac_rst = devm_reset_control_get(priv->device,
3410 STMMAC_RESOURCE_NAME);
3411 if (IS_ERR(priv->stmmac_rst)) {
3412 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
3413 ret = -EPROBE_DEFER;
3416 dev_info(priv->device, "no reset control found\n");
3417 priv->stmmac_rst = NULL;
3419 if (priv->stmmac_rst)
3420 reset_control_deassert(priv->stmmac_rst);
3422 /* Init MAC and get the capabilities */
3423 ret = stmmac_hw_init(priv);
3427 stmmac_check_ether_addr(priv);
3429 ndev->netdev_ops = &stmmac_netdev_ops;
3431 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3434 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3435 ndev->hw_features |= NETIF_F_TSO;
3437 pr_info(" TSO feature enabled\n");
3439 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
3440 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
3441 #ifdef STMMAC_VLAN_TAG_USED
3442 /* Both mac100 and gmac support receive VLAN tag detection */
3443 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3445 priv->msg_enable = netif_msg_init(debug, default_msg_level);
3448 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
3450 /* Rx Watchdog is available in the COREs newer than the 3.40.
3451 * In some case, for example on bugged HW this feature
3452 * has to be disable and this can be done by passing the
3453 * riwt_off field from the platform.
3455 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
3457 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3460 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
3462 spin_lock_init(&priv->lock);
3463 spin_lock_init(&priv->tx_lock);
3465 /* If a specific clk_csr value is passed from the platform
3466 * this means that the CSR Clock Range selection cannot be
3467 * changed at run-time and it is fixed. Viceversa the driver'll try to
3468 * set the MDC clock dynamically according to the csr actual
3471 if (!priv->plat->clk_csr)
3472 stmmac_clk_csr_set(priv);
3474 priv->clk_csr = priv->plat->clk_csr;
3476 stmmac_check_pcs_mode(priv);
3478 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3479 priv->hw->pcs != STMMAC_PCS_TBI &&
3480 priv->hw->pcs != STMMAC_PCS_RTBI) {
3481 /* MDIO bus Registration */
3482 ret = stmmac_mdio_register(ndev);
3484 pr_debug("%s: MDIO bus (id: %d) registration failed",
3485 __func__, priv->plat->bus_id);
3486 goto error_napi_register;
3490 ret = register_netdev(ndev);
3492 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
3493 goto error_netdev_register;
3496 #ifdef CONFIG_DWMAC_MESON
3497 ret = gmac_create_sysfs(
3498 mdiobus_get_phy(priv->mii, priv->plat->phy_addr), priv->ioaddr);
3501 priv_monitor = priv;
3505 error_netdev_register:
3506 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3507 priv->hw->pcs != STMMAC_PCS_TBI &&
3508 priv->hw->pcs != STMMAC_PCS_RTBI)
3509 stmmac_mdio_unregister(ndev);
3510 error_napi_register:
3511 netif_napi_del(&priv->napi);
3513 clk_disable_unprepare(priv->pclk);
3515 clk_disable_unprepare(priv->stmmac_clk);
3521 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
3525 * @dev: device pointer
3526 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3527 * changes the link status, releases the DMA descriptor rings.
3529 int stmmac_dvr_remove(struct device *dev)
3531 struct net_device *ndev = dev_get_drvdata(dev);
3532 struct stmmac_priv *priv = netdev_priv(ndev);
3534 pr_info("%s:\n\tremoving driver", __func__);
3536 priv->hw->dma->stop_rx(priv->ioaddr);
3537 priv->hw->dma->stop_tx(priv->ioaddr);
3539 #ifdef CONFIG_DWMAC_MESON
3540 gmac_remove_sysfs(priv->phydev);
3543 stmmac_set_mac(priv->ioaddr, false);
3544 netif_carrier_off(ndev);
3545 unregister_netdev(ndev);
3546 if (priv->stmmac_rst)
3547 reset_control_assert(priv->stmmac_rst);
3548 clk_disable_unprepare(priv->pclk);
3549 clk_disable_unprepare(priv->stmmac_clk);
3550 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
3551 priv->hw->pcs != STMMAC_PCS_TBI &&
3552 priv->hw->pcs != STMMAC_PCS_RTBI)
3553 stmmac_mdio_unregister(ndev);
3558 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
3561 * stmmac_suspend - suspend callback
3562 * @dev: device pointer
3563 * Description: this is the function to suspend the device and it is called
3564 * by the platform driver to stop the network queue, release the resources,
3565 * program the PMT register (for WoL), clean and release driver resources.
3567 int stmmac_suspend(struct device *dev)
3569 struct net_device *ndev = dev_get_drvdata(dev);
3570 struct stmmac_priv *priv = netdev_priv(ndev);
3571 unsigned long flags;
3573 if (!ndev || !netif_running(ndev))
3577 phy_stop(priv->phydev);
3579 spin_lock_irqsave(&priv->lock, flags);
3581 netif_device_detach(ndev);
3582 netif_stop_queue(ndev);
3585 *napi_disable call might_sleep,if not irq restore
3586 *It will warning bug
3588 spin_unlock_irqrestore(&priv->lock, flags);
3589 napi_disable(&priv->napi);
3590 spin_lock_irqsave(&priv->lock, flags);
3592 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
3593 del_timer_sync(&priv->txtimer);
3595 /* Stop TX/RX DMA */
3596 priv->hw->dma->stop_tx(priv->ioaddr);
3597 priv->hw->dma->stop_rx(priv->ioaddr);
3599 /* Enable Power down mode by programming the PMT regs */
3600 if (device_may_wakeup(priv->device)) {
3601 //priv->hw->mac->pmt(priv->hw, priv->wolopts);
3602 priv->hw->mac->pmt(priv->hw, 0x1 << 5);
3605 stmmac_set_mac(priv->ioaddr, false);
3606 pinctrl_pm_select_sleep_state(priv->device);
3607 /* Disable clock in case of PWM is off */
3608 clk_disable(priv->pclk);
3609 clk_disable(priv->stmmac_clk);
3611 spin_unlock_irqrestore(&priv->lock, flags);
3615 priv->oldduplex = -1;
3618 EXPORT_SYMBOL_GPL(stmmac_suspend);
3621 * stmmac_resume - resume callback
3622 * @dev: device pointer
3623 * Description: when resume this function is invoked to setup the DMA and CORE
3624 * in a usable state.
3626 int stmmac_resume(struct device *dev)
3628 struct net_device *ndev = dev_get_drvdata(dev);
3629 struct stmmac_priv *priv = netdev_priv(ndev);
3630 unsigned long flags;
3632 if (!netif_running(ndev))
3635 /* Power Down bit, into the PM register, is cleared
3636 * automatically as soon as a magic packet or a Wake-up frame
3637 * is received. Anyway, it's better to manually clear
3638 * this bit because it can generate problems while resuming
3639 * from another devices (e.g. serial console).
3641 if (device_may_wakeup(priv->device)) {
3642 spin_lock_irqsave(&priv->lock, flags);
3643 priv->hw->mac->pmt(priv->hw, 0);
3644 spin_unlock_irqrestore(&priv->lock, flags);
3647 pinctrl_pm_select_default_state(priv->device);
3648 /* enable the clk prevously disabled */
3649 clk_enable(priv->stmmac_clk);
3650 clk_enable(priv->pclk);
3651 /* reset the phy so that it's ready */
3653 stmmac_mdio_reset(priv->mii);
3656 #ifndef CONFIG_AMLOGIC_ETH_PRIVE
3657 netif_device_attach(ndev);
3659 spin_lock_irqsave(&priv->lock, flags);
3665 /* reset private mss value to force mss context settings at
3666 * next tso xmit (only used for gmac4).
3670 stmmac_clear_descriptors(priv);
3672 spin_unlock_irqrestore(&priv->lock, flags);
3673 stmmac_hw_setup(ndev, false);
3674 spin_lock_irqsave(&priv->lock, flags);
3676 stmmac_init_tx_coalesce(priv);
3677 stmmac_set_rx_mode(ndev);
3678 #ifdef CONFIG_AMLOGIC_ETH_PRIVE
3679 netif_device_attach(ndev);
3681 napi_enable(&priv->napi);
3683 netif_start_queue(ndev);
3685 spin_unlock_irqrestore(&priv->lock, flags);
3688 phy_start(priv->phydev);
3692 EXPORT_SYMBOL_GPL(stmmac_resume);
3695 static int __init stmmac_cmdline_opt(char *str)
3701 while ((opt = strsep(&str, ",")) != NULL) {
3702 if (!strncmp(opt, "debug:", 6)) {
3703 if (kstrtoint(opt + 6, 0, &debug))
3705 } else if (!strncmp(opt, "phyaddr:", 8)) {
3706 if (kstrtoint(opt + 8, 0, &phyaddr))
3708 } else if (!strncmp(opt, "buf_sz:", 7)) {
3709 if (kstrtoint(opt + 7, 0, &buf_sz))
3711 } else if (!strncmp(opt, "tc:", 3)) {
3712 if (kstrtoint(opt + 3, 0, &tc))
3714 } else if (!strncmp(opt, "watchdog:", 9)) {
3715 if (kstrtoint(opt + 9, 0, &watchdog))
3717 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3718 if (kstrtoint(opt + 10, 0, &flow_ctrl))
3720 } else if (!strncmp(opt, "pause:", 6)) {
3721 if (kstrtoint(opt + 6, 0, &pause))
3723 } else if (!strncmp(opt, "eee_timer:", 10)) {
3724 if (kstrtoint(opt + 10, 0, &eee_timer))
3726 } else if (!strncmp(opt, "chain_mode:", 11)) {
3727 if (kstrtoint(opt + 11, 0, &chain_mode))
3734 pr_err("%s: ERROR broken module parameter conversion", __func__);
3738 __setup("stmmaceth=", stmmac_cmdline_opt);
3741 static int __init stmmac_init(void)
3743 #ifdef CONFIG_DEBUG_FS
3744 /* Create debugfs main directory if it doesn't exist yet */
3745 if (!stmmac_fs_dir) {
3746 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
3748 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
3749 pr_err("ERROR %s, debugfs create directory failed\n",
3750 STMMAC_RESOURCE_NAME);
3760 static void __exit stmmac_exit(void)
3762 #ifdef CONFIG_DEBUG_FS
3763 debugfs_remove_recursive(stmmac_fs_dir);
3767 module_init(stmmac_init)
3768 module_exit(stmmac_exit)
3770 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3771 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3772 MODULE_LICENSE("GPL");