1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 Copyright (C) 2013 Vayavya Labs Pvt Ltd
5 This implements all the API for managing HW timestamp & PTP.
8 Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
10 *******************************************************************************/
13 #include <linux/iopoll.h>
14 #include <linux/delay.h>
15 #include <linux/ptp_clock_kernel.h>
17 #include "stmmac_ptp.h"
21 static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
23 writel(data, ioaddr + PTP_TCR);
26 static void config_sub_second_increment(void __iomem *ioaddr,
27 u32 ptp_clock, int gmac4, u32 *ssinc)
29 u32 value = readl(ioaddr + PTP_TCR);
33 /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
34 * increment to twice the number of nanoseconds of a clock cycle.
35 * The calculation of the default_addend value by the caller will set it
36 * to mid-range = 2^31 when the remainder of this division is zero,
37 * which will make the accumulator overflow once every 2 ptp_clock
38 * cycles, adding twice the number of nanoseconds of a clock cycle :
39 * 2000000000ULL / ptp_clock.
41 if (value & PTP_TCR_TSCFUPDT)
42 data = (2000000000ULL / ptp_clock);
44 data = (1000000000ULL / ptp_clock);
46 /* 0.465ns accuracy */
47 if (!(value & PTP_TCR_TSCTRLSSR))
48 data = (data * 1000) / 465;
50 if (data > PTP_SSIR_SSINC_MAX)
51 data = PTP_SSIR_SSINC_MAX;
55 reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
57 writel(reg_value, ioaddr + PTP_SSIR);
63 static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
67 writel(sec, ioaddr + PTP_STSUR);
68 writel(nsec, ioaddr + PTP_STNSUR);
69 /* issue command to initialize the system time value */
70 value = readl(ioaddr + PTP_TCR);
71 value |= PTP_TCR_TSINIT;
72 writel(value, ioaddr + PTP_TCR);
74 /* wait for present system time initialize to complete */
75 return readl_poll_timeout_atomic(ioaddr + PTP_TCR, value,
76 !(value & PTP_TCR_TSINIT),
80 static int config_addend(void __iomem *ioaddr, u32 addend)
85 writel(addend, ioaddr + PTP_TAR);
86 /* issue command to update the addend value */
87 value = readl(ioaddr + PTP_TCR);
88 value |= PTP_TCR_TSADDREG;
89 writel(value, ioaddr + PTP_TCR);
91 /* wait for present addend update to complete */
94 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
104 static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
105 int add_sub, int gmac4)
111 /* If the new sec value needs to be subtracted with
112 * the system time, then MAC_STSUR reg should be
113 * programmed with (2^32 – <new_sec_value>)
118 value = readl(ioaddr + PTP_TCR);
119 if (value & PTP_TCR_TSCTRLSSR)
120 nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
122 nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
125 writel(sec, ioaddr + PTP_STSUR);
126 value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
127 writel(value, ioaddr + PTP_STNSUR);
129 /* issue command to initialize the system time value */
130 value = readl(ioaddr + PTP_TCR);
131 value |= PTP_TCR_TSUPDT;
132 writel(value, ioaddr + PTP_TCR);
134 /* wait for present system time adjust/update to complete */
137 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
147 static void get_systime(void __iomem *ioaddr, u64 *systime)
151 /* Get the TSS value */
152 sec1 = readl_relaxed(ioaddr + PTP_STSR);
155 /* Get the TSSS value */
156 ns = readl_relaxed(ioaddr + PTP_STNSR);
157 /* Get the TSS value */
158 sec1 = readl_relaxed(ioaddr + PTP_STSR);
159 } while (sec0 != sec1);
162 *systime = ns + (sec1 * 1000000000ULL);
165 static void get_ptptime(void __iomem *ptpaddr, u64 *ptp_time)
169 ns = readl(ptpaddr + PTP_ATNR);
170 ns += readl(ptpaddr + PTP_ATSR) * NSEC_PER_SEC;
175 static void timestamp_interrupt(struct stmmac_priv *priv)
177 u32 num_snapshot, ts_status, tsync_int;
178 struct ptp_clock_event event;
183 if (priv->plat->int_snapshot_en) {
184 wake_up(&priv->tstamp_busy_wait);
188 tsync_int = readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE;
193 /* Read timestamp status to clear interrupt from either external
194 * timestamp or start/end of PPS.
196 ts_status = readl(priv->ioaddr + GMAC_TIMESTAMP_STATUS);
198 if (!priv->plat->ext_snapshot_en)
201 num_snapshot = (ts_status & GMAC_TIMESTAMP_ATSNS_MASK) >>
202 GMAC_TIMESTAMP_ATSNS_SHIFT;
204 for (i = 0; i < num_snapshot; i++) {
205 read_lock_irqsave(&priv->ptp_lock, flags);
206 get_ptptime(priv->ptpaddr, &ptp_time);
207 read_unlock_irqrestore(&priv->ptp_lock, flags);
208 event.type = PTP_CLOCK_EXTTS;
210 event.timestamp = ptp_time;
211 ptp_clock_event(priv->ptp_clock, &event);
215 const struct stmmac_hwtimestamp stmmac_ptp = {
216 .config_hw_tstamping = config_hw_tstamping,
217 .init_systime = init_systime,
218 .config_sub_second_increment = config_sub_second_increment,
219 .config_addend = config_addend,
220 .adjust_systime = adjust_systime,
221 .get_systime = get_systime,
222 .get_ptptime = get_ptptime,
223 .timestamp_interrupt = timestamp_interrupt,