1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
7 #include <linux/stmmac.h>
11 static int dwxgmac2_get_tx_status(struct stmmac_extra_stats *x,
12 struct dma_desc *p, void __iomem *ioaddr)
14 unsigned int tdes3 = le32_to_cpu(p->des3);
17 if (unlikely(tdes3 & XGMAC_TDES3_OWN))
19 if (likely(!(tdes3 & XGMAC_TDES3_LD)))
25 static int dwxgmac2_get_rx_status(struct stmmac_extra_stats *x,
28 unsigned int rdes3 = le32_to_cpu(p->des3);
30 if (unlikely(rdes3 & XGMAC_RDES3_OWN))
32 if (unlikely(rdes3 & XGMAC_RDES3_CTXT))
34 if (likely(!(rdes3 & XGMAC_RDES3_LD)))
36 if (unlikely((rdes3 & XGMAC_RDES3_ES) && (rdes3 & XGMAC_RDES3_LD)))
42 static int dwxgmac2_get_tx_len(struct dma_desc *p)
44 return (le32_to_cpu(p->des2) & XGMAC_TDES2_B1L);
47 static int dwxgmac2_get_tx_owner(struct dma_desc *p)
49 return (le32_to_cpu(p->des3) & XGMAC_TDES3_OWN) > 0;
52 static void dwxgmac2_set_tx_owner(struct dma_desc *p)
54 p->des3 |= cpu_to_le32(XGMAC_TDES3_OWN);
57 static void dwxgmac2_set_rx_owner(struct dma_desc *p, int disable_rx_ic)
59 p->des3 |= cpu_to_le32(XGMAC_RDES3_OWN);
62 p->des3 |= cpu_to_le32(XGMAC_RDES3_IOC);
65 static int dwxgmac2_get_tx_ls(struct dma_desc *p)
67 return (le32_to_cpu(p->des3) & XGMAC_RDES3_LD) > 0;
70 static int dwxgmac2_get_rx_frame_len(struct dma_desc *p, int rx_coe)
72 return (le32_to_cpu(p->des3) & XGMAC_RDES3_PL);
75 static void dwxgmac2_enable_tx_timestamp(struct dma_desc *p)
77 p->des2 |= cpu_to_le32(XGMAC_TDES2_TTSE);
80 static int dwxgmac2_get_tx_timestamp_status(struct dma_desc *p)
82 return 0; /* Not supported */
85 static inline void dwxgmac2_get_timestamp(void *desc, u32 ats, u64 *ts)
87 struct dma_desc *p = (struct dma_desc *)desc;
90 ns += le32_to_cpu(p->des1) * 1000000000ULL;
91 ns += le32_to_cpu(p->des0);
96 static int dwxgmac2_rx_check_timestamp(void *desc)
98 struct dma_desc *p = (struct dma_desc *)desc;
99 unsigned int rdes3 = le32_to_cpu(p->des3);
100 bool desc_valid, ts_valid;
104 desc_valid = !(rdes3 & XGMAC_RDES3_OWN) && (rdes3 & XGMAC_RDES3_CTXT);
105 ts_valid = !(rdes3 & XGMAC_RDES3_TSD) && (rdes3 & XGMAC_RDES3_TSA);
107 if (likely(desc_valid && ts_valid)) {
108 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
116 static int dwxgmac2_get_rx_timestamp_status(void *desc, void *next_desc,
119 struct dma_desc *p = (struct dma_desc *)desc;
120 unsigned int rdes3 = le32_to_cpu(p->des3);
123 if (likely(rdes3 & XGMAC_RDES3_CDA))
124 ret = dwxgmac2_rx_check_timestamp(next_desc);
129 static void dwxgmac2_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
130 int mode, int end, int bfsize)
132 dwxgmac2_set_rx_owner(p, disable_rx_ic);
135 static void dwxgmac2_init_tx_desc(struct dma_desc *p, int mode, int end)
143 static void dwxgmac2_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
144 bool csum_flag, int mode, bool tx_own,
145 bool ls, unsigned int tot_pkt_len)
147 unsigned int tdes3 = le32_to_cpu(p->des3);
149 p->des2 |= cpu_to_le32(len & XGMAC_TDES2_B1L);
151 tdes3 |= tot_pkt_len & XGMAC_TDES3_FL;
153 tdes3 |= XGMAC_TDES3_FD;
155 tdes3 &= ~XGMAC_TDES3_FD;
158 tdes3 |= 0x3 << XGMAC_TDES3_CIC_SHIFT;
160 tdes3 &= ~XGMAC_TDES3_CIC;
163 tdes3 |= XGMAC_TDES3_LD;
165 tdes3 &= ~XGMAC_TDES3_LD;
167 /* Finally set the OWN bit. Later the DMA will start! */
169 tdes3 |= XGMAC_TDES3_OWN;
172 /* When the own bit, for the first frame, has to be set, all
173 * descriptors for the same frame has to be set before, to
174 * avoid race condition.
178 p->des3 = cpu_to_le32(tdes3);
181 static void dwxgmac2_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
182 int len1, int len2, bool tx_own,
183 bool ls, unsigned int tcphdrlen,
184 unsigned int tcppayloadlen)
186 unsigned int tdes3 = le32_to_cpu(p->des3);
189 p->des2 |= cpu_to_le32(len1 & XGMAC_TDES2_B1L);
191 p->des2 |= cpu_to_le32((len2 << XGMAC_TDES2_B2L_SHIFT) &
194 tdes3 |= XGMAC_TDES3_FD | XGMAC_TDES3_TSE;
195 tdes3 |= (tcphdrlen << XGMAC_TDES3_THL_SHIFT) &
197 tdes3 |= tcppayloadlen & XGMAC_TDES3_TPL;
199 tdes3 &= ~XGMAC_TDES3_FD;
203 tdes3 |= XGMAC_TDES3_LD;
205 tdes3 &= ~XGMAC_TDES3_LD;
207 /* Finally set the OWN bit. Later the DMA will start! */
209 tdes3 |= XGMAC_TDES3_OWN;
212 /* When the own bit, for the first frame, has to be set, all
213 * descriptors for the same frame has to be set before, to
214 * avoid race condition.
218 p->des3 = cpu_to_le32(tdes3);
221 static void dwxgmac2_release_tx_desc(struct dma_desc *p, int mode)
229 static void dwxgmac2_set_tx_ic(struct dma_desc *p)
231 p->des2 |= cpu_to_le32(XGMAC_TDES2_IOC);
234 static void dwxgmac2_set_mss(struct dma_desc *p, unsigned int mss)
238 p->des2 = cpu_to_le32(mss);
239 p->des3 = cpu_to_le32(XGMAC_TDES3_CTXT | XGMAC_TDES3_TCMSSV);
242 static void dwxgmac2_set_addr(struct dma_desc *p, dma_addr_t addr)
244 p->des0 = cpu_to_le32(lower_32_bits(addr));
245 p->des1 = cpu_to_le32(upper_32_bits(addr));
248 static void dwxgmac2_clear(struct dma_desc *p)
256 static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash,
257 enum pkt_hash_types *type)
259 unsigned int rdes3 = le32_to_cpu(p->des3);
262 if (rdes3 & XGMAC_RDES3_RSV) {
263 ptype = (rdes3 & XGMAC_RDES3_L34T) >> XGMAC_RDES3_L34T_SHIFT;
266 case XGMAC_L34T_IP4TCP:
267 case XGMAC_L34T_IP4UDP:
268 case XGMAC_L34T_IP6TCP:
269 case XGMAC_L34T_IP6UDP:
270 *type = PKT_HASH_TYPE_L4;
273 *type = PKT_HASH_TYPE_L3;
277 *hash = le32_to_cpu(p->des1);
284 static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len)
286 if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T)
287 *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL;
290 static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
292 p->des2 = cpu_to_le32(lower_32_bits(addr));
293 p->des3 = cpu_to_le32(upper_32_bits(addr));
296 static void dwxgmac2_set_sarc(struct dma_desc *p, u32 sarc_type)
298 sarc_type <<= XGMAC_TDES3_SAIC_SHIFT;
300 p->des3 |= cpu_to_le32(sarc_type & XGMAC_TDES3_SAIC);
303 static void dwxgmac2_set_vlan_tag(struct dma_desc *p, u16 tag, u16 inner_tag,
313 u32 des = inner_tag << XGMAC_TDES2_IVT_SHIFT;
315 des &= XGMAC_TDES2_IVT;
316 p->des2 = cpu_to_le32(des);
318 des = inner_type << XGMAC_TDES3_IVTIR_SHIFT;
319 des &= XGMAC_TDES3_IVTIR;
320 p->des3 = cpu_to_le32(des | XGMAC_TDES3_IVLTV);
324 p->des3 |= cpu_to_le32(tag & XGMAC_TDES3_VT);
325 p->des3 |= cpu_to_le32(XGMAC_TDES3_VLTV);
327 p->des3 |= cpu_to_le32(XGMAC_TDES3_CTXT);
330 static void dwxgmac2_set_vlan(struct dma_desc *p, u32 type)
332 type <<= XGMAC_TDES2_VTIR_SHIFT;
333 p->des2 |= cpu_to_le32(type & XGMAC_TDES2_VTIR);
336 static void dwxgmac2_set_tbs(struct dma_edesc *p, u32 sec, u32 nsec)
338 p->des4 = cpu_to_le32((sec & XGMAC_TDES0_LT) | XGMAC_TDES0_LTV);
339 p->des5 = cpu_to_le32(nsec & XGMAC_TDES1_LT);
344 const struct stmmac_desc_ops dwxgmac210_desc_ops = {
345 .tx_status = dwxgmac2_get_tx_status,
346 .rx_status = dwxgmac2_get_rx_status,
347 .get_tx_len = dwxgmac2_get_tx_len,
348 .get_tx_owner = dwxgmac2_get_tx_owner,
349 .set_tx_owner = dwxgmac2_set_tx_owner,
350 .set_rx_owner = dwxgmac2_set_rx_owner,
351 .get_tx_ls = dwxgmac2_get_tx_ls,
352 .get_rx_frame_len = dwxgmac2_get_rx_frame_len,
353 .enable_tx_timestamp = dwxgmac2_enable_tx_timestamp,
354 .get_tx_timestamp_status = dwxgmac2_get_tx_timestamp_status,
355 .get_rx_timestamp_status = dwxgmac2_get_rx_timestamp_status,
356 .get_timestamp = dwxgmac2_get_timestamp,
357 .set_tx_ic = dwxgmac2_set_tx_ic,
358 .prepare_tx_desc = dwxgmac2_prepare_tx_desc,
359 .prepare_tso_tx_desc = dwxgmac2_prepare_tso_tx_desc,
360 .release_tx_desc = dwxgmac2_release_tx_desc,
361 .init_rx_desc = dwxgmac2_init_rx_desc,
362 .init_tx_desc = dwxgmac2_init_tx_desc,
363 .set_mss = dwxgmac2_set_mss,
364 .set_addr = dwxgmac2_set_addr,
365 .clear = dwxgmac2_clear,
366 .get_rx_hash = dwxgmac2_get_rx_hash,
367 .get_rx_header_len = dwxgmac2_get_rx_header_len,
368 .set_sec_addr = dwxgmac2_set_sec_addr,
369 .set_sarc = dwxgmac2_set_sarc,
370 .set_vlan_tag = dwxgmac2_set_vlan_tag,
371 .set_vlan = dwxgmac2_set_vlan,
372 .set_tbs = dwxgmac2_set_tbs,