1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC support.
7 #include <linux/bitrev.h>
8 #include <linux/crc32.h>
9 #include <linux/iopoll.h>
11 #include "stmmac_ptp.h"
12 #include "dwxlgmac2.h"
15 static void dwxgmac2_core_init(struct mac_device_info *hw,
16 struct net_device *dev)
18 void __iomem *ioaddr = hw->pcsr;
21 tx = readl(ioaddr + XGMAC_TX_CONFIG);
22 rx = readl(ioaddr + XGMAC_RX_CONFIG);
24 tx |= XGMAC_CORE_INIT_TX;
25 rx |= XGMAC_CORE_INIT_RX;
28 tx |= XGMAC_CONFIG_TE;
29 tx &= ~hw->link.speed_mask;
33 tx |= hw->link.xgmii.speed10000;
36 tx |= hw->link.speed2500;
40 tx |= hw->link.speed1000;
45 writel(tx, ioaddr + XGMAC_TX_CONFIG);
46 writel(rx, ioaddr + XGMAC_RX_CONFIG);
47 writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
50 static void xgmac_phylink_get_caps(struct stmmac_priv *priv)
52 priv->phylink_config.mac_capabilities |= MAC_2500FD | MAC_5000FD |
53 MAC_10000FD | MAC_25000FD |
54 MAC_40000FD | MAC_50000FD |
58 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)
60 u32 tx = readl(ioaddr + XGMAC_TX_CONFIG);
61 u32 rx = readl(ioaddr + XGMAC_RX_CONFIG);
64 tx |= XGMAC_CONFIG_TE;
65 rx |= XGMAC_CONFIG_RE;
67 tx &= ~XGMAC_CONFIG_TE;
68 rx &= ~XGMAC_CONFIG_RE;
71 writel(tx, ioaddr + XGMAC_TX_CONFIG);
72 writel(rx, ioaddr + XGMAC_RX_CONFIG);
75 static int dwxgmac2_rx_ipc(struct mac_device_info *hw)
77 void __iomem *ioaddr = hw->pcsr;
80 value = readl(ioaddr + XGMAC_RX_CONFIG);
82 value |= XGMAC_CONFIG_IPC;
84 value &= ~XGMAC_CONFIG_IPC;
85 writel(value, ioaddr + XGMAC_RX_CONFIG);
87 return !!(readl(ioaddr + XGMAC_RX_CONFIG) & XGMAC_CONFIG_IPC);
90 static void dwxgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
93 void __iomem *ioaddr = hw->pcsr;
96 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue);
97 if (mode == MTL_QUEUE_AVB)
98 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
99 else if (mode == MTL_QUEUE_DCB)
100 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
101 writel(value, ioaddr + XGMAC_RXQ_CTRL0);
104 static void dwxgmac2_rx_queue_prio(struct mac_device_info *hw, u32 prio,
107 void __iomem *ioaddr = hw->pcsr;
110 reg = (queue < 4) ? XGMAC_RXQ_CTRL2 : XGMAC_RXQ_CTRL3;
114 value = readl(ioaddr + reg);
115 value &= ~XGMAC_PSRQ(queue);
116 value |= (prio << XGMAC_PSRQ_SHIFT(queue)) & XGMAC_PSRQ(queue);
118 writel(value, ioaddr + reg);
121 static void dwxgmac2_tx_queue_prio(struct mac_device_info *hw, u32 prio,
124 void __iomem *ioaddr = hw->pcsr;
127 reg = (queue < 4) ? XGMAC_TC_PRTY_MAP0 : XGMAC_TC_PRTY_MAP1;
131 value = readl(ioaddr + reg);
132 value &= ~XGMAC_PSTC(queue);
133 value |= (prio << XGMAC_PSTC_SHIFT(queue)) & XGMAC_PSTC(queue);
135 writel(value, ioaddr + reg);
138 static void dwxgmac2_rx_queue_routing(struct mac_device_info *hw,
139 u8 packet, u32 queue)
141 void __iomem *ioaddr = hw->pcsr;
144 static const struct stmmac_rx_routing dwxgmac2_route_possibilities[] = {
145 { XGMAC_AVCPQ, XGMAC_AVCPQ_SHIFT },
146 { XGMAC_PTPQ, XGMAC_PTPQ_SHIFT },
147 { XGMAC_DCBCPQ, XGMAC_DCBCPQ_SHIFT },
148 { XGMAC_UPQ, XGMAC_UPQ_SHIFT },
149 { XGMAC_MCBCQ, XGMAC_MCBCQ_SHIFT },
152 value = readl(ioaddr + XGMAC_RXQ_CTRL1);
154 /* routing configuration */
155 value &= ~dwxgmac2_route_possibilities[packet - 1].reg_mask;
156 value |= (queue << dwxgmac2_route_possibilities[packet - 1].reg_shift) &
157 dwxgmac2_route_possibilities[packet - 1].reg_mask;
159 /* some packets require extra ops */
160 if (packet == PACKET_AVCPQ)
161 value |= FIELD_PREP(XGMAC_TACPQE, 1);
162 else if (packet == PACKET_MCBCQ)
163 value |= FIELD_PREP(XGMAC_MCBCQEN, 1);
165 writel(value, ioaddr + XGMAC_RXQ_CTRL1);
168 static void dwxgmac2_prog_mtl_rx_algorithms(struct mac_device_info *hw,
171 void __iomem *ioaddr = hw->pcsr;
174 value = readl(ioaddr + XGMAC_MTL_OPMODE);
178 case MTL_RX_ALGORITHM_SP:
180 case MTL_RX_ALGORITHM_WSP:
187 writel(value, ioaddr + XGMAC_MTL_OPMODE);
190 static void dwxgmac2_prog_mtl_tx_algorithms(struct mac_device_info *hw,
193 void __iomem *ioaddr = hw->pcsr;
198 value = readl(ioaddr + XGMAC_MTL_OPMODE);
199 value &= ~XGMAC_ETSALG;
202 case MTL_TX_ALGORITHM_WRR:
205 case MTL_TX_ALGORITHM_WFQ:
208 case MTL_TX_ALGORITHM_DWRR:
216 writel(value, ioaddr + XGMAC_MTL_OPMODE);
218 /* Set ETS if desired */
219 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) {
220 value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
224 writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(i));
228 static void dwxgmac2_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
229 struct mac_device_info *hw,
230 u32 weight, u32 queue)
232 void __iomem *ioaddr = hw->pcsr;
234 writel(weight, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
237 static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
240 void __iomem *ioaddr = hw->pcsr;
243 reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
247 value = readl(ioaddr + reg);
248 value &= ~XGMAC_QxMDMACH(queue);
249 value |= (chan << XGMAC_QxMDMACH_SHIFT(queue)) & XGMAC_QxMDMACH(queue);
251 writel(value, ioaddr + reg);
254 static void dwxgmac2_config_cbs(struct stmmac_priv *priv,
255 struct mac_device_info *hw,
256 u32 send_slope, u32 idle_slope,
257 u32 high_credit, u32 low_credit, u32 queue)
259 void __iomem *ioaddr = hw->pcsr;
262 writel(send_slope, ioaddr + XGMAC_MTL_TCx_SENDSLOPE(queue));
263 writel(idle_slope, ioaddr + XGMAC_MTL_TCx_QUANTUM_WEIGHT(queue));
264 writel(high_credit, ioaddr + XGMAC_MTL_TCx_HICREDIT(queue));
265 writel(low_credit, ioaddr + XGMAC_MTL_TCx_LOCREDIT(queue));
267 value = readl(ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
269 value |= XGMAC_CC | XGMAC_CBS;
270 writel(value, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(queue));
273 static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)
275 void __iomem *ioaddr = hw->pcsr;
278 for (i = 0; i < XGMAC_MAC_REGSIZE; i++)
279 reg_space[i] = readl(ioaddr + i * 4);
282 static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
283 struct stmmac_extra_stats *x)
285 void __iomem *ioaddr = hw->pcsr;
289 en = readl(ioaddr + XGMAC_INT_EN);
290 stat = readl(ioaddr + XGMAC_INT_STATUS);
294 if (stat & XGMAC_PMTIS) {
295 x->irq_receive_pmt_irq_n++;
296 readl(ioaddr + XGMAC_PMT);
299 if (stat & XGMAC_LPIIS) {
300 u32 lpi = readl(ioaddr + XGMAC_LPI_CTRL);
302 if (lpi & XGMAC_TLPIEN) {
303 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
304 x->irq_tx_path_in_lpi_mode_n++;
306 if (lpi & XGMAC_TLPIEX) {
307 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
308 x->irq_tx_path_exit_lpi_mode_n++;
310 if (lpi & XGMAC_RLPIEN)
311 x->irq_rx_path_in_lpi_mode_n++;
312 if (lpi & XGMAC_RLPIEX)
313 x->irq_rx_path_exit_lpi_mode_n++;
319 static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv,
320 struct mac_device_info *hw, u32 chan)
322 void __iomem *ioaddr = hw->pcsr;
326 status = readl(ioaddr + XGMAC_MTL_INT_STATUS);
327 if (status & BIT(chan)) {
328 u32 chan_status = readl(ioaddr + XGMAC_MTL_QINT_STATUS(chan));
330 if (chan_status & XGMAC_RXOVFIS)
331 ret |= CORE_IRQ_MTL_RX_OVERFLOW;
333 writel(~0x0, ioaddr + XGMAC_MTL_QINT_STATUS(chan));
339 static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
340 unsigned int fc, unsigned int pause_time,
343 void __iomem *ioaddr = hw->pcsr;
347 writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);
349 for (i = 0; i < tx_cnt; i++) {
350 u32 value = XGMAC_TFE;
353 value |= pause_time << XGMAC_PT_SHIFT;
355 writel(value, ioaddr + XGMAC_Qx_TX_FLOW_CTRL(i));
360 static void dwxgmac2_pmt(struct mac_device_info *hw, unsigned long mode)
362 void __iomem *ioaddr = hw->pcsr;
365 if (mode & WAKE_MAGIC)
366 val |= XGMAC_PWRDWN | XGMAC_MGKPKTEN;
367 if (mode & WAKE_UCAST)
368 val |= XGMAC_PWRDWN | XGMAC_GLBLUCAST | XGMAC_RWKPKTEN;
370 u32 cfg = readl(ioaddr + XGMAC_RX_CONFIG);
371 cfg |= XGMAC_CONFIG_RE;
372 writel(cfg, ioaddr + XGMAC_RX_CONFIG);
375 writel(val, ioaddr + XGMAC_PMT);
378 static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
379 const unsigned char *addr,
382 void __iomem *ioaddr = hw->pcsr;
385 value = (addr[5] << 8) | addr[4];
386 writel(value | XGMAC_AE, ioaddr + XGMAC_ADDRx_HIGH(reg_n));
388 value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
389 writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
392 static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
393 unsigned char *addr, unsigned int reg_n)
395 void __iomem *ioaddr = hw->pcsr;
396 u32 hi_addr, lo_addr;
398 /* Read the MAC address from the hardware */
399 hi_addr = readl(ioaddr + XGMAC_ADDRx_HIGH(reg_n));
400 lo_addr = readl(ioaddr + XGMAC_ADDRx_LOW(reg_n));
402 /* Extract the MAC address from the high and low words */
403 addr[0] = lo_addr & 0xff;
404 addr[1] = (lo_addr >> 8) & 0xff;
405 addr[2] = (lo_addr >> 16) & 0xff;
406 addr[3] = (lo_addr >> 24) & 0xff;
407 addr[4] = hi_addr & 0xff;
408 addr[5] = (hi_addr >> 8) & 0xff;
411 static void dwxgmac2_set_eee_mode(struct mac_device_info *hw,
412 bool en_tx_lpi_clockgating)
414 void __iomem *ioaddr = hw->pcsr;
417 value = readl(ioaddr + XGMAC_LPI_CTRL);
419 value |= XGMAC_LPITXEN | XGMAC_LPITXA;
420 if (en_tx_lpi_clockgating)
421 value |= XGMAC_TXCGE;
423 writel(value, ioaddr + XGMAC_LPI_CTRL);
426 static void dwxgmac2_reset_eee_mode(struct mac_device_info *hw)
428 void __iomem *ioaddr = hw->pcsr;
431 value = readl(ioaddr + XGMAC_LPI_CTRL);
432 value &= ~(XGMAC_LPITXEN | XGMAC_LPITXA | XGMAC_TXCGE);
433 writel(value, ioaddr + XGMAC_LPI_CTRL);
436 static void dwxgmac2_set_eee_pls(struct mac_device_info *hw, int link)
438 void __iomem *ioaddr = hw->pcsr;
441 value = readl(ioaddr + XGMAC_LPI_CTRL);
446 writel(value, ioaddr + XGMAC_LPI_CTRL);
449 static void dwxgmac2_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
451 void __iomem *ioaddr = hw->pcsr;
454 value = (tw & 0xffff) | ((ls & 0x3ff) << 16);
455 writel(value, ioaddr + XGMAC_LPI_TIMER_CTRL);
458 static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
461 int numhashregs, regs;
463 switch (mcbitslog2) {
477 for (regs = 0; regs < numhashregs; regs++)
478 writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
481 static void dwxgmac2_set_filter(struct mac_device_info *hw,
482 struct net_device *dev)
484 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
485 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
486 int mcbitslog2 = hw->mcast_bits_log2;
490 value &= ~(XGMAC_FILTER_PR | XGMAC_FILTER_HMC | XGMAC_FILTER_PM);
491 value |= XGMAC_FILTER_HPF;
493 memset(mc_filter, 0, sizeof(mc_filter));
495 if (dev->flags & IFF_PROMISC) {
496 value |= XGMAC_FILTER_PR;
497 value |= XGMAC_FILTER_PCF;
498 } else if ((dev->flags & IFF_ALLMULTI) ||
499 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
500 value |= XGMAC_FILTER_PM;
502 for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
503 writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
504 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
505 struct netdev_hw_addr *ha;
507 value |= XGMAC_FILTER_HMC;
509 netdev_for_each_mc_addr(ha, dev) {
510 u32 nr = (bitrev32(~crc32_le(~0, ha->addr, 6)) >>
512 mc_filter[nr >> 5] |= (1 << (nr & 0x1F));
516 dwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);
518 /* Handle multiple unicast addresses */
519 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
520 value |= XGMAC_FILTER_PR;
522 struct netdev_hw_addr *ha;
525 netdev_for_each_uc_addr(ha, dev) {
526 dwxgmac2_set_umac_addr(hw, ha->addr, reg);
530 for ( ; reg < XGMAC_ADDR_MAX; reg++) {
531 writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg));
532 writel(0, ioaddr + XGMAC_ADDRx_LOW(reg));
536 writel(value, ioaddr + XGMAC_PACKET_FILTER);
539 static void dwxgmac2_set_mac_loopback(void __iomem *ioaddr, bool enable)
541 u32 value = readl(ioaddr + XGMAC_RX_CONFIG);
544 value |= XGMAC_CONFIG_LM;
546 value &= ~XGMAC_CONFIG_LM;
548 writel(value, ioaddr + XGMAC_RX_CONFIG);
551 static int dwxgmac2_rss_write_reg(void __iomem *ioaddr, bool is_key, int idx,
556 writel(val, ioaddr + XGMAC_RSS_DATA);
557 ctrl |= idx << XGMAC_RSSIA_SHIFT;
558 ctrl |= is_key ? XGMAC_ADDRT : 0x0;
560 writel(ctrl, ioaddr + XGMAC_RSS_ADDR);
562 return readl_poll_timeout(ioaddr + XGMAC_RSS_ADDR, ctrl,
563 !(ctrl & XGMAC_OB), 100, 10000);
566 static int dwxgmac2_rss_configure(struct mac_device_info *hw,
567 struct stmmac_rss *cfg, u32 num_rxq)
569 void __iomem *ioaddr = hw->pcsr;
573 value = readl(ioaddr + XGMAC_RSS_CTRL);
574 if (!cfg || !cfg->enable) {
575 value &= ~XGMAC_RSSE;
576 writel(value, ioaddr + XGMAC_RSS_CTRL);
580 key = (u32 *)cfg->key;
581 for (i = 0; i < (ARRAY_SIZE(cfg->key) / sizeof(u32)); i++) {
582 ret = dwxgmac2_rss_write_reg(ioaddr, true, i, key[i]);
587 for (i = 0; i < ARRAY_SIZE(cfg->table); i++) {
588 ret = dwxgmac2_rss_write_reg(ioaddr, false, i, cfg->table[i]);
593 for (i = 0; i < num_rxq; i++)
594 dwxgmac2_map_mtl_to_dma(hw, i, XGMAC_QDDMACH);
596 value |= XGMAC_UDP4TE | XGMAC_TCP4TE | XGMAC_IP2TE | XGMAC_RSSE;
597 writel(value, ioaddr + XGMAC_RSS_CTRL);
601 static void dwxgmac2_update_vlan_hash(struct mac_device_info *hw, u32 hash,
602 __le16 perfect_match, bool is_double)
604 void __iomem *ioaddr = hw->pcsr;
606 writel(hash, ioaddr + XGMAC_VLAN_HASH_TABLE);
609 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
611 value |= XGMAC_FILTER_VTFE;
613 writel(value, ioaddr + XGMAC_PACKET_FILTER);
615 value = readl(ioaddr + XGMAC_VLAN_TAG);
617 value |= XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV;
619 value |= XGMAC_VLAN_EDVLP;
620 value |= XGMAC_VLAN_ESVL;
621 value |= XGMAC_VLAN_DOVLTC;
623 value &= ~XGMAC_VLAN_EDVLP;
624 value &= ~XGMAC_VLAN_ESVL;
625 value &= ~XGMAC_VLAN_DOVLTC;
628 value &= ~XGMAC_VLAN_VID;
629 writel(value, ioaddr + XGMAC_VLAN_TAG);
630 } else if (perfect_match) {
631 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
633 value |= XGMAC_FILTER_VTFE;
635 writel(value, ioaddr + XGMAC_PACKET_FILTER);
637 value = readl(ioaddr + XGMAC_VLAN_TAG);
639 value &= ~XGMAC_VLAN_VTHM;
640 value |= XGMAC_VLAN_ETV;
642 value |= XGMAC_VLAN_EDVLP;
643 value |= XGMAC_VLAN_ESVL;
644 value |= XGMAC_VLAN_DOVLTC;
646 value &= ~XGMAC_VLAN_EDVLP;
647 value &= ~XGMAC_VLAN_ESVL;
648 value &= ~XGMAC_VLAN_DOVLTC;
651 value &= ~XGMAC_VLAN_VID;
652 writel(value | perfect_match, ioaddr + XGMAC_VLAN_TAG);
654 u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
656 value &= ~XGMAC_FILTER_VTFE;
658 writel(value, ioaddr + XGMAC_PACKET_FILTER);
660 value = readl(ioaddr + XGMAC_VLAN_TAG);
662 value &= ~(XGMAC_VLAN_VTHM | XGMAC_VLAN_ETV);
663 value &= ~(XGMAC_VLAN_EDVLP | XGMAC_VLAN_ESVL);
664 value &= ~XGMAC_VLAN_DOVLTC;
665 value &= ~XGMAC_VLAN_VID;
667 writel(value, ioaddr + XGMAC_VLAN_TAG);
671 struct dwxgmac3_error_desc {
674 const char *detailed_desc;
677 #define STAT_OFF(field) offsetof(struct stmmac_safety_stats, field)
679 static void dwxgmac3_log_error(struct net_device *ndev, u32 value, bool corr,
680 const char *module_name,
681 const struct dwxgmac3_error_desc *desc,
682 unsigned long field_offset,
683 struct stmmac_safety_stats *stats)
685 unsigned long loc, mask;
686 u8 *bptr = (u8 *)stats;
689 ptr = (unsigned long *)(bptr + field_offset);
692 for_each_set_bit(loc, &mask, 32) {
693 netdev_err(ndev, "Found %s error in %s: '%s: %s'\n", corr ?
694 "correctable" : "uncorrectable", module_name,
695 desc[loc].desc, desc[loc].detailed_desc);
697 /* Update counters */
702 static const struct dwxgmac3_error_desc dwxgmac3_mac_errors[32]= {
703 { true, "ATPES", "Application Transmit Interface Parity Check Error" },
704 { true, "DPES", "Descriptor Cache Data Path Parity Check Error" },
705 { true, "TPES", "TSO Data Path Parity Check Error" },
706 { true, "TSOPES", "TSO Header Data Path Parity Check Error" },
707 { true, "MTPES", "MTL Data Path Parity Check Error" },
708 { true, "MTSPES", "MTL TX Status Data Path Parity Check Error" },
709 { true, "MTBUPES", "MAC TBU Data Path Parity Check Error" },
710 { true, "MTFCPES", "MAC TFC Data Path Parity Check Error" },
711 { true, "ARPES", "Application Receive Interface Data Path Parity Check Error" },
712 { true, "MRWCPES", "MTL RWC Data Path Parity Check Error" },
713 { true, "MRRCPES", "MTL RCC Data Path Parity Check Error" },
714 { true, "CWPES", "CSR Write Data Path Parity Check Error" },
715 { true, "ASRPES", "AXI Slave Read Data Path Parity Check Error" },
716 { true, "TTES", "TX FSM Timeout Error" },
717 { true, "RTES", "RX FSM Timeout Error" },
718 { true, "CTES", "CSR FSM Timeout Error" },
719 { true, "ATES", "APP FSM Timeout Error" },
720 { true, "PTES", "PTP FSM Timeout Error" },
721 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
722 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
723 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
724 { true, "MSTTES", "Master Read/Write Timeout Error" },
725 { true, "SLVTES", "Slave Read/Write Timeout Error" },
726 { true, "ATITES", "Application Timeout on ATI Interface Error" },
727 { true, "ARITES", "Application Timeout on ARI Interface Error" },
728 { true, "FSMPES", "FSM State Parity Error" },
729 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
730 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
731 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
732 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
733 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
734 { true, "CPI", "Control Register Parity Check Error" },
737 static void dwxgmac3_handle_mac_err(struct net_device *ndev,
738 void __iomem *ioaddr, bool correctable,
739 struct stmmac_safety_stats *stats)
743 value = readl(ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
744 writel(value, ioaddr + XGMAC_MAC_DPP_FSM_INT_STATUS);
746 dwxgmac3_log_error(ndev, value, correctable, "MAC",
747 dwxgmac3_mac_errors, STAT_OFF(mac_errors), stats);
750 static const struct dwxgmac3_error_desc dwxgmac3_mtl_errors[32]= {
751 { true, "TXCES", "MTL TX Memory Error" },
752 { true, "TXAMS", "MTL TX Memory Address Mismatch Error" },
753 { true, "TXUES", "MTL TX Memory Error" },
754 { false, "UNKNOWN", "Unknown Error" }, /* 3 */
755 { true, "RXCES", "MTL RX Memory Error" },
756 { true, "RXAMS", "MTL RX Memory Address Mismatch Error" },
757 { true, "RXUES", "MTL RX Memory Error" },
758 { false, "UNKNOWN", "Unknown Error" }, /* 7 */
759 { true, "ECES", "MTL EST Memory Error" },
760 { true, "EAMS", "MTL EST Memory Address Mismatch Error" },
761 { true, "EUES", "MTL EST Memory Error" },
762 { false, "UNKNOWN", "Unknown Error" }, /* 11 */
763 { true, "RPCES", "MTL RX Parser Memory Error" },
764 { true, "RPAMS", "MTL RX Parser Memory Address Mismatch Error" },
765 { true, "RPUES", "MTL RX Parser Memory Error" },
766 { false, "UNKNOWN", "Unknown Error" }, /* 15 */
767 { false, "UNKNOWN", "Unknown Error" }, /* 16 */
768 { false, "UNKNOWN", "Unknown Error" }, /* 17 */
769 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
770 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
771 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
772 { false, "UNKNOWN", "Unknown Error" }, /* 21 */
773 { false, "UNKNOWN", "Unknown Error" }, /* 22 */
774 { false, "UNKNOWN", "Unknown Error" }, /* 23 */
775 { false, "UNKNOWN", "Unknown Error" }, /* 24 */
776 { false, "UNKNOWN", "Unknown Error" }, /* 25 */
777 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
778 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
779 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
780 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
781 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
782 { false, "UNKNOWN", "Unknown Error" }, /* 31 */
785 static void dwxgmac3_handle_mtl_err(struct net_device *ndev,
786 void __iomem *ioaddr, bool correctable,
787 struct stmmac_safety_stats *stats)
791 value = readl(ioaddr + XGMAC_MTL_ECC_INT_STATUS);
792 writel(value, ioaddr + XGMAC_MTL_ECC_INT_STATUS);
794 dwxgmac3_log_error(ndev, value, correctable, "MTL",
795 dwxgmac3_mtl_errors, STAT_OFF(mtl_errors), stats);
798 static const struct dwxgmac3_error_desc dwxgmac3_dma_errors[32]= {
799 { true, "TCES", "DMA TSO Memory Error" },
800 { true, "TAMS", "DMA TSO Memory Address Mismatch Error" },
801 { true, "TUES", "DMA TSO Memory Error" },
802 { false, "UNKNOWN", "Unknown Error" }, /* 3 */
803 { true, "DCES", "DMA DCACHE Memory Error" },
804 { true, "DAMS", "DMA DCACHE Address Mismatch Error" },
805 { true, "DUES", "DMA DCACHE Memory Error" },
806 { false, "UNKNOWN", "Unknown Error" }, /* 7 */
807 { false, "UNKNOWN", "Unknown Error" }, /* 8 */
808 { false, "UNKNOWN", "Unknown Error" }, /* 9 */
809 { false, "UNKNOWN", "Unknown Error" }, /* 10 */
810 { false, "UNKNOWN", "Unknown Error" }, /* 11 */
811 { false, "UNKNOWN", "Unknown Error" }, /* 12 */
812 { false, "UNKNOWN", "Unknown Error" }, /* 13 */
813 { false, "UNKNOWN", "Unknown Error" }, /* 14 */
814 { false, "UNKNOWN", "Unknown Error" }, /* 15 */
815 { false, "UNKNOWN", "Unknown Error" }, /* 16 */
816 { false, "UNKNOWN", "Unknown Error" }, /* 17 */
817 { false, "UNKNOWN", "Unknown Error" }, /* 18 */
818 { false, "UNKNOWN", "Unknown Error" }, /* 19 */
819 { false, "UNKNOWN", "Unknown Error" }, /* 20 */
820 { false, "UNKNOWN", "Unknown Error" }, /* 21 */
821 { false, "UNKNOWN", "Unknown Error" }, /* 22 */
822 { false, "UNKNOWN", "Unknown Error" }, /* 23 */
823 { false, "UNKNOWN", "Unknown Error" }, /* 24 */
824 { false, "UNKNOWN", "Unknown Error" }, /* 25 */
825 { false, "UNKNOWN", "Unknown Error" }, /* 26 */
826 { false, "UNKNOWN", "Unknown Error" }, /* 27 */
827 { false, "UNKNOWN", "Unknown Error" }, /* 28 */
828 { false, "UNKNOWN", "Unknown Error" }, /* 29 */
829 { false, "UNKNOWN", "Unknown Error" }, /* 30 */
830 { false, "UNKNOWN", "Unknown Error" }, /* 31 */
833 static const char * const dpp_rx_err = "Read Rx Descriptor Parity checker Error";
834 static const char * const dpp_tx_err = "Read Tx Descriptor Parity checker Error";
835 static const struct dwxgmac3_error_desc dwxgmac3_dma_dpp_errors[32] = {
836 { true, "TDPES0", dpp_tx_err },
837 { true, "TDPES1", dpp_tx_err },
838 { true, "TDPES2", dpp_tx_err },
839 { true, "TDPES3", dpp_tx_err },
840 { true, "TDPES4", dpp_tx_err },
841 { true, "TDPES5", dpp_tx_err },
842 { true, "TDPES6", dpp_tx_err },
843 { true, "TDPES7", dpp_tx_err },
844 { true, "TDPES8", dpp_tx_err },
845 { true, "TDPES9", dpp_tx_err },
846 { true, "TDPES10", dpp_tx_err },
847 { true, "TDPES11", dpp_tx_err },
848 { true, "TDPES12", dpp_tx_err },
849 { true, "TDPES13", dpp_tx_err },
850 { true, "TDPES14", dpp_tx_err },
851 { true, "TDPES15", dpp_tx_err },
852 { true, "RDPES0", dpp_rx_err },
853 { true, "RDPES1", dpp_rx_err },
854 { true, "RDPES2", dpp_rx_err },
855 { true, "RDPES3", dpp_rx_err },
856 { true, "RDPES4", dpp_rx_err },
857 { true, "RDPES5", dpp_rx_err },
858 { true, "RDPES6", dpp_rx_err },
859 { true, "RDPES7", dpp_rx_err },
860 { true, "RDPES8", dpp_rx_err },
861 { true, "RDPES9", dpp_rx_err },
862 { true, "RDPES10", dpp_rx_err },
863 { true, "RDPES11", dpp_rx_err },
864 { true, "RDPES12", dpp_rx_err },
865 { true, "RDPES13", dpp_rx_err },
866 { true, "RDPES14", dpp_rx_err },
867 { true, "RDPES15", dpp_rx_err },
870 static void dwxgmac3_handle_dma_err(struct net_device *ndev,
871 void __iomem *ioaddr, bool correctable,
872 struct stmmac_safety_stats *stats)
876 value = readl(ioaddr + XGMAC_DMA_ECC_INT_STATUS);
877 writel(value, ioaddr + XGMAC_DMA_ECC_INT_STATUS);
879 dwxgmac3_log_error(ndev, value, correctable, "DMA",
880 dwxgmac3_dma_errors, STAT_OFF(dma_errors), stats);
882 value = readl(ioaddr + XGMAC_DMA_DPP_INT_STATUS);
883 writel(value, ioaddr + XGMAC_DMA_DPP_INT_STATUS);
885 dwxgmac3_log_error(ndev, value, false, "DMA_DPP",
886 dwxgmac3_dma_dpp_errors,
887 STAT_OFF(dma_dpp_errors), stats);
891 dwxgmac3_safety_feat_config(void __iomem *ioaddr, unsigned int asp,
892 struct stmmac_safety_feature_cfg *safety_cfg)
899 /* 1. Enable Safety Features */
900 writel(0x0, ioaddr + XGMAC_MTL_ECC_CONTROL);
902 /* 2. Enable MTL Safety Interrupts */
903 value = readl(ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
904 value |= XGMAC_RPCEIE; /* RX Parser Memory Correctable Error */
905 value |= XGMAC_ECEIE; /* EST Memory Correctable Error */
906 value |= XGMAC_RXCEIE; /* RX Memory Correctable Error */
907 value |= XGMAC_TXCEIE; /* TX Memory Correctable Error */
908 writel(value, ioaddr + XGMAC_MTL_ECC_INT_ENABLE);
910 /* 3. Enable DMA Safety Interrupts */
911 value = readl(ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
912 value |= XGMAC_DCEIE; /* Descriptor Cache Memory Correctable Error */
913 value |= XGMAC_TCEIE; /* TSO Memory Correctable Error */
914 writel(value, ioaddr + XGMAC_DMA_ECC_INT_ENABLE);
916 /* 0x2: Without ECC or Parity Ports on External Application Interface
917 * 0x4: Only ECC Protection for External Memory feature is selected
919 if (asp == 0x2 || asp == 0x4)
922 /* 4. Enable Parity and Timeout for FSM */
923 value = readl(ioaddr + XGMAC_MAC_FSM_CONTROL);
924 value |= XGMAC_PRTYEN; /* FSM Parity Feature */
925 value |= XGMAC_TMOUTEN; /* FSM Timeout Feature */
926 writel(value, ioaddr + XGMAC_MAC_FSM_CONTROL);
928 /* 5. Enable Data Path Parity Protection */
929 value = readl(ioaddr + XGMAC_MTL_DPP_CONTROL);
930 /* already enabled by default, explicit enable it again */
931 value &= ~XGMAC_DDPP_DISABLE;
932 writel(value, ioaddr + XGMAC_MTL_DPP_CONTROL);
937 static int dwxgmac3_safety_feat_irq_status(struct net_device *ndev,
938 void __iomem *ioaddr,
940 struct stmmac_safety_stats *stats)
949 mtl = readl(ioaddr + XGMAC_MTL_SAFETY_INT_STATUS);
950 dma = readl(ioaddr + XGMAC_DMA_SAFETY_INT_STATUS);
952 err = (mtl & XGMAC_MCSIS) || (dma & XGMAC_MCSIS);
955 dwxgmac3_handle_mac_err(ndev, ioaddr, corr, stats);
959 err = (mtl & (XGMAC_MEUIS | XGMAC_MECIS)) ||
960 (dma & (XGMAC_MSUIS | XGMAC_MSCIS));
961 corr = (mtl & XGMAC_MECIS) || (dma & XGMAC_MSCIS);
963 dwxgmac3_handle_mtl_err(ndev, ioaddr, corr, stats);
967 /* DMA_DPP_Interrupt_Status is indicated by MCSIS bit in
968 * DMA_Safety_Interrupt_Status, so we handle DMA Data Path
971 err = dma & (XGMAC_DEUIS | XGMAC_DECIS | XGMAC_MCSIS);
972 corr = dma & XGMAC_DECIS;
974 dwxgmac3_handle_dma_err(ndev, ioaddr, corr, stats);
981 static const struct dwxgmac3_error {
982 const struct dwxgmac3_error_desc *desc;
983 } dwxgmac3_all_errors[] = {
984 { dwxgmac3_mac_errors },
985 { dwxgmac3_mtl_errors },
986 { dwxgmac3_dma_errors },
987 { dwxgmac3_dma_dpp_errors },
990 static int dwxgmac3_safety_feat_dump(struct stmmac_safety_stats *stats,
991 int index, unsigned long *count,
994 int module = index / 32, offset = index % 32;
995 unsigned long *ptr = (unsigned long *)stats;
997 if (module >= ARRAY_SIZE(dwxgmac3_all_errors))
999 if (!dwxgmac3_all_errors[module].desc[offset].valid)
1002 *count = *(ptr + index);
1004 *desc = dwxgmac3_all_errors[module].desc[offset].desc;
1008 static int dwxgmac3_rxp_disable(void __iomem *ioaddr)
1010 u32 val = readl(ioaddr + XGMAC_MTL_OPMODE);
1013 writel(val, ioaddr + XGMAC_MTL_OPMODE);
1018 static void dwxgmac3_rxp_enable(void __iomem *ioaddr)
1022 val = readl(ioaddr + XGMAC_MTL_OPMODE);
1024 writel(val, ioaddr + XGMAC_MTL_OPMODE);
1027 static int dwxgmac3_rxp_update_single_entry(void __iomem *ioaddr,
1028 struct stmmac_tc_entry *entry,
1033 for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
1034 int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
1037 /* Wait for ready */
1038 ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
1039 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1044 val = *((u32 *)&entry->val + i);
1045 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_DATA);
1048 val = real_pos & XGMAC_ADDR;
1049 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1053 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1056 val |= XGMAC_STARTBUSY;
1057 writel(val, ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST);
1060 ret = readl_poll_timeout(ioaddr + XGMAC_MTL_RXP_IACC_CTRL_ST,
1061 val, !(val & XGMAC_STARTBUSY), 1, 10000);
1069 static struct stmmac_tc_entry *
1070 dwxgmac3_rxp_get_next_entry(struct stmmac_tc_entry *entries,
1071 unsigned int count, u32 curr_prio)
1073 struct stmmac_tc_entry *entry;
1074 u32 min_prio = ~0x0;
1075 int i, min_prio_idx;
1078 for (i = count - 1; i >= 0; i--) {
1079 entry = &entries[i];
1081 /* Do not update unused entries */
1084 /* Do not update already updated entries (i.e. fragments) */
1087 /* Let last entry be updated last */
1090 /* Do not return fragments */
1093 /* Check if we already checked this prio */
1094 if (entry->prio < curr_prio)
1096 /* Check if this is the minimum prio */
1097 if (entry->prio < min_prio) {
1098 min_prio = entry->prio;
1105 return &entries[min_prio_idx];
1109 static int dwxgmac3_rxp_config(void __iomem *ioaddr,
1110 struct stmmac_tc_entry *entries,
1113 struct stmmac_tc_entry *entry, *frag;
1114 int i, ret, nve = 0;
1118 /* Force disable RX */
1119 old_val = readl(ioaddr + XGMAC_RX_CONFIG);
1120 val = old_val & ~XGMAC_CONFIG_RE;
1121 writel(val, ioaddr + XGMAC_RX_CONFIG);
1123 /* Disable RX Parser */
1124 ret = dwxgmac3_rxp_disable(ioaddr);
1128 /* Set all entries as NOT in HW */
1129 for (i = 0; i < count; i++) {
1130 entry = &entries[i];
1131 entry->in_hw = false;
1134 /* Update entries by reverse order */
1136 entry = dwxgmac3_rxp_get_next_entry(entries, count, curr_prio);
1140 curr_prio = entry->prio;
1141 frag = entry->frag_ptr;
1143 /* Set special fragment requirements */
1148 entry->val.ok_index = nve + 2;
1151 ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
1155 entry->table_pos = nve++;
1156 entry->in_hw = true;
1158 if (frag && !frag->in_hw) {
1159 ret = dwxgmac3_rxp_update_single_entry(ioaddr, frag, nve);
1162 frag->table_pos = nve++;
1170 /* Update all pass entry */
1171 for (i = 0; i < count; i++) {
1172 entry = &entries[i];
1173 if (!entry->is_last)
1176 ret = dwxgmac3_rxp_update_single_entry(ioaddr, entry, nve);
1180 entry->table_pos = nve++;
1183 /* Assume n. of parsable entries == n. of valid entries */
1184 val = (nve << 16) & XGMAC_NPE;
1185 val |= nve & XGMAC_NVE;
1186 writel(val, ioaddr + XGMAC_MTL_RXP_CONTROL_STATUS);
1188 /* Enable RX Parser */
1189 dwxgmac3_rxp_enable(ioaddr);
1193 writel(old_val, ioaddr + XGMAC_RX_CONFIG);
1197 static int dwxgmac2_get_mac_tx_timestamp(struct mac_device_info *hw, u64 *ts)
1199 void __iomem *ioaddr = hw->pcsr;
1202 if (readl_poll_timeout_atomic(ioaddr + XGMAC_TIMESTAMP_STATUS,
1203 value, value & XGMAC_TXTSC, 100, 10000))
1206 *ts = readl(ioaddr + XGMAC_TXTIMESTAMP_NSEC) & XGMAC_TXTSSTSLO;
1207 *ts += readl(ioaddr + XGMAC_TXTIMESTAMP_SEC) * 1000000000ULL;
1211 static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index,
1212 struct stmmac_pps_cfg *cfg, bool enable,
1213 u32 sub_second_inc, u32 systime_flags)
1215 u32 tnsec = readl(ioaddr + XGMAC_PPSx_TARGET_TIME_NSEC(index));
1216 u32 val = readl(ioaddr + XGMAC_PPS_CONTROL);
1219 if (!cfg->available)
1221 if (tnsec & XGMAC_TRGTBUSY0)
1223 if (!sub_second_inc || !systime_flags)
1226 val &= ~XGMAC_PPSx_MASK(index);
1229 val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_STOP);
1230 writel(val, ioaddr + XGMAC_PPS_CONTROL);
1234 val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_START);
1235 val |= XGMAC_TRGTMODSELx(index, XGMAC_PPSCMD_START);
1237 /* XGMAC Core has 4 PPS outputs at most.
1239 * Prior XGMAC Core 3.20, Fixed mode or Flexible mode are selectable for
1240 * PPS0 only via PPSEN0. PPS{1,2,3} are in Flexible mode by default,
1241 * and can not be switched to Fixed mode, since PPSEN{1,2,3} are
1242 * read-only reserved to 0.
1243 * But we always set PPSEN{1,2,3} do not make things worse ;-)
1245 * From XGMAC Core 3.20 and later, PPSEN{0,1,2,3} are writable and must
1246 * be set, or the PPS outputs stay in Fixed PPS mode by default.
1248 val |= XGMAC_PPSENx(index);
1250 writel(cfg->start.tv_sec, ioaddr + XGMAC_PPSx_TARGET_TIME_SEC(index));
1252 if (!(systime_flags & PTP_TCR_TSCTRLSSR))
1253 cfg->start.tv_nsec = (cfg->start.tv_nsec * 1000) / 465;
1254 writel(cfg->start.tv_nsec, ioaddr + XGMAC_PPSx_TARGET_TIME_NSEC(index));
1256 period = cfg->period.tv_sec * 1000000000;
1257 period += cfg->period.tv_nsec;
1259 do_div(period, sub_second_inc);
1264 writel(period - 1, ioaddr + XGMAC_PPSx_INTERVAL(index));
1270 writel(period - 1, ioaddr + XGMAC_PPSx_WIDTH(index));
1272 /* Finally, activate it */
1273 writel(val, ioaddr + XGMAC_PPS_CONTROL);
1277 static void dwxgmac2_sarc_configure(void __iomem *ioaddr, int val)
1279 u32 value = readl(ioaddr + XGMAC_TX_CONFIG);
1281 value &= ~XGMAC_CONFIG_SARC;
1282 value |= val << XGMAC_CONFIG_SARC_SHIFT;
1284 writel(value, ioaddr + XGMAC_TX_CONFIG);
1287 static void dwxgmac2_enable_vlan(struct mac_device_info *hw, u32 type)
1289 void __iomem *ioaddr = hw->pcsr;
1292 value = readl(ioaddr + XGMAC_VLAN_INCL);
1293 value |= XGMAC_VLAN_VLTI;
1294 value |= XGMAC_VLAN_CSVL; /* Only use SVLAN */
1295 value &= ~XGMAC_VLAN_VLC;
1296 value |= (type << XGMAC_VLAN_VLC_SHIFT) & XGMAC_VLAN_VLC;
1297 writel(value, ioaddr + XGMAC_VLAN_INCL);
1300 static int dwxgmac2_filter_wait(struct mac_device_info *hw)
1302 void __iomem *ioaddr = hw->pcsr;
1305 if (readl_poll_timeout(ioaddr + XGMAC_L3L4_ADDR_CTRL, value,
1306 !(value & XGMAC_XB), 100, 10000))
1311 static int dwxgmac2_filter_read(struct mac_device_info *hw, u32 filter_no,
1314 void __iomem *ioaddr = hw->pcsr;
1318 ret = dwxgmac2_filter_wait(hw);
1322 value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1323 value |= XGMAC_TT | XGMAC_XB;
1324 writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1326 ret = dwxgmac2_filter_wait(hw);
1330 *data = readl(ioaddr + XGMAC_L3L4_DATA);
1334 static int dwxgmac2_filter_write(struct mac_device_info *hw, u32 filter_no,
1337 void __iomem *ioaddr = hw->pcsr;
1341 ret = dwxgmac2_filter_wait(hw);
1345 writel(data, ioaddr + XGMAC_L3L4_DATA);
1347 value = ((filter_no << XGMAC_IDDR_FNUM) | reg) << XGMAC_IDDR_SHIFT;
1349 writel(value, ioaddr + XGMAC_L3L4_ADDR_CTRL);
1351 return dwxgmac2_filter_wait(hw);
1354 static int dwxgmac2_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1355 bool en, bool ipv6, bool sa, bool inv,
1358 void __iomem *ioaddr = hw->pcsr;
1362 value = readl(ioaddr + XGMAC_PACKET_FILTER);
1363 value |= XGMAC_FILTER_IPFE;
1364 writel(value, ioaddr + XGMAC_PACKET_FILTER);
1366 ret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, &value);
1370 /* For IPv6 not both SA/DA filters can be active */
1372 value |= XGMAC_L3PEN0;
1373 value &= ~(XGMAC_L3SAM0 | XGMAC_L3SAIM0);
1374 value &= ~(XGMAC_L3DAM0 | XGMAC_L3DAIM0);
1376 value |= XGMAC_L3SAM0;
1378 value |= XGMAC_L3SAIM0;
1380 value |= XGMAC_L3DAM0;
1382 value |= XGMAC_L3DAIM0;
1385 value &= ~XGMAC_L3PEN0;
1387 value |= XGMAC_L3SAM0;
1389 value |= XGMAC_L3SAIM0;
1391 value |= XGMAC_L3DAM0;
1393 value |= XGMAC_L3DAIM0;
1397 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);
1402 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR0, match);
1406 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3_ADDR1, match);
1412 return dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);
1417 static int dwxgmac2_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1418 bool en, bool udp, bool sa, bool inv,
1421 void __iomem *ioaddr = hw->pcsr;
1425 value = readl(ioaddr + XGMAC_PACKET_FILTER);
1426 value |= XGMAC_FILTER_IPFE;
1427 writel(value, ioaddr + XGMAC_PACKET_FILTER);
1429 ret = dwxgmac2_filter_read(hw, filter_no, XGMAC_L3L4_CTRL, &value);
1434 value |= XGMAC_L4PEN0;
1436 value &= ~XGMAC_L4PEN0;
1439 value &= ~(XGMAC_L4SPM0 | XGMAC_L4SPIM0);
1440 value &= ~(XGMAC_L4DPM0 | XGMAC_L4DPIM0);
1442 value |= XGMAC_L4SPM0;
1444 value |= XGMAC_L4SPIM0;
1446 value |= XGMAC_L4DPM0;
1448 value |= XGMAC_L4DPIM0;
1451 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, value);
1456 value = match & XGMAC_L4SP0;
1458 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1462 value = (match << XGMAC_L4DP0_SHIFT) & XGMAC_L4DP0;
1464 ret = dwxgmac2_filter_write(hw, filter_no, XGMAC_L4_ADDR, value);
1470 return dwxgmac2_filter_write(hw, filter_no, XGMAC_L3L4_CTRL, 0);
1475 static void dwxgmac2_set_arp_offload(struct mac_device_info *hw, bool en,
1478 void __iomem *ioaddr = hw->pcsr;
1481 writel(addr, ioaddr + XGMAC_ARP_ADDR);
1483 value = readl(ioaddr + XGMAC_RX_CONFIG);
1485 value |= XGMAC_CONFIG_ARPEN;
1487 value &= ~XGMAC_CONFIG_ARPEN;
1488 writel(value, ioaddr + XGMAC_RX_CONFIG);
1491 static int dwxgmac3_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
1495 writel(val, ioaddr + XGMAC_MTL_EST_GCL_DATA);
1497 ctrl = (reg << XGMAC_ADDR_SHIFT);
1498 ctrl |= gcl ? 0 : XGMAC_GCRR;
1500 writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
1503 writel(ctrl, ioaddr + XGMAC_MTL_EST_GCL_CONTROL);
1505 return readl_poll_timeout_atomic(ioaddr + XGMAC_MTL_EST_GCL_CONTROL,
1506 ctrl, !(ctrl & XGMAC_SRWO), 100, 5000);
1509 static int dwxgmac3_est_configure(void __iomem *ioaddr, struct stmmac_est *cfg,
1510 unsigned int ptp_rate)
1515 ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_LOW, cfg->btr[0], false);
1516 ret |= dwxgmac3_est_write(ioaddr, XGMAC_BTR_HIGH, cfg->btr[1], false);
1517 ret |= dwxgmac3_est_write(ioaddr, XGMAC_TER, cfg->ter, false);
1518 ret |= dwxgmac3_est_write(ioaddr, XGMAC_LLR, cfg->gcl_size, false);
1519 ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_LOW, cfg->ctr[0], false);
1520 ret |= dwxgmac3_est_write(ioaddr, XGMAC_CTR_HIGH, cfg->ctr[1], false);
1524 for (i = 0; i < cfg->gcl_size; i++) {
1525 ret = dwxgmac3_est_write(ioaddr, i, cfg->gcl[i], true);
1530 ctrl = readl(ioaddr + XGMAC_MTL_EST_CONTROL);
1531 ctrl &= ~XGMAC_PTOV;
1532 ctrl |= ((1000000000 / ptp_rate) * 9) << XGMAC_PTOV_SHIFT;
1534 ctrl |= XGMAC_EEST | XGMAC_SSWL;
1536 ctrl &= ~XGMAC_EEST;
1538 writel(ctrl, ioaddr + XGMAC_MTL_EST_CONTROL);
1542 static void dwxgmac3_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
1544 u32 num_rxq, bool enable)
1549 value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
1551 value &= ~XGMAC_EFPE;
1553 writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
1557 value = readl(ioaddr + XGMAC_RXQ_CTRL1);
1559 value |= (num_rxq - 1) << XGMAC_RQ_SHIFT;
1560 writel(value, ioaddr + XGMAC_RXQ_CTRL1);
1562 value = readl(ioaddr + XGMAC_FPE_CTRL_STS);
1563 value |= XGMAC_EFPE;
1564 writel(value, ioaddr + XGMAC_FPE_CTRL_STS);
1567 const struct stmmac_ops dwxgmac210_ops = {
1568 .core_init = dwxgmac2_core_init,
1569 .phylink_get_caps = xgmac_phylink_get_caps,
1570 .set_mac = dwxgmac2_set_mac,
1571 .rx_ipc = dwxgmac2_rx_ipc,
1572 .rx_queue_enable = dwxgmac2_rx_queue_enable,
1573 .rx_queue_prio = dwxgmac2_rx_queue_prio,
1574 .tx_queue_prio = dwxgmac2_tx_queue_prio,
1575 .rx_queue_routing = dwxgmac2_rx_queue_routing,
1576 .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
1577 .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
1578 .set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
1579 .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
1580 .config_cbs = dwxgmac2_config_cbs,
1581 .dump_regs = dwxgmac2_dump_regs,
1582 .host_irq_status = dwxgmac2_host_irq_status,
1583 .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
1584 .flow_ctrl = dwxgmac2_flow_ctrl,
1585 .pmt = dwxgmac2_pmt,
1586 .set_umac_addr = dwxgmac2_set_umac_addr,
1587 .get_umac_addr = dwxgmac2_get_umac_addr,
1588 .set_eee_mode = dwxgmac2_set_eee_mode,
1589 .reset_eee_mode = dwxgmac2_reset_eee_mode,
1590 .set_eee_timer = dwxgmac2_set_eee_timer,
1591 .set_eee_pls = dwxgmac2_set_eee_pls,
1592 .pcs_ctrl_ane = NULL,
1594 .pcs_get_adv_lp = NULL,
1596 .set_filter = dwxgmac2_set_filter,
1597 .safety_feat_config = dwxgmac3_safety_feat_config,
1598 .safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
1599 .safety_feat_dump = dwxgmac3_safety_feat_dump,
1600 .set_mac_loopback = dwxgmac2_set_mac_loopback,
1601 .rss_configure = dwxgmac2_rss_configure,
1602 .update_vlan_hash = dwxgmac2_update_vlan_hash,
1603 .rxp_config = dwxgmac3_rxp_config,
1604 .get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,
1605 .flex_pps_config = dwxgmac2_flex_pps_config,
1606 .sarc_configure = dwxgmac2_sarc_configure,
1607 .enable_vlan = dwxgmac2_enable_vlan,
1608 .config_l3_filter = dwxgmac2_config_l3_filter,
1609 .config_l4_filter = dwxgmac2_config_l4_filter,
1610 .set_arp_offload = dwxgmac2_set_arp_offload,
1611 .est_configure = dwxgmac3_est_configure,
1612 .fpe_configure = dwxgmac3_fpe_configure,
1615 static void dwxlgmac2_rx_queue_enable(struct mac_device_info *hw, u8 mode,
1618 void __iomem *ioaddr = hw->pcsr;
1621 value = readl(ioaddr + XLGMAC_RXQ_ENABLE_CTRL0) & ~XGMAC_RXQEN(queue);
1622 if (mode == MTL_QUEUE_AVB)
1623 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue);
1624 else if (mode == MTL_QUEUE_DCB)
1625 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue);
1626 writel(value, ioaddr + XLGMAC_RXQ_ENABLE_CTRL0);
1629 const struct stmmac_ops dwxlgmac2_ops = {
1630 .core_init = dwxgmac2_core_init,
1631 .phylink_get_caps = xgmac_phylink_get_caps,
1632 .set_mac = dwxgmac2_set_mac,
1633 .rx_ipc = dwxgmac2_rx_ipc,
1634 .rx_queue_enable = dwxlgmac2_rx_queue_enable,
1635 .rx_queue_prio = dwxgmac2_rx_queue_prio,
1636 .tx_queue_prio = dwxgmac2_tx_queue_prio,
1637 .rx_queue_routing = dwxgmac2_rx_queue_routing,
1638 .prog_mtl_rx_algorithms = dwxgmac2_prog_mtl_rx_algorithms,
1639 .prog_mtl_tx_algorithms = dwxgmac2_prog_mtl_tx_algorithms,
1640 .set_mtl_tx_queue_weight = dwxgmac2_set_mtl_tx_queue_weight,
1641 .map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
1642 .config_cbs = dwxgmac2_config_cbs,
1643 .dump_regs = dwxgmac2_dump_regs,
1644 .host_irq_status = dwxgmac2_host_irq_status,
1645 .host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
1646 .flow_ctrl = dwxgmac2_flow_ctrl,
1647 .pmt = dwxgmac2_pmt,
1648 .set_umac_addr = dwxgmac2_set_umac_addr,
1649 .get_umac_addr = dwxgmac2_get_umac_addr,
1650 .set_eee_mode = dwxgmac2_set_eee_mode,
1651 .reset_eee_mode = dwxgmac2_reset_eee_mode,
1652 .set_eee_timer = dwxgmac2_set_eee_timer,
1653 .set_eee_pls = dwxgmac2_set_eee_pls,
1654 .pcs_ctrl_ane = NULL,
1656 .pcs_get_adv_lp = NULL,
1658 .set_filter = dwxgmac2_set_filter,
1659 .safety_feat_config = dwxgmac3_safety_feat_config,
1660 .safety_feat_irq_status = dwxgmac3_safety_feat_irq_status,
1661 .safety_feat_dump = dwxgmac3_safety_feat_dump,
1662 .set_mac_loopback = dwxgmac2_set_mac_loopback,
1663 .rss_configure = dwxgmac2_rss_configure,
1664 .update_vlan_hash = dwxgmac2_update_vlan_hash,
1665 .rxp_config = dwxgmac3_rxp_config,
1666 .get_mac_tx_timestamp = dwxgmac2_get_mac_tx_timestamp,
1667 .flex_pps_config = dwxgmac2_flex_pps_config,
1668 .sarc_configure = dwxgmac2_sarc_configure,
1669 .enable_vlan = dwxgmac2_enable_vlan,
1670 .config_l3_filter = dwxgmac2_config_l3_filter,
1671 .config_l4_filter = dwxgmac2_config_l4_filter,
1672 .set_arp_offload = dwxgmac2_set_arp_offload,
1673 .est_configure = dwxgmac3_est_configure,
1674 .fpe_configure = dwxgmac3_fpe_configure,
1677 int dwxgmac2_setup(struct stmmac_priv *priv)
1679 struct mac_device_info *mac = priv->hw;
1681 dev_info(priv->device, "\tXGMAC2\n");
1683 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1684 mac->pcsr = priv->ioaddr;
1685 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1686 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1687 mac->mcast_bits_log2 = 0;
1689 if (mac->multicast_filter_bins)
1690 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1692 mac->link.duplex = 0;
1693 mac->link.speed10 = XGMAC_CONFIG_SS_10_MII;
1694 mac->link.speed100 = XGMAC_CONFIG_SS_100_MII;
1695 mac->link.speed1000 = XGMAC_CONFIG_SS_1000_GMII;
1696 mac->link.speed2500 = XGMAC_CONFIG_SS_2500_GMII;
1697 mac->link.xgmii.speed2500 = XGMAC_CONFIG_SS_2500;
1698 mac->link.xgmii.speed5000 = XGMAC_CONFIG_SS_5000;
1699 mac->link.xgmii.speed10000 = XGMAC_CONFIG_SS_10000;
1700 mac->link.speed_mask = XGMAC_CONFIG_SS_MASK;
1702 mac->mii.addr = XGMAC_MDIO_ADDR;
1703 mac->mii.data = XGMAC_MDIO_DATA;
1704 mac->mii.addr_shift = 16;
1705 mac->mii.addr_mask = GENMASK(20, 16);
1706 mac->mii.reg_shift = 0;
1707 mac->mii.reg_mask = GENMASK(15, 0);
1708 mac->mii.clk_csr_shift = 19;
1709 mac->mii.clk_csr_mask = GENMASK(21, 19);
1714 int dwxlgmac2_setup(struct stmmac_priv *priv)
1716 struct mac_device_info *mac = priv->hw;
1718 dev_info(priv->device, "\tXLGMAC\n");
1720 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1721 mac->pcsr = priv->ioaddr;
1722 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1723 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1724 mac->mcast_bits_log2 = 0;
1726 if (mac->multicast_filter_bins)
1727 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1729 mac->link.duplex = 0;
1730 mac->link.speed1000 = XLGMAC_CONFIG_SS_1000;
1731 mac->link.speed2500 = XLGMAC_CONFIG_SS_2500;
1732 mac->link.xgmii.speed10000 = XLGMAC_CONFIG_SS_10G;
1733 mac->link.xlgmii.speed25000 = XLGMAC_CONFIG_SS_25G;
1734 mac->link.xlgmii.speed40000 = XLGMAC_CONFIG_SS_40G;
1735 mac->link.xlgmii.speed50000 = XLGMAC_CONFIG_SS_50G;
1736 mac->link.xlgmii.speed100000 = XLGMAC_CONFIG_SS_100G;
1737 mac->link.speed_mask = XLGMAC_CONFIG_SS;
1739 mac->mii.addr = XGMAC_MDIO_ADDR;
1740 mac->mii.data = XGMAC_MDIO_DATA;
1741 mac->mii.addr_shift = 16;
1742 mac->mii.addr_mask = GENMASK(20, 16);
1743 mac->mii.reg_shift = 0;
1744 mac->mii.reg_mask = GENMASK(15, 0);
1745 mac->mii.clk_csr_shift = 19;
1746 mac->mii.clk_csr_mask = GENMASK(21, 19);