1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
4 * stmmac XGMAC definitions.
7 #ifndef __STMMAC_DWXGMAC2_H__
8 #define __STMMAC_DWXGMAC2_H__
13 #define XGMAC_JUMBO_LEN 16368
16 #define XGMAC_TX_CONFIG 0x00000000
17 #define XGMAC_CONFIG_SS_OFF 29
18 #define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)
19 #define XGMAC_CONFIG_SS_10000 (0x0 << XGMAC_CONFIG_SS_OFF)
20 #define XGMAC_CONFIG_SS_2500_GMII (0x2 << XGMAC_CONFIG_SS_OFF)
21 #define XGMAC_CONFIG_SS_1000_GMII (0x3 << XGMAC_CONFIG_SS_OFF)
22 #define XGMAC_CONFIG_SS_100_MII (0x4 << XGMAC_CONFIG_SS_OFF)
23 #define XGMAC_CONFIG_SS_5000 (0x5 << XGMAC_CONFIG_SS_OFF)
24 #define XGMAC_CONFIG_SS_2500 (0x6 << XGMAC_CONFIG_SS_OFF)
25 #define XGMAC_CONFIG_SS_10_MII (0x7 << XGMAC_CONFIG_SS_OFF)
26 #define XGMAC_CONFIG_SARC GENMASK(22, 20)
27 #define XGMAC_CONFIG_SARC_SHIFT 20
28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
30 #define XGMAC_CORE_INIT_TX (XGMAC_CONFIG_JD)
31 #define XGMAC_RX_CONFIG 0x00000004
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34 #define XGMAC_CONFIG_GPSL_SHIFT 16
35 #define XGMAC_CONFIG_HDSMS GENMASK(14, 12)
36 #define XGMAC_CONFIG_HDSMS_SHIFT 12
37 #define XGMAC_CONFIG_HDSMS_256 (0x2 << XGMAC_CONFIG_HDSMS_SHIFT)
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
42 #define XGMAC_CONFIG_WD BIT(7)
43 #define XGMAC_CONFIG_GPSLCE BIT(6)
44 #define XGMAC_CONFIG_CST BIT(2)
45 #define XGMAC_CONFIG_ACS BIT(1)
46 #define XGMAC_CONFIG_RE BIT(0)
47 #define XGMAC_CORE_INIT_RX (XGMAC_CONFIG_GPSLCE | XGMAC_CONFIG_WD | \
48 (XGMAC_JUMBO_LEN << XGMAC_CONFIG_GPSL_SHIFT))
49 #define XGMAC_PACKET_FILTER 0x00000008
50 #define XGMAC_FILTER_RA BIT(31)
51 #define XGMAC_FILTER_IPFE BIT(20)
52 #define XGMAC_FILTER_VTFE BIT(16)
53 #define XGMAC_FILTER_HPF BIT(10)
54 #define XGMAC_FILTER_PCF BIT(7)
55 #define XGMAC_FILTER_PM BIT(4)
56 #define XGMAC_FILTER_HMC BIT(2)
57 #define XGMAC_FILTER_PR BIT(0)
58 #define XGMAC_HASH_TABLE(x) (0x00000010 + (x) * 4)
59 #define XGMAC_MAX_HASH_TABLE 8
60 #define XGMAC_VLAN_TAG 0x00000050
61 #define XGMAC_VLAN_EDVLP BIT(26)
62 #define XGMAC_VLAN_VTHM BIT(25)
63 #define XGMAC_VLAN_DOVLTC BIT(20)
64 #define XGMAC_VLAN_ESVL BIT(18)
65 #define XGMAC_VLAN_ETV BIT(16)
66 #define XGMAC_VLAN_VID GENMASK(15, 0)
67 #define XGMAC_VLAN_HASH_TABLE 0x00000058
68 #define XGMAC_VLAN_INCL 0x00000060
69 #define XGMAC_VLAN_VLTI BIT(20)
70 #define XGMAC_VLAN_CSVL BIT(19)
71 #define XGMAC_VLAN_VLC GENMASK(17, 16)
72 #define XGMAC_VLAN_VLC_SHIFT 16
73 #define XGMAC_RXQ_CTRL0 0x000000a0
74 #define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
75 #define XGMAC_RXQEN_SHIFT(x) ((x) * 2)
76 #define XGMAC_RXQ_CTRL1 0x000000a4
77 #define XGMAC_AVCPQ GENMASK(31, 28)
78 #define XGMAC_AVCPQ_SHIFT 28
79 #define XGMAC_PTPQ GENMASK(27, 24)
80 #define XGMAC_PTPQ_SHIFT 24
81 #define XGMAC_TACPQE BIT(23)
82 #define XGMAC_DCBCPQ GENMASK(19, 16)
83 #define XGMAC_DCBCPQ_SHIFT 16
84 #define XGMAC_MCBCQEN BIT(15)
85 #define XGMAC_MCBCQ GENMASK(11, 8)
86 #define XGMAC_MCBCQ_SHIFT 8
87 #define XGMAC_RQ GENMASK(7, 4)
88 #define XGMAC_RQ_SHIFT 4
89 #define XGMAC_UPQ GENMASK(3, 0)
90 #define XGMAC_UPQ_SHIFT 0
91 #define XGMAC_RXQ_CTRL2 0x000000a8
92 #define XGMAC_RXQ_CTRL3 0x000000ac
93 #define XGMAC_PSRQ(x) GENMASK((x) * 8 + 7, (x) * 8)
94 #define XGMAC_PSRQ_SHIFT(x) ((x) * 8)
95 #define XGMAC_INT_STATUS 0x000000b0
96 #define XGMAC_LPIIS BIT(5)
97 #define XGMAC_PMTIS BIT(4)
98 #define XGMAC_INT_EN 0x000000b4
99 #define XGMAC_TSIE BIT(12)
100 #define XGMAC_LPIIE BIT(5)
101 #define XGMAC_PMTIE BIT(4)
102 #define XGMAC_INT_DEFAULT_EN (XGMAC_LPIIE | XGMAC_PMTIE)
103 #define XGMAC_Qx_TX_FLOW_CTRL(x) (0x00000070 + (x) * 4)
104 #define XGMAC_PT GENMASK(31, 16)
105 #define XGMAC_PT_SHIFT 16
106 #define XGMAC_TFE BIT(1)
107 #define XGMAC_RX_FLOW_CTRL 0x00000090
108 #define XGMAC_RFE BIT(0)
109 #define XGMAC_PMT 0x000000c0
110 #define XGMAC_GLBLUCAST BIT(9)
111 #define XGMAC_RWKPKTEN BIT(2)
112 #define XGMAC_MGKPKTEN BIT(1)
113 #define XGMAC_PWRDWN BIT(0)
114 #define XGMAC_LPI_CTRL 0x000000d0
115 #define XGMAC_TXCGE BIT(21)
116 #define XGMAC_LPITXA BIT(19)
117 #define XGMAC_PLS BIT(17)
118 #define XGMAC_LPITXEN BIT(16)
119 #define XGMAC_RLPIEX BIT(3)
120 #define XGMAC_RLPIEN BIT(2)
121 #define XGMAC_TLPIEX BIT(1)
122 #define XGMAC_TLPIEN BIT(0)
123 #define XGMAC_LPI_TIMER_CTRL 0x000000d4
124 #define XGMAC_HW_FEATURE0 0x0000011c
125 #define XGMAC_HWFEAT_EDMA BIT(31)
126 #define XGMAC_HWFEAT_EDIFFC BIT(30)
127 #define XGMAC_HWFEAT_VXN BIT(29)
128 #define XGMAC_HWFEAT_SAVLANINS BIT(27)
129 #define XGMAC_HWFEAT_TSSTSSEL GENMASK(26, 25)
130 #define XGMAC_HWFEAT_ADDMACADRSEL GENMASK(22, 18)
131 #define XGMAC_HWFEAT_RXCOESEL BIT(16)
132 #define XGMAC_HWFEAT_TXCOESEL BIT(14)
133 #define XGMAC_HWFEAT_EEESEL BIT(13)
134 #define XGMAC_HWFEAT_TSSEL BIT(12)
135 #define XGMAC_HWFEAT_AVSEL BIT(11)
136 #define XGMAC_HWFEAT_RAVSEL BIT(10)
137 #define XGMAC_HWFEAT_ARPOFFSEL BIT(9)
138 #define XGMAC_HWFEAT_MMCSEL BIT(8)
139 #define XGMAC_HWFEAT_MGKSEL BIT(7)
140 #define XGMAC_HWFEAT_RWKSEL BIT(6)
141 #define XGMAC_HWFEAT_SMASEL BIT(5)
142 #define XGMAC_HWFEAT_VLHASH BIT(4)
143 #define XGMAC_HWFEAT_HDSEL BIT(3)
144 #define XGMAC_HWFEAT_GMIISEL BIT(1)
145 #define XGMAC_HW_FEATURE1 0x00000120
146 #define XGMAC_HWFEAT_L3L4FNUM GENMASK(30, 27)
147 #define XGMAC_HWFEAT_HASHTBLSZ GENMASK(25, 24)
148 #define XGMAC_HWFEAT_NUMTC GENMASK(23, 21)
149 #define XGMAC_HWFEAT_RSSEN BIT(20)
150 #define XGMAC_HWFEAT_DBGMEMA BIT(19)
151 #define XGMAC_HWFEAT_TSOEN BIT(18)
152 #define XGMAC_HWFEAT_SPHEN BIT(17)
153 #define XGMAC_HWFEAT_DCBEN BIT(16)
154 #define XGMAC_HWFEAT_ADDR64 GENMASK(15, 14)
155 #define XGMAC_HWFEAT_ADVTHWORD BIT(13)
156 #define XGMAC_HWFEAT_PTOEN BIT(12)
157 #define XGMAC_HWFEAT_OSTEN BIT(11)
158 #define XGMAC_HWFEAT_TXFIFOSIZE GENMASK(10, 6)
159 #define XGMAC_HWFEAT_PFCEN BIT(5)
160 #define XGMAC_HWFEAT_RXFIFOSIZE GENMASK(4, 0)
161 #define XGMAC_HW_FEATURE2 0x00000124
162 #define XGMAC_HWFEAT_AUXSNAPNUM GENMASK(30, 28)
163 #define XGMAC_HWFEAT_PPSOUTNUM GENMASK(26, 24)
164 #define XGMAC_HWFEAT_TXCHCNT GENMASK(21, 18)
165 #define XGMAC_HWFEAT_RXCHCNT GENMASK(15, 12)
166 #define XGMAC_HWFEAT_TXQCNT GENMASK(9, 6)
167 #define XGMAC_HWFEAT_RXQCNT GENMASK(3, 0)
168 #define XGMAC_HW_FEATURE3 0x00000128
169 #define XGMAC_HWFEAT_TBSCH GENMASK(31, 28)
170 #define XGMAC_HWFEAT_TBSSEL BIT(27)
171 #define XGMAC_HWFEAT_FPESEL BIT(26)
172 #define XGMAC_HWFEAT_SGFSEL BIT(25)
173 #define XGMAC_HWFEAT_ESTWID GENMASK(24, 23)
174 #define XGMAC_HWFEAT_ESTDEP GENMASK(22, 20)
175 #define XGMAC_HWFEAT_ESTSEL BIT(19)
176 #define XGMAC_HWFEAT_TTSFD GENMASK(18, 16)
177 #define XGMAC_HWFEAT_ASP GENMASK(15, 14)
178 #define XGMAC_HWFEAT_DVLAN BIT(13)
179 #define XGMAC_HWFEAT_FRPES GENMASK(12, 11)
180 #define XGMAC_HWFEAT_FRPPB GENMASK(10, 9)
181 #define XGMAC_HWFEAT_POUOST BIT(8)
182 #define XGMAC_HWFEAT_FRPPIPE GENMASK(7, 5)
183 #define XGMAC_HWFEAT_CBTISEL BIT(4)
184 #define XGMAC_HWFEAT_FRPSEL BIT(3)
185 #define XGMAC_HWFEAT_NRVF GENMASK(2, 0)
186 #define XGMAC_HW_FEATURE4 0x0000012c
187 #define XGMAC_HWFEAT_EASP BIT(4)
188 #define XGMAC_HWFEAT_PCSEL GENMASK(1, 0)
189 #define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150
190 #define XGMAC_MAC_FSM_CONTROL 0x00000158
191 #define XGMAC_PRTYEN BIT(1)
192 #define XGMAC_TMOUTEN BIT(0)
193 #define XGMAC_MDIO_ADDR 0x00000200
194 #define XGMAC_MDIO_DATA 0x00000204
195 #define XGMAC_MDIO_C22P 0x00000220
196 #define XGMAC_FPE_CTRL_STS 0x00000280
197 #define XGMAC_EFPE BIT(0)
198 #define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8)
199 #define XGMAC_ADDR_MAX 32
200 #define XGMAC_AE BIT(31)
201 #define XGMAC_DCS GENMASK(19, 16)
202 #define XGMAC_DCS_SHIFT 16
203 #define XGMAC_ADDRx_LOW(x) (0x00000304 + (x) * 0x8)
204 #define XGMAC_L3L4_ADDR_CTRL 0x00000c00
205 #define XGMAC_IDDR GENMASK(16, 8)
206 #define XGMAC_IDDR_SHIFT 8
207 #define XGMAC_IDDR_FNUM 4
208 #define XGMAC_TT BIT(1)
209 #define XGMAC_XB BIT(0)
210 #define XGMAC_L3L4_DATA 0x00000c04
211 #define XGMAC_L3L4_CTRL 0x0
212 #define XGMAC_L4DPIM0 BIT(21)
213 #define XGMAC_L4DPM0 BIT(20)
214 #define XGMAC_L4SPIM0 BIT(19)
215 #define XGMAC_L4SPM0 BIT(18)
216 #define XGMAC_L4PEN0 BIT(16)
217 #define XGMAC_L3HDBM0 GENMASK(15, 11)
218 #define XGMAC_L3HSBM0 GENMASK(10, 6)
219 #define XGMAC_L3DAIM0 BIT(5)
220 #define XGMAC_L3DAM0 BIT(4)
221 #define XGMAC_L3SAIM0 BIT(3)
222 #define XGMAC_L3SAM0 BIT(2)
223 #define XGMAC_L3PEN0 BIT(0)
224 #define XGMAC_L4_ADDR 0x1
225 #define XGMAC_L4DP0 GENMASK(31, 16)
226 #define XGMAC_L4DP0_SHIFT 16
227 #define XGMAC_L4SP0 GENMASK(15, 0)
228 #define XGMAC_L3_ADDR0 0x4
229 #define XGMAC_L3_ADDR1 0x5
230 #define XGMAC_L3_ADDR2 0x6
231 #define XMGAC_L3_ADDR3 0x7
232 #define XGMAC_ARP_ADDR 0x00000c10
233 #define XGMAC_RSS_CTRL 0x00000c80
234 #define XGMAC_UDP4TE BIT(3)
235 #define XGMAC_TCP4TE BIT(2)
236 #define XGMAC_IP2TE BIT(1)
237 #define XGMAC_RSSE BIT(0)
238 #define XGMAC_RSS_ADDR 0x00000c88
239 #define XGMAC_RSSIA_SHIFT 8
240 #define XGMAC_ADDRT BIT(2)
241 #define XGMAC_CT BIT(1)
242 #define XGMAC_OB BIT(0)
243 #define XGMAC_RSS_DATA 0x00000c8c
244 #define XGMAC_TIMESTAMP_STATUS 0x00000d20
245 #define XGMAC_TXTSC BIT(15)
246 #define XGMAC_TXTIMESTAMP_NSEC 0x00000d30
247 #define XGMAC_TXTSSTSLO GENMASK(30, 0)
248 #define XGMAC_TXTIMESTAMP_SEC 0x00000d34
249 #define XGMAC_PPS_CONTROL 0x00000d70
250 #define XGMAC_PPS_MAXIDX(x) ((((x) + 1) * 8) - 1)
251 #define XGMAC_PPS_MINIDX(x) ((x) * 8)
252 #define XGMAC_PPSx_MASK(x) \
253 GENMASK(XGMAC_PPS_MAXIDX(x), XGMAC_PPS_MINIDX(x))
254 #define XGMAC_TRGTMODSELx(x, val) \
255 GENMASK(XGMAC_PPS_MAXIDX(x) - 1, XGMAC_PPS_MAXIDX(x) - 2) & \
256 ((val) << (XGMAC_PPS_MAXIDX(x) - 2))
257 #define XGMAC_PPSCMDx(x, val) \
258 GENMASK(XGMAC_PPS_MINIDX(x) + 3, XGMAC_PPS_MINIDX(x)) & \
259 ((val) << XGMAC_PPS_MINIDX(x))
260 #define XGMAC_PPSCMD_START 0x2
261 #define XGMAC_PPSCMD_STOP 0x5
262 #define XGMAC_PPSENx(x) BIT(4 + (x) * 8)
263 #define XGMAC_PPSx_TARGET_TIME_SEC(x) (0x00000d80 + (x) * 0x10)
264 #define XGMAC_PPSx_TARGET_TIME_NSEC(x) (0x00000d84 + (x) * 0x10)
265 #define XGMAC_TRGTBUSY0 BIT(31)
266 #define XGMAC_PPSx_INTERVAL(x) (0x00000d88 + (x) * 0x10)
267 #define XGMAC_PPSx_WIDTH(x) (0x00000d8c + (x) * 0x10)
270 #define XGMAC_MTL_OPMODE 0x00001000
271 #define XGMAC_FRPE BIT(15)
272 #define XGMAC_ETSALG GENMASK(6, 5)
273 #define XGMAC_WRR (0x0 << 5)
274 #define XGMAC_WFQ (0x1 << 5)
275 #define XGMAC_DWRR (0x2 << 5)
276 #define XGMAC_RAA BIT(2)
277 #define XGMAC_MTL_INT_STATUS 0x00001020
278 #define XGMAC_MTL_RXQ_DMA_MAP0 0x00001030
279 #define XGMAC_MTL_RXQ_DMA_MAP1 0x00001034
280 #define XGMAC_QxMDMACH(x) GENMASK((x) * 8 + 7, (x) * 8)
281 #define XGMAC_QxMDMACH_SHIFT(x) ((x) * 8)
282 #define XGMAC_QDDMACH BIT(7)
283 #define XGMAC_TC_PRTY_MAP0 0x00001040
284 #define XGMAC_TC_PRTY_MAP1 0x00001044
285 #define XGMAC_PSTC(x) GENMASK((x) * 8 + 7, (x) * 8)
286 #define XGMAC_PSTC_SHIFT(x) ((x) * 8)
287 #define XGMAC_MTL_EST_CONTROL 0x00001050
288 #define XGMAC_PTOV GENMASK(31, 23)
289 #define XGMAC_PTOV_SHIFT 23
290 #define XGMAC_SSWL BIT(1)
291 #define XGMAC_EEST BIT(0)
292 #define XGMAC_MTL_EST_GCL_CONTROL 0x00001080
293 #define XGMAC_BTR_LOW 0x0
294 #define XGMAC_BTR_HIGH 0x1
295 #define XGMAC_CTR_LOW 0x2
296 #define XGMAC_CTR_HIGH 0x3
297 #define XGMAC_TER 0x4
298 #define XGMAC_LLR 0x5
299 #define XGMAC_ADDR_SHIFT 8
300 #define XGMAC_GCRR BIT(2)
301 #define XGMAC_SRWO BIT(0)
302 #define XGMAC_MTL_EST_GCL_DATA 0x00001084
303 #define XGMAC_MTL_RXP_CONTROL_STATUS 0x000010a0
304 #define XGMAC_RXPI BIT(31)
305 #define XGMAC_NPE GENMASK(23, 16)
306 #define XGMAC_NVE GENMASK(7, 0)
307 #define XGMAC_MTL_RXP_IACC_CTRL_ST 0x000010b0
308 #define XGMAC_STARTBUSY BIT(31)
309 #define XGMAC_WRRDN BIT(16)
310 #define XGMAC_ADDR GENMASK(9, 0)
311 #define XGMAC_MTL_RXP_IACC_DATA 0x000010b4
312 #define XGMAC_MTL_ECC_CONTROL 0x000010c0
313 #define XGMAC_MTL_SAFETY_INT_STATUS 0x000010c4
314 #define XGMAC_MEUIS BIT(1)
315 #define XGMAC_MECIS BIT(0)
316 #define XGMAC_MTL_ECC_INT_ENABLE 0x000010c8
317 #define XGMAC_RPCEIE BIT(12)
318 #define XGMAC_ECEIE BIT(8)
319 #define XGMAC_RXCEIE BIT(4)
320 #define XGMAC_TXCEIE BIT(0)
321 #define XGMAC_MTL_ECC_INT_STATUS 0x000010cc
322 #define XGMAC_MTL_DPP_CONTROL 0x000010e0
323 #define XGMAC_DPP_DISABLE BIT(0)
324 #define XGMAC_MTL_TXQ_OPMODE(x) (0x00001100 + (0x80 * (x)))
325 #define XGMAC_TQS GENMASK(25, 16)
326 #define XGMAC_TQS_SHIFT 16
327 #define XGMAC_Q2TCMAP GENMASK(10, 8)
328 #define XGMAC_Q2TCMAP_SHIFT 8
329 #define XGMAC_TTC GENMASK(6, 4)
330 #define XGMAC_TTC_SHIFT 4
331 #define XGMAC_TXQEN GENMASK(3, 2)
332 #define XGMAC_TXQEN_SHIFT 2
333 #define XGMAC_TSF BIT(1)
334 #define XGMAC_MTL_TCx_ETS_CONTROL(x) (0x00001110 + (0x80 * (x)))
335 #define XGMAC_MTL_TCx_QUANTUM_WEIGHT(x) (0x00001118 + (0x80 * (x)))
336 #define XGMAC_MTL_TCx_SENDSLOPE(x) (0x0000111c + (0x80 * (x)))
337 #define XGMAC_MTL_TCx_HICREDIT(x) (0x00001120 + (0x80 * (x)))
338 #define XGMAC_MTL_TCx_LOCREDIT(x) (0x00001124 + (0x80 * (x)))
339 #define XGMAC_CC BIT(3)
340 #define XGMAC_TSA GENMASK(1, 0)
341 #define XGMAC_SP (0x0 << 0)
342 #define XGMAC_CBS (0x1 << 0)
343 #define XGMAC_ETS (0x2 << 0)
344 #define XGMAC_MTL_RXQ_OPMODE(x) (0x00001140 + (0x80 * (x)))
345 #define XGMAC_RQS GENMASK(25, 16)
346 #define XGMAC_RQS_SHIFT 16
347 #define XGMAC_EHFC BIT(7)
348 #define XGMAC_RSF BIT(5)
349 #define XGMAC_RTC GENMASK(1, 0)
350 #define XGMAC_RTC_SHIFT 0
351 #define XGMAC_MTL_RXQ_FLOW_CONTROL(x) (0x00001150 + (0x80 * (x)))
352 #define XGMAC_RFD GENMASK(31, 17)
353 #define XGMAC_RFD_SHIFT 17
354 #define XGMAC_RFA GENMASK(15, 1)
355 #define XGMAC_RFA_SHIFT 1
356 #define XGMAC_MTL_QINTEN(x) (0x00001170 + (0x80 * (x)))
357 #define XGMAC_RXOIE BIT(16)
358 #define XGMAC_MTL_QINT_STATUS(x) (0x00001174 + (0x80 * (x)))
359 #define XGMAC_RXOVFIS BIT(16)
360 #define XGMAC_ABPSIS BIT(1)
361 #define XGMAC_TXUNFIS BIT(0)
362 #define XGMAC_MAC_REGSIZE (XGMAC_MTL_QINT_STATUS(15) / 4)
365 #define XGMAC_DMA_MODE 0x00003000
366 #define XGMAC_SWR BIT(0)
367 #define XGMAC_DMA_SYSBUS_MODE 0x00003004
368 #define XGMAC_WR_OSR_LMT GENMASK(29, 24)
369 #define XGMAC_WR_OSR_LMT_SHIFT 24
370 #define XGMAC_RD_OSR_LMT GENMASK(21, 16)
371 #define XGMAC_RD_OSR_LMT_SHIFT 16
372 #define XGMAC_EN_LPI BIT(15)
373 #define XGMAC_LPI_XIT_PKT BIT(14)
374 #define XGMAC_AAL BIT(12)
375 #define XGMAC_EAME BIT(11)
376 #define XGMAC_BLEN GENMASK(7, 1)
377 #define XGMAC_BLEN256 BIT(7)
378 #define XGMAC_BLEN128 BIT(6)
379 #define XGMAC_BLEN64 BIT(5)
380 #define XGMAC_BLEN32 BIT(4)
381 #define XGMAC_BLEN16 BIT(3)
382 #define XGMAC_BLEN8 BIT(2)
383 #define XGMAC_BLEN4 BIT(1)
384 #define XGMAC_UNDEF BIT(0)
385 #define XGMAC_TX_EDMA_CTRL 0x00003040
386 #define XGMAC_TDPS GENMASK(29, 0)
387 #define XGMAC_RX_EDMA_CTRL 0x00003044
388 #define XGMAC_RDPS GENMASK(29, 0)
389 #define XGMAC_DMA_TBS_CTRL0 0x00003054
390 #define XGMAC_DMA_TBS_CTRL1 0x00003058
391 #define XGMAC_DMA_TBS_CTRL2 0x0000305c
392 #define XGMAC_DMA_TBS_CTRL3 0x00003060
393 #define XGMAC_FTOS GENMASK(31, 8)
394 #define XGMAC_FTOV BIT(0)
395 #define XGMAC_DEF_FTOS (XGMAC_FTOS | XGMAC_FTOV)
396 #define XGMAC_DMA_SAFETY_INT_STATUS 0x00003064
397 #define XGMAC_MCSIS BIT(31)
398 #define XGMAC_MSUIS BIT(29)
399 #define XGMAC_MSCIS BIT(28)
400 #define XGMAC_DEUIS BIT(1)
401 #define XGMAC_DECIS BIT(0)
402 #define XGMAC_DMA_ECC_INT_ENABLE 0x00003068
403 #define XGMAC_DCEIE BIT(1)
404 #define XGMAC_TCEIE BIT(0)
405 #define XGMAC_DMA_ECC_INT_STATUS 0x0000306c
406 #define XGMAC_DMA_DPP_INT_STATUS 0x00003074
407 #define XGMAC_DMA_CH_CONTROL(x) (0x00003100 + (0x80 * (x)))
408 #define XGMAC_SPH BIT(24)
409 #define XGMAC_PBLx8 BIT(16)
410 #define XGMAC_DMA_CH_TX_CONTROL(x) (0x00003104 + (0x80 * (x)))
411 #define XGMAC_EDSE BIT(28)
412 #define XGMAC_TxPBL GENMASK(21, 16)
413 #define XGMAC_TxPBL_SHIFT 16
414 #define XGMAC_TSE BIT(12)
415 #define XGMAC_OSP BIT(4)
416 #define XGMAC_TXST BIT(0)
417 #define XGMAC_DMA_CH_RX_CONTROL(x) (0x00003108 + (0x80 * (x)))
418 #define XGMAC_RxPBL GENMASK(21, 16)
419 #define XGMAC_RxPBL_SHIFT 16
420 #define XGMAC_RBSZ GENMASK(14, 1)
421 #define XGMAC_RBSZ_SHIFT 1
422 #define XGMAC_RXST BIT(0)
423 #define XGMAC_DMA_CH_TxDESC_HADDR(x) (0x00003110 + (0x80 * (x)))
424 #define XGMAC_DMA_CH_TxDESC_LADDR(x) (0x00003114 + (0x80 * (x)))
425 #define XGMAC_DMA_CH_RxDESC_HADDR(x) (0x00003118 + (0x80 * (x)))
426 #define XGMAC_DMA_CH_RxDESC_LADDR(x) (0x0000311c + (0x80 * (x)))
427 #define XGMAC_DMA_CH_TxDESC_TAIL_LPTR(x) (0x00003124 + (0x80 * (x)))
428 #define XGMAC_DMA_CH_RxDESC_TAIL_LPTR(x) (0x0000312c + (0x80 * (x)))
429 #define XGMAC_DMA_CH_TxDESC_RING_LEN(x) (0x00003130 + (0x80 * (x)))
430 #define XGMAC_DMA_CH_RxDESC_RING_LEN(x) (0x00003134 + (0x80 * (x)))
431 #define XGMAC_DMA_CH_INT_EN(x) (0x00003138 + (0x80 * (x)))
432 #define XGMAC_NIE BIT(15)
433 #define XGMAC_AIE BIT(14)
434 #define XGMAC_RBUE BIT(7)
435 #define XGMAC_RIE BIT(6)
436 #define XGMAC_TBUE BIT(2)
437 #define XGMAC_TIE BIT(0)
438 #define XGMAC_DMA_INT_DEFAULT_EN (XGMAC_NIE | XGMAC_AIE | XGMAC_RBUE | \
439 XGMAC_RIE | XGMAC_TIE)
440 #define XGMAC_DMA_INT_DEFAULT_RX (XGMAC_RBUE | XGMAC_RIE)
441 #define XGMAC_DMA_INT_DEFAULT_TX (XGMAC_TIE)
442 #define XGMAC_DMA_CH_Rx_WATCHDOG(x) (0x0000313c + (0x80 * (x)))
443 #define XGMAC_RWT GENMASK(7, 0)
444 #define XGMAC_DMA_CH_STATUS(x) (0x00003160 + (0x80 * (x)))
445 #define XGMAC_NIS BIT(15)
446 #define XGMAC_AIS BIT(14)
447 #define XGMAC_FBE BIT(12)
448 #define XGMAC_RBU BIT(7)
449 #define XGMAC_RI BIT(6)
450 #define XGMAC_TBU BIT(2)
451 #define XGMAC_TPS BIT(1)
452 #define XGMAC_TI BIT(0)
453 #define XGMAC_REGSIZE ((0x0000317c + (0x80 * 15)) / 4)
455 #define XGMAC_DMA_STATUS_MSK_COMMON (XGMAC_NIS | XGMAC_AIS | XGMAC_FBE)
456 #define XGMAC_DMA_STATUS_MSK_RX (XGMAC_RBU | XGMAC_RI | \
457 XGMAC_DMA_STATUS_MSK_COMMON)
458 #define XGMAC_DMA_STATUS_MSK_TX (XGMAC_TBU | XGMAC_TPS | XGMAC_TI | \
459 XGMAC_DMA_STATUS_MSK_COMMON)
462 #define XGMAC_TDES0_LTV BIT(31)
463 #define XGMAC_TDES0_LT GENMASK(7, 0)
464 #define XGMAC_TDES1_LT GENMASK(31, 8)
465 #define XGMAC_TDES2_IVT GENMASK(31, 16)
466 #define XGMAC_TDES2_IVT_SHIFT 16
467 #define XGMAC_TDES2_IOC BIT(31)
468 #define XGMAC_TDES2_TTSE BIT(30)
469 #define XGMAC_TDES2_B2L GENMASK(29, 16)
470 #define XGMAC_TDES2_B2L_SHIFT 16
471 #define XGMAC_TDES2_VTIR GENMASK(15, 14)
472 #define XGMAC_TDES2_VTIR_SHIFT 14
473 #define XGMAC_TDES2_B1L GENMASK(13, 0)
474 #define XGMAC_TDES3_OWN BIT(31)
475 #define XGMAC_TDES3_CTXT BIT(30)
476 #define XGMAC_TDES3_FD BIT(29)
477 #define XGMAC_TDES3_LD BIT(28)
478 #define XGMAC_TDES3_CPC GENMASK(27, 26)
479 #define XGMAC_TDES3_CPC_SHIFT 26
480 #define XGMAC_TDES3_TCMSSV BIT(26)
481 #define XGMAC_TDES3_SAIC GENMASK(25, 23)
482 #define XGMAC_TDES3_SAIC_SHIFT 23
483 #define XGMAC_TDES3_TBSV BIT(24)
484 #define XGMAC_TDES3_THL GENMASK(22, 19)
485 #define XGMAC_TDES3_THL_SHIFT 19
486 #define XGMAC_TDES3_IVTIR GENMASK(19, 18)
487 #define XGMAC_TDES3_IVTIR_SHIFT 18
488 #define XGMAC_TDES3_TSE BIT(18)
489 #define XGMAC_TDES3_IVLTV BIT(17)
490 #define XGMAC_TDES3_CIC GENMASK(17, 16)
491 #define XGMAC_TDES3_CIC_SHIFT 16
492 #define XGMAC_TDES3_TPL GENMASK(17, 0)
493 #define XGMAC_TDES3_VLTV BIT(16)
494 #define XGMAC_TDES3_VT GENMASK(15, 0)
495 #define XGMAC_TDES3_FL GENMASK(14, 0)
496 #define XGMAC_RDES2_HL GENMASK(9, 0)
497 #define XGMAC_RDES3_OWN BIT(31)
498 #define XGMAC_RDES3_CTXT BIT(30)
499 #define XGMAC_RDES3_IOC BIT(30)
500 #define XGMAC_RDES3_LD BIT(28)
501 #define XGMAC_RDES3_CDA BIT(27)
502 #define XGMAC_RDES3_RSV BIT(26)
503 #define XGMAC_RDES3_L34T GENMASK(23, 20)
504 #define XGMAC_RDES3_L34T_SHIFT 20
505 #define XGMAC_L34T_IP4TCP 0x1
506 #define XGMAC_L34T_IP4UDP 0x2
507 #define XGMAC_L34T_IP6TCP 0x9
508 #define XGMAC_L34T_IP6UDP 0xA
509 #define XGMAC_RDES3_ES BIT(15)
510 #define XGMAC_RDES3_PL GENMASK(13, 0)
511 #define XGMAC_RDES3_TSD BIT(6)
512 #define XGMAC_RDES3_TSA BIT(4)
514 #endif /* __STMMAC_DWXGMAC2_H__ */
projects / platform / kernel / linux-starfive.git / blob