1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
6 * This only implements the mac core functions for this chip.
8 * Copyright (C) 2015 STMicroelectronics Ltd
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
18 #include "stmmac_pcs.h"
22 static void dwmac4_core_init(struct mac_device_info *hw,
23 struct net_device *dev)
25 struct stmmac_priv *priv = netdev_priv(dev);
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
29 value |= GMAC_CORE_INIT;
32 value |= GMAC_CONFIG_TE;
34 value &= hw->link.speed_mask;
37 value |= hw->link.speed1000;
40 value |= hw->link.speed100;
43 value |= hw->link.speed10;
48 writel(value, ioaddr + GMAC_CONFIG);
50 /* Enable GMAC interrupts */
51 value = GMAC_INT_DEFAULT_ENABLE;
54 value |= GMAC_PCS_IRQ_DEFAULT;
56 /* Enable FPE interrupt */
57 if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
58 value |= GMAC_INT_FPE_EN;
60 writel(value, ioaddr + GMAC_INT_EN);
62 if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
63 init_waitqueue_head(&priv->tstamp_busy_wait);
66 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
69 void __iomem *ioaddr = hw->pcsr;
70 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
72 value &= GMAC_RX_QUEUE_CLEAR(queue);
73 if (mode == MTL_QUEUE_AVB)
74 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
75 else if (mode == MTL_QUEUE_DCB)
76 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
78 writel(value, ioaddr + GMAC_RXQ_CTRL0);
81 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
84 void __iomem *ioaddr = hw->pcsr;
88 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
92 value = readl(ioaddr + base_register);
94 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
95 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
96 GMAC_RXQCTRL_PSRQX_MASK(queue);
97 writel(value, ioaddr + base_register);
100 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
103 void __iomem *ioaddr = hw->pcsr;
107 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
111 value = readl(ioaddr + base_register);
113 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
114 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
115 GMAC_TXQCTRL_PSTQX_MASK(queue);
117 writel(value, ioaddr + base_register);
120 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
121 u8 packet, u32 queue)
123 void __iomem *ioaddr = hw->pcsr;
126 static const struct stmmac_rx_routing route_possibilities[] = {
127 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
128 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
129 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
130 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
131 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
134 value = readl(ioaddr + GMAC_RXQ_CTRL1);
136 /* routing configuration */
137 value &= ~route_possibilities[packet - 1].reg_mask;
138 value |= (queue << route_possibilities[packet-1].reg_shift) &
139 route_possibilities[packet - 1].reg_mask;
141 /* some packets require extra ops */
142 if (packet == PACKET_AVCPQ) {
143 value &= ~GMAC_RXQCTRL_TACPQE;
144 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
145 } else if (packet == PACKET_MCBCQ) {
146 value &= ~GMAC_RXQCTRL_MCBCQEN;
147 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
150 writel(value, ioaddr + GMAC_RXQ_CTRL1);
153 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
156 void __iomem *ioaddr = hw->pcsr;
157 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
159 value &= ~MTL_OPERATION_RAA;
161 case MTL_RX_ALGORITHM_SP:
162 value |= MTL_OPERATION_RAA_SP;
164 case MTL_RX_ALGORITHM_WSP:
165 value |= MTL_OPERATION_RAA_WSP;
171 writel(value, ioaddr + MTL_OPERATION_MODE);
174 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
177 void __iomem *ioaddr = hw->pcsr;
178 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
180 value &= ~MTL_OPERATION_SCHALG_MASK;
182 case MTL_TX_ALGORITHM_WRR:
183 value |= MTL_OPERATION_SCHALG_WRR;
185 case MTL_TX_ALGORITHM_WFQ:
186 value |= MTL_OPERATION_SCHALG_WFQ;
188 case MTL_TX_ALGORITHM_DWRR:
189 value |= MTL_OPERATION_SCHALG_DWRR;
191 case MTL_TX_ALGORITHM_SP:
192 value |= MTL_OPERATION_SCHALG_SP;
198 writel(value, ioaddr + MTL_OPERATION_MODE);
201 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
202 u32 weight, u32 queue)
204 void __iomem *ioaddr = hw->pcsr;
205 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
207 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
208 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
209 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
212 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
214 void __iomem *ioaddr = hw->pcsr;
218 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
220 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
222 if (queue == 0 || queue == 4) {
223 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
224 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
225 } else if (queue > 4) {
226 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
227 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
229 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
230 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
234 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
236 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
239 static void dwmac4_config_cbs(struct mac_device_info *hw,
240 u32 send_slope, u32 idle_slope,
241 u32 high_credit, u32 low_credit, u32 queue)
243 void __iomem *ioaddr = hw->pcsr;
246 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
247 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
248 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
249 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
250 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
252 /* enable AV algorithm */
253 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
254 value |= MTL_ETS_CTRL_AVALG;
255 value |= MTL_ETS_CTRL_CC;
256 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
258 /* configure send slope */
259 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
260 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
261 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
262 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
264 /* configure idle slope (same register as tx weight) */
265 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
267 /* configure high credit */
268 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
269 value &= ~MTL_HIGH_CRED_HC_MASK;
270 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
271 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
273 /* configure high credit */
274 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
275 value &= ~MTL_HIGH_CRED_LC_MASK;
276 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
277 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
280 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
282 void __iomem *ioaddr = hw->pcsr;
285 for (i = 0; i < GMAC_REG_NUM; i++)
286 reg_space[i] = readl(ioaddr + i * 4);
289 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
291 void __iomem *ioaddr = hw->pcsr;
292 u32 value = readl(ioaddr + GMAC_CONFIG);
295 value |= GMAC_CONFIG_IPC;
297 value &= ~GMAC_CONFIG_IPC;
299 writel(value, ioaddr + GMAC_CONFIG);
301 value = readl(ioaddr + GMAC_CONFIG);
303 return !!(value & GMAC_CONFIG_IPC);
306 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
308 void __iomem *ioaddr = hw->pcsr;
309 unsigned int pmt = 0;
312 if (mode & WAKE_MAGIC) {
313 pr_debug("GMAC: WOL Magic frame\n");
314 pmt |= power_down | magic_pkt_en;
316 if (mode & WAKE_UCAST) {
317 pr_debug("GMAC: WOL on global unicast\n");
318 pmt |= power_down | global_unicast | wake_up_frame_en;
322 /* The receiver must be enabled for WOL before powering down */
323 config = readl(ioaddr + GMAC_CONFIG);
324 config |= GMAC_CONFIG_RE;
325 writel(config, ioaddr + GMAC_CONFIG);
327 writel(pmt, ioaddr + GMAC_PMT);
330 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
331 const unsigned char *addr, unsigned int reg_n)
333 void __iomem *ioaddr = hw->pcsr;
335 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
336 GMAC_ADDR_LOW(reg_n));
339 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
340 unsigned char *addr, unsigned int reg_n)
342 void __iomem *ioaddr = hw->pcsr;
344 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
345 GMAC_ADDR_LOW(reg_n));
348 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
349 bool en_tx_lpi_clockgating)
351 void __iomem *ioaddr = hw->pcsr;
354 /* Enable the link status receive on RGMII, SGMII ore SMII
355 * receive path and instruct the transmit to enter in LPI
358 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
359 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
361 if (en_tx_lpi_clockgating)
362 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
364 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
367 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
369 void __iomem *ioaddr = hw->pcsr;
372 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
373 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
374 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
377 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
379 void __iomem *ioaddr = hw->pcsr;
382 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
385 value |= GMAC4_LPI_CTRL_STATUS_PLS;
387 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
389 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
392 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
394 void __iomem *ioaddr = hw->pcsr;
395 int value = et & STMMAC_ET_MAX;
398 /* Program LPI entry timer value into register */
399 writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
401 /* Enable/disable LPI entry timer */
402 regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
403 regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
406 regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
408 regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
410 writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
413 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
415 void __iomem *ioaddr = hw->pcsr;
416 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
418 /* Program the timers in the LPI timer control register:
419 * LS: minimum time (ms) for which the link
420 * status from PHY should be ok before transmitting
422 * TW: minimum time (us) for which the core waits
423 * after it has stopped transmitting the LPI pattern.
425 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
428 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
430 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
433 val = readl(ioaddr + GMAC_VLAN_TAG);
434 val &= ~GMAC_VLAN_TAG_VID;
435 val |= GMAC_VLAN_TAG_ETV | vid;
437 writel(val, ioaddr + GMAC_VLAN_TAG);
440 static int dwmac4_write_vlan_filter(struct net_device *dev,
441 struct mac_device_info *hw,
444 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
448 if (index >= hw->num_vlan)
451 writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
453 val = readl(ioaddr + GMAC_VLAN_TAG);
454 val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
455 GMAC_VLAN_TAG_CTRL_CT |
456 GMAC_VLAN_TAG_CTRL_OB);
457 val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
459 writel(val, ioaddr + GMAC_VLAN_TAG);
461 for (i = 0; i < timeout; i++) {
462 val = readl(ioaddr + GMAC_VLAN_TAG);
463 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
468 netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
473 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
474 struct mac_device_info *hw,
475 __be16 proto, u16 vid)
486 "Adding VLAN in promisc mode not supported\n");
490 /* Single Rx VLAN Filter */
491 if (hw->num_vlan == 1) {
492 /* For single VLAN filter, VID 0 means VLAN promiscuous */
494 netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
498 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
499 netdev_err(dev, "Only single VLAN ID supported\n");
503 hw->vlan_filter[0] = vid;
504 dwmac4_write_single_vlan(dev, vid);
509 /* Extended Rx VLAN Filter Enable */
510 val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
512 for (i = 0; i < hw->num_vlan; i++) {
513 if (hw->vlan_filter[i] == val)
515 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
520 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
525 ret = dwmac4_write_vlan_filter(dev, hw, index, val);
528 hw->vlan_filter[index] = val;
533 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
534 struct mac_device_info *hw,
535 __be16 proto, u16 vid)
541 "Deleting VLAN in promisc mode not supported\n");
545 /* Single Rx VLAN Filter */
546 if (hw->num_vlan == 1) {
547 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
548 hw->vlan_filter[0] = 0;
549 dwmac4_write_single_vlan(dev, 0);
554 /* Extended Rx VLAN Filter Enable */
555 for (i = 0; i < hw->num_vlan; i++) {
556 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
557 ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
560 hw->vlan_filter[i] = 0;
569 static void dwmac4_vlan_promisc_enable(struct net_device *dev,
570 struct mac_device_info *hw)
572 void __iomem *ioaddr = hw->pcsr;
578 /* Single Rx VLAN Filter */
579 if (hw->num_vlan == 1) {
580 dwmac4_write_single_vlan(dev, 0);
584 /* Extended Rx VLAN Filter Enable */
585 for (i = 0; i < hw->num_vlan; i++) {
586 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
587 val = hw->vlan_filter[i] & ~GMAC_VLAN_TAG_DATA_VEN;
588 dwmac4_write_vlan_filter(dev, hw, i, val);
592 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
593 if (hash & GMAC_VLAN_VLHT) {
594 value = readl(ioaddr + GMAC_VLAN_TAG);
595 if (value & GMAC_VLAN_VTHM) {
596 value &= ~GMAC_VLAN_VTHM;
597 writel(value, ioaddr + GMAC_VLAN_TAG);
602 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
603 struct mac_device_info *hw)
605 void __iomem *ioaddr = hw->pcsr;
611 /* Single Rx VLAN Filter */
612 if (hw->num_vlan == 1) {
613 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
617 /* Extended Rx VLAN Filter Enable */
618 for (i = 0; i < hw->num_vlan; i++) {
619 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
620 val = hw->vlan_filter[i];
621 dwmac4_write_vlan_filter(dev, hw, i, val);
625 hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
626 if (hash & GMAC_VLAN_VLHT) {
627 value = readl(ioaddr + GMAC_VLAN_TAG);
628 value |= GMAC_VLAN_VTHM;
629 writel(value, ioaddr + GMAC_VLAN_TAG);
633 static void dwmac4_set_filter(struct mac_device_info *hw,
634 struct net_device *dev)
636 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
637 int numhashregs = (hw->multicast_filter_bins >> 5);
638 int mcbitslog2 = hw->mcast_bits_log2;
643 memset(mc_filter, 0, sizeof(mc_filter));
645 value = readl(ioaddr + GMAC_PACKET_FILTER);
646 value &= ~GMAC_PACKET_FILTER_HMC;
647 value &= ~GMAC_PACKET_FILTER_HPF;
648 value &= ~GMAC_PACKET_FILTER_PCF;
649 value &= ~GMAC_PACKET_FILTER_PM;
650 value &= ~GMAC_PACKET_FILTER_PR;
651 value &= ~GMAC_PACKET_FILTER_RA;
652 if (dev->flags & IFF_PROMISC) {
653 /* VLAN Tag Filter Fail Packets Queuing */
654 if (hw->vlan_fail_q_en) {
655 value = readl(ioaddr + GMAC_RXQ_CTRL4);
656 value &= ~GMAC_RXQCTRL_VFFQ_MASK;
657 value |= GMAC_RXQCTRL_VFFQE |
658 (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
659 writel(value, ioaddr + GMAC_RXQ_CTRL4);
660 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
662 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
665 } else if ((dev->flags & IFF_ALLMULTI) ||
666 (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
668 value |= GMAC_PACKET_FILTER_PM;
669 /* Set all the bits of the HASH tab */
670 memset(mc_filter, 0xff, sizeof(mc_filter));
671 } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
672 struct netdev_hw_addr *ha;
674 /* Hash filter for multicast */
675 value |= GMAC_PACKET_FILTER_HMC;
677 netdev_for_each_mc_addr(ha, dev) {
678 /* The upper n bits of the calculated CRC are used to
679 * index the contents of the hash table. The number of
680 * bits used depends on the hardware configuration
681 * selected at core configuration time.
683 u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
684 ETH_ALEN)) >> (32 - mcbitslog2);
685 /* The most significant bit determines the register to
686 * use (H/L) while the other 5 bits determine the bit
687 * within the register.
689 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
693 for (i = 0; i < numhashregs; i++)
694 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
696 value |= GMAC_PACKET_FILTER_HPF;
698 /* Handle multiple unicast addresses */
699 if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
700 /* Switch to promiscuous mode if more than 128 addrs
703 value |= GMAC_PACKET_FILTER_PR;
705 struct netdev_hw_addr *ha;
708 netdev_for_each_uc_addr(ha, dev) {
709 dwmac4_set_umac_addr(hw, ha->addr, reg);
713 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
714 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
715 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
721 if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
722 value |= GMAC_PACKET_FILTER_VTFE;
724 writel(value, ioaddr + GMAC_PACKET_FILTER);
726 if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en) {
729 dwmac4_vlan_promisc_enable(dev, hw);
734 dwmac4_restore_hw_vlan_rx_fltr(dev, hw);
739 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
740 unsigned int fc, unsigned int pause_time,
743 void __iomem *ioaddr = hw->pcsr;
744 unsigned int flow = 0;
747 pr_debug("GMAC Flow-Control:\n");
749 pr_debug("\tReceive Flow-Control ON\n");
750 flow |= GMAC_RX_FLOW_CTRL_RFE;
752 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
755 pr_debug("\tTransmit Flow-Control ON\n");
758 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
760 for (queue = 0; queue < tx_cnt; queue++) {
761 flow = GMAC_TX_FLOW_CTRL_TFE;
765 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
767 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
770 for (queue = 0; queue < tx_cnt; queue++)
771 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
775 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
778 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
781 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
783 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
786 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
788 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
791 /* RGMII or SMII interface */
792 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
796 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
799 /* Check the link status */
800 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
805 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
806 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
807 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
808 x->pcs_speed = SPEED_1000;
809 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
810 x->pcs_speed = SPEED_100;
812 x->pcs_speed = SPEED_10;
814 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
816 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
817 x->pcs_duplex ? "Full" : "Half");
820 pr_info("Link is Down\n");
824 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
826 void __iomem *ioaddr = hw->pcsr;
827 u32 mtl_int_qx_status;
830 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
832 /* Check MTL Interrupt */
833 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
834 /* read Queue x Interrupt status */
835 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
837 if (status & MTL_RX_OVERFLOW_INT) {
838 /* clear Interrupt */
839 writel(status | MTL_RX_OVERFLOW_INT,
840 ioaddr + MTL_CHAN_INT_CTRL(chan));
841 ret = CORE_IRQ_MTL_RX_OVERFLOW;
848 static int dwmac4_irq_status(struct mac_device_info *hw,
849 struct stmmac_extra_stats *x)
851 void __iomem *ioaddr = hw->pcsr;
852 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
853 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
856 /* Discard disabled bits */
857 intr_status &= intr_enable;
859 /* Not used events (e.g. MMC interrupts) are not handled. */
860 if ((intr_status & mmc_tx_irq))
862 if (unlikely(intr_status & mmc_rx_irq))
864 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
865 x->mmc_rx_csum_offload_irq_n++;
866 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
867 if (unlikely(intr_status & pmt_irq)) {
868 readl(ioaddr + GMAC_PMT);
869 x->irq_receive_pmt_irq_n++;
872 /* MAC tx/rx EEE LPI entry/exit interrupts */
873 if (intr_status & lpi_irq) {
874 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
875 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
877 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
878 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
879 x->irq_tx_path_in_lpi_mode_n++;
881 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
882 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
883 x->irq_tx_path_exit_lpi_mode_n++;
885 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
886 x->irq_rx_path_in_lpi_mode_n++;
887 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
888 x->irq_rx_path_exit_lpi_mode_n++;
891 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
892 if (intr_status & PCS_RGSMIIIS_IRQ)
893 dwmac4_phystatus(ioaddr, x);
898 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
899 u32 rx_queues, u32 tx_queues)
904 for (queue = 0; queue < tx_queues; queue++) {
905 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
907 if (value & MTL_DEBUG_TXSTSFSTS)
908 x->mtl_tx_status_fifo_full++;
909 if (value & MTL_DEBUG_TXFSTS)
910 x->mtl_tx_fifo_not_empty++;
911 if (value & MTL_DEBUG_TWCSTS)
913 if (value & MTL_DEBUG_TRCSTS_MASK) {
914 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
915 >> MTL_DEBUG_TRCSTS_SHIFT;
916 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
917 x->mtl_tx_fifo_read_ctrl_write++;
918 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
919 x->mtl_tx_fifo_read_ctrl_wait++;
920 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
921 x->mtl_tx_fifo_read_ctrl_read++;
923 x->mtl_tx_fifo_read_ctrl_idle++;
925 if (value & MTL_DEBUG_TXPAUSED)
926 x->mac_tx_in_pause++;
929 for (queue = 0; queue < rx_queues; queue++) {
930 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
932 if (value & MTL_DEBUG_RXFSTS_MASK) {
933 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
934 >> MTL_DEBUG_RRCSTS_SHIFT;
936 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
937 x->mtl_rx_fifo_fill_level_full++;
938 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
939 x->mtl_rx_fifo_fill_above_thresh++;
940 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
941 x->mtl_rx_fifo_fill_below_thresh++;
943 x->mtl_rx_fifo_fill_level_empty++;
945 if (value & MTL_DEBUG_RRCSTS_MASK) {
946 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
947 MTL_DEBUG_RRCSTS_SHIFT;
949 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
950 x->mtl_rx_fifo_read_ctrl_flush++;
951 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
952 x->mtl_rx_fifo_read_ctrl_read_data++;
953 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
954 x->mtl_rx_fifo_read_ctrl_status++;
956 x->mtl_rx_fifo_read_ctrl_idle++;
958 if (value & MTL_DEBUG_RWCSTS)
959 x->mtl_rx_fifo_ctrl_active++;
963 value = readl(ioaddr + GMAC_DEBUG);
965 if (value & GMAC_DEBUG_TFCSTS_MASK) {
966 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
967 >> GMAC_DEBUG_TFCSTS_SHIFT;
969 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
970 x->mac_tx_frame_ctrl_xfer++;
971 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
972 x->mac_tx_frame_ctrl_pause++;
973 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
974 x->mac_tx_frame_ctrl_wait++;
976 x->mac_tx_frame_ctrl_idle++;
978 if (value & GMAC_DEBUG_TPESTS)
979 x->mac_gmii_tx_proto_engine++;
980 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
981 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
982 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
983 if (value & GMAC_DEBUG_RPESTS)
984 x->mac_gmii_rx_proto_engine++;
987 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
989 u32 value = readl(ioaddr + GMAC_CONFIG);
992 value |= GMAC_CONFIG_LM;
994 value &= ~GMAC_CONFIG_LM;
996 writel(value, ioaddr + GMAC_CONFIG);
999 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
1000 __le16 perfect_match, bool is_double)
1002 void __iomem *ioaddr = hw->pcsr;
1005 writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
1007 value = readl(ioaddr + GMAC_VLAN_TAG);
1010 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
1012 value |= GMAC_VLAN_EDVLP;
1013 value |= GMAC_VLAN_ESVL;
1014 value |= GMAC_VLAN_DOVLTC;
1017 writel(value, ioaddr + GMAC_VLAN_TAG);
1018 } else if (perfect_match) {
1019 u32 value = GMAC_VLAN_ETV;
1022 value |= GMAC_VLAN_EDVLP;
1023 value |= GMAC_VLAN_ESVL;
1024 value |= GMAC_VLAN_DOVLTC;
1027 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
1029 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
1030 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
1031 value &= ~GMAC_VLAN_DOVLTC;
1032 value &= ~GMAC_VLAN_VID;
1034 writel(value, ioaddr + GMAC_VLAN_TAG);
1038 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
1040 u32 value = readl(ioaddr + GMAC_CONFIG);
1042 value &= ~GMAC_CONFIG_SARC;
1043 value |= val << GMAC_CONFIG_SARC_SHIFT;
1045 writel(value, ioaddr + GMAC_CONFIG);
1048 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1050 void __iomem *ioaddr = hw->pcsr;
1053 value = readl(ioaddr + GMAC_VLAN_INCL);
1054 value |= GMAC_VLAN_VLTI;
1055 value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1056 value &= ~GMAC_VLAN_VLC;
1057 value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1058 writel(value, ioaddr + GMAC_VLAN_INCL);
1061 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1064 void __iomem *ioaddr = hw->pcsr;
1067 writel(addr, ioaddr + GMAC_ARP_ADDR);
1069 value = readl(ioaddr + GMAC_CONFIG);
1071 value |= GMAC_CONFIG_ARPEN;
1073 value &= ~GMAC_CONFIG_ARPEN;
1074 writel(value, ioaddr + GMAC_CONFIG);
1077 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1078 bool en, bool ipv6, bool sa, bool inv,
1081 void __iomem *ioaddr = hw->pcsr;
1084 value = readl(ioaddr + GMAC_PACKET_FILTER);
1085 value |= GMAC_PACKET_FILTER_IPFE;
1086 writel(value, ioaddr + GMAC_PACKET_FILTER);
1088 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1090 /* For IPv6 not both SA/DA filters can be active */
1092 value |= GMAC_L3PEN0;
1093 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1094 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1096 value |= GMAC_L3SAM0;
1098 value |= GMAC_L3SAIM0;
1100 value |= GMAC_L3DAM0;
1102 value |= GMAC_L3DAIM0;
1105 value &= ~GMAC_L3PEN0;
1107 value |= GMAC_L3SAM0;
1109 value |= GMAC_L3SAIM0;
1111 value |= GMAC_L3DAM0;
1113 value |= GMAC_L3DAIM0;
1117 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1120 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1122 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1126 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1131 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1132 bool en, bool udp, bool sa, bool inv,
1135 void __iomem *ioaddr = hw->pcsr;
1138 value = readl(ioaddr + GMAC_PACKET_FILTER);
1139 value |= GMAC_PACKET_FILTER_IPFE;
1140 writel(value, ioaddr + GMAC_PACKET_FILTER);
1142 value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1144 value |= GMAC_L4PEN0;
1146 value &= ~GMAC_L4PEN0;
1149 value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1150 value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1152 value |= GMAC_L4SPM0;
1154 value |= GMAC_L4SPIM0;
1156 value |= GMAC_L4DPM0;
1158 value |= GMAC_L4DPIM0;
1161 writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1164 value = match & GMAC_L4SP0;
1166 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1169 writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1172 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1177 const struct stmmac_ops dwmac4_ops = {
1178 .core_init = dwmac4_core_init,
1179 .set_mac = stmmac_set_mac,
1180 .rx_ipc = dwmac4_rx_ipc_enable,
1181 .rx_queue_enable = dwmac4_rx_queue_enable,
1182 .rx_queue_prio = dwmac4_rx_queue_priority,
1183 .tx_queue_prio = dwmac4_tx_queue_priority,
1184 .rx_queue_routing = dwmac4_rx_queue_routing,
1185 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1186 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1187 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1188 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1189 .config_cbs = dwmac4_config_cbs,
1190 .dump_regs = dwmac4_dump_regs,
1191 .host_irq_status = dwmac4_irq_status,
1192 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1193 .flow_ctrl = dwmac4_flow_ctrl,
1195 .set_umac_addr = dwmac4_set_umac_addr,
1196 .get_umac_addr = dwmac4_get_umac_addr,
1197 .set_eee_mode = dwmac4_set_eee_mode,
1198 .reset_eee_mode = dwmac4_reset_eee_mode,
1199 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1200 .set_eee_timer = dwmac4_set_eee_timer,
1201 .set_eee_pls = dwmac4_set_eee_pls,
1202 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1203 .pcs_rane = dwmac4_rane,
1204 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1205 .debug = dwmac4_debug,
1206 .set_filter = dwmac4_set_filter,
1207 .set_mac_loopback = dwmac4_set_mac_loopback,
1208 .update_vlan_hash = dwmac4_update_vlan_hash,
1209 .sarc_configure = dwmac4_sarc_configure,
1210 .enable_vlan = dwmac4_enable_vlan,
1211 .set_arp_offload = dwmac4_set_arp_offload,
1212 .config_l3_filter = dwmac4_config_l3_filter,
1213 .config_l4_filter = dwmac4_config_l4_filter,
1214 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1215 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1216 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1219 const struct stmmac_ops dwmac410_ops = {
1220 .core_init = dwmac4_core_init,
1221 .set_mac = stmmac_dwmac4_set_mac,
1222 .rx_ipc = dwmac4_rx_ipc_enable,
1223 .rx_queue_enable = dwmac4_rx_queue_enable,
1224 .rx_queue_prio = dwmac4_rx_queue_priority,
1225 .tx_queue_prio = dwmac4_tx_queue_priority,
1226 .rx_queue_routing = dwmac4_rx_queue_routing,
1227 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1228 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1229 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1230 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1231 .config_cbs = dwmac4_config_cbs,
1232 .dump_regs = dwmac4_dump_regs,
1233 .host_irq_status = dwmac4_irq_status,
1234 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1235 .flow_ctrl = dwmac4_flow_ctrl,
1237 .set_umac_addr = dwmac4_set_umac_addr,
1238 .get_umac_addr = dwmac4_get_umac_addr,
1239 .set_eee_mode = dwmac4_set_eee_mode,
1240 .reset_eee_mode = dwmac4_reset_eee_mode,
1241 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1242 .set_eee_timer = dwmac4_set_eee_timer,
1243 .set_eee_pls = dwmac4_set_eee_pls,
1244 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1245 .pcs_rane = dwmac4_rane,
1246 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1247 .debug = dwmac4_debug,
1248 .set_filter = dwmac4_set_filter,
1249 .flex_pps_config = dwmac5_flex_pps_config,
1250 .set_mac_loopback = dwmac4_set_mac_loopback,
1251 .update_vlan_hash = dwmac4_update_vlan_hash,
1252 .sarc_configure = dwmac4_sarc_configure,
1253 .enable_vlan = dwmac4_enable_vlan,
1254 .set_arp_offload = dwmac4_set_arp_offload,
1255 .config_l3_filter = dwmac4_config_l3_filter,
1256 .config_l4_filter = dwmac4_config_l4_filter,
1257 .est_configure = dwmac5_est_configure,
1258 .est_irq_status = dwmac5_est_irq_status,
1259 .fpe_configure = dwmac5_fpe_configure,
1260 .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1261 .fpe_irq_status = dwmac5_fpe_irq_status,
1262 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1263 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1264 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1267 const struct stmmac_ops dwmac510_ops = {
1268 .core_init = dwmac4_core_init,
1269 .set_mac = stmmac_dwmac4_set_mac,
1270 .rx_ipc = dwmac4_rx_ipc_enable,
1271 .rx_queue_enable = dwmac4_rx_queue_enable,
1272 .rx_queue_prio = dwmac4_rx_queue_priority,
1273 .tx_queue_prio = dwmac4_tx_queue_priority,
1274 .rx_queue_routing = dwmac4_rx_queue_routing,
1275 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1276 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1277 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1278 .map_mtl_to_dma = dwmac4_map_mtl_dma,
1279 .config_cbs = dwmac4_config_cbs,
1280 .dump_regs = dwmac4_dump_regs,
1281 .host_irq_status = dwmac4_irq_status,
1282 .host_mtl_irq_status = dwmac4_irq_mtl_status,
1283 .flow_ctrl = dwmac4_flow_ctrl,
1285 .set_umac_addr = dwmac4_set_umac_addr,
1286 .get_umac_addr = dwmac4_get_umac_addr,
1287 .set_eee_mode = dwmac4_set_eee_mode,
1288 .reset_eee_mode = dwmac4_reset_eee_mode,
1289 .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1290 .set_eee_timer = dwmac4_set_eee_timer,
1291 .set_eee_pls = dwmac4_set_eee_pls,
1292 .pcs_ctrl_ane = dwmac4_ctrl_ane,
1293 .pcs_rane = dwmac4_rane,
1294 .pcs_get_adv_lp = dwmac4_get_adv_lp,
1295 .debug = dwmac4_debug,
1296 .set_filter = dwmac4_set_filter,
1297 .safety_feat_config = dwmac5_safety_feat_config,
1298 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1299 .safety_feat_dump = dwmac5_safety_feat_dump,
1300 .rxp_config = dwmac5_rxp_config,
1301 .flex_pps_config = dwmac5_flex_pps_config,
1302 .set_mac_loopback = dwmac4_set_mac_loopback,
1303 .update_vlan_hash = dwmac4_update_vlan_hash,
1304 .sarc_configure = dwmac4_sarc_configure,
1305 .enable_vlan = dwmac4_enable_vlan,
1306 .set_arp_offload = dwmac4_set_arp_offload,
1307 .config_l3_filter = dwmac4_config_l3_filter,
1308 .config_l4_filter = dwmac4_config_l4_filter,
1309 .est_configure = dwmac5_est_configure,
1310 .est_irq_status = dwmac5_est_irq_status,
1311 .fpe_configure = dwmac5_fpe_configure,
1312 .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1313 .fpe_irq_status = dwmac5_fpe_irq_status,
1314 .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1315 .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1316 .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1319 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1323 val = readl(ioaddr + GMAC_HW_FEATURE3);
1324 switch (val & GMAC_HW_FEAT_NRVF) {
1350 int dwmac4_setup(struct stmmac_priv *priv)
1352 struct mac_device_info *mac = priv->hw;
1354 dev_info(priv->device, "\tDWMAC4/5\n");
1356 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1357 mac->pcsr = priv->ioaddr;
1358 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1359 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1360 mac->mcast_bits_log2 = 0;
1362 if (mac->multicast_filter_bins)
1363 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1365 mac->link.duplex = GMAC_CONFIG_DM;
1366 mac->link.speed10 = GMAC_CONFIG_PS;
1367 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1368 mac->link.speed1000 = 0;
1369 mac->link.speed2500 = GMAC_CONFIG_FES;
1370 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1371 mac->mii.addr = GMAC_MDIO_ADDR;
1372 mac->mii.data = GMAC_MDIO_DATA;
1373 mac->mii.addr_shift = 21;
1374 mac->mii.addr_mask = GENMASK(25, 21);
1375 mac->mii.reg_shift = 16;
1376 mac->mii.reg_mask = GENMASK(20, 16);
1377 mac->mii.clk_csr_shift = 8;
1378 mac->mii.clk_csr_mask = GENMASK(11, 8);
1379 mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);