drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  * DWC Ether MAC version 4.00  has been used for developing this code.
   5  *
   6  * This only implements the mac core functions for this chip.
   7  *
   8  * Copyright (C) 2015  STMicroelectronics Ltd
   9  *
  10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  11  */
  12
  13 #include <linux/crc32.h>
  14 #include <linux/slab.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/io.h>
  17 #include "stmmac.h"
  18 #include "stmmac_pcs.h"
  19 #include "dwmac4.h"
  20 #include "dwmac5.h"
  21
  22 static void dwmac4_core_init(struct mac_device_info *hw,
  23                              struct net_device *dev)
  24 {
  25         struct stmmac_priv *priv = netdev_priv(dev);
  26         void __iomem *ioaddr = hw->pcsr;
  27         u32 value = readl(ioaddr + GMAC_CONFIG);
  28         u32 clk_rate;
  29
  30         value |= GMAC_CORE_INIT;
  31
  32         if (hw->ps) {
  33                 value |= GMAC_CONFIG_TE;
  34
  35                 value &= hw->link.speed_mask;
  36                 switch (hw->ps) {
  37                 case SPEED_1000:
  38                         value |= hw->link.speed1000;
  39                         break;
  40                 case SPEED_100:
  41                         value |= hw->link.speed100;
  42                         break;
  43                 case SPEED_10:
  44                         value |= hw->link.speed10;
  45                         break;
  46                 }
  47         }
  48
  49         writel(value, ioaddr + GMAC_CONFIG);
  50
  51         /* Configure LPI 1us counter to number of CSR clock ticks in 1us - 1 */
  52         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
  53         writel((clk_rate / 1000000) - 1, ioaddr + GMAC4_MAC_ONEUS_TIC_COUNTER);
  54
  55         /* Enable GMAC interrupts */
  56         value = GMAC_INT_DEFAULT_ENABLE;
  57
  58         if (hw->pcs)
  59                 value |= GMAC_PCS_IRQ_DEFAULT;
  60
  61         /* Enable FPE interrupt */
  62         if ((GMAC_HW_FEAT_FPESEL & readl(ioaddr + GMAC_HW_FEATURE3)) >> 26)
  63                 value |= GMAC_INT_FPE_EN;
  64
  65         writel(value, ioaddr + GMAC_INT_EN);
  66
  67         if (GMAC_INT_DEFAULT_ENABLE & GMAC_INT_TSIE)
  68                 init_waitqueue_head(&priv->tstamp_busy_wait);
  69 }
  70
  71 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  72                                    u8 mode, u32 queue)
  73 {
  74         void __iomem *ioaddr = hw->pcsr;
  75         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  76
  77         value &= GMAC_RX_QUEUE_CLEAR(queue);
  78         if (mode == MTL_QUEUE_AVB)
  79                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  80         else if (mode == MTL_QUEUE_DCB)
  81                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  82
  83         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  84 }
  85
  86 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  87                                      u32 prio, u32 queue)
  88 {
  89         void __iomem *ioaddr = hw->pcsr;
  90         u32 base_register;
  91         u32 value;
  92
  93         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  94         if (queue >= 4)
  95                 queue -= 4;
  96
  97         value = readl(ioaddr + base_register);
  98
  99         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
 100         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
 101                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
 102         writel(value, ioaddr + base_register);
 103 }
 104
 105 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
 106                                      u32 prio, u32 queue)
 107 {
 108         void __iomem *ioaddr = hw->pcsr;
 109         u32 base_register;
 110         u32 value;
 111
 112         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 113         if (queue >= 4)
 114                 queue -= 4;
 115
 116         value = readl(ioaddr + base_register);
 117
 118         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 119         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 120                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 121
 122         writel(value, ioaddr + base_register);
 123 }
 124
 125 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
 126                                     u8 packet, u32 queue)
 127 {
 128         void __iomem *ioaddr = hw->pcsr;
 129         u32 value;
 130
 131         static const struct stmmac_rx_routing route_possibilities[] = {
 132                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 133                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 134                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 135                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 136                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 137         };
 138
 139         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 140
 141         /* routing configuration */
 142         value &= ~route_possibilities[packet - 1].reg_mask;
 143         value |= (queue << route_possibilities[packet-1].reg_shift) &
 144                  route_possibilities[packet - 1].reg_mask;
 145
 146         /* some packets require extra ops */
 147         if (packet == PACKET_AVCPQ) {
 148                 value &= ~GMAC_RXQCTRL_TACPQE;
 149                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 150         } else if (packet == PACKET_MCBCQ) {
 151                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 152                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 153         }
 154
 155         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 156 }
 157
 158 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 159                                           u32 rx_alg)
 160 {
 161         void __iomem *ioaddr = hw->pcsr;
 162         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 163
 164         value &= ~MTL_OPERATION_RAA;
 165         switch (rx_alg) {
 166         case MTL_RX_ALGORITHM_SP:
 167                 value |= MTL_OPERATION_RAA_SP;
 168                 break;
 169         case MTL_RX_ALGORITHM_WSP:
 170                 value |= MTL_OPERATION_RAA_WSP;
 171                 break;
 172         default:
 173                 break;
 174         }
 175
 176         writel(value, ioaddr + MTL_OPERATION_MODE);
 177 }
 178
 179 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 180                                           u32 tx_alg)
 181 {
 182         void __iomem *ioaddr = hw->pcsr;
 183         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 184
 185         value &= ~MTL_OPERATION_SCHALG_MASK;
 186         switch (tx_alg) {
 187         case MTL_TX_ALGORITHM_WRR:
 188                 value |= MTL_OPERATION_SCHALG_WRR;
 189                 break;
 190         case MTL_TX_ALGORITHM_WFQ:
 191                 value |= MTL_OPERATION_SCHALG_WFQ;
 192                 break;
 193         case MTL_TX_ALGORITHM_DWRR:
 194                 value |= MTL_OPERATION_SCHALG_DWRR;
 195                 break;
 196         case MTL_TX_ALGORITHM_SP:
 197                 value |= MTL_OPERATION_SCHALG_SP;
 198                 break;
 199         default:
 200                 break;
 201         }
 202
 203         writel(value, ioaddr + MTL_OPERATION_MODE);
 204 }
 205
 206 static void dwmac4_set_mtl_tx_queue_weight(struct stmmac_priv *priv,
 207                                            struct mac_device_info *hw,
 208                                            u32 weight, u32 queue)
 209 {
 210         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 211         void __iomem *ioaddr = hw->pcsr;
 212         u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs,
 213                                                              queue));
 214
 215         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 216         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 217         writel(value, ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, queue));
 218 }
 219
 220 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 221 {
 222         void __iomem *ioaddr = hw->pcsr;
 223         u32 value;
 224
 225         if (queue < 4) {
 226                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 227                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 228                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 229                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 230         } else {
 231                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 232                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue - 4);
 233                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue - 4);
 234                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 235         }
 236 }
 237
 238 static void dwmac4_config_cbs(struct stmmac_priv *priv,
 239                               struct mac_device_info *hw,
 240                               u32 send_slope, u32 idle_slope,
 241                               u32 high_credit, u32 low_credit, u32 queue)
 242 {
 243         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 244         void __iomem *ioaddr = hw->pcsr;
 245         u32 value;
 246
 247         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 248         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 249         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 250         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 251         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 252
 253         /* enable AV algorithm */
 254         value = readl(ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
 255         value |= MTL_ETS_CTRL_AVALG;
 256         value |= MTL_ETS_CTRL_CC;
 257         writel(value, ioaddr + mtl_etsx_ctrl_base_addr(dwmac4_addrs, queue));
 258
 259         /* configure send slope */
 260         value = readl(ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
 261                                                             queue));
 262         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 263         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 264         writel(value, ioaddr + mtl_send_slp_credx_base_addr(dwmac4_addrs,
 265                                                             queue));
 266
 267         /* configure idle slope (same register as tx weight) */
 268         dwmac4_set_mtl_tx_queue_weight(priv, hw, idle_slope, queue);
 269
 270         /* configure high credit */
 271         value = readl(ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
 272         value &= ~MTL_HIGH_CRED_HC_MASK;
 273         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 274         writel(value, ioaddr + mtl_high_credx_base_addr(dwmac4_addrs, queue));
 275
 276         /* configure high credit */
 277         value = readl(ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
 278         value &= ~MTL_HIGH_CRED_LC_MASK;
 279         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 280         writel(value, ioaddr + mtl_low_credx_base_addr(dwmac4_addrs, queue));
 281 }
 282
 283 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 284 {
 285         void __iomem *ioaddr = hw->pcsr;
 286         int i;
 287
 288         for (i = 0; i < GMAC_REG_NUM; i++)
 289                 reg_space[i] = readl(ioaddr + i * 4);
 290 }
 291
 292 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 293 {
 294         void __iomem *ioaddr = hw->pcsr;
 295         u32 value = readl(ioaddr + GMAC_CONFIG);
 296
 297         if (hw->rx_csum)
 298                 value |= GMAC_CONFIG_IPC;
 299         else
 300                 value &= ~GMAC_CONFIG_IPC;
 301
 302         writel(value, ioaddr + GMAC_CONFIG);
 303
 304         value = readl(ioaddr + GMAC_CONFIG);
 305
 306         return !!(value & GMAC_CONFIG_IPC);
 307 }
 308
 309 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 310 {
 311         void __iomem *ioaddr = hw->pcsr;
 312         unsigned int pmt = 0;
 313         u32 config;
 314
 315         if (mode & WAKE_MAGIC) {
 316                 pr_debug("GMAC: WOL Magic frame\n");
 317                 pmt |= power_down | magic_pkt_en;
 318         }
 319         if (mode & WAKE_UCAST) {
 320                 pr_debug("GMAC: WOL on global unicast\n");
 321                 pmt |= power_down | global_unicast | wake_up_frame_en;
 322         }
 323
 324         if (pmt) {
 325                 /* The receiver must be enabled for WOL before powering down */
 326                 config = readl(ioaddr + GMAC_CONFIG);
 327                 config |= GMAC_CONFIG_RE;
 328                 writel(config, ioaddr + GMAC_CONFIG);
 329         }
 330         writel(pmt, ioaddr + GMAC_PMT);
 331 }
 332
 333 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 334                                  const unsigned char *addr, unsigned int reg_n)
 335 {
 336         void __iomem *ioaddr = hw->pcsr;
 337
 338         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 339                                    GMAC_ADDR_LOW(reg_n));
 340 }
 341
 342 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 343                                  unsigned char *addr, unsigned int reg_n)
 344 {
 345         void __iomem *ioaddr = hw->pcsr;
 346
 347         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 348                                    GMAC_ADDR_LOW(reg_n));
 349 }
 350
 351 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 352                                 bool en_tx_lpi_clockgating)
 353 {
 354         void __iomem *ioaddr = hw->pcsr;
 355         u32 value;
 356
 357         /* Enable the link status receive on RGMII, SGMII ore SMII
 358          * receive path and instruct the transmit to enter in LPI
 359          * state.
 360          */
 361         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 362         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 363
 364         if (en_tx_lpi_clockgating)
 365                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 366
 367         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 368 }
 369
 370 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 371 {
 372         void __iomem *ioaddr = hw->pcsr;
 373         u32 value;
 374
 375         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 376         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 377         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 378 }
 379
 380 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 381 {
 382         void __iomem *ioaddr = hw->pcsr;
 383         u32 value;
 384
 385         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 386
 387         if (link)
 388                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 389         else
 390                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 391
 392         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 393 }
 394
 395 static void dwmac4_set_eee_lpi_entry_timer(struct mac_device_info *hw, int et)
 396 {
 397         void __iomem *ioaddr = hw->pcsr;
 398         int value = et & STMMAC_ET_MAX;
 399         int regval;
 400
 401         /* Program LPI entry timer value into register */
 402         writel(value, ioaddr + GMAC4_LPI_ENTRY_TIMER);
 403
 404         /* Enable/disable LPI entry timer */
 405         regval = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 406         regval |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 407
 408         if (et)
 409                 regval |= GMAC4_LPI_CTRL_STATUS_LPIATE;
 410         else
 411                 regval &= ~GMAC4_LPI_CTRL_STATUS_LPIATE;
 412
 413         writel(regval, ioaddr + GMAC4_LPI_CTRL_STATUS);
 414 }
 415
 416 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 417 {
 418         void __iomem *ioaddr = hw->pcsr;
 419         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 420
 421         /* Program the timers in the LPI timer control register:
 422          * LS: minimum time (ms) for which the link
 423          *  status from PHY should be ok before transmitting
 424          *  the LPI pattern.
 425          * TW: minimum time (us) for which the core waits
 426          *  after it has stopped transmitting the LPI pattern.
 427          */
 428         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 429 }
 430
 431 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
 432 {
 433         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 434         u32 val;
 435
 436         val = readl(ioaddr + GMAC_VLAN_TAG);
 437         val &= ~GMAC_VLAN_TAG_VID;
 438         val |= GMAC_VLAN_TAG_ETV | vid;
 439
 440         writel(val, ioaddr + GMAC_VLAN_TAG);
 441 }
 442
 443 static int dwmac4_write_vlan_filter(struct net_device *dev,
 444                                     struct mac_device_info *hw,
 445                                     u8 index, u32 data)
 446 {
 447         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 448         int i, timeout = 10;
 449         u32 val;
 450
 451         if (index >= hw->num_vlan)
 452                 return -EINVAL;
 453
 454         writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
 455
 456         val = readl(ioaddr + GMAC_VLAN_TAG);
 457         val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
 458                 GMAC_VLAN_TAG_CTRL_CT |
 459                 GMAC_VLAN_TAG_CTRL_OB);
 460         val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
 461
 462         writel(val, ioaddr + GMAC_VLAN_TAG);
 463
 464         for (i = 0; i < timeout; i++) {
 465                 val = readl(ioaddr + GMAC_VLAN_TAG);
 466                 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
 467                         return 0;
 468                 udelay(1);
 469         }
 470
 471         netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
 472
 473         return -EBUSY;
 474 }
 475
 476 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
 477                                       struct mac_device_info *hw,
 478                                       __be16 proto, u16 vid)
 479 {
 480         int index = -1;
 481         u32 val = 0;
 482         int i, ret;
 483
 484         if (vid > 4095)
 485                 return -EINVAL;
 486
 487         /* Single Rx VLAN Filter */
 488         if (hw->num_vlan == 1) {
 489                 /* For single VLAN filter, VID 0 means VLAN promiscuous */
 490                 if (vid == 0) {
 491                         netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
 492                         return -EPERM;
 493                 }
 494
 495                 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
 496                         netdev_err(dev, "Only single VLAN ID supported\n");
 497                         return -EPERM;
 498                 }
 499
 500                 hw->vlan_filter[0] = vid;
 501                 dwmac4_write_single_vlan(dev, vid);
 502
 503                 return 0;
 504         }
 505
 506         /* Extended Rx VLAN Filter Enable */
 507         val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
 508
 509         for (i = 0; i < hw->num_vlan; i++) {
 510                 if (hw->vlan_filter[i] == val)
 511                         return 0;
 512                 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
 513                         index = i;
 514         }
 515
 516         if (index == -1) {
 517                 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
 518                            hw->num_vlan);
 519                 return -EPERM;
 520         }
 521
 522         ret = dwmac4_write_vlan_filter(dev, hw, index, val);
 523
 524         if (!ret)
 525                 hw->vlan_filter[index] = val;
 526
 527         return ret;
 528 }
 529
 530 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
 531                                       struct mac_device_info *hw,
 532                                       __be16 proto, u16 vid)
 533 {
 534         int i, ret = 0;
 535
 536         /* Single Rx VLAN Filter */
 537         if (hw->num_vlan == 1) {
 538                 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
 539                         hw->vlan_filter[0] = 0;
 540                         dwmac4_write_single_vlan(dev, 0);
 541                 }
 542                 return 0;
 543         }
 544
 545         /* Extended Rx VLAN Filter Enable */
 546         for (i = 0; i < hw->num_vlan; i++) {
 547                 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
 548                         ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
 549
 550                         if (!ret)
 551                                 hw->vlan_filter[i] = 0;
 552                         else
 553                                 return ret;
 554                 }
 555         }
 556
 557         return ret;
 558 }
 559
 560 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
 561                                            struct mac_device_info *hw)
 562 {
 563         void __iomem *ioaddr = hw->pcsr;
 564         u32 value;
 565         u32 hash;
 566         u32 val;
 567         int i;
 568
 569         /* Single Rx VLAN Filter */
 570         if (hw->num_vlan == 1) {
 571                 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
 572                 return;
 573         }
 574
 575         /* Extended Rx VLAN Filter Enable */
 576         for (i = 0; i < hw->num_vlan; i++) {
 577                 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
 578                         val = hw->vlan_filter[i];
 579                         dwmac4_write_vlan_filter(dev, hw, i, val);
 580                 }
 581         }
 582
 583         hash = readl(ioaddr + GMAC_VLAN_HASH_TABLE);
 584         if (hash & GMAC_VLAN_VLHT) {
 585                 value = readl(ioaddr + GMAC_VLAN_TAG);
 586                 value |= GMAC_VLAN_VTHM;
 587                 writel(value, ioaddr + GMAC_VLAN_TAG);
 588         }
 589 }
 590
 591 static void dwmac4_set_filter(struct mac_device_info *hw,
 592                               struct net_device *dev)
 593 {
 594         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 595         int numhashregs = (hw->multicast_filter_bins >> 5);
 596         int mcbitslog2 = hw->mcast_bits_log2;
 597         unsigned int value;
 598         u32 mc_filter[8];
 599         int i;
 600
 601         memset(mc_filter, 0, sizeof(mc_filter));
 602
 603         value = readl(ioaddr + GMAC_PACKET_FILTER);
 604         value &= ~GMAC_PACKET_FILTER_HMC;
 605         value &= ~GMAC_PACKET_FILTER_HPF;
 606         value &= ~GMAC_PACKET_FILTER_PCF;
 607         value &= ~GMAC_PACKET_FILTER_PM;
 608         value &= ~GMAC_PACKET_FILTER_PR;
 609         value &= ~GMAC_PACKET_FILTER_RA;
 610         if (dev->flags & IFF_PROMISC) {
 611                 /* VLAN Tag Filter Fail Packets Queuing */
 612                 if (hw->vlan_fail_q_en) {
 613                         value = readl(ioaddr + GMAC_RXQ_CTRL4);
 614                         value &= ~GMAC_RXQCTRL_VFFQ_MASK;
 615                         value |= GMAC_RXQCTRL_VFFQE |
 616                                  (hw->vlan_fail_q << GMAC_RXQCTRL_VFFQ_SHIFT);
 617                         writel(value, ioaddr + GMAC_RXQ_CTRL4);
 618                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_RA;
 619                 } else {
 620                         value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
 621                 }
 622
 623         } else if ((dev->flags & IFF_ALLMULTI) ||
 624                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 625                 /* Pass all multi */
 626                 value |= GMAC_PACKET_FILTER_PM;
 627                 /* Set all the bits of the HASH tab */
 628                 memset(mc_filter, 0xff, sizeof(mc_filter));
 629         } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
 630                 struct netdev_hw_addr *ha;
 631
 632                 /* Hash filter for multicast */
 633                 value |= GMAC_PACKET_FILTER_HMC;
 634
 635                 netdev_for_each_mc_addr(ha, dev) {
 636                         /* The upper n bits of the calculated CRC are used to
 637                          * index the contents of the hash table. The number of
 638                          * bits used depends on the hardware configuration
 639                          * selected at core configuration time.
 640                          */
 641                         u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 642                                         ETH_ALEN)) >> (32 - mcbitslog2);
 643                         /* The most significant bit determines the register to
 644                          * use (H/L) while the other 5 bits determine the bit
 645                          * within the register.
 646                          */
 647                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
 648                 }
 649         }
 650
 651         for (i = 0; i < numhashregs; i++)
 652                 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
 653
 654         value |= GMAC_PACKET_FILTER_HPF;
 655
 656         /* Handle multiple unicast addresses */
 657         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 658                 /* Switch to promiscuous mode if more than 128 addrs
 659                  * are required
 660                  */
 661                 value |= GMAC_PACKET_FILTER_PR;
 662         } else {
 663                 struct netdev_hw_addr *ha;
 664                 int reg = 1;
 665
 666                 netdev_for_each_uc_addr(ha, dev) {
 667                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 668                         reg++;
 669                 }
 670
 671                 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
 672                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 673                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 674                         reg++;
 675                 }
 676         }
 677
 678         /* VLAN filtering */
 679         if (dev->flags & IFF_PROMISC && !hw->vlan_fail_q_en)
 680                 value &= ~GMAC_PACKET_FILTER_VTFE;
 681         else if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
 682                 value |= GMAC_PACKET_FILTER_VTFE;
 683
 684         writel(value, ioaddr + GMAC_PACKET_FILTER);
 685 }
 686
 687 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 688                              unsigned int fc, unsigned int pause_time,
 689                              u32 tx_cnt)
 690 {
 691         void __iomem *ioaddr = hw->pcsr;
 692         unsigned int flow = 0;
 693         u32 queue = 0;
 694
 695         pr_debug("GMAC Flow-Control:\n");
 696         if (fc & FLOW_RX) {
 697                 pr_debug("\tReceive Flow-Control ON\n");
 698                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 699         } else {
 700                 pr_debug("\tReceive Flow-Control OFF\n");
 701         }
 702         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 703
 704         if (fc & FLOW_TX) {
 705                 pr_debug("\tTransmit Flow-Control ON\n");
 706
 707                 if (duplex)
 708                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 709
 710                 for (queue = 0; queue < tx_cnt; queue++) {
 711                         flow = GMAC_TX_FLOW_CTRL_TFE;
 712
 713                         if (duplex)
 714                                 flow |=
 715                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 716
 717                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 718                 }
 719         } else {
 720                 for (queue = 0; queue < tx_cnt; queue++)
 721                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 722         }
 723 }
 724
 725 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 726                             bool loopback)
 727 {
 728         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 729 }
 730
 731 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 732 {
 733         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 734 }
 735
 736 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 737 {
 738         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 739 }
 740
 741 /* RGMII or SMII interface */
 742 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 743 {
 744         u32 status;
 745
 746         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 747         x->irq_rgmii_n++;
 748
 749         /* Check the link status */
 750         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 751                 int speed_value;
 752
 753                 x->pcs_link = 1;
 754
 755                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 756                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 757                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 758                         x->pcs_speed = SPEED_1000;
 759                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 760                         x->pcs_speed = SPEED_100;
 761                 else
 762                         x->pcs_speed = SPEED_10;
 763
 764                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 765
 766                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 767                         x->pcs_duplex ? "Full" : "Half");
 768         } else {
 769                 x->pcs_link = 0;
 770                 pr_info("Link is Down\n");
 771         }
 772 }
 773
 774 static int dwmac4_irq_mtl_status(struct stmmac_priv *priv,
 775                                  struct mac_device_info *hw, u32 chan)
 776 {
 777         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 778         void __iomem *ioaddr = hw->pcsr;
 779         u32 mtl_int_qx_status;
 780         int ret = 0;
 781
 782         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 783
 784         /* Check MTL Interrupt */
 785         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 786                 /* read Queue x Interrupt status */
 787                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs,
 788                                                               chan));
 789
 790                 if (status & MTL_RX_OVERFLOW_INT) {
 791                         /*  clear Interrupt */
 792                         writel(status | MTL_RX_OVERFLOW_INT,
 793                                ioaddr + MTL_CHAN_INT_CTRL(dwmac4_addrs, chan));
 794                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 795                 }
 796         }
 797
 798         return ret;
 799 }
 800
 801 static int dwmac4_irq_status(struct mac_device_info *hw,
 802                              struct stmmac_extra_stats *x)
 803 {
 804         void __iomem *ioaddr = hw->pcsr;
 805         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 806         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 807         int ret = 0;
 808
 809         /* Discard disabled bits */
 810         intr_status &= intr_enable;
 811
 812         /* Not used events (e.g. MMC interrupts) are not handled. */
 813         if ((intr_status & mmc_tx_irq))
 814                 x->mmc_tx_irq_n++;
 815         if (unlikely(intr_status & mmc_rx_irq))
 816                 x->mmc_rx_irq_n++;
 817         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 818                 x->mmc_rx_csum_offload_irq_n++;
 819         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 820         if (unlikely(intr_status & pmt_irq)) {
 821                 readl(ioaddr + GMAC_PMT);
 822                 x->irq_receive_pmt_irq_n++;
 823         }
 824
 825         /* MAC tx/rx EEE LPI entry/exit interrupts */
 826         if (intr_status & lpi_irq) {
 827                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 828                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 829
 830                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 831                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 832                         x->irq_tx_path_in_lpi_mode_n++;
 833                 }
 834                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 835                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 836                         x->irq_tx_path_exit_lpi_mode_n++;
 837                 }
 838                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 839                         x->irq_rx_path_in_lpi_mode_n++;
 840                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 841                         x->irq_rx_path_exit_lpi_mode_n++;
 842         }
 843
 844         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 845         if (intr_status & PCS_RGSMIIIS_IRQ)
 846                 dwmac4_phystatus(ioaddr, x);
 847
 848         return ret;
 849 }
 850
 851 static void dwmac4_debug(struct stmmac_priv *priv, void __iomem *ioaddr,
 852                          struct stmmac_extra_stats *x,
 853                          u32 rx_queues, u32 tx_queues)
 854 {
 855         const struct dwmac4_addrs *dwmac4_addrs = priv->plat->dwmac4_addrs;
 856         u32 value;
 857         u32 queue;
 858
 859         for (queue = 0; queue < tx_queues; queue++) {
 860                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(dwmac4_addrs, queue));
 861
 862                 if (value & MTL_DEBUG_TXSTSFSTS)
 863                         x->mtl_tx_status_fifo_full++;
 864                 if (value & MTL_DEBUG_TXFSTS)
 865                         x->mtl_tx_fifo_not_empty++;
 866                 if (value & MTL_DEBUG_TWCSTS)
 867                         x->mmtl_fifo_ctrl++;
 868                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 869                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 870                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 871                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 872                                 x->mtl_tx_fifo_read_ctrl_write++;
 873                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 874                                 x->mtl_tx_fifo_read_ctrl_wait++;
 875                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 876                                 x->mtl_tx_fifo_read_ctrl_read++;
 877                         else
 878                                 x->mtl_tx_fifo_read_ctrl_idle++;
 879                 }
 880                 if (value & MTL_DEBUG_TXPAUSED)
 881                         x->mac_tx_in_pause++;
 882         }
 883
 884         for (queue = 0; queue < rx_queues; queue++) {
 885                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(dwmac4_addrs, queue));
 886
 887                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 888                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 889                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 890
 891                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 892                                 x->mtl_rx_fifo_fill_level_full++;
 893                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 894                                 x->mtl_rx_fifo_fill_above_thresh++;
 895                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 896                                 x->mtl_rx_fifo_fill_below_thresh++;
 897                         else
 898                                 x->mtl_rx_fifo_fill_level_empty++;
 899                 }
 900                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 901                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 902                                      MTL_DEBUG_RRCSTS_SHIFT;
 903
 904                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 905                                 x->mtl_rx_fifo_read_ctrl_flush++;
 906                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 907                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 908                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 909                                 x->mtl_rx_fifo_read_ctrl_status++;
 910                         else
 911                                 x->mtl_rx_fifo_read_ctrl_idle++;
 912                 }
 913                 if (value & MTL_DEBUG_RWCSTS)
 914                         x->mtl_rx_fifo_ctrl_active++;
 915         }
 916
 917         /* GMAC debug */
 918         value = readl(ioaddr + GMAC_DEBUG);
 919
 920         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 921                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 922                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 923
 924                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 925                         x->mac_tx_frame_ctrl_xfer++;
 926                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 927                         x->mac_tx_frame_ctrl_pause++;
 928                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 929                         x->mac_tx_frame_ctrl_wait++;
 930                 else
 931                         x->mac_tx_frame_ctrl_idle++;
 932         }
 933         if (value & GMAC_DEBUG_TPESTS)
 934                 x->mac_gmii_tx_proto_engine++;
 935         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 936                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 937                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 938         if (value & GMAC_DEBUG_RPESTS)
 939                 x->mac_gmii_rx_proto_engine++;
 940 }
 941
 942 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
 943 {
 944         u32 value = readl(ioaddr + GMAC_CONFIG);
 945
 946         if (enable)
 947                 value |= GMAC_CONFIG_LM;
 948         else
 949                 value &= ~GMAC_CONFIG_LM;
 950
 951         writel(value, ioaddr + GMAC_CONFIG);
 952 }
 953
 954 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
 955                                     __le16 perfect_match, bool is_double)
 956 {
 957         void __iomem *ioaddr = hw->pcsr;
 958         u32 value;
 959
 960         writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
 961
 962         value = readl(ioaddr + GMAC_VLAN_TAG);
 963
 964         if (hash) {
 965                 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
 966                 if (is_double) {
 967                         value |= GMAC_VLAN_EDVLP;
 968                         value |= GMAC_VLAN_ESVL;
 969                         value |= GMAC_VLAN_DOVLTC;
 970                 }
 971
 972                 writel(value, ioaddr + GMAC_VLAN_TAG);
 973         } else if (perfect_match) {
 974                 u32 value = GMAC_VLAN_ETV;
 975
 976                 if (is_double) {
 977                         value |= GMAC_VLAN_EDVLP;
 978                         value |= GMAC_VLAN_ESVL;
 979                         value |= GMAC_VLAN_DOVLTC;
 980                 }
 981
 982                 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
 983         } else {
 984                 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
 985                 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
 986                 value &= ~GMAC_VLAN_DOVLTC;
 987                 value &= ~GMAC_VLAN_VID;
 988
 989                 writel(value, ioaddr + GMAC_VLAN_TAG);
 990         }
 991 }
 992
 993 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
 994 {
 995         u32 value = readl(ioaddr + GMAC_CONFIG);
 996
 997         value &= ~GMAC_CONFIG_SARC;
 998         value |= val << GMAC_CONFIG_SARC_SHIFT;
 999
1000         writel(value, ioaddr + GMAC_CONFIG);
1001 }
1002
1003 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
1004 {
1005         void __iomem *ioaddr = hw->pcsr;
1006         u32 value;
1007
1008         value = readl(ioaddr + GMAC_VLAN_INCL);
1009         value |= GMAC_VLAN_VLTI;
1010         value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
1011         value &= ~GMAC_VLAN_VLC;
1012         value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
1013         writel(value, ioaddr + GMAC_VLAN_INCL);
1014 }
1015
1016 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
1017                                    u32 addr)
1018 {
1019         void __iomem *ioaddr = hw->pcsr;
1020         u32 value;
1021
1022         writel(addr, ioaddr + GMAC_ARP_ADDR);
1023
1024         value = readl(ioaddr + GMAC_CONFIG);
1025         if (en)
1026                 value |= GMAC_CONFIG_ARPEN;
1027         else
1028                 value &= ~GMAC_CONFIG_ARPEN;
1029         writel(value, ioaddr + GMAC_CONFIG);
1030 }
1031
1032 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
1033                                    bool en, bool ipv6, bool sa, bool inv,
1034                                    u32 match)
1035 {
1036         void __iomem *ioaddr = hw->pcsr;
1037         u32 value;
1038
1039         value = readl(ioaddr + GMAC_PACKET_FILTER);
1040         value |= GMAC_PACKET_FILTER_IPFE;
1041         writel(value, ioaddr + GMAC_PACKET_FILTER);
1042
1043         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1044
1045         /* For IPv6 not both SA/DA filters can be active */
1046         if (ipv6) {
1047                 value |= GMAC_L3PEN0;
1048                 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
1049                 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
1050                 if (sa) {
1051                         value |= GMAC_L3SAM0;
1052                         if (inv)
1053                                 value |= GMAC_L3SAIM0;
1054                 } else {
1055                         value |= GMAC_L3DAM0;
1056                         if (inv)
1057                                 value |= GMAC_L3DAIM0;
1058                 }
1059         } else {
1060                 value &= ~GMAC_L3PEN0;
1061                 if (sa) {
1062                         value |= GMAC_L3SAM0;
1063                         if (inv)
1064                                 value |= GMAC_L3SAIM0;
1065                 } else {
1066                         value |= GMAC_L3DAM0;
1067                         if (inv)
1068                                 value |= GMAC_L3DAIM0;
1069                 }
1070         }
1071
1072         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1073
1074         if (sa) {
1075                 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1076         } else {
1077                 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1078         }
1079
1080         if (!en)
1081                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1082
1083         return 0;
1084 }
1085
1086 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1087                                    bool en, bool udp, bool sa, bool inv,
1088                                    u32 match)
1089 {
1090         void __iomem *ioaddr = hw->pcsr;
1091         u32 value;
1092
1093         value = readl(ioaddr + GMAC_PACKET_FILTER);
1094         value |= GMAC_PACKET_FILTER_IPFE;
1095         writel(value, ioaddr + GMAC_PACKET_FILTER);
1096
1097         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1098         if (udp) {
1099                 value |= GMAC_L4PEN0;
1100         } else {
1101                 value &= ~GMAC_L4PEN0;
1102         }
1103
1104         value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1105         value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1106         if (sa) {
1107                 value |= GMAC_L4SPM0;
1108                 if (inv)
1109                         value |= GMAC_L4SPIM0;
1110         } else {
1111                 value |= GMAC_L4DPM0;
1112                 if (inv)
1113                         value |= GMAC_L4DPIM0;
1114         }
1115
1116         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1117
1118         if (sa) {
1119                 value = match & GMAC_L4SP0;
1120         } else {
1121                 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1122         }
1123
1124         writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1125
1126         if (!en)
1127                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1128
1129         return 0;
1130 }
1131
1132 const struct stmmac_ops dwmac4_ops = {
1133         .core_init = dwmac4_core_init,
1134         .set_mac = stmmac_set_mac,
1135         .rx_ipc = dwmac4_rx_ipc_enable,
1136         .rx_queue_enable = dwmac4_rx_queue_enable,
1137         .rx_queue_prio = dwmac4_rx_queue_priority,
1138         .tx_queue_prio = dwmac4_tx_queue_priority,
1139         .rx_queue_routing = dwmac4_rx_queue_routing,
1140         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1141         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1142         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1143         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1144         .config_cbs = dwmac4_config_cbs,
1145         .dump_regs = dwmac4_dump_regs,
1146         .host_irq_status = dwmac4_irq_status,
1147         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1148         .flow_ctrl = dwmac4_flow_ctrl,
1149         .pmt = dwmac4_pmt,
1150         .set_umac_addr = dwmac4_set_umac_addr,
1151         .get_umac_addr = dwmac4_get_umac_addr,
1152         .set_eee_mode = dwmac4_set_eee_mode,
1153         .reset_eee_mode = dwmac4_reset_eee_mode,
1154         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1155         .set_eee_timer = dwmac4_set_eee_timer,
1156         .set_eee_pls = dwmac4_set_eee_pls,
1157         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1158         .pcs_rane = dwmac4_rane,
1159         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1160         .debug = dwmac4_debug,
1161         .set_filter = dwmac4_set_filter,
1162         .set_mac_loopback = dwmac4_set_mac_loopback,
1163         .update_vlan_hash = dwmac4_update_vlan_hash,
1164         .sarc_configure = dwmac4_sarc_configure,
1165         .enable_vlan = dwmac4_enable_vlan,
1166         .set_arp_offload = dwmac4_set_arp_offload,
1167         .config_l3_filter = dwmac4_config_l3_filter,
1168         .config_l4_filter = dwmac4_config_l4_filter,
1169         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1170         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1171         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1172 };
1173
1174 const struct stmmac_ops dwmac410_ops = {
1175         .core_init = dwmac4_core_init,
1176         .set_mac = stmmac_dwmac4_set_mac,
1177         .rx_ipc = dwmac4_rx_ipc_enable,
1178         .rx_queue_enable = dwmac4_rx_queue_enable,
1179         .rx_queue_prio = dwmac4_rx_queue_priority,
1180         .tx_queue_prio = dwmac4_tx_queue_priority,
1181         .rx_queue_routing = dwmac4_rx_queue_routing,
1182         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1183         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1184         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1185         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1186         .config_cbs = dwmac4_config_cbs,
1187         .dump_regs = dwmac4_dump_regs,
1188         .host_irq_status = dwmac4_irq_status,
1189         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1190         .flow_ctrl = dwmac4_flow_ctrl,
1191         .pmt = dwmac4_pmt,
1192         .set_umac_addr = dwmac4_set_umac_addr,
1193         .get_umac_addr = dwmac4_get_umac_addr,
1194         .set_eee_mode = dwmac4_set_eee_mode,
1195         .reset_eee_mode = dwmac4_reset_eee_mode,
1196         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1197         .set_eee_timer = dwmac4_set_eee_timer,
1198         .set_eee_pls = dwmac4_set_eee_pls,
1199         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1200         .pcs_rane = dwmac4_rane,
1201         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1202         .debug = dwmac4_debug,
1203         .set_filter = dwmac4_set_filter,
1204         .flex_pps_config = dwmac5_flex_pps_config,
1205         .set_mac_loopback = dwmac4_set_mac_loopback,
1206         .update_vlan_hash = dwmac4_update_vlan_hash,
1207         .sarc_configure = dwmac4_sarc_configure,
1208         .enable_vlan = dwmac4_enable_vlan,
1209         .set_arp_offload = dwmac4_set_arp_offload,
1210         .config_l3_filter = dwmac4_config_l3_filter,
1211         .config_l4_filter = dwmac4_config_l4_filter,
1212         .est_configure = dwmac5_est_configure,
1213         .est_irq_status = dwmac5_est_irq_status,
1214         .fpe_configure = dwmac5_fpe_configure,
1215         .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1216         .fpe_irq_status = dwmac5_fpe_irq_status,
1217         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1218         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1219         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1220 };
1221
1222 const struct stmmac_ops dwmac510_ops = {
1223         .core_init = dwmac4_core_init,
1224         .set_mac = stmmac_dwmac4_set_mac,
1225         .rx_ipc = dwmac4_rx_ipc_enable,
1226         .rx_queue_enable = dwmac4_rx_queue_enable,
1227         .rx_queue_prio = dwmac4_rx_queue_priority,
1228         .tx_queue_prio = dwmac4_tx_queue_priority,
1229         .rx_queue_routing = dwmac4_rx_queue_routing,
1230         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1231         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1232         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1233         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1234         .config_cbs = dwmac4_config_cbs,
1235         .dump_regs = dwmac4_dump_regs,
1236         .host_irq_status = dwmac4_irq_status,
1237         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1238         .flow_ctrl = dwmac4_flow_ctrl,
1239         .pmt = dwmac4_pmt,
1240         .set_umac_addr = dwmac4_set_umac_addr,
1241         .get_umac_addr = dwmac4_get_umac_addr,
1242         .set_eee_mode = dwmac4_set_eee_mode,
1243         .reset_eee_mode = dwmac4_reset_eee_mode,
1244         .set_eee_lpi_entry_timer = dwmac4_set_eee_lpi_entry_timer,
1245         .set_eee_timer = dwmac4_set_eee_timer,
1246         .set_eee_pls = dwmac4_set_eee_pls,
1247         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1248         .pcs_rane = dwmac4_rane,
1249         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1250         .debug = dwmac4_debug,
1251         .set_filter = dwmac4_set_filter,
1252         .safety_feat_config = dwmac5_safety_feat_config,
1253         .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1254         .safety_feat_dump = dwmac5_safety_feat_dump,
1255         .rxp_config = dwmac5_rxp_config,
1256         .flex_pps_config = dwmac5_flex_pps_config,
1257         .set_mac_loopback = dwmac4_set_mac_loopback,
1258         .update_vlan_hash = dwmac4_update_vlan_hash,
1259         .sarc_configure = dwmac4_sarc_configure,
1260         .enable_vlan = dwmac4_enable_vlan,
1261         .set_arp_offload = dwmac4_set_arp_offload,
1262         .config_l3_filter = dwmac4_config_l3_filter,
1263         .config_l4_filter = dwmac4_config_l4_filter,
1264         .est_configure = dwmac5_est_configure,
1265         .est_irq_status = dwmac5_est_irq_status,
1266         .fpe_configure = dwmac5_fpe_configure,
1267         .fpe_send_mpacket = dwmac5_fpe_send_mpacket,
1268         .fpe_irq_status = dwmac5_fpe_irq_status,
1269         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1270         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1271         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1272 };
1273
1274 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1275 {
1276         u32 val, num_vlan;
1277
1278         val = readl(ioaddr + GMAC_HW_FEATURE3);
1279         switch (val & GMAC_HW_FEAT_NRVF) {
1280         case 0:
1281                 num_vlan = 1;
1282                 break;
1283         case 1:
1284                 num_vlan = 4;
1285                 break;
1286         case 2:
1287                 num_vlan = 8;
1288                 break;
1289         case 3:
1290                 num_vlan = 16;
1291                 break;
1292         case 4:
1293                 num_vlan = 24;
1294                 break;
1295         case 5:
1296                 num_vlan = 32;
1297                 break;
1298         default:
1299                 num_vlan = 1;
1300         }
1301
1302         return num_vlan;
1303 }
1304
1305 int dwmac4_setup(struct stmmac_priv *priv)
1306 {
1307         struct mac_device_info *mac = priv->hw;
1308
1309         dev_info(priv->device, "\tDWMAC4/5\n");
1310
1311         priv->dev->priv_flags |= IFF_UNICAST_FLT;
1312         mac->pcsr = priv->ioaddr;
1313         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1314         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1315         mac->mcast_bits_log2 = 0;
1316
1317         if (mac->multicast_filter_bins)
1318                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1319
1320         mac->link.duplex = GMAC_CONFIG_DM;
1321         mac->link.speed10 = GMAC_CONFIG_PS;
1322         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1323         mac->link.speed1000 = 0;
1324         mac->link.speed2500 = GMAC_CONFIG_FES;
1325         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1326         mac->mii.addr = GMAC_MDIO_ADDR;
1327         mac->mii.data = GMAC_MDIO_DATA;
1328         mac->mii.addr_shift = 21;
1329         mac->mii.addr_mask = GENMASK(25, 21);
1330         mac->mii.reg_shift = 16;
1331         mac->mii.reg_mask = GENMASK(20, 16);
1332         mac->mii.clk_csr_shift = 8;
1333         mac->mii.clk_csr_mask = GENMASK(11, 8);
1334         mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1335
1336         return 0;
1337 }