1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/platform_device.h>
4 #include <linux/module.h>
5 #include <linux/stmmac.h>
8 #include "stmmac_platform.h"
10 static const char *const mgbe_clks[] = {
11 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
17 struct clk_bulk_data *clks;
19 struct reset_control *rst_mac;
20 struct reset_control *rst_pcs;
29 #define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
30 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
31 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
32 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
33 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
34 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
35 #define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
36 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
37 #define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
38 #define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
39 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
40 #define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
41 #define XPCS_WRAP_UPHY_STATUS 0x8044
42 #define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
43 #define XPCS_WRAP_IRQ_STATUS 0x8050
44 #define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)
46 #define XPCS_REG_ADDR_SHIFT 10
47 #define XPCS_REG_ADDR_MASK 0x1fff
48 #define XPCS_ADDR 0x3fc
50 #define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
51 #define MAC_SBD_INTR BIT(2)
52 #define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
55 static int __maybe_unused tegra_mgbe_suspend(struct device *dev)
57 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
60 err = stmmac_suspend(dev);
64 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
66 return reset_control_assert(mgbe->rst_mac);
69 static int __maybe_unused tegra_mgbe_resume(struct device *dev)
71 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
75 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
79 err = reset_control_deassert(mgbe->rst_mac);
83 /* Enable common interrupt at wrapper level */
84 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
87 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
89 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
90 if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
92 value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
93 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
96 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
97 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
100 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
101 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
105 err = stmmac_resume(dev);
107 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
112 static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_data)
114 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
118 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
119 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
120 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
122 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
123 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
124 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
126 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
127 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
128 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
130 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
131 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
132 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
134 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
135 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
136 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
138 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
139 (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
142 dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
146 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
147 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
148 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
150 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
151 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
152 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
154 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
155 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
156 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
158 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
159 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
160 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
162 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
163 value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
166 dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
171 writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
176 static void mgbe_uphy_lane_bringup_serdes_down(struct net_device *ndev, void *mgbe_data)
178 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
181 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
182 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
183 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
185 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
186 value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
187 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
189 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
190 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
191 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
193 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
194 value |= XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
195 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
197 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
198 value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
199 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
202 static int tegra_mgbe_probe(struct platform_device *pdev)
204 struct plat_stmmacenet_data *plat;
205 struct stmmac_resources res;
206 struct tegra_mgbe *mgbe;
210 mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
214 mgbe->dev = &pdev->dev;
216 memset(&res, 0, sizeof(res));
218 irq = platform_get_irq(pdev, 0);
222 mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
223 if (IS_ERR(mgbe->hv))
224 return PTR_ERR(mgbe->hv);
226 mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
227 if (IS_ERR(mgbe->regs))
228 return PTR_ERR(mgbe->regs);
230 mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
231 if (IS_ERR(mgbe->xpcs))
232 return PTR_ERR(mgbe->xpcs);
234 res.addr = mgbe->regs;
237 mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks),
238 sizeof(*mgbe->clks), GFP_KERNEL);
242 for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++)
243 mgbe->clks[i].id = mgbe_clks[i];
245 err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
249 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
253 /* Perform MAC reset */
254 mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
255 if (IS_ERR(mgbe->rst_mac)) {
256 err = PTR_ERR(mgbe->rst_mac);
260 err = reset_control_assert(mgbe->rst_mac);
264 usleep_range(2000, 4000);
266 err = reset_control_deassert(mgbe->rst_mac);
270 /* Perform PCS reset */
271 mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
272 if (IS_ERR(mgbe->rst_pcs)) {
273 err = PTR_ERR(mgbe->rst_pcs);
277 err = reset_control_assert(mgbe->rst_pcs);
281 usleep_range(2000, 4000);
283 err = reset_control_deassert(mgbe->rst_pcs);
287 plat = stmmac_probe_config_dt(pdev, res.mac);
294 plat->flags |= STMMAC_FLAG_TSO_EN;
296 plat->bsp_priv = mgbe;
298 if (!plat->mdio_node)
299 plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");
301 if (!plat->mdio_bus_data) {
302 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
304 if (!plat->mdio_bus_data) {
310 plat->mdio_bus_data->needs_reset = true;
312 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
313 if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
314 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
315 value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
316 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
319 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
320 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
323 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
327 plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up;
328 plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down;
330 /* Tx FIFO Size - 128KB */
331 plat->tx_fifo_size = 131072;
332 /* Rx FIFO Size - 192KB */
333 plat->rx_fifo_size = 196608;
335 /* Enable common interrupt at wrapper level */
336 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
339 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
341 plat->flags |= STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP;
343 err = stmmac_dvr_probe(&pdev->dev, plat, &res);
350 stmmac_remove_config_dt(pdev, plat);
352 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
357 static void tegra_mgbe_remove(struct platform_device *pdev)
359 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);
361 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
363 stmmac_pltfr_remove(pdev);
366 static const struct of_device_id tegra_mgbe_match[] = {
367 { .compatible = "nvidia,tegra234-mgbe", },
370 MODULE_DEVICE_TABLE(of, tegra_mgbe_match);
372 static SIMPLE_DEV_PM_OPS(tegra_mgbe_pm_ops, tegra_mgbe_suspend, tegra_mgbe_resume);
374 static struct platform_driver tegra_mgbe_driver = {
375 .probe = tegra_mgbe_probe,
376 .remove_new = tegra_mgbe_remove,
378 .name = "tegra-mgbe",
379 .pm = &tegra_mgbe_pm_ops,
380 .of_match_table = tegra_mgbe_match,
383 module_platform_driver(tegra_mgbe_driver);
385 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
386 MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
387 MODULE_LICENSE("GPL");