1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
11 #include "stmmac_ptp.h"
13 struct intel_priv_data {
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 unsigned long crossts_adj;
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20 * discovered via DMI, with the address of PHY connected to the MAC. The
21 * negative value of the address means that MAC controller is not connected
24 struct stmmac_pci_func_data {
29 struct stmmac_pci_dmi_data {
30 const struct stmmac_pci_func_data *func;
34 struct stmmac_pci_info {
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 const struct dmi_system_id *dmi_list)
41 const struct stmmac_pci_func_data *func_data;
42 const struct stmmac_pci_dmi_data *dmi_data;
43 const struct dmi_system_id *dmi_id;
44 int func = PCI_FUNC(pdev->devfn);
47 dmi_id = dmi_first_match(dmi_list);
51 dmi_data = dmi_id->driver_data;
52 func_data = dmi_data->func;
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 if (func_data->func == func)
56 return func_data->phy_addr;
61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 int phyreg, u32 mask, u32 val)
64 unsigned int retries = 10;
68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 if ((val_rd & mask) == (val & mask))
71 udelay(POLL_DELAY_US);
77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
79 struct intel_priv_data *intel_priv = priv_data;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 int serdes_phy_addr = 0;
84 if (!intel_priv->mdio_adhoc_addr)
87 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
89 /* Set the serdes rate and the PCLK rate */
90 data = mdiobus_read(priv->mii, serdes_phy_addr,
93 data &= ~SERDES_RATE_MASK;
94 data &= ~SERDES_PCLK_MASK;
96 if (priv->plat->max_speed == 2500)
97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 data |= SERDES_PLL_CLK;
108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
110 /* check for clk_ack assertion */
111 data = serdes_status_poll(priv, serdes_phy_addr,
117 dev_err(priv->device, "Serdes PLL clk request timeout\n");
121 /* assert lane reset */
122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
126 /* check for assert lane reset reflection */
127 data = serdes_status_poll(priv, serdes_phy_addr,
133 dev_err(priv->device, "Serdes assert lane reset timeout\n");
137 /* move power state to P0 */
138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
140 data &= ~SERDES_PWR_ST_MASK;
141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
145 /* Check for P0 state */
146 data = serdes_status_poll(priv, serdes_phy_addr,
149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
152 dev_err(priv->device, "Serdes power state P0 timeout.\n");
156 /* PSE only - ungate SGMII PHY Rx Clock */
157 if (intel_priv->is_pse)
158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 0, SERDES_PHY_RX_CLK);
164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
166 struct intel_priv_data *intel_priv = intel_data;
167 struct stmmac_priv *priv = netdev_priv(ndev);
168 int serdes_phy_addr = 0;
171 if (!intel_priv->mdio_adhoc_addr)
174 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
176 /* PSE only - gate SGMII PHY Rx Clock */
177 if (intel_priv->is_pse)
178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 SERDES_PHY_RX_CLK, 0);
181 /* move power state to P3 */
182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
184 data &= ~SERDES_PWR_ST_MASK;
185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
189 /* Check for P3 state */
190 data = serdes_status_poll(priv, serdes_phy_addr,
193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
196 dev_err(priv->device, "Serdes power state P3 timeout\n");
200 /* de-assert clk_req */
201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 data &= ~SERDES_PLL_CLK;
203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
205 /* check for clk_ack de-assert */
206 data = serdes_status_poll(priv, serdes_phy_addr,
209 (u32)~SERDES_PLL_CLK);
212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
216 /* de-assert lane reset */
217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
221 /* check for de-assert lane reset reflection */
222 data = serdes_status_poll(priv, serdes_phy_addr,
228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
235 struct intel_priv_data *intel_priv = intel_data;
236 struct stmmac_priv *priv = netdev_priv(ndev);
237 int serdes_phy_addr = 0;
240 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
242 /* Determine the link speed mode: 2.5Gbps/1Gbps */
243 data = mdiobus_read(priv->mii, serdes_phy_addr,
246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 SERDES_LINK_MODE_2G5) {
248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 priv->plat->max_speed = 2500;
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 priv->plat->mdio_bus_data->xpcs_an_inband = false;
253 priv->plat->max_speed = 1000;
257 /* Program PTP Clock Frequency for different variant of
258 * Intel mGBE that has slightly different GPO mapping
260 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
262 struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
263 struct intel_priv_data *intel_priv;
266 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
268 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
270 if (intel_priv->is_pse) {
271 /* For PSE GbE, use 200MHz */
272 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
273 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
275 /* For PCH GbE, use 200MHz */
276 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
277 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
280 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
283 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
288 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
289 ns <<= GMAC4_ART_TIME_SHIFT;
290 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
291 ns <<= GMAC4_ART_TIME_SHIFT;
292 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
293 ns <<= GMAC4_ART_TIME_SHIFT;
294 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
299 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
301 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
304 static int intel_crosststamp(ktime_t *device,
305 struct system_counterval_t *system,
308 struct intel_priv_data *intel_priv;
310 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
311 void __iomem *ptpaddr = priv->ptpaddr;
312 void __iomem *ioaddr = priv->hw->pcsr;
321 if (!boot_cpu_has(X86_FEATURE_ART))
324 intel_priv = priv->plat->bsp_priv;
326 /* Both internal crosstimestamping and external triggered event
327 * timestamping cannot be run concurrently.
329 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
332 priv->plat->int_snapshot_en = 1;
334 mutex_lock(&priv->aux_ts_lock);
335 /* Enable Internal snapshot trigger */
336 acr_value = readl(ptpaddr + PTP_ACR);
337 acr_value &= ~PTP_ACR_MASK;
338 switch (priv->plat->int_snapshot_num) {
340 acr_value |= PTP_ACR_ATSEN0;
343 acr_value |= PTP_ACR_ATSEN1;
346 acr_value |= PTP_ACR_ATSEN2;
349 acr_value |= PTP_ACR_ATSEN3;
352 mutex_unlock(&priv->aux_ts_lock);
353 priv->plat->int_snapshot_en = 0;
356 writel(acr_value, ptpaddr + PTP_ACR);
359 acr_value = readl(ptpaddr + PTP_ACR);
360 acr_value |= PTP_ACR_ATSFC;
361 writel(acr_value, ptpaddr + PTP_ACR);
362 /* Release the mutex */
363 mutex_unlock(&priv->aux_ts_lock);
365 /* Trigger Internal snapshot signal
366 * Create a rising edge by just toggle the GPO1 to low
369 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
370 gpio_value &= ~GMAC_GPO1;
371 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
372 gpio_value |= GMAC_GPO1;
373 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
375 /* Time sync done Indication - Interrupt method */
376 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
377 stmmac_cross_ts_isr(priv),
379 priv->plat->int_snapshot_en = 0;
383 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
384 GMAC_TIMESTAMP_ATSNS_MASK) >>
385 GMAC_TIMESTAMP_ATSNS_SHIFT;
387 /* Repeat until the timestamps are from the FIFO last segment */
388 for (i = 0; i < num_snapshot; i++) {
389 read_lock_irqsave(&priv->ptp_lock, flags);
390 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
391 *device = ns_to_ktime(ptp_time);
392 read_unlock_irqrestore(&priv->ptp_lock, flags);
393 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
394 *system = convert_art_to_tsc(art_time);
397 system->cycles *= intel_priv->crossts_adj;
398 priv->plat->int_snapshot_en = 0;
403 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
406 if (boot_cpu_has(X86_FEATURE_ART)) {
407 unsigned int art_freq;
409 /* On systems that support ART, ART frequency can be obtained
410 * from ECX register of CPUID leaf (0x15).
412 art_freq = cpuid_ecx(ART_CPUID_LEAF);
413 do_div(art_freq, base);
414 intel_priv->crossts_adj = art_freq;
418 static void common_default_data(struct plat_stmmacenet_data *plat)
420 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
422 plat->force_sf_dma_mode = 1;
424 plat->mdio_bus_data->needs_reset = true;
426 /* Set default value for multicast hash bins */
427 plat->multicast_filter_bins = HASH_TABLE_SIZE;
429 /* Set default value for unicast filter entries */
430 plat->unicast_filter_entries = 1;
432 /* Set the maxmtu to a default of JUMBO_LEN */
433 plat->maxmtu = JUMBO_LEN;
435 /* Set default number of RX and TX queues to use */
436 plat->tx_queues_to_use = 1;
437 plat->rx_queues_to_use = 1;
439 /* Disable Priority config by default */
440 plat->tx_queues_cfg[0].use_prio = false;
441 plat->rx_queues_cfg[0].use_prio = false;
443 /* Disable RX queues routing by default */
444 plat->rx_queues_cfg[0].pkt_route = 0x0;
447 static int intel_mgbe_common_data(struct pci_dev *pdev,
448 struct plat_stmmacenet_data *plat)
450 struct fwnode_handle *fwnode;
460 plat->force_sf_dma_mode = 0;
461 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE);
463 /* Multiplying factor to the clk_eee_i clock time
464 * period to make it closer to 100 ns. This value
465 * should be programmed such that the clk_eee_time_period *
466 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
467 * clk_eee frequency is 19.2Mhz
468 * clk_eee_time_period is 52ns
469 * 52ns * (1 + 1) = 104ns
470 * MULT_FACT_100NS = 1
472 plat->mult_fact_100ns = 1;
474 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
476 for (i = 0; i < plat->rx_queues_to_use; i++) {
477 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
478 plat->rx_queues_cfg[i].chan = i;
480 /* Disable Priority config by default */
481 plat->rx_queues_cfg[i].use_prio = false;
483 /* Disable RX queues routing by default */
484 plat->rx_queues_cfg[i].pkt_route = 0x0;
487 for (i = 0; i < plat->tx_queues_to_use; i++) {
488 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
490 /* Disable Priority config by default */
491 plat->tx_queues_cfg[i].use_prio = false;
492 /* Default TX Q0 to use TSO and rest TXQ for TBS */
494 plat->tx_queues_cfg[i].tbs_en = 1;
497 /* FIFO size is 4096 bytes for 1 tx/rx queue */
498 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
499 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
501 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
502 plat->tx_queues_cfg[0].weight = 0x09;
503 plat->tx_queues_cfg[1].weight = 0x0A;
504 plat->tx_queues_cfg[2].weight = 0x0B;
505 plat->tx_queues_cfg[3].weight = 0x0C;
506 plat->tx_queues_cfg[4].weight = 0x0D;
507 plat->tx_queues_cfg[5].weight = 0x0E;
508 plat->tx_queues_cfg[6].weight = 0x0F;
509 plat->tx_queues_cfg[7].weight = 0x10;
511 plat->dma_cfg->pbl = 32;
512 plat->dma_cfg->pblx8 = true;
513 plat->dma_cfg->fixed_burst = 0;
514 plat->dma_cfg->mixed_burst = 0;
515 plat->dma_cfg->aal = 0;
516 plat->dma_cfg->dche = true;
518 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
523 plat->axi->axi_lpi_en = 0;
524 plat->axi->axi_xit_frm = 0;
525 plat->axi->axi_wr_osr_lmt = 1;
526 plat->axi->axi_rd_osr_lmt = 1;
527 plat->axi->axi_blen[0] = 4;
528 plat->axi->axi_blen[1] = 8;
529 plat->axi->axi_blen[2] = 16;
531 plat->ptp_max_adj = plat->clk_ptp_rate;
532 plat->eee_usecs_rate = plat->clk_ptp_rate;
534 /* Set system clock */
535 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
537 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
541 if (IS_ERR(plat->stmmac_clk)) {
542 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
543 plat->stmmac_clk = NULL;
546 ret = clk_prepare_enable(plat->stmmac_clk);
548 clk_unregister_fixed_rate(plat->stmmac_clk);
552 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
554 /* Set default value for multicast hash bins */
555 plat->multicast_filter_bins = HASH_TABLE_SIZE;
557 /* Set default value for unicast filter entries */
558 plat->unicast_filter_entries = 1;
560 /* Set the maxmtu to a default of JUMBO_LEN */
561 plat->maxmtu = JUMBO_LEN;
563 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN;
565 /* Use the last Rx queue */
566 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
568 /* For fixed-link setup, we allow phy-mode setting */
569 fwnode = dev_fwnode(&pdev->dev);
573 /* "phy-mode" setting is optional. If it is set,
574 * we allow either sgmii or 1000base-x for now.
576 phy_mode = fwnode_get_phy_mode(fwnode);
578 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
579 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
580 plat->phy_interface = phy_mode;
582 dev_warn(&pdev->dev, "Invalid phy-mode\n");
586 /* Intel mgbe SGMII interface uses pcs-xcps */
587 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
588 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
589 plat->mdio_bus_data->has_xpcs = true;
590 plat->mdio_bus_data->xpcs_an_inband = true;
593 /* For fixed-link setup, we clear xpcs_an_inband */
595 struct fwnode_handle *fixed_node;
597 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
599 plat->mdio_bus_data->xpcs_an_inband = false;
601 fwnode_handle_put(fixed_node);
604 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
605 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
606 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
608 plat->int_snapshot_num = AUX_SNAPSHOT1;
609 plat->ext_snapshot_num = AUX_SNAPSHOT0;
611 plat->crosststamp = intel_crosststamp;
612 plat->int_snapshot_en = 0;
614 /* Setup MSI vector offset specific to Intel mGbE controller */
615 plat->msi_mac_vec = 29;
616 plat->msi_lpi_vec = 28;
617 plat->msi_sfty_ce_vec = 27;
618 plat->msi_sfty_ue_vec = 26;
619 plat->msi_rx_base_vec = 0;
620 plat->msi_tx_base_vec = 1;
625 static int ehl_common_data(struct pci_dev *pdev,
626 struct plat_stmmacenet_data *plat)
628 plat->rx_queues_to_use = 8;
629 plat->tx_queues_to_use = 8;
630 plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
632 plat->safety_feat_cfg->tsoee = 1;
633 plat->safety_feat_cfg->mrxpee = 1;
634 plat->safety_feat_cfg->mestee = 1;
635 plat->safety_feat_cfg->mrxee = 1;
636 plat->safety_feat_cfg->mtxee = 1;
637 plat->safety_feat_cfg->epsi = 0;
638 plat->safety_feat_cfg->edpp = 0;
639 plat->safety_feat_cfg->prtyen = 0;
640 plat->safety_feat_cfg->tmouten = 0;
642 return intel_mgbe_common_data(pdev, plat);
645 static int ehl_sgmii_data(struct pci_dev *pdev,
646 struct plat_stmmacenet_data *plat)
649 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
650 plat->speed_mode_2500 = intel_speed_mode_2500;
651 plat->serdes_powerup = intel_serdes_powerup;
652 plat->serdes_powerdown = intel_serdes_powerdown;
654 plat->clk_ptp_rate = 204800000;
656 return ehl_common_data(pdev, plat);
659 static struct stmmac_pci_info ehl_sgmii1g_info = {
660 .setup = ehl_sgmii_data,
663 static int ehl_rgmii_data(struct pci_dev *pdev,
664 struct plat_stmmacenet_data *plat)
667 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
669 plat->clk_ptp_rate = 204800000;
671 return ehl_common_data(pdev, plat);
674 static struct stmmac_pci_info ehl_rgmii1g_info = {
675 .setup = ehl_rgmii_data,
678 static int ehl_pse0_common_data(struct pci_dev *pdev,
679 struct plat_stmmacenet_data *plat)
681 struct intel_priv_data *intel_priv = plat->bsp_priv;
683 intel_priv->is_pse = true;
685 plat->host_dma_width = 32;
687 plat->clk_ptp_rate = 200000000;
689 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
691 return ehl_common_data(pdev, plat);
694 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
695 struct plat_stmmacenet_data *plat)
697 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
698 return ehl_pse0_common_data(pdev, plat);
701 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
702 .setup = ehl_pse0_rgmii1g_data,
705 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
706 struct plat_stmmacenet_data *plat)
708 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
709 plat->speed_mode_2500 = intel_speed_mode_2500;
710 plat->serdes_powerup = intel_serdes_powerup;
711 plat->serdes_powerdown = intel_serdes_powerdown;
712 return ehl_pse0_common_data(pdev, plat);
715 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
716 .setup = ehl_pse0_sgmii1g_data,
719 static int ehl_pse1_common_data(struct pci_dev *pdev,
720 struct plat_stmmacenet_data *plat)
722 struct intel_priv_data *intel_priv = plat->bsp_priv;
724 intel_priv->is_pse = true;
726 plat->host_dma_width = 32;
728 plat->clk_ptp_rate = 200000000;
730 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
732 return ehl_common_data(pdev, plat);
735 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
736 struct plat_stmmacenet_data *plat)
738 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
739 return ehl_pse1_common_data(pdev, plat);
742 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
743 .setup = ehl_pse1_rgmii1g_data,
746 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
747 struct plat_stmmacenet_data *plat)
749 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
750 plat->speed_mode_2500 = intel_speed_mode_2500;
751 plat->serdes_powerup = intel_serdes_powerup;
752 plat->serdes_powerdown = intel_serdes_powerdown;
753 return ehl_pse1_common_data(pdev, plat);
756 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
757 .setup = ehl_pse1_sgmii1g_data,
760 static int tgl_common_data(struct pci_dev *pdev,
761 struct plat_stmmacenet_data *plat)
763 plat->rx_queues_to_use = 6;
764 plat->tx_queues_to_use = 4;
765 plat->clk_ptp_rate = 204800000;
766 plat->speed_mode_2500 = intel_speed_mode_2500;
768 plat->safety_feat_cfg->tsoee = 1;
769 plat->safety_feat_cfg->mrxpee = 0;
770 plat->safety_feat_cfg->mestee = 1;
771 plat->safety_feat_cfg->mrxee = 1;
772 plat->safety_feat_cfg->mtxee = 1;
773 plat->safety_feat_cfg->epsi = 0;
774 plat->safety_feat_cfg->edpp = 0;
775 plat->safety_feat_cfg->prtyen = 0;
776 plat->safety_feat_cfg->tmouten = 0;
778 return intel_mgbe_common_data(pdev, plat);
781 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
782 struct plat_stmmacenet_data *plat)
785 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
786 plat->serdes_powerup = intel_serdes_powerup;
787 plat->serdes_powerdown = intel_serdes_powerdown;
788 return tgl_common_data(pdev, plat);
791 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
792 .setup = tgl_sgmii_phy0_data,
795 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
796 struct plat_stmmacenet_data *plat)
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
800 plat->serdes_powerup = intel_serdes_powerup;
801 plat->serdes_powerdown = intel_serdes_powerdown;
802 return tgl_common_data(pdev, plat);
805 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
806 .setup = tgl_sgmii_phy1_data,
809 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
810 struct plat_stmmacenet_data *plat)
813 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
815 /* SerDes power up and power down are done in BIOS for ADL */
817 return tgl_common_data(pdev, plat);
820 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
821 .setup = adls_sgmii_phy0_data,
824 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
825 struct plat_stmmacenet_data *plat)
828 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
830 /* SerDes power up and power down are done in BIOS for ADL */
832 return tgl_common_data(pdev, plat);
835 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
836 .setup = adls_sgmii_phy1_data,
838 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
845 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
846 .func = galileo_stmmac_func_data,
847 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
850 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
861 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
862 .func = iot2040_stmmac_func_data,
863 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
866 static const struct dmi_system_id quark_pci_dmi[] = {
869 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
871 .driver_data = (void *)&galileo_stmmac_dmi_data,
875 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
877 .driver_data = (void *)&galileo_stmmac_dmi_data,
879 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
880 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
881 * has only one pci network device while other asset tags are
882 * for IOT2040 which has two.
886 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
887 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
888 "6ES7647-0AA00-0YA2"),
890 .driver_data = (void *)&galileo_stmmac_dmi_data,
894 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
896 .driver_data = (void *)&iot2040_stmmac_dmi_data,
901 static int quark_default_data(struct pci_dev *pdev,
902 struct plat_stmmacenet_data *plat)
906 /* Set common default data first */
907 common_default_data(plat);
909 /* Refuse to load the driver and register net device if MAC controller
910 * does not connect to any PHY interface.
912 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
914 /* Return error to the caller on DMI enabled boards. */
915 if (dmi_get_system_info(DMI_BOARD_NAME))
918 /* Galileo boards with old firmware don't support DMI. We always
919 * use 1 here as PHY address, so at least the first found MAC
920 * controller would be probed.
925 plat->bus_id = pci_dev_id(pdev);
926 plat->phy_addr = ret;
927 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
929 plat->dma_cfg->pbl = 16;
930 plat->dma_cfg->pblx8 = true;
931 plat->dma_cfg->fixed_burst = 1;
937 static const struct stmmac_pci_info quark_info = {
938 .setup = quark_default_data,
941 static int stmmac_config_single_msi(struct pci_dev *pdev,
942 struct plat_stmmacenet_data *plat,
943 struct stmmac_resources *res)
947 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
949 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
954 res->irq = pci_irq_vector(pdev, 0);
955 res->wol_irq = res->irq;
956 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN;
957 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
963 static int stmmac_config_multi_msi(struct pci_dev *pdev,
964 struct plat_stmmacenet_data *plat,
965 struct stmmac_resources *res)
970 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
971 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
972 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
977 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
978 PCI_IRQ_MSI | PCI_IRQ_MSIX);
980 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
986 for (i = 0; i < plat->rx_queues_to_use; i++) {
987 res->rx_irq[i] = pci_irq_vector(pdev,
988 plat->msi_rx_base_vec + i * 2);
992 for (i = 0; i < plat->tx_queues_to_use; i++) {
993 res->tx_irq[i] = pci_irq_vector(pdev,
994 plat->msi_tx_base_vec + i * 2);
997 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
998 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
999 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
1000 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
1001 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
1002 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
1003 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
1004 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1005 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1006 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1008 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN;
1009 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1015 * intel_eth_pci_probe
1017 * @pdev: pci device pointer
1018 * @id: pointer to table of device id/id's.
1020 * Description: This probing function gets called for all PCI devices which
1021 * match the ID table and are not "owned" by other driver yet. This function
1022 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1023 * matches the device. The probe functions returns zero when the driver choose
1024 * to take "ownership" of the device or an error code(-ve no) otherwise.
1026 static int intel_eth_pci_probe(struct pci_dev *pdev,
1027 const struct pci_device_id *id)
1029 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1030 struct intel_priv_data *intel_priv;
1031 struct plat_stmmacenet_data *plat;
1032 struct stmmac_resources res;
1035 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1039 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1043 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1044 sizeof(*plat->mdio_bus_data),
1046 if (!plat->mdio_bus_data)
1049 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1054 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1055 sizeof(*plat->safety_feat_cfg),
1057 if (!plat->safety_feat_cfg)
1060 /* Enable pci device */
1061 ret = pcim_enable_device(pdev);
1063 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1068 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1072 pci_set_master(pdev);
1074 plat->bsp_priv = intel_priv;
1075 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1076 intel_priv->crossts_adj = 1;
1078 /* Initialize all MSI vectors to invalid so that it can be set
1079 * according to platform data settings below.
1080 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1082 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1083 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1084 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1085 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1086 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1087 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1088 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1090 ret = info->setup(pdev, plat);
1094 memset(&res, 0, sizeof(res));
1095 res.addr = pcim_iomap_table(pdev)[0];
1097 if (plat->eee_usecs_rate > 0) {
1100 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1101 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1104 ret = stmmac_config_multi_msi(pdev, plat, &res);
1106 ret = stmmac_config_single_msi(pdev, plat, &res);
1108 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1114 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1122 clk_disable_unprepare(plat->stmmac_clk);
1123 clk_unregister_fixed_rate(plat->stmmac_clk);
1128 * intel_eth_pci_remove
1130 * @pdev: pci device pointer
1131 * Description: this function calls the main to free the net resources
1132 * and releases the PCI resources.
1134 static void intel_eth_pci_remove(struct pci_dev *pdev)
1136 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1137 struct stmmac_priv *priv = netdev_priv(ndev);
1139 stmmac_dvr_remove(&pdev->dev);
1141 clk_disable_unprepare(priv->plat->stmmac_clk);
1142 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1145 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1147 struct pci_dev *pdev = to_pci_dev(dev);
1150 ret = stmmac_suspend(dev);
1154 ret = pci_save_state(pdev);
1158 pci_wake_from_d3(pdev, true);
1159 pci_set_power_state(pdev, PCI_D3hot);
1163 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1165 struct pci_dev *pdev = to_pci_dev(dev);
1168 pci_restore_state(pdev);
1169 pci_set_power_state(pdev, PCI_D0);
1171 ret = pcim_enable_device(pdev);
1175 pci_set_master(pdev);
1177 return stmmac_resume(dev);
1180 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1181 intel_eth_pci_resume);
1183 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937
1184 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
1185 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
1186 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
1187 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1188 * which are named PSE0 and PSE1
1190 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
1192 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
1193 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
1194 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
1195 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
1196 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
1197 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
1198 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
1199 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
1200 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
1201 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac
1202 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac
1204 static const struct pci_device_id intel_eth_pci_id_table[] = {
1205 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1206 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1207 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1208 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1209 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1210 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1211 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1212 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1213 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1214 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1215 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1216 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1217 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1218 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1219 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1220 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1221 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1224 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1226 static struct pci_driver intel_eth_pci_driver = {
1227 .name = "intel-eth-pci",
1228 .id_table = intel_eth_pci_id_table,
1229 .probe = intel_eth_pci_probe,
1230 .remove = intel_eth_pci_remove,
1232 .pm = &intel_eth_pm_ops,
1236 module_pci_driver(intel_eth_pci_driver);
1238 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1239 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1240 MODULE_LICENSE("GPL v2");