1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8
10 #include <linux/gpio/consumer.h>
11 #include <linux/kernel.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
15 #include <linux/of_net.h>
16 #include <linux/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/stmmac.h>
23 #include "stmmac_platform.h"
25 #define GPR_ENET_QOS_INTF_MODE_MASK GENMASK(21, 16)
26 #define GPR_ENET_QOS_INTF_SEL_MII (0x0 << 16)
27 #define GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 16)
28 #define GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 16)
29 #define GPR_ENET_QOS_CLK_GEN_EN (0x1 << 19)
30 #define GPR_ENET_QOS_CLK_TX_CLK_SEL (0x1 << 20)
31 #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
33 #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
34 #define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
35 #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
36 #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
37 #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
38 #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0)
40 #define DMA_BUS_MODE 0x00001000
41 #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
42 #define RMII_RESET_SPEED (0x3 << 14)
43 #define CTRL_SPEED_MASK GENMASK(15, 14)
45 struct imx_dwmac_ops {
48 bool mac_rgmii_txclk_auto_adj;
50 int (*fix_soc_reset)(void *priv, void __iomem *ioaddr);
51 int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat);
52 void (*fix_mac_speed)(void *priv, unsigned int speed, unsigned int mode);
55 struct imx_priv_data {
59 struct regmap *intf_regmap;
62 void __iomem *base_addr;
64 const struct imx_dwmac_ops *ops;
65 struct plat_stmmacenet_data *plat_dat;
68 static int imx8mp_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
70 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
73 switch (plat_dat->mac_interface) {
74 case PHY_INTERFACE_MODE_MII:
75 val = GPR_ENET_QOS_INTF_SEL_MII;
77 case PHY_INTERFACE_MODE_RMII:
78 val = GPR_ENET_QOS_INTF_SEL_RMII;
79 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL);
81 case PHY_INTERFACE_MODE_RGMII:
82 case PHY_INTERFACE_MODE_RGMII_ID:
83 case PHY_INTERFACE_MODE_RGMII_RXID:
84 case PHY_INTERFACE_MODE_RGMII_TXID:
85 val = GPR_ENET_QOS_INTF_SEL_RGMII |
86 GPR_ENET_QOS_RGMII_EN;
89 pr_debug("imx dwmac doesn't support %d interface\n",
90 plat_dat->mac_interface);
94 val |= GPR_ENET_QOS_CLK_GEN_EN;
95 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
96 GPR_ENET_QOS_INTF_MODE_MASK, val);
100 imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
104 /* TBD: depends on imx8dxl scu interfaces to be upstreamed */
108 static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)
110 struct imx_priv_data *dwmac = plat_dat->bsp_priv;
113 switch (plat_dat->mac_interface) {
114 case PHY_INTERFACE_MODE_MII:
115 val = MX93_GPR_ENET_QOS_INTF_SEL_MII;
117 case PHY_INTERFACE_MODE_RMII:
118 val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;
120 case PHY_INTERFACE_MODE_RGMII:
121 case PHY_INTERFACE_MODE_RGMII_ID:
122 case PHY_INTERFACE_MODE_RGMII_RXID:
123 case PHY_INTERFACE_MODE_RGMII_TXID:
124 val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;
127 dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",
128 plat_dat->mac_interface);
132 val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
133 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
134 MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);
137 static int imx_dwmac_clks_config(void *priv, bool enabled)
139 struct imx_priv_data *dwmac = priv;
143 ret = clk_prepare_enable(dwmac->clk_mem);
145 dev_err(dwmac->dev, "mem clock enable failed\n");
149 ret = clk_prepare_enable(dwmac->clk_tx);
151 dev_err(dwmac->dev, "tx clock enable failed\n");
152 clk_disable_unprepare(dwmac->clk_mem);
156 clk_disable_unprepare(dwmac->clk_tx);
157 clk_disable_unprepare(dwmac->clk_mem);
163 static int imx_dwmac_init(struct platform_device *pdev, void *priv)
165 struct plat_stmmacenet_data *plat_dat;
166 struct imx_priv_data *dwmac = priv;
169 plat_dat = dwmac->plat_dat;
171 if (dwmac->ops->set_intf_mode) {
172 ret = dwmac->ops->set_intf_mode(plat_dat);
180 static void imx_dwmac_exit(struct platform_device *pdev, void *priv)
182 /* nothing to do now */
185 static void imx_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
187 struct plat_stmmacenet_data *plat_dat;
188 struct imx_priv_data *dwmac = priv;
192 plat_dat = dwmac->plat_dat;
194 if (dwmac->ops->mac_rgmii_txclk_auto_adj ||
195 (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) ||
196 (plat_dat->mac_interface == PHY_INTERFACE_MODE_MII))
210 dev_err(dwmac->dev, "invalid speed %u\n", speed);
214 err = clk_set_rate(dwmac->clk_tx, rate);
216 dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
219 static void imx93_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
221 struct imx_priv_data *dwmac = priv;
225 imx_dwmac_fix_speed(priv, speed, mode);
227 if (!dwmac || mode != MLO_AN_FIXED)
230 if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
233 iface &= MX93_GPR_ENET_QOS_INTF_MASK;
234 if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
237 old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
238 ctrl = old_ctrl & ~CTRL_SPEED_MASK;
239 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
240 MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
241 writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
243 /* Ensure the settings for CTRL are applied. */
244 readl(dwmac->base_addr + MAC_CTRL_REG);
246 usleep_range(10, 20);
247 iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
248 regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
249 MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
251 writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
254 static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
256 struct plat_stmmacenet_data *plat_dat = priv;
257 u32 value = readl(ioaddr + DMA_BUS_MODE);
260 value |= DMA_BUS_MODE_SFT_RESET;
261 writel(value, ioaddr + DMA_BUS_MODE);
263 if (plat_dat->mac_interface == PHY_INTERFACE_MODE_RMII) {
264 usleep_range(100, 200);
265 writel(RMII_RESET_SPEED, ioaddr + MAC_CTRL_REG);
268 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value,
269 !(value & DMA_BUS_MODE_SFT_RESET),
274 imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev)
276 struct device_node *np = dev->of_node;
279 dwmac->rmii_refclk_ext = of_property_read_bool(np, "snps,rmii_refclk_ext");
281 dwmac->clk_tx = devm_clk_get(dev, "tx");
282 if (IS_ERR(dwmac->clk_tx)) {
283 dev_err(dev, "failed to get tx clock\n");
284 return PTR_ERR(dwmac->clk_tx);
287 dwmac->clk_mem = NULL;
289 if (of_machine_is_compatible("fsl,imx8dxl") ||
290 of_machine_is_compatible("fsl,imx93")) {
291 dwmac->clk_mem = devm_clk_get(dev, "mem");
292 if (IS_ERR(dwmac->clk_mem)) {
293 dev_err(dev, "failed to get mem clock\n");
294 return PTR_ERR(dwmac->clk_mem);
298 if (of_machine_is_compatible("fsl,imx8mp") ||
299 of_machine_is_compatible("fsl,imx93")) {
300 /* Binding doc describes the propety:
301 * is required by i.MX8MP, i.MX93.
302 * is optinoal for i.MX8DXL.
304 dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");
305 if (IS_ERR(dwmac->intf_regmap))
306 return PTR_ERR(dwmac->intf_regmap);
308 err = of_property_read_u32_index(np, "intf_mode", 1, &dwmac->intf_reg_off);
310 dev_err(dev, "Can't get intf mode reg offset (%d)\n", err);
318 static int imx_dwmac_probe(struct platform_device *pdev)
320 struct plat_stmmacenet_data *plat_dat;
321 struct stmmac_resources stmmac_res;
322 struct imx_priv_data *dwmac;
323 const struct imx_dwmac_ops *data;
326 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
330 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
334 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
335 if (IS_ERR(plat_dat))
336 return PTR_ERR(plat_dat);
338 data = of_device_get_match_data(&pdev->dev);
340 dev_err(&pdev->dev, "failed to get match data\n");
346 dwmac->dev = &pdev->dev;
348 ret = imx_dwmac_parse_dt(dwmac, &pdev->dev);
350 dev_err(&pdev->dev, "failed to parse OF data\n");
354 if (data->flags & STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY)
355 plat_dat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY;
357 plat_dat->host_dma_width = dwmac->ops->addr_width;
358 plat_dat->init = imx_dwmac_init;
359 plat_dat->exit = imx_dwmac_exit;
360 plat_dat->clks_config = imx_dwmac_clks_config;
361 plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
362 plat_dat->bsp_priv = dwmac;
363 dwmac->plat_dat = plat_dat;
364 dwmac->base_addr = stmmac_res.addr;
366 ret = imx_dwmac_clks_config(dwmac, true);
368 goto err_clks_config;
370 ret = imx_dwmac_init(pdev, dwmac);
374 if (dwmac->ops->fix_mac_speed)
375 plat_dat->fix_mac_speed = dwmac->ops->fix_mac_speed;
376 dwmac->plat_dat->fix_soc_reset = dwmac->ops->fix_soc_reset;
378 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
385 imx_dwmac_exit(pdev, plat_dat->bsp_priv);
387 imx_dwmac_clks_config(dwmac, false);
391 stmmac_remove_config_dt(pdev, plat_dat);
395 static struct imx_dwmac_ops imx8mp_dwmac_data = {
397 .mac_rgmii_txclk_auto_adj = false,
398 .set_intf_mode = imx8mp_set_intf_mode,
399 .flags = STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY,
402 static struct imx_dwmac_ops imx8dxl_dwmac_data = {
404 .mac_rgmii_txclk_auto_adj = true,
405 .set_intf_mode = imx8dxl_set_intf_mode,
408 static struct imx_dwmac_ops imx93_dwmac_data = {
410 .mac_rgmii_txclk_auto_adj = true,
411 .set_intf_mode = imx93_set_intf_mode,
412 .fix_soc_reset = imx_dwmac_mx93_reset,
413 .fix_mac_speed = imx93_dwmac_fix_speed,
416 static const struct of_device_id imx_dwmac_match[] = {
417 { .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },
418 { .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },
419 { .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },
422 MODULE_DEVICE_TABLE(of, imx_dwmac_match);
424 static struct platform_driver imx_dwmac_driver = {
425 .probe = imx_dwmac_probe,
426 .remove_new = stmmac_pltfr_remove,
429 .pm = &stmmac_pltfr_pm_ops,
430 .of_match_table = imx_dwmac_match,
433 module_platform_driver(imx_dwmac_driver);
435 MODULE_AUTHOR("NXP");
436 MODULE_DESCRIPTION("NXP imx8 DWMAC Specific Glue layer");
437 MODULE_LICENSE("GPL v2");