1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
5 * Copyright (C) 2016 Joao Pinto <jpinto@synopsys.com>
9 #include <linux/clk-provider.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/ethtool.h>
14 #include <linux/iopoll.h>
15 #include <linux/ioport.h>
16 #include <linux/module.h>
18 #include <linux/of_net.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/stmmac.h>
24 #include "stmmac_platform.h"
31 struct reset_control *rst;
32 struct clk *clk_master;
33 struct clk *clk_slave;
37 struct gpio_desc *reset;
40 static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
41 struct plat_stmmacenet_data *plat_dat)
43 struct device *dev = &pdev->dev;
49 plat_dat->axi = kzalloc(sizeof(struct stmmac_axi), GFP_KERNEL);
55 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev,
57 if (device_property_read_u32(dev, "snps,write-requests",
58 &plat_dat->axi->axi_wr_osr_lmt)) {
60 * Since the register has a reset value of 1, if property
61 * is missing, default to 1.
63 plat_dat->axi->axi_wr_osr_lmt = 1;
66 * If property exists, to keep the behavior from dwc_eth_qos,
67 * subtract one after parsing.
69 plat_dat->axi->axi_wr_osr_lmt--;
72 if (device_property_read_u32(dev, "snps,read-requests",
73 &plat_dat->axi->axi_rd_osr_lmt)) {
75 * Since the register has a reset value of 1, if property
76 * is missing, default to 1.
78 plat_dat->axi->axi_rd_osr_lmt = 1;
81 * If property exists, to keep the behavior from dwc_eth_qos,
82 * subtract one after parsing.
84 plat_dat->axi->axi_rd_osr_lmt--;
86 device_property_read_u32(dev, "snps,burst-map", &burst_map);
88 /* converts burst-map bitmask to burst array */
89 for (bit_index = 0; bit_index < 7; bit_index++) {
90 if (burst_map & (1 << bit_index)) {
93 plat_dat->axi->axi_blen[a_index] = 4; break;
95 plat_dat->axi->axi_blen[a_index] = 8; break;
97 plat_dat->axi->axi_blen[a_index] = 16; break;
99 plat_dat->axi->axi_blen[a_index] = 32; break;
101 plat_dat->axi->axi_blen[a_index] = 64; break;
103 plat_dat->axi->axi_blen[a_index] = 128; break;
105 plat_dat->axi->axi_blen[a_index] = 256; break;
113 /* dwc-qos needs GMAC4, AAL, TSO and PMT */
114 plat_dat->has_gmac4 = 1;
115 plat_dat->dma_cfg->aal = 1;
116 plat_dat->flags |= STMMAC_FLAG_TSO_EN;
122 static int dwc_qos_probe(struct platform_device *pdev,
123 struct plat_stmmacenet_data *plat_dat,
124 struct stmmac_resources *stmmac_res)
128 plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk");
129 if (IS_ERR(plat_dat->stmmac_clk)) {
130 dev_err(&pdev->dev, "apb_pclk clock not found.\n");
131 return PTR_ERR(plat_dat->stmmac_clk);
134 err = clk_prepare_enable(plat_dat->stmmac_clk);
136 dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n",
141 plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk");
142 if (IS_ERR(plat_dat->pclk)) {
143 dev_err(&pdev->dev, "phy_ref_clk clock not found.\n");
144 err = PTR_ERR(plat_dat->pclk);
148 err = clk_prepare_enable(plat_dat->pclk);
150 dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n",
158 clk_disable_unprepare(plat_dat->stmmac_clk);
162 static void dwc_qos_remove(struct platform_device *pdev)
164 struct net_device *ndev = platform_get_drvdata(pdev);
165 struct stmmac_priv *priv = netdev_priv(ndev);
167 clk_disable_unprepare(priv->plat->pclk);
168 clk_disable_unprepare(priv->plat->stmmac_clk);
171 #define SDMEMCOMPPADCTRL 0x8800
172 #define SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
174 #define AUTO_CAL_CONFIG 0x8804
175 #define AUTO_CAL_CONFIG_START BIT(31)
176 #define AUTO_CAL_CONFIG_ENABLE BIT(29)
178 #define AUTO_CAL_STATUS 0x880c
179 #define AUTO_CAL_STATUS_ACTIVE BIT(31)
181 static void tegra_eqos_fix_speed(void *priv, unsigned int speed, unsigned int mode)
183 struct tegra_eqos *eqos = priv;
184 unsigned long rate = 125000000;
185 bool needs_calibration = false;
191 needs_calibration = true;
196 needs_calibration = true;
205 dev_err(eqos->dev, "invalid speed %u\n", speed);
209 if (needs_calibration) {
211 value = readl(eqos->regs + SDMEMCOMPPADCTRL);
212 value |= SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
213 writel(value, eqos->regs + SDMEMCOMPPADCTRL);
217 value = readl(eqos->regs + AUTO_CAL_CONFIG);
218 value |= AUTO_CAL_CONFIG_START | AUTO_CAL_CONFIG_ENABLE;
219 writel(value, eqos->regs + AUTO_CAL_CONFIG);
221 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
223 value & AUTO_CAL_STATUS_ACTIVE,
226 dev_err(eqos->dev, "calibration did not start\n");
230 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS,
232 (value & AUTO_CAL_STATUS_ACTIVE) == 0,
235 dev_err(eqos->dev, "calibration didn't finish\n");
240 value = readl(eqos->regs + SDMEMCOMPPADCTRL);
241 value &= ~SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD;
242 writel(value, eqos->regs + SDMEMCOMPPADCTRL);
244 value = readl(eqos->regs + AUTO_CAL_CONFIG);
245 value &= ~AUTO_CAL_CONFIG_ENABLE;
246 writel(value, eqos->regs + AUTO_CAL_CONFIG);
249 err = clk_set_rate(eqos->clk_tx, rate);
251 dev_err(eqos->dev, "failed to set TX rate: %d\n", err);
254 static int tegra_eqos_init(struct platform_device *pdev, void *priv)
256 struct tegra_eqos *eqos = priv;
260 rate = clk_get_rate(eqos->clk_slave);
262 value = (rate / 1000000) - 1;
263 writel(value, eqos->regs + GMAC_1US_TIC_COUNTER);
268 static int tegra_eqos_probe(struct platform_device *pdev,
269 struct plat_stmmacenet_data *data,
270 struct stmmac_resources *res)
272 struct device *dev = &pdev->dev;
273 struct tegra_eqos *eqos;
276 eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL);
280 eqos->dev = &pdev->dev;
281 eqos->regs = res->addr;
283 if (!is_of_node(dev->fwnode))
284 goto bypass_clk_reset_gpio;
286 eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus");
287 if (IS_ERR(eqos->clk_master)) {
288 err = PTR_ERR(eqos->clk_master);
292 err = clk_prepare_enable(eqos->clk_master);
296 eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus");
297 if (IS_ERR(eqos->clk_slave)) {
298 err = PTR_ERR(eqos->clk_slave);
302 data->stmmac_clk = eqos->clk_slave;
304 err = clk_prepare_enable(eqos->clk_slave);
308 eqos->clk_rx = devm_clk_get(&pdev->dev, "rx");
309 if (IS_ERR(eqos->clk_rx)) {
310 err = PTR_ERR(eqos->clk_rx);
314 err = clk_prepare_enable(eqos->clk_rx);
318 eqos->clk_tx = devm_clk_get(&pdev->dev, "tx");
319 if (IS_ERR(eqos->clk_tx)) {
320 err = PTR_ERR(eqos->clk_tx);
324 err = clk_prepare_enable(eqos->clk_tx);
328 eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH);
329 if (IS_ERR(eqos->reset)) {
330 err = PTR_ERR(eqos->reset);
334 usleep_range(2000, 4000);
335 gpiod_set_value(eqos->reset, 0);
337 /* MDIO bus was already reset just above */
338 data->mdio_bus_data->needs_reset = false;
340 eqos->rst = devm_reset_control_get(&pdev->dev, "eqos");
341 if (IS_ERR(eqos->rst)) {
342 err = PTR_ERR(eqos->rst);
346 err = reset_control_assert(eqos->rst);
350 usleep_range(2000, 4000);
352 err = reset_control_deassert(eqos->rst);
356 usleep_range(2000, 4000);
358 bypass_clk_reset_gpio:
359 data->fix_mac_speed = tegra_eqos_fix_speed;
360 data->init = tegra_eqos_init;
361 data->bsp_priv = eqos;
362 data->flags |= STMMAC_FLAG_SPH_DISABLE;
364 err = tegra_eqos_init(pdev, eqos);
370 reset_control_assert(eqos->rst);
372 gpiod_set_value(eqos->reset, 1);
374 clk_disable_unprepare(eqos->clk_tx);
376 clk_disable_unprepare(eqos->clk_rx);
378 clk_disable_unprepare(eqos->clk_slave);
380 clk_disable_unprepare(eqos->clk_master);
385 static void tegra_eqos_remove(struct platform_device *pdev)
387 struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev);
389 reset_control_assert(eqos->rst);
390 gpiod_set_value(eqos->reset, 1);
391 clk_disable_unprepare(eqos->clk_tx);
392 clk_disable_unprepare(eqos->clk_rx);
393 clk_disable_unprepare(eqos->clk_slave);
394 clk_disable_unprepare(eqos->clk_master);
397 struct dwc_eth_dwmac_data {
398 int (*probe)(struct platform_device *pdev,
399 struct plat_stmmacenet_data *data,
400 struct stmmac_resources *res);
401 void (*remove)(struct platform_device *pdev);
404 static const struct dwc_eth_dwmac_data dwc_qos_data = {
405 .probe = dwc_qos_probe,
406 .remove = dwc_qos_remove,
409 static const struct dwc_eth_dwmac_data tegra_eqos_data = {
410 .probe = tegra_eqos_probe,
411 .remove = tegra_eqos_remove,
414 static int dwc_eth_dwmac_probe(struct platform_device *pdev)
416 const struct dwc_eth_dwmac_data *data;
417 struct plat_stmmacenet_data *plat_dat;
418 struct stmmac_resources stmmac_res;
421 data = device_get_match_data(&pdev->dev);
423 memset(&stmmac_res, 0, sizeof(struct stmmac_resources));
426 * Since stmmac_platform supports name IRQ only, basic platform
427 * resource initialization is done in the glue logic.
429 stmmac_res.irq = platform_get_irq(pdev, 0);
430 if (stmmac_res.irq < 0)
431 return stmmac_res.irq;
432 stmmac_res.wol_irq = stmmac_res.irq;
434 stmmac_res.addr = devm_platform_ioremap_resource(pdev, 0);
435 if (IS_ERR(stmmac_res.addr))
436 return PTR_ERR(stmmac_res.addr);
438 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
439 if (IS_ERR(plat_dat))
440 return PTR_ERR(plat_dat);
442 ret = data->probe(pdev, plat_dat, &stmmac_res);
444 dev_err_probe(&pdev->dev, ret, "failed to probe subdriver\n");
449 ret = dwc_eth_dwmac_config_dt(pdev, plat_dat);
453 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
462 stmmac_remove_config_dt(pdev, plat_dat);
467 static void dwc_eth_dwmac_remove(struct platform_device *pdev)
469 struct net_device *ndev = platform_get_drvdata(pdev);
470 struct stmmac_priv *priv = netdev_priv(ndev);
471 const struct dwc_eth_dwmac_data *data;
473 data = device_get_match_data(&pdev->dev);
475 stmmac_dvr_remove(&pdev->dev);
479 stmmac_remove_config_dt(pdev, priv->plat);
482 static const struct of_device_id dwc_eth_dwmac_match[] = {
483 { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
484 { .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
487 MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
489 static struct platform_driver dwc_eth_dwmac_driver = {
490 .probe = dwc_eth_dwmac_probe,
491 .remove_new = dwc_eth_dwmac_remove,
493 .name = "dwc-eth-dwmac",
494 .pm = &stmmac_pltfr_pm_ops,
495 .of_match_table = dwc_eth_dwmac_match,
498 module_platform_driver(dwc_eth_dwmac_driver);
500 MODULE_AUTHOR("Joao Pinto <jpinto@synopsys.com>");
501 MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver");
502 MODULE_LICENSE("GPL v2");