1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
4 * Copyright 2014 Panasonic Corporation
5 * Copyright 2015-2017 Socionext Inc.
8 #include <linux/bitops.h>
10 #include <linux/etherdevice.h>
11 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/mii.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/of_net.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_platform.h>
21 #include <linux/phy.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
25 #include <linux/u64_stats_sync.h>
27 /* General Register Group */
28 #define AVE_IDR 0x000 /* ID */
29 #define AVE_VR 0x004 /* Version */
30 #define AVE_GRR 0x008 /* Global Reset */
31 #define AVE_CFGR 0x00c /* Configuration */
33 /* Interrupt Register Group */
34 #define AVE_GIMR 0x100 /* Global Interrupt Mask */
35 #define AVE_GISR 0x104 /* Global Interrupt Status */
37 /* MAC Register Group */
38 #define AVE_TXCR 0x200 /* TX Setup */
39 #define AVE_RXCR 0x204 /* RX Setup */
40 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
41 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
42 #define AVE_MDIOCTR 0x214 /* MDIO Control */
43 #define AVE_MDIOAR 0x218 /* MDIO Address */
44 #define AVE_MDIOWDR 0x21c /* MDIO Data */
45 #define AVE_MDIOSR 0x220 /* MDIO Status */
46 #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
48 /* Descriptor Control Register Group */
49 #define AVE_DESCC 0x300 /* Descriptor Control */
50 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
51 #define AVE_RXDC0 0x308 /* RX Descriptor Ring0 Configuration */
52 #define AVE_IIRQC 0x34c /* Interval IRQ Control */
54 /* Packet Filter Register Group */
55 #define AVE_PKTF_BASE 0x800 /* PF Base Address */
56 #define AVE_PFMBYTE_BASE 0xd00 /* PF Mask Byte Base Address */
57 #define AVE_PFMBIT_BASE 0xe00 /* PF Mask Bit Base Address */
58 #define AVE_PFSEL_BASE 0xf00 /* PF Selector Base Address */
59 #define AVE_PFEN 0xffc /* Packet Filter Enable */
60 #define AVE_PKTF(ent) (AVE_PKTF_BASE + (ent) * 0x40)
61 #define AVE_PFMBYTE(ent) (AVE_PFMBYTE_BASE + (ent) * 8)
62 #define AVE_PFMBIT(ent) (AVE_PFMBIT_BASE + (ent) * 4)
63 #define AVE_PFSEL(ent) (AVE_PFSEL_BASE + (ent) * 4)
65 /* 64bit descriptor memory */
66 #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
68 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
69 #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
71 #define AVE_TXDM_SIZE_64 0x0ba0 /* Tx Descriptor Memory Size 3KB */
72 #define AVE_RXDM_SIZE_64 0x6000 /* Rx Descriptor Memory Size 24KB */
74 /* 32bit descriptor memory */
75 #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
77 #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
78 #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
80 #define AVE_TXDM_SIZE_32 0x07c0 /* Tx Descriptor Memory Size 2KB */
81 #define AVE_RXDM_SIZE_32 0x4000 /* Rx Descriptor Memory Size 16KB */
83 /* RMII Bridge Register Group */
84 #define AVE_RSTCTRL 0x8028 /* Reset control */
85 #define AVE_RSTCTRL_RMIIRST BIT(16)
86 #define AVE_LINKSEL 0x8034 /* Link speed setting */
87 #define AVE_LINKSEL_100M BIT(0)
90 #define AVE_GRR_RXFFR BIT(5) /* Reset RxFIFO */
91 #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
92 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
95 #define AVE_CFGR_FLE BIT(31) /* Filter Function */
96 #define AVE_CFGR_CHE BIT(30) /* Checksum Function */
97 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
98 #define AVE_CFGR_IPFCEN BIT(24) /* IP fragment sum Enable */
100 /* AVE_GISR (common with GIMR) */
101 #define AVE_GI_PHY BIT(24) /* PHY interrupt */
102 #define AVE_GI_TX BIT(16) /* Tx complete */
103 #define AVE_GI_RXERR BIT(8) /* Receive frame more than max size */
104 #define AVE_GI_RXOVF BIT(7) /* Overflow at the RxFIFO */
105 #define AVE_GI_RXDROP BIT(6) /* Drop packet */
106 #define AVE_GI_RXIINT BIT(5) /* Interval interrupt */
109 #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
110 #define AVE_TXCR_TXSPD_1G BIT(17)
111 #define AVE_TXCR_TXSPD_100 BIT(16)
114 #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
115 #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
116 #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
117 #define AVE_RXCR_AFEN BIT(19) /* MAC address filter */
118 #define AVE_RXCR_DRPEN BIT(18) /* Drop pause frame */
119 #define AVE_RXCR_MPSIZ_MASK GENMASK(10, 0)
122 #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
123 #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
126 #define AVE_MDIOSR_STS BIT(0) /* access status */
129 #define AVE_DESCC_STATUS_MASK GENMASK(31, 16)
130 #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
131 #define AVE_DESCC_RDSTP BIT(4) /* Pause Rx descriptor */
132 #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
135 #define AVE_TXDC_SIZE GENMASK(27, 16) /* Size of Tx descriptor */
136 #define AVE_TXDC_ADDR GENMASK(11, 0) /* Start address */
137 #define AVE_TXDC_ADDR_START 0
140 #define AVE_RXDC0_SIZE GENMASK(30, 16) /* Size of Rx descriptor */
141 #define AVE_RXDC0_ADDR GENMASK(14, 0) /* Start address */
142 #define AVE_RXDC0_ADDR_START 0
145 #define AVE_IIRQC_EN0 BIT(27) /* Enable interval interrupt Ring0 */
146 #define AVE_IIRQC_BSCK GENMASK(15, 0) /* Interval count unit */
148 /* Command status for descriptor */
149 #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
150 #define AVE_STS_INTR BIT(29) /* Request for interrupt */
151 #define AVE_STS_OK BIT(27) /* Normal transmit */
153 #define AVE_STS_NOCSUM BIT(28) /* No use HW checksum */
154 #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
155 #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
156 #define AVE_STS_OWC BIT(21) /* Out of window,Late Collision */
157 #define AVE_STS_EC BIT(20) /* Excess collision occurred */
158 #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
160 #define AVE_STS_CSSV BIT(21) /* Checksum check performed */
161 #define AVE_STS_CSER BIT(20) /* Checksum error detected */
162 #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
165 #define AVE_PFMBYTE_MASK0 (GENMASK(31, 8) | GENMASK(5, 0))
166 #define AVE_PFMBYTE_MASK1 GENMASK(25, 0)
167 #define AVE_PFMBIT_MASK GENMASK(15, 0)
169 #define AVE_PF_SIZE 17 /* Number of all packet filter */
170 #define AVE_PF_MULTICAST_SIZE 7 /* Number of multicast filter */
172 #define AVE_PFNUM_FILTER 0 /* No.0 */
173 #define AVE_PFNUM_UNICAST 1 /* No.1 */
174 #define AVE_PFNUM_BROADCAST 2 /* No.2 */
175 #define AVE_PFNUM_MULTICAST 11 /* No.11-17 */
177 /* NETIF Message control */
178 #define AVE_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
187 /* Parameter for descriptor */
188 #define AVE_NR_TXDESC 32 /* Tx descriptor */
189 #define AVE_NR_RXDESC 64 /* Rx descriptor */
191 #define AVE_DESC_OFS_CMDSTS 0
192 #define AVE_DESC_OFS_ADDRL 4
193 #define AVE_DESC_OFS_ADDRU 8
195 /* Parameter for ethernet frame */
196 #define AVE_MAX_ETHFRAME 1518
198 /* Parameter for interrupt */
199 #define AVE_INTM_COUNT 20
200 #define AVE_FORCE_TXINTCNT 1
203 #define SG_ETPINMODE 0x540
204 #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
205 #define SG_ETPINMODE_RMII(ins) BIT(ins)
207 #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit)
209 #define AVE_MAX_CLKS 4
210 #define AVE_MAX_RSTS 2
225 struct sk_buff *skbs;
230 struct ave_desc_info {
231 u32 ndesc; /* number of descriptor */
232 u32 daddr; /* start address of descriptor */
233 u32 proc_idx; /* index of processing packet */
234 u32 done_idx; /* index of processed packet */
235 struct ave_desc *desc; /* skb info related descriptor */
239 struct u64_stats_sync syncp;
252 unsigned int desc_size;
255 struct clk *clk[AVE_MAX_CLKS];
257 struct reset_control *rst[AVE_MAX_RSTS];
258 phy_interface_t phy_mode;
259 struct phy_device *phydev;
260 struct mii_bus *mdio;
261 struct regmap *regmap;
262 unsigned int pinmode_mask;
263 unsigned int pinmode_val;
266 struct ave_stats stats_rx;
267 struct ave_stats stats_tx;
270 struct net_device *ndev;
271 struct napi_struct napi_rx;
272 struct napi_struct napi_tx;
275 struct ave_desc_info rx;
276 struct ave_desc_info tx;
283 const struct ave_soc_data *data;
286 struct ave_soc_data {
288 const char *clock_names[AVE_MAX_CLKS];
289 const char *reset_names[AVE_MAX_RSTS];
290 int (*get_pinmode)(struct ave_private *priv,
291 phy_interface_t phy_mode, u32 arg);
294 static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry,
297 struct ave_private *priv = netdev_priv(ndev);
300 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr)
301 + entry * priv->desc_size + offset;
303 return readl(priv->base + addr);
306 static u32 ave_desc_read_cmdsts(struct net_device *ndev, enum desc_id id,
309 return ave_desc_read(ndev, id, entry, AVE_DESC_OFS_CMDSTS);
312 static void ave_desc_write(struct net_device *ndev, enum desc_id id,
313 int entry, int offset, u32 val)
315 struct ave_private *priv = netdev_priv(ndev);
318 addr = ((id == AVE_DESCID_TX) ? priv->tx.daddr : priv->rx.daddr)
319 + entry * priv->desc_size + offset;
321 writel(val, priv->base + addr);
324 static void ave_desc_write_cmdsts(struct net_device *ndev, enum desc_id id,
327 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_CMDSTS, val);
330 static void ave_desc_write_addr(struct net_device *ndev, enum desc_id id,
331 int entry, dma_addr_t paddr)
333 struct ave_private *priv = netdev_priv(ndev);
335 ave_desc_write(ndev, id, entry, AVE_DESC_OFS_ADDRL,
336 lower_32_bits(paddr));
337 if (IS_DESC_64BIT(priv))
338 ave_desc_write(ndev, id,
339 entry, AVE_DESC_OFS_ADDRU,
340 upper_32_bits(paddr));
343 static u32 ave_irq_disable_all(struct net_device *ndev)
345 struct ave_private *priv = netdev_priv(ndev);
348 ret = readl(priv->base + AVE_GIMR);
349 writel(0, priv->base + AVE_GIMR);
354 static void ave_irq_restore(struct net_device *ndev, u32 val)
356 struct ave_private *priv = netdev_priv(ndev);
358 writel(val, priv->base + AVE_GIMR);
361 static void ave_irq_enable(struct net_device *ndev, u32 bitflag)
363 struct ave_private *priv = netdev_priv(ndev);
365 writel(readl(priv->base + AVE_GIMR) | bitflag, priv->base + AVE_GIMR);
366 writel(bitflag, priv->base + AVE_GISR);
369 static void ave_hw_write_macaddr(struct net_device *ndev,
370 const unsigned char *mac_addr,
373 struct ave_private *priv = netdev_priv(ndev);
375 writel(mac_addr[0] | mac_addr[1] << 8 |
376 mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1);
377 writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2);
380 static void ave_hw_read_version(struct net_device *ndev, char *buf, int len)
382 struct ave_private *priv = netdev_priv(ndev);
383 u32 major, minor, vr;
385 vr = readl(priv->base + AVE_VR);
386 major = (vr & GENMASK(15, 8)) >> 8;
387 minor = (vr & GENMASK(7, 0));
388 snprintf(buf, len, "v%u.%u", major, minor);
391 static void ave_ethtool_get_drvinfo(struct net_device *ndev,
392 struct ethtool_drvinfo *info)
394 struct device *dev = ndev->dev.parent;
396 strlcpy(info->driver, dev->driver->name, sizeof(info->driver));
397 strlcpy(info->bus_info, dev_name(dev), sizeof(info->bus_info));
398 ave_hw_read_version(ndev, info->fw_version, sizeof(info->fw_version));
401 static u32 ave_ethtool_get_msglevel(struct net_device *ndev)
403 struct ave_private *priv = netdev_priv(ndev);
405 return priv->msg_enable;
408 static void ave_ethtool_set_msglevel(struct net_device *ndev, u32 val)
410 struct ave_private *priv = netdev_priv(ndev);
412 priv->msg_enable = val;
415 static void ave_ethtool_get_wol(struct net_device *ndev,
416 struct ethtool_wolinfo *wol)
422 phy_ethtool_get_wol(ndev->phydev, wol);
425 static int ave_ethtool_set_wol(struct net_device *ndev,
426 struct ethtool_wolinfo *wol)
431 (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)))
434 ret = phy_ethtool_set_wol(ndev->phydev, wol);
436 device_set_wakeup_enable(&ndev->dev, !!wol->wolopts);
441 static void ave_ethtool_get_pauseparam(struct net_device *ndev,
442 struct ethtool_pauseparam *pause)
444 struct ave_private *priv = netdev_priv(ndev);
446 pause->autoneg = priv->pause_auto;
447 pause->rx_pause = priv->pause_rx;
448 pause->tx_pause = priv->pause_tx;
451 static int ave_ethtool_set_pauseparam(struct net_device *ndev,
452 struct ethtool_pauseparam *pause)
454 struct ave_private *priv = netdev_priv(ndev);
455 struct phy_device *phydev = ndev->phydev;
460 priv->pause_auto = pause->autoneg;
461 priv->pause_rx = pause->rx_pause;
462 priv->pause_tx = pause->tx_pause;
464 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
469 static const struct ethtool_ops ave_ethtool_ops = {
470 .get_link_ksettings = phy_ethtool_get_link_ksettings,
471 .set_link_ksettings = phy_ethtool_set_link_ksettings,
472 .get_drvinfo = ave_ethtool_get_drvinfo,
473 .nway_reset = phy_ethtool_nway_reset,
474 .get_link = ethtool_op_get_link,
475 .get_msglevel = ave_ethtool_get_msglevel,
476 .set_msglevel = ave_ethtool_set_msglevel,
477 .get_wol = ave_ethtool_get_wol,
478 .set_wol = ave_ethtool_set_wol,
479 .get_pauseparam = ave_ethtool_get_pauseparam,
480 .set_pauseparam = ave_ethtool_set_pauseparam,
483 static int ave_mdiobus_read(struct mii_bus *bus, int phyid, int regnum)
485 struct net_device *ndev = bus->priv;
486 struct ave_private *priv;
490 priv = netdev_priv(ndev);
493 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR);
496 mdioctl = readl(priv->base + AVE_MDIOCTR);
497 writel((mdioctl | AVE_MDIOCTR_RREQ) & ~AVE_MDIOCTR_WREQ,
498 priv->base + AVE_MDIOCTR);
500 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr,
501 !(mdiosr & AVE_MDIOSR_STS), 20, 2000);
503 netdev_err(ndev, "failed to read (phy:%d reg:%x)\n",
508 return readl(priv->base + AVE_MDIORDR) & GENMASK(15, 0);
511 static int ave_mdiobus_write(struct mii_bus *bus, int phyid, int regnum,
514 struct net_device *ndev = bus->priv;
515 struct ave_private *priv;
519 priv = netdev_priv(ndev);
522 writel((phyid << 8) | regnum, priv->base + AVE_MDIOAR);
525 writel(val, priv->base + AVE_MDIOWDR);
528 mdioctl = readl(priv->base + AVE_MDIOCTR);
529 writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
530 priv->base + AVE_MDIOCTR);
532 ret = readl_poll_timeout(priv->base + AVE_MDIOSR, mdiosr,
533 !(mdiosr & AVE_MDIOSR_STS), 20, 2000);
535 netdev_err(ndev, "failed to write (phy:%d reg:%x)\n",
541 static int ave_dma_map(struct net_device *ndev, struct ave_desc *desc,
542 void *ptr, size_t len, enum dma_data_direction dir,
547 map_addr = dma_map_single(ndev->dev.parent, ptr, len, dir);
548 if (unlikely(dma_mapping_error(ndev->dev.parent, map_addr)))
551 desc->skbs_dma = map_addr;
552 desc->skbs_dmalen = len;
558 static void ave_dma_unmap(struct net_device *ndev, struct ave_desc *desc,
559 enum dma_data_direction dir)
564 dma_unmap_single(ndev->dev.parent,
565 desc->skbs_dma, desc->skbs_dmalen, dir);
569 /* Prepare Rx descriptor and memory */
570 static int ave_rxdesc_prepare(struct net_device *ndev, int entry)
572 struct ave_private *priv = netdev_priv(ndev);
577 skb = priv->rx.desc[entry].skbs;
579 skb = netdev_alloc_skb_ip_align(ndev,
582 netdev_err(ndev, "can't allocate skb for Rx\n");
587 /* set disable to cmdsts */
588 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry,
589 AVE_STS_INTR | AVE_STS_OWN);
592 * Rx buffer set to the Rx descriptor has two restrictions:
593 * - Rx buffer address is 4 byte aligned.
594 * - Rx buffer begins with 2 byte headroom, and data will be put from
596 * To satisfy this, specify the address to put back the buffer
597 * pointer advanced by NET_IP_ALIGN by netdev_alloc_skb_ip_align(),
598 * and expand the map size by NET_IP_ALIGN.
600 ret = ave_dma_map(ndev, &priv->rx.desc[entry],
601 skb->data - NET_IP_ALIGN,
602 AVE_MAX_ETHFRAME + NET_IP_ALIGN,
603 DMA_FROM_DEVICE, &paddr);
605 netdev_err(ndev, "can't map skb for Rx\n");
606 dev_kfree_skb_any(skb);
609 priv->rx.desc[entry].skbs = skb;
611 /* set buffer pointer */
612 ave_desc_write_addr(ndev, AVE_DESCID_RX, entry, paddr);
614 /* set enable to cmdsts */
615 ave_desc_write_cmdsts(ndev, AVE_DESCID_RX, entry,
616 AVE_STS_INTR | AVE_MAX_ETHFRAME);
621 /* Switch state of descriptor */
622 static int ave_desc_switch(struct net_device *ndev, enum desc_state state)
624 struct ave_private *priv = netdev_priv(ndev);
630 writel(AVE_DESCC_TD | AVE_DESCC_RD0, priv->base + AVE_DESCC);
634 writel(0, priv->base + AVE_DESCC);
635 if (readl_poll_timeout(priv->base + AVE_DESCC, val, !val,
637 netdev_err(ndev, "can't stop descriptor\n");
642 case AVE_DESC_RX_SUSPEND:
643 val = readl(priv->base + AVE_DESCC);
644 val |= AVE_DESCC_RDSTP;
645 val &= ~AVE_DESCC_STATUS_MASK;
646 writel(val, priv->base + AVE_DESCC);
647 if (readl_poll_timeout(priv->base + AVE_DESCC, val,
648 val & (AVE_DESCC_RDSTP << 16),
650 netdev_err(ndev, "can't suspend descriptor\n");
655 case AVE_DESC_RX_PERMIT:
656 val = readl(priv->base + AVE_DESCC);
657 val &= ~AVE_DESCC_RDSTP;
658 val &= ~AVE_DESCC_STATUS_MASK;
659 writel(val, priv->base + AVE_DESCC);
670 static int ave_tx_complete(struct net_device *ndev)
672 struct ave_private *priv = netdev_priv(ndev);
673 u32 proc_idx, done_idx, ndesc, cmdsts;
674 unsigned int nr_freebuf = 0;
675 unsigned int tx_packets = 0;
676 unsigned int tx_bytes = 0;
678 proc_idx = priv->tx.proc_idx;
679 done_idx = priv->tx.done_idx;
680 ndesc = priv->tx.ndesc;
682 /* free pre-stored skb from done_idx to proc_idx */
683 while (proc_idx != done_idx) {
684 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_TX, done_idx);
686 /* do nothing if owner is HW (==1 for Tx) */
687 if (cmdsts & AVE_STS_OWN)
690 /* check Tx status and updates statistics */
691 if (cmdsts & AVE_STS_OK) {
692 tx_bytes += cmdsts & AVE_STS_PKTLEN_TX_MASK;
694 if (cmdsts & AVE_STS_LAST)
698 if (cmdsts & AVE_STS_LAST) {
699 priv->stats_tx.errors++;
700 if (cmdsts & (AVE_STS_OWC | AVE_STS_EC))
701 priv->stats_tx.collisions++;
706 if (priv->tx.desc[done_idx].skbs) {
707 ave_dma_unmap(ndev, &priv->tx.desc[done_idx],
709 dev_consume_skb_any(priv->tx.desc[done_idx].skbs);
710 priv->tx.desc[done_idx].skbs = NULL;
713 done_idx = (done_idx + 1) % ndesc;
716 priv->tx.done_idx = done_idx;
719 u64_stats_update_begin(&priv->stats_tx.syncp);
720 priv->stats_tx.packets += tx_packets;
721 priv->stats_tx.bytes += tx_bytes;
722 u64_stats_update_end(&priv->stats_tx.syncp);
724 /* wake queue for freeing buffer */
725 if (unlikely(netif_queue_stopped(ndev)) && nr_freebuf)
726 netif_wake_queue(ndev);
731 static int ave_rx_receive(struct net_device *ndev, int num)
733 struct ave_private *priv = netdev_priv(ndev);
734 unsigned int rx_packets = 0;
735 unsigned int rx_bytes = 0;
736 u32 proc_idx, done_idx;
742 proc_idx = priv->rx.proc_idx;
743 done_idx = priv->rx.done_idx;
744 ndesc = priv->rx.ndesc;
745 restpkt = ((proc_idx + ndesc - 1) - done_idx) % ndesc;
747 for (npkts = 0; npkts < num; npkts++) {
748 /* we can't receive more packet, so fill desc quickly */
752 cmdsts = ave_desc_read_cmdsts(ndev, AVE_DESCID_RX, proc_idx);
754 /* do nothing if owner is HW (==0 for Rx) */
755 if (!(cmdsts & AVE_STS_OWN))
758 if (!(cmdsts & AVE_STS_OK)) {
759 priv->stats_rx.errors++;
760 proc_idx = (proc_idx + 1) % ndesc;
764 pktlen = cmdsts & AVE_STS_PKTLEN_RX_MASK;
766 /* get skbuff for rx */
767 skb = priv->rx.desc[proc_idx].skbs;
768 priv->rx.desc[proc_idx].skbs = NULL;
770 ave_dma_unmap(ndev, &priv->rx.desc[proc_idx], DMA_FROM_DEVICE);
773 skb_put(skb, pktlen);
774 skb->protocol = eth_type_trans(skb, ndev);
776 if ((cmdsts & AVE_STS_CSSV) && (!(cmdsts & AVE_STS_CSER)))
777 skb->ip_summed = CHECKSUM_UNNECESSARY;
782 netif_receive_skb(skb);
784 proc_idx = (proc_idx + 1) % ndesc;
787 priv->rx.proc_idx = proc_idx;
790 u64_stats_update_begin(&priv->stats_rx.syncp);
791 priv->stats_rx.packets += rx_packets;
792 priv->stats_rx.bytes += rx_bytes;
793 u64_stats_update_end(&priv->stats_rx.syncp);
795 /* refill the Rx buffers */
796 while (proc_idx != done_idx) {
797 if (ave_rxdesc_prepare(ndev, done_idx))
799 done_idx = (done_idx + 1) % ndesc;
802 priv->rx.done_idx = done_idx;
807 static int ave_napi_poll_rx(struct napi_struct *napi, int budget)
809 struct ave_private *priv;
810 struct net_device *ndev;
813 priv = container_of(napi, struct ave_private, napi_rx);
816 num = ave_rx_receive(ndev, budget);
818 napi_complete_done(napi, num);
820 /* enable Rx interrupt when NAPI finishes */
821 ave_irq_enable(ndev, AVE_GI_RXIINT);
827 static int ave_napi_poll_tx(struct napi_struct *napi, int budget)
829 struct ave_private *priv;
830 struct net_device *ndev;
833 priv = container_of(napi, struct ave_private, napi_tx);
836 num = ave_tx_complete(ndev);
839 /* enable Tx interrupt when NAPI finishes */
840 ave_irq_enable(ndev, AVE_GI_TX);
845 static void ave_global_reset(struct net_device *ndev)
847 struct ave_private *priv = netdev_priv(ndev);
850 /* set config register */
851 val = AVE_CFGR_FLE | AVE_CFGR_IPFCEN | AVE_CFGR_CHE;
852 if (!phy_interface_mode_is_rgmii(priv->phy_mode))
854 writel(val, priv->base + AVE_CFGR);
856 /* reset RMII register */
857 val = readl(priv->base + AVE_RSTCTRL);
858 val &= ~AVE_RSTCTRL_RMIIRST;
859 writel(val, priv->base + AVE_RSTCTRL);
862 writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->base + AVE_GRR);
865 /* 1st, negate PHY reset only */
866 writel(AVE_GRR_GRST, priv->base + AVE_GRR);
870 writel(0, priv->base + AVE_GRR);
873 /* negate RMII register */
874 val = readl(priv->base + AVE_RSTCTRL);
875 val |= AVE_RSTCTRL_RMIIRST;
876 writel(val, priv->base + AVE_RSTCTRL);
878 ave_irq_disable_all(ndev);
881 static void ave_rxfifo_reset(struct net_device *ndev)
883 struct ave_private *priv = netdev_priv(ndev);
886 /* save and disable MAC receive op */
887 rxcr_org = readl(priv->base + AVE_RXCR);
888 writel(rxcr_org & (~AVE_RXCR_RXEN), priv->base + AVE_RXCR);
890 /* suspend Rx descriptor */
891 ave_desc_switch(ndev, AVE_DESC_RX_SUSPEND);
893 /* receive all packets before descriptor starts */
894 ave_rx_receive(ndev, priv->rx.ndesc);
897 writel(AVE_GRR_RXFFR, priv->base + AVE_GRR);
901 writel(0, priv->base + AVE_GRR);
904 /* negate interrupt status */
905 writel(AVE_GI_RXOVF, priv->base + AVE_GISR);
907 /* permit descriptor */
908 ave_desc_switch(ndev, AVE_DESC_RX_PERMIT);
910 /* restore MAC reccieve op */
911 writel(rxcr_org, priv->base + AVE_RXCR);
914 static irqreturn_t ave_irq_handler(int irq, void *netdev)
916 struct net_device *ndev = (struct net_device *)netdev;
917 struct ave_private *priv = netdev_priv(ndev);
918 u32 gimr_val, gisr_val;
920 gimr_val = ave_irq_disable_all(ndev);
922 /* get interrupt status */
923 gisr_val = readl(priv->base + AVE_GISR);
926 if (gisr_val & AVE_GI_PHY)
927 writel(AVE_GI_PHY, priv->base + AVE_GISR);
929 /* check exceeding packet */
930 if (gisr_val & AVE_GI_RXERR) {
931 writel(AVE_GI_RXERR, priv->base + AVE_GISR);
932 netdev_err(ndev, "receive a packet exceeding frame buffer\n");
935 gisr_val &= gimr_val;
939 /* RxFIFO overflow */
940 if (gisr_val & AVE_GI_RXOVF) {
941 priv->stats_rx.fifo_errors++;
942 ave_rxfifo_reset(ndev);
947 if (gisr_val & AVE_GI_RXDROP) {
948 priv->stats_rx.dropped++;
949 writel(AVE_GI_RXDROP, priv->base + AVE_GISR);
953 if (gisr_val & AVE_GI_RXIINT) {
954 napi_schedule(&priv->napi_rx);
955 /* still force to disable Rx interrupt until NAPI finishes */
956 gimr_val &= ~AVE_GI_RXIINT;
960 if (gisr_val & AVE_GI_TX) {
961 napi_schedule(&priv->napi_tx);
962 /* still force to disable Tx interrupt until NAPI finishes */
963 gimr_val &= ~AVE_GI_TX;
967 ave_irq_restore(ndev, gimr_val);
972 static int ave_pfsel_start(struct net_device *ndev, unsigned int entry)
974 struct ave_private *priv = netdev_priv(ndev);
977 if (WARN_ON(entry > AVE_PF_SIZE))
980 val = readl(priv->base + AVE_PFEN);
981 writel(val | BIT(entry), priv->base + AVE_PFEN);
986 static int ave_pfsel_stop(struct net_device *ndev, unsigned int entry)
988 struct ave_private *priv = netdev_priv(ndev);
991 if (WARN_ON(entry > AVE_PF_SIZE))
994 val = readl(priv->base + AVE_PFEN);
995 writel(val & ~BIT(entry), priv->base + AVE_PFEN);
1000 static int ave_pfsel_set_macaddr(struct net_device *ndev,
1002 const unsigned char *mac_addr,
1003 unsigned int set_size)
1005 struct ave_private *priv = netdev_priv(ndev);
1007 if (WARN_ON(entry > AVE_PF_SIZE))
1009 if (WARN_ON(set_size > 6))
1012 ave_pfsel_stop(ndev, entry);
1014 /* set MAC address for the filter */
1015 ave_hw_write_macaddr(ndev, mac_addr,
1016 AVE_PKTF(entry), AVE_PKTF(entry) + 4);
1019 writel(GENMASK(31, set_size) & AVE_PFMBYTE_MASK0,
1020 priv->base + AVE_PFMBYTE(entry));
1021 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4);
1023 /* set bit mask filter */
1024 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry));
1026 /* set selector to ring 0 */
1027 writel(0, priv->base + AVE_PFSEL(entry));
1029 /* restart filter */
1030 ave_pfsel_start(ndev, entry);
1035 static void ave_pfsel_set_promisc(struct net_device *ndev,
1036 unsigned int entry, u32 rxring)
1038 struct ave_private *priv = netdev_priv(ndev);
1040 if (WARN_ON(entry > AVE_PF_SIZE))
1043 ave_pfsel_stop(ndev, entry);
1046 writel(AVE_PFMBYTE_MASK0, priv->base + AVE_PFMBYTE(entry));
1047 writel(AVE_PFMBYTE_MASK1, priv->base + AVE_PFMBYTE(entry) + 4);
1049 /* set bit mask filter */
1050 writel(AVE_PFMBIT_MASK, priv->base + AVE_PFMBIT(entry));
1052 /* set selector to rxring */
1053 writel(rxring, priv->base + AVE_PFSEL(entry));
1055 ave_pfsel_start(ndev, entry);
1058 static void ave_pfsel_init(struct net_device *ndev)
1060 unsigned char bcast_mac[ETH_ALEN];
1063 eth_broadcast_addr(bcast_mac);
1065 for (i = 0; i < AVE_PF_SIZE; i++)
1066 ave_pfsel_stop(ndev, i);
1068 /* promiscious entry, select ring 0 */
1069 ave_pfsel_set_promisc(ndev, AVE_PFNUM_FILTER, 0);
1072 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6);
1074 /* broadcast entry */
1075 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_BROADCAST, bcast_mac, 6);
1078 static void ave_phy_adjust_link(struct net_device *ndev)
1080 struct ave_private *priv = netdev_priv(ndev);
1081 struct phy_device *phydev = ndev->phydev;
1082 u32 val, txcr, rxcr, rxcr_org;
1083 u16 rmt_adv = 0, lcl_adv = 0;
1086 /* set RGMII speed */
1087 val = readl(priv->base + AVE_TXCR);
1088 val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
1090 if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
1091 val |= AVE_TXCR_TXSPD_1G;
1092 else if (phydev->speed == SPEED_100)
1093 val |= AVE_TXCR_TXSPD_100;
1095 writel(val, priv->base + AVE_TXCR);
1097 /* set RMII speed (100M/10M only) */
1098 if (!phy_interface_is_rgmii(phydev)) {
1099 val = readl(priv->base + AVE_LINKSEL);
1100 if (phydev->speed == SPEED_10)
1101 val &= ~AVE_LINKSEL_100M;
1103 val |= AVE_LINKSEL_100M;
1104 writel(val, priv->base + AVE_LINKSEL);
1107 /* check current RXCR/TXCR */
1108 rxcr = readl(priv->base + AVE_RXCR);
1109 txcr = readl(priv->base + AVE_TXCR);
1112 if (phydev->duplex) {
1113 rxcr |= AVE_RXCR_FDUPEN;
1116 rmt_adv |= LPA_PAUSE_CAP;
1117 if (phydev->asym_pause)
1118 rmt_adv |= LPA_PAUSE_ASYM;
1120 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1121 cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1122 if (cap & FLOW_CTRL_TX)
1123 txcr |= AVE_TXCR_FLOCTR;
1125 txcr &= ~AVE_TXCR_FLOCTR;
1126 if (cap & FLOW_CTRL_RX)
1127 rxcr |= AVE_RXCR_FLOCTR;
1129 rxcr &= ~AVE_RXCR_FLOCTR;
1131 rxcr &= ~AVE_RXCR_FDUPEN;
1132 rxcr &= ~AVE_RXCR_FLOCTR;
1133 txcr &= ~AVE_TXCR_FLOCTR;
1136 if (rxcr_org != rxcr) {
1137 /* disable Rx mac */
1138 writel(rxcr & ~AVE_RXCR_RXEN, priv->base + AVE_RXCR);
1139 /* change and enable TX/Rx mac */
1140 writel(txcr, priv->base + AVE_TXCR);
1141 writel(rxcr, priv->base + AVE_RXCR);
1144 phy_print_status(phydev);
1147 static void ave_macaddr_init(struct net_device *ndev)
1149 ave_hw_write_macaddr(ndev, ndev->dev_addr, AVE_RXMAC1R, AVE_RXMAC2R);
1151 /* pfsel unicast entry */
1152 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_UNICAST, ndev->dev_addr, 6);
1155 static int ave_init(struct net_device *ndev)
1157 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL };
1158 struct ave_private *priv = netdev_priv(ndev);
1159 struct device *dev = ndev->dev.parent;
1160 struct device_node *np = dev->of_node;
1161 struct device_node *mdio_np;
1162 struct phy_device *phydev;
1165 /* enable clk because of hw access until ndo_open */
1166 for (nc = 0; nc < priv->nclks; nc++) {
1167 ret = clk_prepare_enable(priv->clk[nc]);
1169 dev_err(dev, "can't enable clock\n");
1170 goto out_clk_disable;
1174 for (nr = 0; nr < priv->nrsts; nr++) {
1175 ret = reset_control_deassert(priv->rst[nr]);
1177 dev_err(dev, "can't deassert reset\n");
1178 goto out_reset_assert;
1182 ret = regmap_update_bits(priv->regmap, SG_ETPINMODE,
1183 priv->pinmode_mask, priv->pinmode_val);
1187 ave_global_reset(ndev);
1189 mdio_np = of_get_child_by_name(np, "mdio");
1191 dev_err(dev, "mdio node not found\n");
1193 goto out_reset_assert;
1195 ret = of_mdiobus_register(priv->mdio, mdio_np);
1196 of_node_put(mdio_np);
1198 dev_err(dev, "failed to register mdiobus\n");
1199 goto out_reset_assert;
1202 phydev = of_phy_get_and_connect(ndev, np, ave_phy_adjust_link);
1204 dev_err(dev, "could not attach to PHY\n");
1206 goto out_mdio_unregister;
1209 priv->phydev = phydev;
1211 ave_ethtool_get_wol(ndev, &wol);
1212 device_set_wakeup_capable(&ndev->dev, !!wol.supported);
1214 /* set wol initial state disabled */
1216 ave_ethtool_set_wol(ndev, &wol);
1218 if (!phy_interface_is_rgmii(phydev))
1219 phy_set_max_speed(phydev, SPEED_100);
1221 phy_support_asym_pause(phydev);
1223 phy_attached_info(phydev);
1227 out_mdio_unregister:
1228 mdiobus_unregister(priv->mdio);
1231 reset_control_assert(priv->rst[nr]);
1234 clk_disable_unprepare(priv->clk[nc]);
1239 static void ave_uninit(struct net_device *ndev)
1241 struct ave_private *priv = netdev_priv(ndev);
1244 phy_disconnect(priv->phydev);
1245 mdiobus_unregister(priv->mdio);
1247 /* disable clk because of hw access after ndo_stop */
1248 for (i = 0; i < priv->nrsts; i++)
1249 reset_control_assert(priv->rst[i]);
1250 for (i = 0; i < priv->nclks; i++)
1251 clk_disable_unprepare(priv->clk[i]);
1254 static int ave_open(struct net_device *ndev)
1256 struct ave_private *priv = netdev_priv(ndev);
1261 ret = request_irq(priv->irq, ave_irq_handler, IRQF_SHARED, ndev->name,
1266 priv->tx.desc = kcalloc(priv->tx.ndesc, sizeof(*priv->tx.desc),
1268 if (!priv->tx.desc) {
1273 priv->rx.desc = kcalloc(priv->rx.ndesc, sizeof(*priv->rx.desc),
1275 if (!priv->rx.desc) {
1276 kfree(priv->tx.desc);
1281 /* initialize Tx work and descriptor */
1282 priv->tx.proc_idx = 0;
1283 priv->tx.done_idx = 0;
1284 for (entry = 0; entry < priv->tx.ndesc; entry++) {
1285 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, entry, 0);
1286 ave_desc_write_addr(ndev, AVE_DESCID_TX, entry, 0);
1288 writel(AVE_TXDC_ADDR_START |
1289 (((priv->tx.ndesc * priv->desc_size) << 16) & AVE_TXDC_SIZE),
1290 priv->base + AVE_TXDC);
1292 /* initialize Rx work and descriptor */
1293 priv->rx.proc_idx = 0;
1294 priv->rx.done_idx = 0;
1295 for (entry = 0; entry < priv->rx.ndesc; entry++) {
1296 if (ave_rxdesc_prepare(ndev, entry))
1299 writel(AVE_RXDC0_ADDR_START |
1300 (((priv->rx.ndesc * priv->desc_size) << 16) & AVE_RXDC0_SIZE),
1301 priv->base + AVE_RXDC0);
1303 ave_desc_switch(ndev, AVE_DESC_START);
1305 ave_pfsel_init(ndev);
1306 ave_macaddr_init(ndev);
1308 /* set Rx configuration */
1309 /* full duplex, enable pause drop, enalbe flow control */
1310 val = AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_DRPEN |
1311 AVE_RXCR_FLOCTR | (AVE_MAX_ETHFRAME & AVE_RXCR_MPSIZ_MASK);
1312 writel(val, priv->base + AVE_RXCR);
1314 /* set Tx configuration */
1315 /* enable flow control, disable loopback */
1316 writel(AVE_TXCR_FLOCTR, priv->base + AVE_TXCR);
1318 /* enable timer, clear EN,INTM, and mask interval unit(BSCK) */
1319 val = readl(priv->base + AVE_IIRQC) & AVE_IIRQC_BSCK;
1320 val |= AVE_IIRQC_EN0 | (AVE_INTM_COUNT << 16);
1321 writel(val, priv->base + AVE_IIRQC);
1323 val = AVE_GI_RXIINT | AVE_GI_RXOVF | AVE_GI_TX | AVE_GI_RXDROP;
1324 ave_irq_restore(ndev, val);
1326 napi_enable(&priv->napi_rx);
1327 napi_enable(&priv->napi_tx);
1329 phy_start(ndev->phydev);
1330 phy_start_aneg(ndev->phydev);
1331 netif_start_queue(ndev);
1336 disable_irq(priv->irq);
1337 free_irq(priv->irq, ndev);
1342 static int ave_stop(struct net_device *ndev)
1344 struct ave_private *priv = netdev_priv(ndev);
1347 ave_irq_disable_all(ndev);
1348 disable_irq(priv->irq);
1349 free_irq(priv->irq, ndev);
1351 netif_tx_disable(ndev);
1352 phy_stop(ndev->phydev);
1353 napi_disable(&priv->napi_tx);
1354 napi_disable(&priv->napi_rx);
1356 ave_desc_switch(ndev, AVE_DESC_STOP);
1358 /* free Tx buffer */
1359 for (entry = 0; entry < priv->tx.ndesc; entry++) {
1360 if (!priv->tx.desc[entry].skbs)
1363 ave_dma_unmap(ndev, &priv->tx.desc[entry], DMA_TO_DEVICE);
1364 dev_kfree_skb_any(priv->tx.desc[entry].skbs);
1365 priv->tx.desc[entry].skbs = NULL;
1367 priv->tx.proc_idx = 0;
1368 priv->tx.done_idx = 0;
1370 /* free Rx buffer */
1371 for (entry = 0; entry < priv->rx.ndesc; entry++) {
1372 if (!priv->rx.desc[entry].skbs)
1375 ave_dma_unmap(ndev, &priv->rx.desc[entry], DMA_FROM_DEVICE);
1376 dev_kfree_skb_any(priv->rx.desc[entry].skbs);
1377 priv->rx.desc[entry].skbs = NULL;
1379 priv->rx.proc_idx = 0;
1380 priv->rx.done_idx = 0;
1382 kfree(priv->tx.desc);
1383 kfree(priv->rx.desc);
1388 static int ave_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1390 struct ave_private *priv = netdev_priv(ndev);
1391 u32 proc_idx, done_idx, ndesc, cmdsts;
1395 proc_idx = priv->tx.proc_idx;
1396 done_idx = priv->tx.done_idx;
1397 ndesc = priv->tx.ndesc;
1398 freepkt = ((done_idx + ndesc - 1) - proc_idx) % ndesc;
1400 /* stop queue when not enough entry */
1401 if (unlikely(freepkt < 1)) {
1402 netif_stop_queue(ndev);
1403 return NETDEV_TX_BUSY;
1406 /* add padding for short packet */
1407 if (skb_put_padto(skb, ETH_ZLEN)) {
1408 priv->stats_tx.dropped++;
1409 return NETDEV_TX_OK;
1413 * Tx buffer set to the Tx descriptor doesn't have any restriction.
1415 ret = ave_dma_map(ndev, &priv->tx.desc[proc_idx],
1416 skb->data, skb->len, DMA_TO_DEVICE, &paddr);
1418 dev_kfree_skb_any(skb);
1419 priv->stats_tx.dropped++;
1420 return NETDEV_TX_OK;
1423 priv->tx.desc[proc_idx].skbs = skb;
1425 ave_desc_write_addr(ndev, AVE_DESCID_TX, proc_idx, paddr);
1427 cmdsts = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
1428 (skb->len & AVE_STS_PKTLEN_TX_MASK);
1430 /* set interrupt per AVE_FORCE_TXINTCNT or when queue is stopped */
1431 if (!(proc_idx % AVE_FORCE_TXINTCNT) || netif_queue_stopped(ndev))
1432 cmdsts |= AVE_STS_INTR;
1434 /* disable checksum calculation when skb doesn't calurate checksum */
1435 if (skb->ip_summed == CHECKSUM_NONE ||
1436 skb->ip_summed == CHECKSUM_UNNECESSARY)
1437 cmdsts |= AVE_STS_NOCSUM;
1439 ave_desc_write_cmdsts(ndev, AVE_DESCID_TX, proc_idx, cmdsts);
1441 priv->tx.proc_idx = (proc_idx + 1) % ndesc;
1443 return NETDEV_TX_OK;
1446 static int ave_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
1448 return phy_mii_ioctl(ndev->phydev, ifr, cmd);
1451 static const u8 v4multi_macadr[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
1452 static const u8 v6multi_macadr[] = { 0x33, 0x00, 0x00, 0x00, 0x00, 0x00 };
1454 static void ave_set_rx_mode(struct net_device *ndev)
1456 struct ave_private *priv = netdev_priv(ndev);
1457 struct netdev_hw_addr *hw_adr;
1461 /* MAC addr filter enable for promiscious mode */
1462 mc_cnt = netdev_mc_count(ndev);
1463 val = readl(priv->base + AVE_RXCR);
1464 if (ndev->flags & IFF_PROMISC || !mc_cnt)
1465 val &= ~AVE_RXCR_AFEN;
1467 val |= AVE_RXCR_AFEN;
1468 writel(val, priv->base + AVE_RXCR);
1470 /* set all multicast address */
1471 if ((ndev->flags & IFF_ALLMULTI) || mc_cnt > AVE_PF_MULTICAST_SIZE) {
1472 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST,
1474 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + 1,
1477 /* stop all multicast filter */
1478 for (count = 0; count < AVE_PF_MULTICAST_SIZE; count++)
1479 ave_pfsel_stop(ndev, AVE_PFNUM_MULTICAST + count);
1481 /* set multicast addresses */
1483 netdev_for_each_mc_addr(hw_adr, ndev) {
1484 if (count == mc_cnt)
1486 ave_pfsel_set_macaddr(ndev, AVE_PFNUM_MULTICAST + count,
1493 static void ave_get_stats64(struct net_device *ndev,
1494 struct rtnl_link_stats64 *stats)
1496 struct ave_private *priv = netdev_priv(ndev);
1500 start = u64_stats_fetch_begin_irq(&priv->stats_rx.syncp);
1501 stats->rx_packets = priv->stats_rx.packets;
1502 stats->rx_bytes = priv->stats_rx.bytes;
1503 } while (u64_stats_fetch_retry_irq(&priv->stats_rx.syncp, start));
1506 start = u64_stats_fetch_begin_irq(&priv->stats_tx.syncp);
1507 stats->tx_packets = priv->stats_tx.packets;
1508 stats->tx_bytes = priv->stats_tx.bytes;
1509 } while (u64_stats_fetch_retry_irq(&priv->stats_tx.syncp, start));
1511 stats->rx_errors = priv->stats_rx.errors;
1512 stats->tx_errors = priv->stats_tx.errors;
1513 stats->rx_dropped = priv->stats_rx.dropped;
1514 stats->tx_dropped = priv->stats_tx.dropped;
1515 stats->rx_fifo_errors = priv->stats_rx.fifo_errors;
1516 stats->collisions = priv->stats_tx.collisions;
1519 static int ave_set_mac_address(struct net_device *ndev, void *p)
1521 int ret = eth_mac_addr(ndev, p);
1526 ave_macaddr_init(ndev);
1531 static const struct net_device_ops ave_netdev_ops = {
1532 .ndo_init = ave_init,
1533 .ndo_uninit = ave_uninit,
1534 .ndo_open = ave_open,
1535 .ndo_stop = ave_stop,
1536 .ndo_start_xmit = ave_start_xmit,
1537 .ndo_do_ioctl = ave_ioctl,
1538 .ndo_set_rx_mode = ave_set_rx_mode,
1539 .ndo_get_stats64 = ave_get_stats64,
1540 .ndo_set_mac_address = ave_set_mac_address,
1543 static int ave_probe(struct platform_device *pdev)
1545 const struct ave_soc_data *data;
1546 struct device *dev = &pdev->dev;
1547 char buf[ETHTOOL_FWVERS_LEN];
1548 struct of_phandle_args args;
1549 phy_interface_t phy_mode;
1550 struct ave_private *priv;
1551 struct net_device *ndev;
1552 struct device_node *np;
1553 struct resource *res;
1554 const void *mac_addr;
1561 data = of_device_get_match_data(dev);
1566 phy_mode = of_get_phy_mode(np);
1568 dev_err(dev, "phy-mode not found\n");
1572 irq = platform_get_irq(pdev, 0);
1574 dev_err(dev, "IRQ not found\n");
1578 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579 base = devm_ioremap_resource(dev, res);
1581 return PTR_ERR(base);
1583 ndev = alloc_etherdev(sizeof(struct ave_private));
1585 dev_err(dev, "can't allocate ethernet device\n");
1589 ndev->netdev_ops = &ave_netdev_ops;
1590 ndev->ethtool_ops = &ave_ethtool_ops;
1591 SET_NETDEV_DEV(ndev, dev);
1593 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM);
1594 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_RXCSUM);
1596 ndev->max_mtu = AVE_MAX_ETHFRAME - (ETH_HLEN + ETH_FCS_LEN);
1598 mac_addr = of_get_mac_address(np);
1600 ether_addr_copy(ndev->dev_addr, mac_addr);
1602 /* if the mac address is invalid, use random mac address */
1603 if (!is_valid_ether_addr(ndev->dev_addr)) {
1604 eth_hw_addr_random(ndev);
1605 dev_warn(dev, "Using random MAC address: %pM\n",
1609 priv = netdev_priv(ndev);
1613 priv->msg_enable = netif_msg_init(-1, AVE_DEFAULT_MSG_ENABLE);
1614 priv->phy_mode = phy_mode;
1617 if (IS_DESC_64BIT(priv)) {
1618 priv->desc_size = AVE_DESC_SIZE_64;
1619 priv->tx.daddr = AVE_TXDM_64;
1620 priv->rx.daddr = AVE_RXDM_64;
1621 dma_mask = DMA_BIT_MASK(64);
1623 priv->desc_size = AVE_DESC_SIZE_32;
1624 priv->tx.daddr = AVE_TXDM_32;
1625 priv->rx.daddr = AVE_RXDM_32;
1626 dma_mask = DMA_BIT_MASK(32);
1628 ret = dma_set_mask(dev, dma_mask);
1630 goto out_free_netdev;
1632 priv->tx.ndesc = AVE_NR_TXDESC;
1633 priv->rx.ndesc = AVE_NR_RXDESC;
1635 u64_stats_init(&priv->stats_tx.syncp);
1636 u64_stats_init(&priv->stats_rx.syncp);
1638 for (i = 0; i < AVE_MAX_CLKS; i++) {
1639 name = priv->data->clock_names[i];
1642 priv->clk[i] = devm_clk_get(dev, name);
1643 if (IS_ERR(priv->clk[i])) {
1644 ret = PTR_ERR(priv->clk[i]);
1645 goto out_free_netdev;
1650 for (i = 0; i < AVE_MAX_RSTS; i++) {
1651 name = priv->data->reset_names[i];
1654 priv->rst[i] = devm_reset_control_get_shared(dev, name);
1655 if (IS_ERR(priv->rst[i])) {
1656 ret = PTR_ERR(priv->rst[i]);
1657 goto out_free_netdev;
1662 ret = of_parse_phandle_with_fixed_args(np,
1663 "socionext,syscon-phy-mode",
1666 netdev_err(ndev, "can't get syscon-phy-mode property\n");
1667 goto out_free_netdev;
1669 priv->regmap = syscon_node_to_regmap(args.np);
1670 of_node_put(args.np);
1671 if (IS_ERR(priv->regmap)) {
1672 netdev_err(ndev, "can't map syscon-phy-mode\n");
1673 ret = PTR_ERR(priv->regmap);
1674 goto out_free_netdev;
1676 ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]);
1678 netdev_err(ndev, "invalid phy-mode setting\n");
1679 goto out_free_netdev;
1682 priv->mdio = devm_mdiobus_alloc(dev);
1685 goto out_free_netdev;
1687 priv->mdio->priv = ndev;
1688 priv->mdio->parent = dev;
1689 priv->mdio->read = ave_mdiobus_read;
1690 priv->mdio->write = ave_mdiobus_write;
1691 priv->mdio->name = "uniphier-mdio";
1692 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%x",
1693 pdev->name, pdev->id);
1695 /* Register as a NAPI supported driver */
1696 netif_napi_add(ndev, &priv->napi_rx, ave_napi_poll_rx, priv->rx.ndesc);
1697 netif_tx_napi_add(ndev, &priv->napi_tx, ave_napi_poll_tx,
1700 platform_set_drvdata(pdev, ndev);
1702 ret = register_netdev(ndev);
1704 dev_err(dev, "failed to register netdevice\n");
1708 /* get ID and version */
1709 ave_id = readl(priv->base + AVE_IDR);
1710 ave_hw_read_version(ndev, buf, sizeof(buf));
1712 dev_info(dev, "Socionext %c%c%c%c Ethernet IP %s (irq=%d, phy=%s)\n",
1713 (ave_id >> 24) & 0xff, (ave_id >> 16) & 0xff,
1714 (ave_id >> 8) & 0xff, (ave_id >> 0) & 0xff,
1715 buf, priv->irq, phy_modes(phy_mode));
1720 netif_napi_del(&priv->napi_rx);
1721 netif_napi_del(&priv->napi_tx);
1728 static int ave_remove(struct platform_device *pdev)
1730 struct net_device *ndev = platform_get_drvdata(pdev);
1731 struct ave_private *priv = netdev_priv(ndev);
1733 unregister_netdev(ndev);
1734 netif_napi_del(&priv->napi_rx);
1735 netif_napi_del(&priv->napi_tx);
1741 #ifdef CONFIG_PM_SLEEP
1742 static int ave_suspend(struct device *dev)
1744 struct net_device *ndev = dev_get_drvdata(dev);
1745 struct ave_private *priv = netdev_priv(ndev);
1748 if (netif_running(ndev)) {
1749 ret = ave_stop(ndev);
1750 netif_device_detach(ndev);
1756 static int ave_resume(struct device *dev)
1758 struct net_device *ndev = dev_get_drvdata(dev);
1759 struct ave_private *priv = netdev_priv(ndev);
1762 ave_global_reset(ndev);
1765 ret = phy_resume(ndev->phydev);
1770 if (netif_running(ndev)) {
1771 ret = ave_open(ndev);
1772 netif_device_attach(ndev);
1778 static SIMPLE_DEV_PM_OPS(ave_pm_ops, ave_suspend, ave_resume);
1779 #define AVE_PM_OPS (&ave_pm_ops)
1781 #define AVE_PM_OPS NULL
1784 static int ave_pro4_get_pinmode(struct ave_private *priv,
1785 phy_interface_t phy_mode, u32 arg)
1790 priv->pinmode_mask = SG_ETPINMODE_RMII(0);
1793 case PHY_INTERFACE_MODE_RMII:
1794 priv->pinmode_val = SG_ETPINMODE_RMII(0);
1796 case PHY_INTERFACE_MODE_MII:
1797 case PHY_INTERFACE_MODE_RGMII:
1798 priv->pinmode_val = 0;
1807 static int ave_ld11_get_pinmode(struct ave_private *priv,
1808 phy_interface_t phy_mode, u32 arg)
1813 priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
1816 case PHY_INTERFACE_MODE_INTERNAL:
1817 priv->pinmode_val = 0;
1819 case PHY_INTERFACE_MODE_RMII:
1820 priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
1829 static int ave_ld20_get_pinmode(struct ave_private *priv,
1830 phy_interface_t phy_mode, u32 arg)
1835 priv->pinmode_mask = SG_ETPINMODE_RMII(0);
1838 case PHY_INTERFACE_MODE_RMII:
1839 priv->pinmode_val = SG_ETPINMODE_RMII(0);
1841 case PHY_INTERFACE_MODE_RGMII:
1842 priv->pinmode_val = 0;
1851 static int ave_pxs3_get_pinmode(struct ave_private *priv,
1852 phy_interface_t phy_mode, u32 arg)
1857 priv->pinmode_mask = SG_ETPINMODE_RMII(arg);
1860 case PHY_INTERFACE_MODE_RMII:
1861 priv->pinmode_val = SG_ETPINMODE_RMII(arg);
1863 case PHY_INTERFACE_MODE_RGMII:
1864 priv->pinmode_val = 0;
1873 static const struct ave_soc_data ave_pro4_data = {
1874 .is_desc_64bit = false,
1876 "gio", "ether", "ether-gb", "ether-phy",
1881 .get_pinmode = ave_pro4_get_pinmode,
1884 static const struct ave_soc_data ave_pxs2_data = {
1885 .is_desc_64bit = false,
1892 .get_pinmode = ave_pro4_get_pinmode,
1895 static const struct ave_soc_data ave_ld11_data = {
1896 .is_desc_64bit = false,
1903 .get_pinmode = ave_ld11_get_pinmode,
1906 static const struct ave_soc_data ave_ld20_data = {
1907 .is_desc_64bit = true,
1914 .get_pinmode = ave_ld20_get_pinmode,
1917 static const struct ave_soc_data ave_pxs3_data = {
1918 .is_desc_64bit = false,
1925 .get_pinmode = ave_pxs3_get_pinmode,
1928 static const struct of_device_id of_ave_match[] = {
1930 .compatible = "socionext,uniphier-pro4-ave4",
1931 .data = &ave_pro4_data,
1934 .compatible = "socionext,uniphier-pxs2-ave4",
1935 .data = &ave_pxs2_data,
1938 .compatible = "socionext,uniphier-ld11-ave4",
1939 .data = &ave_ld11_data,
1942 .compatible = "socionext,uniphier-ld20-ave4",
1943 .data = &ave_ld20_data,
1946 .compatible = "socionext,uniphier-pxs3-ave4",
1947 .data = &ave_pxs3_data,
1951 MODULE_DEVICE_TABLE(of, of_ave_match);
1953 static struct platform_driver ave_driver = {
1955 .remove = ave_remove,
1959 .of_match_table = of_ave_match,
1962 module_platform_driver(ave_driver);
1964 MODULE_DESCRIPTION("Socionext UniPhier AVE ethernet driver");
1965 MODULE_LICENSE("GPL v2");