drivers/net/ethernet/sfc/tx.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/tcp.h>
  13 #include <linux/ip.h>
  14 #include <linux/in.h>
  15 #include <linux/ipv6.h>
  16 #include <linux/slab.h>
  17 #include <net/ipv6.h>
  18 #include <linux/if_ether.h>
  19 #include <linux/highmem.h>
  20 #include <linux/cache.h>
  21 #include "net_driver.h"
  22 #include "efx.h"
  23 #include "io.h"
  24 #include "nic.h"
  25 #include "workarounds.h"
  26 #include "ef10_regs.h"
  27
  28 #ifdef EFX_USE_PIO
  29
  30 #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE
  31 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
  32 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
  33
  34 #endif /* EFX_USE_PIO */
  35
  36 static inline unsigned int
  37 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
  38 {
  39         return tx_queue->insert_count & tx_queue->ptr_mask;
  40 }
  41
  42 static inline struct efx_tx_buffer *
  43 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
  44 {
  45         return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
  46 }
  47
  48 static inline struct efx_tx_buffer *
  49 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
  50 {
  51         struct efx_tx_buffer *buffer =
  52                 __efx_tx_queue_get_insert_buffer(tx_queue);
  53
  54         EFX_BUG_ON_PARANOID(buffer->len);
  55         EFX_BUG_ON_PARANOID(buffer->flags);
  56         EFX_BUG_ON_PARANOID(buffer->unmap_len);
  57
  58         return buffer;
  59 }
  60
  61 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  62                                struct efx_tx_buffer *buffer,
  63                                unsigned int *pkts_compl,
  64                                unsigned int *bytes_compl)
  65 {
  66         if (buffer->unmap_len) {
  67                 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
  68                 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
  69                 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
  70                         dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
  71                                          DMA_TO_DEVICE);
  72                 else
  73                         dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
  74                                        DMA_TO_DEVICE);
  75                 buffer->unmap_len = 0;
  76         }
  77
  78         if (buffer->flags & EFX_TX_BUF_SKB) {
  79                 (*pkts_compl)++;
  80                 (*bytes_compl) += buffer->skb->len;
  81                 dev_consume_skb_any((struct sk_buff *)buffer->skb);
  82                 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  83                            "TX queue %d transmission id %x complete\n",
  84                            tx_queue->queue, tx_queue->read_count);
  85         } else if (buffer->flags & EFX_TX_BUF_HEAP) {
  86                 kfree(buffer->heap_buf);
  87         }
  88
  89         buffer->len = 0;
  90         buffer->flags = 0;
  91 }
  92
  93 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  94                                struct sk_buff *skb);
  95
  96 static inline unsigned
  97 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  98 {
  99         /* Depending on the NIC revision, we can use descriptor
 100          * lengths up to 8K or 8K-1.  However, since PCI Express
 101          * devices must split read requests at 4K boundaries, there is
 102          * little benefit from using descriptors that cross those
 103          * boundaries and we keep things simple by not doing so.
 104          */
 105         unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
 106
 107         /* Work around hardware bug for unaligned buffers. */
 108         if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
 109                 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
 110
 111         return len;
 112 }
 113
 114 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
 115 {
 116         /* Header and payload descriptor for each output segment, plus
 117          * one for every input fragment boundary within a segment
 118          */
 119         unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
 120
 121         /* Possibly one more per segment for the alignment workaround,
 122          * or for option descriptors
 123          */
 124         if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
 125                 max_descs += EFX_TSO_MAX_SEGS;
 126
 127         /* Possibly more for PCIe page boundaries within input fragments */
 128         if (PAGE_SIZE > EFX_PAGE_SIZE)
 129                 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
 130                                    DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
 131
 132         return max_descs;
 133 }
 134
 135 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
 136 {
 137         /* We need to consider both queues that the net core sees as one */
 138         struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
 139         struct efx_nic *efx = txq1->efx;
 140         unsigned int fill_level;
 141
 142         fill_level = max(txq1->insert_count - txq1->old_read_count,
 143                          txq2->insert_count - txq2->old_read_count);
 144         if (likely(fill_level < efx->txq_stop_thresh))
 145                 return;
 146
 147         /* We used the stale old_read_count above, which gives us a
 148          * pessimistic estimate of the fill level (which may even
 149          * validly be >= efx->txq_entries).  Now try again using
 150          * read_count (more likely to be a cache miss).
 151          *
 152          * If we read read_count and then conditionally stop the
 153          * queue, it is possible for the completion path to race with
 154          * us and complete all outstanding descriptors in the middle,
 155          * after which there will be no more completions to wake it.
 156          * Therefore we stop the queue first, then read read_count
 157          * (with a memory barrier to ensure the ordering), then
 158          * restart the queue if the fill level turns out to be low
 159          * enough.
 160          */
 161         netif_tx_stop_queue(txq1->core_txq);
 162         smp_mb();
 163         txq1->old_read_count = ACCESS_ONCE(txq1->read_count);
 164         txq2->old_read_count = ACCESS_ONCE(txq2->read_count);
 165
 166         fill_level = max(txq1->insert_count - txq1->old_read_count,
 167                          txq2->insert_count - txq2->old_read_count);
 168         EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
 169         if (likely(fill_level < efx->txq_stop_thresh)) {
 170                 smp_mb();
 171                 if (likely(!efx->loopback_selftest))
 172                         netif_tx_start_queue(txq1->core_txq);
 173         }
 174 }
 175
 176 #ifdef EFX_USE_PIO
 177
 178 struct efx_short_copy_buffer {
 179         int used;
 180         u8 buf[L1_CACHE_BYTES];
 181 };
 182
 183 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
 184  * Advances piobuf pointer. Leaves additional data in the copy buffer.
 185  */
 186 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
 187                                     u8 *data, int len,
 188                                     struct efx_short_copy_buffer *copy_buf)
 189 {
 190         int block_len = len & ~(sizeof(copy_buf->buf) - 1);
 191
 192         __iowrite64_copy(*piobuf, data, block_len >> 3);
 193         *piobuf += block_len;
 194         len -= block_len;
 195
 196         if (len) {
 197                 data += block_len;
 198                 BUG_ON(copy_buf->used);
 199                 BUG_ON(len > sizeof(copy_buf->buf));
 200                 memcpy(copy_buf->buf, data, len);
 201                 copy_buf->used = len;
 202         }
 203 }
 204
 205 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
 206  * Advances piobuf pointer. Leaves additional data in the copy buffer.
 207  */
 208 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
 209                                        u8 *data, int len,
 210                                        struct efx_short_copy_buffer *copy_buf)
 211 {
 212         if (copy_buf->used) {
 213                 /* if the copy buffer is partially full, fill it up and write */
 214                 int copy_to_buf =
 215                         min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
 216
 217                 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
 218                 copy_buf->used += copy_to_buf;
 219
 220                 /* if we didn't fill it up then we're done for now */
 221                 if (copy_buf->used < sizeof(copy_buf->buf))
 222                         return;
 223
 224                 __iowrite64_copy(*piobuf, copy_buf->buf,
 225                                  sizeof(copy_buf->buf) >> 3);
 226                 *piobuf += sizeof(copy_buf->buf);
 227                 data += copy_to_buf;
 228                 len -= copy_to_buf;
 229                 copy_buf->used = 0;
 230         }
 231
 232         efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
 233 }
 234
 235 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
 236                                   struct efx_short_copy_buffer *copy_buf)
 237 {
 238         /* if there's anything in it, write the whole buffer, including junk */
 239         if (copy_buf->used)
 240                 __iowrite64_copy(piobuf, copy_buf->buf,
 241                                  sizeof(copy_buf->buf) >> 3);
 242 }
 243
 244 /* Traverse skb structure and copy fragments in to PIO buffer.
 245  * Advances piobuf pointer.
 246  */
 247 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
 248                                      u8 __iomem **piobuf,
 249                                      struct efx_short_copy_buffer *copy_buf)
 250 {
 251         int i;
 252
 253         efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
 254                                 copy_buf);
 255
 256         for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
 257                 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
 258                 u8 *vaddr;
 259
 260                 vaddr = kmap_atomic(skb_frag_page(f));
 261
 262                 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset,
 263                                            skb_frag_size(f), copy_buf);
 264                 kunmap_atomic(vaddr);
 265         }
 266
 267         EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list);
 268 }
 269
 270 static struct efx_tx_buffer *
 271 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
 272 {
 273         struct efx_tx_buffer *buffer =
 274                 efx_tx_queue_get_insert_buffer(tx_queue);
 275         u8 __iomem *piobuf = tx_queue->piobuf;
 276
 277         /* Copy to PIO buffer. Ensure the writes are padded to the end
 278          * of a cache line, as this is required for write-combining to be
 279          * effective on at least x86.
 280          */
 281
 282         if (skb_shinfo(skb)->nr_frags) {
 283                 /* The size of the copy buffer will ensure all writes
 284                  * are the size of a cache line.
 285                  */
 286                 struct efx_short_copy_buffer copy_buf;
 287
 288                 copy_buf.used = 0;
 289
 290                 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
 291                                          &piobuf, &copy_buf);
 292                 efx_flush_copy_buffer(tx_queue->efx, piobuf, &copy_buf);
 293         } else {
 294                 /* Pad the write to the size of a cache line.
 295                  * We can do this because we know the skb_shared_info sruct is
 296                  * after the source, and the destination buffer is big enough.
 297                  */
 298                 BUILD_BUG_ON(L1_CACHE_BYTES >
 299                              SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
 300                 __iowrite64_copy(tx_queue->piobuf, skb->data,
 301                                  ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
 302         }
 303
 304         EFX_POPULATE_QWORD_5(buffer->option,
 305                              ESF_DZ_TX_DESC_IS_OPT, 1,
 306                              ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
 307                              ESF_DZ_TX_PIO_CONT, 0,
 308                              ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
 309                              ESF_DZ_TX_PIO_BUF_ADDR,
 310                              tx_queue->piobuf_offset);
 311         ++tx_queue->pio_packets;
 312         ++tx_queue->insert_count;
 313         return buffer;
 314 }
 315 #endif /* EFX_USE_PIO */
 316
 317 /*
 318  * Add a socket buffer to a TX queue
 319  *
 320  * This maps all fragments of a socket buffer for DMA and adds them to
 321  * the TX queue.  The queue's insert pointer will be incremented by
 322  * the number of fragments in the socket buffer.
 323  *
 324  * If any DMA mapping fails, any mapped fragments will be unmapped,
 325  * the queue's insert pointer will be restored to its original value.
 326  *
 327  * This function is split out from efx_hard_start_xmit to allow the
 328  * loopback test to direct packets via specific TX queues.
 329  *
 330  * Returns NETDEV_TX_OK.
 331  * You must hold netif_tx_lock() to call this function.
 332  */
 333 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
 334 {
 335         struct efx_nic *efx = tx_queue->efx;
 336         struct device *dma_dev = &efx->pci_dev->dev;
 337         struct efx_tx_buffer *buffer;
 338         unsigned int old_insert_count = tx_queue->insert_count;
 339         skb_frag_t *fragment;
 340         unsigned int len, unmap_len = 0;
 341         dma_addr_t dma_addr, unmap_addr = 0;
 342         unsigned int dma_len;
 343         unsigned short dma_flags;
 344         int i = 0;
 345
 346         if (skb_shinfo(skb)->gso_size)
 347                 return efx_enqueue_skb_tso(tx_queue, skb);
 348
 349         /* Get size of the initial fragment */
 350         len = skb_headlen(skb);
 351
 352         /* Pad if necessary */
 353         if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
 354                 EFX_BUG_ON_PARANOID(skb->data_len);
 355                 len = 32 + 1;
 356                 if (skb_pad(skb, len - skb->len))
 357                         return NETDEV_TX_OK;
 358         }
 359
 360         /* Consider using PIO for short packets */
 361 #ifdef EFX_USE_PIO
 362         if (skb->len <= efx_piobuf_size && !skb->xmit_more &&
 363             efx_nic_may_tx_pio(tx_queue)) {
 364                 buffer = efx_enqueue_skb_pio(tx_queue, skb);
 365                 dma_flags = EFX_TX_BUF_OPTION;
 366                 goto finish_packet;
 367         }
 368 #endif
 369
 370         /* Map for DMA.  Use dma_map_single rather than dma_map_page
 371          * since this is more efficient on machines with sparse
 372          * memory.
 373          */
 374         dma_flags = EFX_TX_BUF_MAP_SINGLE;
 375         dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE);
 376
 377         /* Process all fragments */
 378         while (1) {
 379                 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
 380                         goto dma_err;
 381
 382                 /* Store fields for marking in the per-fragment final
 383                  * descriptor */
 384                 unmap_len = len;
 385                 unmap_addr = dma_addr;
 386
 387                 /* Add to TX queue, splitting across DMA boundaries */
 388                 do {
 389                         buffer = efx_tx_queue_get_insert_buffer(tx_queue);
 390
 391                         dma_len = efx_max_tx_len(efx, dma_addr);
 392                         if (likely(dma_len >= len))
 393                                 dma_len = len;
 394
 395                         /* Fill out per descriptor fields */
 396                         buffer->len = dma_len;
 397                         buffer->dma_addr = dma_addr;
 398                         buffer->flags = EFX_TX_BUF_CONT;
 399                         len -= dma_len;
 400                         dma_addr += dma_len;
 401                         ++tx_queue->insert_count;
 402                 } while (len);
 403
 404                 /* Transfer ownership of the unmapping to the final buffer */
 405                 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
 406                 buffer->unmap_len = unmap_len;
 407                 buffer->dma_offset = buffer->dma_addr - unmap_addr;
 408                 unmap_len = 0;
 409
 410                 /* Get address and size of next fragment */
 411                 if (i >= skb_shinfo(skb)->nr_frags)
 412                         break;
 413                 fragment = &skb_shinfo(skb)->frags[i];
 414                 len = skb_frag_size(fragment);
 415                 i++;
 416                 /* Map for DMA */
 417                 dma_flags = 0;
 418                 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
 419                                             DMA_TO_DEVICE);
 420         }
 421
 422         /* Transfer ownership of the skb to the final buffer */
 423 #ifdef EFX_USE_PIO
 424 finish_packet:
 425 #endif
 426         buffer->skb = skb;
 427         buffer->flags = EFX_TX_BUF_SKB | dma_flags;
 428
 429         netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
 430
 431         efx_tx_maybe_stop_queue(tx_queue);
 432
 433         /* Pass off to hardware */
 434         if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) {
 435                 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
 436
 437                 /* There could be packets left on the partner queue if those
 438                  * SKBs had skb->xmit_more set. If we do not push those they
 439                  * could be left for a long time and cause a netdev watchdog.
 440                  */
 441                 if (txq2->xmit_more_available)
 442                         efx_nic_push_buffers(txq2);
 443
 444                 efx_nic_push_buffers(tx_queue);
 445         } else {
 446                 tx_queue->xmit_more_available = skb->xmit_more;
 447         }
 448
 449         tx_queue->tx_packets++;
 450
 451         return NETDEV_TX_OK;
 452
 453  dma_err:
 454         netif_err(efx, tx_err, efx->net_dev,
 455                   " TX queue %d could not map skb with %d bytes %d "
 456                   "fragments for DMA\n", tx_queue->queue, skb->len,
 457                   skb_shinfo(skb)->nr_frags + 1);
 458
 459         /* Mark the packet as transmitted, and free the SKB ourselves */
 460         dev_kfree_skb_any(skb);
 461
 462         /* Work backwards until we hit the original insert pointer value */
 463         while (tx_queue->insert_count != old_insert_count) {
 464                 unsigned int pkts_compl = 0, bytes_compl = 0;
 465                 --tx_queue->insert_count;
 466                 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
 467                 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
 468         }
 469
 470         /* Free the fragment we were mid-way through pushing */
 471         if (unmap_len) {
 472                 if (dma_flags & EFX_TX_BUF_MAP_SINGLE)
 473                         dma_unmap_single(dma_dev, unmap_addr, unmap_len,
 474                                          DMA_TO_DEVICE);
 475                 else
 476                         dma_unmap_page(dma_dev, unmap_addr, unmap_len,
 477                                        DMA_TO_DEVICE);
 478         }
 479
 480         return NETDEV_TX_OK;
 481 }
 482
 483 /* Remove packets from the TX queue
 484  *
 485  * This removes packets from the TX queue, up to and including the
 486  * specified index.
 487  */
 488 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
 489                                 unsigned int index,
 490                                 unsigned int *pkts_compl,
 491                                 unsigned int *bytes_compl)
 492 {
 493         struct efx_nic *efx = tx_queue->efx;
 494         unsigned int stop_index, read_ptr;
 495
 496         stop_index = (index + 1) & tx_queue->ptr_mask;
 497         read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
 498
 499         while (read_ptr != stop_index) {
 500                 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
 501
 502                 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
 503                     unlikely(buffer->len == 0)) {
 504                         netif_err(efx, tx_err, efx->net_dev,
 505                                   "TX queue %d spurious TX completion id %x\n",
 506                                   tx_queue->queue, read_ptr);
 507                         efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
 508                         return;
 509                 }
 510
 511                 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
 512
 513                 ++tx_queue->read_count;
 514                 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
 515         }
 516 }
 517
 518 /* Initiate a packet transmission.  We use one channel per CPU
 519  * (sharing when we have more CPUs than channels).  On Falcon, the TX
 520  * completion events will be directed back to the CPU that transmitted
 521  * the packet, which should be cache-efficient.
 522  *
 523  * Context: non-blocking.
 524  * Note that returning anything other than NETDEV_TX_OK will cause the
 525  * OS to free the skb.
 526  */
 527 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
 528                                 struct net_device *net_dev)
 529 {
 530         struct efx_nic *efx = netdev_priv(net_dev);
 531         struct efx_tx_queue *tx_queue;
 532         unsigned index, type;
 533
 534         EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
 535
 536         /* PTP "event" packet */
 537         if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
 538             unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
 539                 return efx_ptp_tx(efx, skb);
 540         }
 541
 542         index = skb_get_queue_mapping(skb);
 543         type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
 544         if (index >= efx->n_tx_channels) {
 545                 index -= efx->n_tx_channels;
 546                 type |= EFX_TXQ_TYPE_HIGHPRI;
 547         }
 548         tx_queue = efx_get_tx_queue(efx, index, type);
 549
 550         return efx_enqueue_skb(tx_queue, skb);
 551 }
 552
 553 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
 554 {
 555         struct efx_nic *efx = tx_queue->efx;
 556
 557         /* Must be inverse of queue lookup in efx_hard_start_xmit() */
 558         tx_queue->core_txq =
 559                 netdev_get_tx_queue(efx->net_dev,
 560                                     tx_queue->queue / EFX_TXQ_TYPES +
 561                                     ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 562                                      efx->n_tx_channels : 0));
 563 }
 564
 565 int efx_setup_tc(struct net_device *net_dev, u32 handle, u8 num_tc)
 566 {
 567         struct efx_nic *efx = netdev_priv(net_dev);
 568         struct efx_channel *channel;
 569         struct efx_tx_queue *tx_queue;
 570         unsigned tc;
 571         int rc;
 572
 573         if (handle != TC_H_ROOT)
 574                 return -EINVAL;
 575
 576         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC)
 577                 return -EINVAL;
 578
 579         if (num_tc == net_dev->num_tc)
 580                 return 0;
 581
 582         for (tc = 0; tc < num_tc; tc++) {
 583                 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
 584                 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
 585         }
 586
 587         if (num_tc > net_dev->num_tc) {
 588                 /* Initialise high-priority queues as necessary */
 589                 efx_for_each_channel(channel, efx) {
 590                         efx_for_each_possible_channel_tx_queue(tx_queue,
 591                                                                channel) {
 592                                 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
 593                                         continue;
 594                                 if (!tx_queue->buffer) {
 595                                         rc = efx_probe_tx_queue(tx_queue);
 596                                         if (rc)
 597                                                 return rc;
 598                                 }
 599                                 if (!tx_queue->initialised)
 600                                         efx_init_tx_queue(tx_queue);
 601                                 efx_init_tx_queue_core_txq(tx_queue);
 602                         }
 603                 }
 604         } else {
 605                 /* Reduce number of classes before number of queues */
 606                 net_dev->num_tc = num_tc;
 607         }
 608
 609         rc = netif_set_real_num_tx_queues(net_dev,
 610                                           max_t(int, num_tc, 1) *
 611                                           efx->n_tx_channels);
 612         if (rc)
 613                 return rc;
 614
 615         /* Do not destroy high-priority queues when they become
 616          * unused.  We would have to flush them first, and it is
 617          * fairly difficult to flush a subset of TX queues.  Leave
 618          * it to efx_fini_channels().
 619          */
 620
 621         net_dev->num_tc = num_tc;
 622         return 0;
 623 }
 624
 625 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
 626 {
 627         unsigned fill_level;
 628         struct efx_nic *efx = tx_queue->efx;
 629         struct efx_tx_queue *txq2;
 630         unsigned int pkts_compl = 0, bytes_compl = 0;
 631
 632         EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
 633
 634         efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
 635         tx_queue->pkts_compl += pkts_compl;
 636         tx_queue->bytes_compl += bytes_compl;
 637
 638         if (pkts_compl > 1)
 639                 ++tx_queue->merge_events;
 640
 641         /* See if we need to restart the netif queue.  This memory
 642          * barrier ensures that we write read_count (inside
 643          * efx_dequeue_buffers()) before reading the queue status.
 644          */
 645         smp_mb();
 646         if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
 647             likely(efx->port_enabled) &&
 648             likely(netif_device_present(efx->net_dev))) {
 649                 txq2 = efx_tx_queue_partner(tx_queue);
 650                 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
 651                                  txq2->insert_count - txq2->read_count);
 652                 if (fill_level <= efx->txq_wake_thresh)
 653                         netif_tx_wake_queue(tx_queue->core_txq);
 654         }
 655
 656         /* Check whether the hardware queue is now empty */
 657         if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
 658                 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
 659                 if (tx_queue->read_count == tx_queue->old_write_count) {
 660                         smp_mb();
 661                         tx_queue->empty_read_count =
 662                                 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
 663                 }
 664         }
 665 }
 666
 667 /* Size of page-based TSO header buffers.  Larger blocks must be
 668  * allocated from the heap.
 669  */
 670 #define TSOH_STD_SIZE   128
 671 #define TSOH_PER_PAGE   (PAGE_SIZE / TSOH_STD_SIZE)
 672
 673 /* At most half the descriptors in the queue at any time will refer to
 674  * a TSO header buffer, since they must always be followed by a
 675  * payload descriptor referring to an skb.
 676  */
 677 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue)
 678 {
 679         return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE);
 680 }
 681
 682 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
 683 {
 684         struct efx_nic *efx = tx_queue->efx;
 685         unsigned int entries;
 686         int rc;
 687
 688         /* Create the smallest power-of-two aligned ring */
 689         entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
 690         EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
 691         tx_queue->ptr_mask = entries - 1;
 692
 693         netif_dbg(efx, probe, efx->net_dev,
 694                   "creating TX queue %d size %#x mask %#x\n",
 695                   tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
 696
 697         /* Allocate software ring */
 698         tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
 699                                    GFP_KERNEL);
 700         if (!tx_queue->buffer)
 701                 return -ENOMEM;
 702
 703         if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) {
 704                 tx_queue->tsoh_page =
 705                         kcalloc(efx_tsoh_page_count(tx_queue),
 706                                 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL);
 707                 if (!tx_queue->tsoh_page) {
 708                         rc = -ENOMEM;
 709                         goto fail1;
 710                 }
 711         }
 712
 713         /* Allocate hardware ring */
 714         rc = efx_nic_probe_tx(tx_queue);
 715         if (rc)
 716                 goto fail2;
 717
 718         return 0;
 719
 720 fail2:
 721         kfree(tx_queue->tsoh_page);
 722         tx_queue->tsoh_page = NULL;
 723 fail1:
 724         kfree(tx_queue->buffer);
 725         tx_queue->buffer = NULL;
 726         return rc;
 727 }
 728
 729 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
 730 {
 731         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 732                   "initialising TX queue %d\n", tx_queue->queue);
 733
 734         tx_queue->insert_count = 0;
 735         tx_queue->write_count = 0;
 736         tx_queue->old_write_count = 0;
 737         tx_queue->read_count = 0;
 738         tx_queue->old_read_count = 0;
 739         tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
 740         tx_queue->xmit_more_available = false;
 741
 742         /* Set up TX descriptor ring */
 743         efx_nic_init_tx(tx_queue);
 744
 745         tx_queue->initialised = true;
 746 }
 747
 748 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
 749 {
 750         struct efx_tx_buffer *buffer;
 751
 752         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 753                   "shutting down TX queue %d\n", tx_queue->queue);
 754
 755         if (!tx_queue->buffer)
 756                 return;
 757
 758         /* Free any buffers left in the ring */
 759         while (tx_queue->read_count != tx_queue->write_count) {
 760                 unsigned int pkts_compl = 0, bytes_compl = 0;
 761                 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
 762                 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
 763
 764                 ++tx_queue->read_count;
 765         }
 766         tx_queue->xmit_more_available = false;
 767         netdev_tx_reset_queue(tx_queue->core_txq);
 768 }
 769
 770 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
 771 {
 772         int i;
 773
 774         if (!tx_queue->buffer)
 775                 return;
 776
 777         netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
 778                   "destroying TX queue %d\n", tx_queue->queue);
 779         efx_nic_remove_tx(tx_queue);
 780
 781         if (tx_queue->tsoh_page) {
 782                 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++)
 783                         efx_nic_free_buffer(tx_queue->efx,
 784                                             &tx_queue->tsoh_page[i]);
 785                 kfree(tx_queue->tsoh_page);
 786                 tx_queue->tsoh_page = NULL;
 787         }
 788
 789         kfree(tx_queue->buffer);
 790         tx_queue->buffer = NULL;
 791 }
 792
 793
 794 /* Efx TCP segmentation acceleration.
 795  *
 796  * Why?  Because by doing it here in the driver we can go significantly
 797  * faster than the GSO.
 798  *
 799  * Requires TX checksum offload support.
 800  */
 801
 802 #define PTR_DIFF(p1, p2)  ((u8 *)(p1) - (u8 *)(p2))
 803
 804 /**
 805  * struct tso_state - TSO state for an SKB
 806  * @out_len: Remaining length in current segment
 807  * @seqnum: Current sequence number
 808  * @ipv4_id: Current IPv4 ID, host endian
 809  * @packet_space: Remaining space in current packet
 810  * @dma_addr: DMA address of current position
 811  * @in_len: Remaining length in current SKB fragment
 812  * @unmap_len: Length of SKB fragment
 813  * @unmap_addr: DMA address of SKB fragment
 814  * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
 815  * @protocol: Network protocol (after any VLAN header)
 816  * @ip_off: Offset of IP header
 817  * @tcp_off: Offset of TCP header
 818  * @header_len: Number of bytes of header
 819  * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
 820  * @header_dma_addr: Header DMA address, when using option descriptors
 821  * @header_unmap_len: Header DMA mapped length, or 0 if not using option
 822  *      descriptors
 823  *
 824  * The state used during segmentation.  It is put into this data structure
 825  * just to make it easy to pass into inline functions.
 826  */
 827 struct tso_state {
 828         /* Output position */
 829         unsigned out_len;
 830         unsigned seqnum;
 831         u16 ipv4_id;
 832         unsigned packet_space;
 833
 834         /* Input position */
 835         dma_addr_t dma_addr;
 836         unsigned in_len;
 837         unsigned unmap_len;
 838         dma_addr_t unmap_addr;
 839         unsigned short dma_flags;
 840
 841         __be16 protocol;
 842         unsigned int ip_off;
 843         unsigned int tcp_off;
 844         unsigned header_len;
 845         unsigned int ip_base_len;
 846         dma_addr_t header_dma_addr;
 847         unsigned int header_unmap_len;
 848 };
 849
 850
 851 /*
 852  * Verify that our various assumptions about sk_buffs and the conditions
 853  * under which TSO will be attempted hold true.  Return the protocol number.
 854  */
 855 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
 856 {
 857         __be16 protocol = skb->protocol;
 858
 859         EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
 860                             protocol);
 861         if (protocol == htons(ETH_P_8021Q)) {
 862                 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
 863                 protocol = veh->h_vlan_encapsulated_proto;
 864         }
 865
 866         if (protocol == htons(ETH_P_IP)) {
 867                 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
 868         } else {
 869                 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
 870                 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
 871         }
 872         EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
 873                              + (tcp_hdr(skb)->doff << 2u)) >
 874                             skb_headlen(skb));
 875
 876         return protocol;
 877 }
 878
 879 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue,
 880                                struct efx_tx_buffer *buffer, unsigned int len)
 881 {
 882         u8 *result;
 883
 884         EFX_BUG_ON_PARANOID(buffer->len);
 885         EFX_BUG_ON_PARANOID(buffer->flags);
 886         EFX_BUG_ON_PARANOID(buffer->unmap_len);
 887
 888         if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) {
 889                 unsigned index =
 890                         (tx_queue->insert_count & tx_queue->ptr_mask) / 2;
 891                 struct efx_buffer *page_buf =
 892                         &tx_queue->tsoh_page[index / TSOH_PER_PAGE];
 893                 unsigned offset =
 894                         TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN;
 895
 896                 if (unlikely(!page_buf->addr) &&
 897                     efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
 898                                          GFP_ATOMIC))
 899                         return NULL;
 900
 901                 result = (u8 *)page_buf->addr + offset;
 902                 buffer->dma_addr = page_buf->dma_addr + offset;
 903                 buffer->flags = EFX_TX_BUF_CONT;
 904         } else {
 905                 tx_queue->tso_long_headers++;
 906
 907                 buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC);
 908                 if (unlikely(!buffer->heap_buf))
 909                         return NULL;
 910                 result = (u8 *)buffer->heap_buf + NET_IP_ALIGN;
 911                 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP;
 912         }
 913
 914         buffer->len = len;
 915
 916         return result;
 917 }
 918
 919 /**
 920  * efx_tx_queue_insert - push descriptors onto the TX queue
 921  * @tx_queue:           Efx TX queue
 922  * @dma_addr:           DMA address of fragment
 923  * @len:                Length of fragment
 924  * @final_buffer:       The final buffer inserted into the queue
 925  *
 926  * Push descriptors onto the TX queue.
 927  */
 928 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
 929                                 dma_addr_t dma_addr, unsigned len,
 930                                 struct efx_tx_buffer **final_buffer)
 931 {
 932         struct efx_tx_buffer *buffer;
 933         struct efx_nic *efx = tx_queue->efx;
 934         unsigned dma_len;
 935
 936         EFX_BUG_ON_PARANOID(len <= 0);
 937
 938         while (1) {
 939                 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
 940                 ++tx_queue->insert_count;
 941
 942                 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
 943                                     tx_queue->read_count >=
 944                                     efx->txq_entries);
 945
 946                 buffer->dma_addr = dma_addr;
 947
 948                 dma_len = efx_max_tx_len(efx, dma_addr);
 949
 950                 /* If there is enough space to send then do so */
 951                 if (dma_len >= len)
 952                         break;
 953
 954                 buffer->len = dma_len;
 955                 buffer->flags = EFX_TX_BUF_CONT;
 956                 dma_addr += dma_len;
 957                 len -= dma_len;
 958         }
 959
 960         EFX_BUG_ON_PARANOID(!len);
 961         buffer->len = len;
 962         *final_buffer = buffer;
 963 }
 964
 965
 966 /*
 967  * Put a TSO header into the TX queue.
 968  *
 969  * This is special-cased because we know that it is small enough to fit in
 970  * a single fragment, and we know it doesn't cross a page boundary.  It
 971  * also allows us to not worry about end-of-packet etc.
 972  */
 973 static int efx_tso_put_header(struct efx_tx_queue *tx_queue,
 974                               struct efx_tx_buffer *buffer, u8 *header)
 975 {
 976         if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) {
 977                 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev,
 978                                                   header, buffer->len,
 979                                                   DMA_TO_DEVICE);
 980                 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev,
 981                                                buffer->dma_addr))) {
 982                         kfree(buffer->heap_buf);
 983                         buffer->len = 0;
 984                         buffer->flags = 0;
 985                         return -ENOMEM;
 986                 }
 987                 buffer->unmap_len = buffer->len;
 988                 buffer->dma_offset = 0;
 989                 buffer->flags |= EFX_TX_BUF_MAP_SINGLE;
 990         }
 991
 992         ++tx_queue->insert_count;
 993         return 0;
 994 }
 995
 996
 997 /* Remove buffers put into a tx_queue.  None of the buffers must have
 998  * an skb attached.
 999  */
1000 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
1001                                unsigned int insert_count)
1002 {
1003         struct efx_tx_buffer *buffer;
1004
1005         /* Work backwards until we hit the original insert pointer value */
1006         while (tx_queue->insert_count != insert_count) {
1007                 --tx_queue->insert_count;
1008                 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
1009                 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL);
1010         }
1011 }
1012
1013
1014 /* Parse the SKB header and initialise state. */
1015 static int tso_start(struct tso_state *st, struct efx_nic *efx,
1016                      struct efx_tx_queue *tx_queue,
1017                      const struct sk_buff *skb)
1018 {
1019         struct device *dma_dev = &efx->pci_dev->dev;
1020         unsigned int header_len, in_len;
1021         bool use_opt_desc = false;
1022         dma_addr_t dma_addr;
1023
1024         if (tx_queue->tso_version == 1)
1025                 use_opt_desc = true;
1026
1027         st->ip_off = skb_network_header(skb) - skb->data;
1028         st->tcp_off = skb_transport_header(skb) - skb->data;
1029         header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u);
1030         in_len = skb_headlen(skb) - header_len;
1031         st->header_len = header_len;
1032         st->in_len = in_len;
1033         if (st->protocol == htons(ETH_P_IP)) {
1034                 st->ip_base_len = st->header_len - st->ip_off;
1035                 st->ipv4_id = ntohs(ip_hdr(skb)->id);
1036         } else {
1037                 st->ip_base_len = st->header_len - st->tcp_off;
1038                 st->ipv4_id = 0;
1039         }
1040         st->seqnum = ntohl(tcp_hdr(skb)->seq);
1041
1042         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
1043         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
1044         EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
1045
1046         st->out_len = skb->len - header_len;
1047
1048         if (!use_opt_desc) {
1049                 st->header_unmap_len = 0;
1050
1051                 if (likely(in_len == 0)) {
1052                         st->dma_flags = 0;
1053                         st->unmap_len = 0;
1054                         return 0;
1055                 }
1056
1057                 dma_addr = dma_map_single(dma_dev, skb->data + header_len,
1058                                           in_len, DMA_TO_DEVICE);
1059                 st->dma_flags = EFX_TX_BUF_MAP_SINGLE;
1060                 st->dma_addr = dma_addr;
1061                 st->unmap_addr = dma_addr;
1062                 st->unmap_len = in_len;
1063         } else {
1064                 dma_addr = dma_map_single(dma_dev, skb->data,
1065                                           skb_headlen(skb), DMA_TO_DEVICE);
1066                 st->header_dma_addr = dma_addr;
1067                 st->header_unmap_len = skb_headlen(skb);
1068                 st->dma_flags = 0;
1069                 st->dma_addr = dma_addr + header_len;
1070                 st->unmap_len = 0;
1071         }
1072
1073         return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0;
1074 }
1075
1076 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
1077                             skb_frag_t *frag)
1078 {
1079         st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0,
1080                                           skb_frag_size(frag), DMA_TO_DEVICE);
1081         if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) {
1082                 st->dma_flags = 0;
1083                 st->unmap_len = skb_frag_size(frag);
1084                 st->in_len = skb_frag_size(frag);
1085                 st->dma_addr = st->unmap_addr;
1086                 return 0;
1087         }
1088         return -ENOMEM;
1089 }
1090
1091
1092 /**
1093  * tso_fill_packet_with_fragment - form descriptors for the current fragment
1094  * @tx_queue:           Efx TX queue
1095  * @skb:                Socket buffer
1096  * @st:                 TSO state
1097  *
1098  * Form descriptors for the current fragment, until we reach the end
1099  * of fragment or end-of-packet.
1100  */
1101 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
1102                                           const struct sk_buff *skb,
1103                                           struct tso_state *st)
1104 {
1105         struct efx_tx_buffer *buffer;
1106         int n;
1107
1108         if (st->in_len == 0)
1109                 return;
1110         if (st->packet_space == 0)
1111                 return;
1112
1113         EFX_BUG_ON_PARANOID(st->in_len <= 0);
1114         EFX_BUG_ON_PARANOID(st->packet_space <= 0);
1115
1116         n = min(st->in_len, st->packet_space);
1117
1118         st->packet_space -= n;
1119         st->out_len -= n;
1120         st->in_len -= n;
1121
1122         efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
1123
1124         if (st->out_len == 0) {
1125                 /* Transfer ownership of the skb */
1126                 buffer->skb = skb;
1127                 buffer->flags = EFX_TX_BUF_SKB;
1128         } else if (st->packet_space != 0) {
1129                 buffer->flags = EFX_TX_BUF_CONT;
1130         }
1131
1132         if (st->in_len == 0) {
1133                 /* Transfer ownership of the DMA mapping */
1134                 buffer->unmap_len = st->unmap_len;
1135                 buffer->dma_offset = buffer->unmap_len - buffer->len;
1136                 buffer->flags |= st->dma_flags;
1137                 st->unmap_len = 0;
1138         }
1139
1140         st->dma_addr += n;
1141 }
1142
1143
1144 /**
1145  * tso_start_new_packet - generate a new header and prepare for the new packet
1146  * @tx_queue:           Efx TX queue
1147  * @skb:                Socket buffer
1148  * @st:                 TSO state
1149  *
1150  * Generate a new header and prepare for the new packet.  Return 0 on
1151  * success, or -%ENOMEM if failed to alloc header.
1152  */
1153 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
1154                                 const struct sk_buff *skb,
1155                                 struct tso_state *st)
1156 {
1157         struct efx_tx_buffer *buffer =
1158                 efx_tx_queue_get_insert_buffer(tx_queue);
1159         bool is_last = st->out_len <= skb_shinfo(skb)->gso_size;
1160         u8 tcp_flags_clear;
1161
1162         if (!is_last) {
1163                 st->packet_space = skb_shinfo(skb)->gso_size;
1164                 tcp_flags_clear = 0x09; /* mask out FIN and PSH */
1165         } else {
1166                 st->packet_space = st->out_len;
1167                 tcp_flags_clear = 0x00;
1168         }
1169
1170         if (!st->header_unmap_len) {
1171                 /* Allocate and insert a DMA-mapped header buffer. */
1172                 struct tcphdr *tsoh_th;
1173                 unsigned ip_length;
1174                 u8 *header;
1175                 int rc;
1176
1177                 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len);
1178                 if (!header)
1179                         return -ENOMEM;
1180
1181                 tsoh_th = (struct tcphdr *)(header + st->tcp_off);
1182
1183                 /* Copy and update the headers. */
1184                 memcpy(header, skb->data, st->header_len);
1185
1186                 tsoh_th->seq = htonl(st->seqnum);
1187                 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear;
1188
1189                 ip_length = st->ip_base_len + st->packet_space;
1190
1191                 if (st->protocol == htons(ETH_P_IP)) {
1192                         struct iphdr *tsoh_iph =
1193                                 (struct iphdr *)(header + st->ip_off);
1194
1195                         tsoh_iph->tot_len = htons(ip_length);
1196                         tsoh_iph->id = htons(st->ipv4_id);
1197                 } else {
1198                         struct ipv6hdr *tsoh_iph =
1199                                 (struct ipv6hdr *)(header + st->ip_off);
1200
1201                         tsoh_iph->payload_len = htons(ip_length);
1202                 }
1203
1204                 rc = efx_tso_put_header(tx_queue, buffer, header);
1205                 if (unlikely(rc))
1206                         return rc;
1207         } else {
1208                 /* Send the original headers with a TSO option descriptor
1209                  * in front
1210                  */
1211                 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear;
1212
1213                 buffer->flags = EFX_TX_BUF_OPTION;
1214                 buffer->len = 0;
1215                 buffer->unmap_len = 0;
1216                 EFX_POPULATE_QWORD_5(buffer->option,
1217                                      ESF_DZ_TX_DESC_IS_OPT, 1,
1218                                      ESF_DZ_TX_OPTION_TYPE,
1219                                      ESE_DZ_TX_OPTION_DESC_TSO,
1220                                      ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
1221                                      ESF_DZ_TX_TSO_IP_ID, st->ipv4_id,
1222                                      ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum);
1223                 ++tx_queue->insert_count;
1224
1225                 /* We mapped the headers in tso_start().  Unmap them
1226                  * when the last segment is completed.
1227                  */
1228                 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
1229                 buffer->dma_addr = st->header_dma_addr;
1230                 buffer->len = st->header_len;
1231                 if (is_last) {
1232                         buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE;
1233                         buffer->unmap_len = st->header_unmap_len;
1234                         buffer->dma_offset = 0;
1235                         /* Ensure we only unmap them once in case of a
1236                          * later DMA mapping error and rollback
1237                          */
1238                         st->header_unmap_len = 0;
1239                 } else {
1240                         buffer->flags = EFX_TX_BUF_CONT;
1241                         buffer->unmap_len = 0;
1242                 }
1243                 ++tx_queue->insert_count;
1244         }
1245
1246         st->seqnum += skb_shinfo(skb)->gso_size;
1247
1248         /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1249         ++st->ipv4_id;
1250
1251         ++tx_queue->tso_packets;
1252
1253         ++tx_queue->tx_packets;
1254
1255         return 0;
1256 }
1257
1258
1259 /**
1260  * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1261  * @tx_queue:           Efx TX queue
1262  * @skb:                Socket buffer
1263  *
1264  * Context: You must hold netif_tx_lock() to call this function.
1265  *
1266  * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1267  * @skb was not enqueued.  In all cases @skb is consumed.  Return
1268  * %NETDEV_TX_OK.
1269  */
1270 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1271                                struct sk_buff *skb)
1272 {
1273         struct efx_nic *efx = tx_queue->efx;
1274         unsigned int old_insert_count = tx_queue->insert_count;
1275         int frag_i, rc;
1276         struct tso_state state;
1277
1278         /* Find the packet protocol and sanity-check it */
1279         state.protocol = efx_tso_check_protocol(skb);
1280
1281         rc = tso_start(&state, efx, tx_queue, skb);
1282         if (rc)
1283                 goto mem_err;
1284
1285         if (likely(state.in_len == 0)) {
1286                 /* Grab the first payload fragment. */
1287                 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1288                 frag_i = 0;
1289                 rc = tso_get_fragment(&state, efx,
1290                                       skb_shinfo(skb)->frags + frag_i);
1291                 if (rc)
1292                         goto mem_err;
1293         } else {
1294                 /* Payload starts in the header area. */
1295                 frag_i = -1;
1296         }
1297
1298         if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1299                 goto mem_err;
1300
1301         while (1) {
1302                 tso_fill_packet_with_fragment(tx_queue, skb, &state);
1303
1304                 /* Move onto the next fragment? */
1305                 if (state.in_len == 0) {
1306                         if (++frag_i >= skb_shinfo(skb)->nr_frags)
1307                                 /* End of payload reached. */
1308                                 break;
1309                         rc = tso_get_fragment(&state, efx,
1310                                               skb_shinfo(skb)->frags + frag_i);
1311                         if (rc)
1312                                 goto mem_err;
1313                 }
1314
1315                 /* Start at new packet? */
1316                 if (state.packet_space == 0 &&
1317                     tso_start_new_packet(tx_queue, skb, &state) < 0)
1318                         goto mem_err;
1319         }
1320
1321         netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
1322
1323         efx_tx_maybe_stop_queue(tx_queue);
1324
1325         /* Pass off to hardware */
1326         if (!skb->xmit_more || netif_xmit_stopped(tx_queue->core_txq)) {
1327                 struct efx_tx_queue *txq2 = efx_tx_queue_partner(tx_queue);
1328
1329                 /* There could be packets left on the partner queue if those
1330                  * SKBs had skb->xmit_more set. If we do not push those they
1331                  * could be left for a long time and cause a netdev watchdog.
1332                  */
1333                 if (txq2->xmit_more_available)
1334                         efx_nic_push_buffers(txq2);
1335
1336                 efx_nic_push_buffers(tx_queue);
1337         } else {
1338                 tx_queue->xmit_more_available = skb->xmit_more;
1339         }
1340
1341         tx_queue->tso_bursts++;
1342         return NETDEV_TX_OK;
1343
1344  mem_err:
1345         netif_err(efx, tx_err, efx->net_dev,
1346                   "Out of memory for TSO headers, or DMA mapping error\n");
1347         dev_kfree_skb_any(skb);
1348
1349         /* Free the DMA mapping we were in the process of writing out */
1350         if (state.unmap_len) {
1351                 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE)
1352                         dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr,
1353                                          state.unmap_len, DMA_TO_DEVICE);
1354                 else
1355                         dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr,
1356                                        state.unmap_len, DMA_TO_DEVICE);
1357         }
1358
1359         /* Free the header DMA mapping, if using option descriptors */
1360         if (state.header_unmap_len)
1361                 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr,
1362                                  state.header_unmap_len, DMA_TO_DEVICE);
1363
1364         efx_enqueue_unwind(tx_queue, old_insert_count);
1365         return NETDEV_TX_OK;
1366 }