1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/rwsem.h>
29 #include <linux/vmalloc.h>
30 #include <linux/i2c.h>
31 #include <linux/mtd/mtd.h>
32 #include <net/busy_poll.h>
38 /**************************************************************************
42 **************************************************************************/
44 #define EFX_DRIVER_VERSION "4.1"
47 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
54 /**************************************************************************
58 **************************************************************************/
60 #define EFX_MAX_CHANNELS 32U
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 #define EFX_EXTRA_CHANNEL_IOV 0
63 #define EFX_EXTRA_CHANNEL_PTP 1
64 #define EFX_MAX_EXTRA_CHANNELS 2U
66 /* Checksum generation is a per-queue option in hardware, so each
67 * queue visible to the networking core is backed by two hardware TX
69 #define EFX_MAX_TX_TC 2
70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
73 #define EFX_TXQ_TYPES 4
74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
76 /* Maximum possible MTU the driver supports */
77 #define EFX_MAX_MTU (9 * 1024)
79 /* Minimum MTU, from RFC791 (IP) */
80 #define EFX_MIN_MTU 68
82 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
83 * and should be a multiple of the cache line size.
85 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
87 /* If possible, we should ensure cache line alignment at start and end
88 * of every buffer. Otherwise, we just need to ensure 4-byte
89 * alignment of the network header.
92 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94 #define EFX_RX_BUF_ALIGNMENT 4
97 /* Forward declare Precision Time Protocol (PTP) support structure. */
99 struct hwtstamp_config;
101 struct efx_self_tests;
104 * struct efx_buffer - A general-purpose DMA buffer
105 * @addr: host base address of the buffer
106 * @dma_addr: DMA base address of the buffer
107 * @len: Buffer length, in bytes
109 * The NIC uses these buffers for its interrupt status registers and
119 * struct efx_special_buffer - DMA buffer entered into buffer table
120 * @buf: Standard &struct efx_buffer
121 * @index: Buffer index within controller;s buffer table
122 * @entries: Number of buffer table entries
124 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
125 * Event and descriptor rings are addressed via one or more buffer
126 * table entries (and so can be physically non-contiguous, although we
127 * currently do not take advantage of that). On Falcon and Siena we
128 * have to take care of allocating and initialising the entries
129 * ourselves. On later hardware this is managed by the firmware and
130 * @index and @entries are left as 0.
132 struct efx_special_buffer {
133 struct efx_buffer buf;
135 unsigned int entries;
139 * struct efx_tx_buffer - buffer state for a TX descriptor
140 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
141 * freed when descriptor completes
142 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
143 * @dma_addr: DMA address of the fragment.
144 * @flags: Flags for allocation and DMA mapping type
145 * @len: Length of this fragment.
146 * This field is zero when the queue slot is empty.
147 * @unmap_len: Length of this fragment to unmap
148 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
149 * Only valid if @unmap_len != 0.
151 struct efx_tx_buffer {
152 const struct sk_buff *skb;
157 unsigned short flags;
159 unsigned short unmap_len;
160 unsigned short dma_offset;
162 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
163 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
164 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
165 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
168 * struct efx_tx_queue - An Efx TX queue
170 * This is a ring buffer of TX fragments.
171 * Since the TX completion path always executes on the same
172 * CPU and the xmit path can operate on different CPUs,
173 * performance is increased by ensuring that the completion
174 * path and the xmit path operate on different cache lines.
175 * This is particularly important if the xmit path is always
176 * executing on one CPU which is different from the completion
177 * path. There is also a cache line for members which are
178 * read but not written on the fast path.
180 * @efx: The associated Efx NIC
181 * @queue: DMA queue number
182 * @tso_version: Version of TSO in use for this queue.
183 * @channel: The associated channel
184 * @core_txq: The networking core TX queue structure
185 * @buffer: The software buffer ring
186 * @cb_page: Array of pages of copy buffers. Carved up according to
187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
188 * @txd: The hardware descriptor ring
189 * @ptr_mask: The size of the ring minus 1.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191 * Size of the region is efx_piobuf_size.
192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193 * @initialised: Has hardware queue been initialised?
194 * @handle_tso: TSO xmit preparation handler. Sets up the TSO metadata and
195 * may also map tx data, depending on the nature of the TSO implementation.
196 * @read_count: Current read pointer.
197 * This is the number of buffers that have been removed from both rings.
198 * @old_write_count: The value of @write_count when last checked.
199 * This is here for performance reasons. The xmit path will
200 * only get the up-to-date value of @write_count if this
201 * variable indicates that the queue is empty. This is to
202 * avoid cache-line ping-pong between the xmit path and the
204 * @merge_events: Number of TX merged completion events
205 * @insert_count: Current insert pointer
206 * This is the number of buffers that have been added to the
208 * @write_count: Current write pointer
209 * This is the number of buffers that have been added to the
211 * @packet_write_count: Completable write pointer
212 * This is the write pointer of the last packet written.
213 * Normally this will equal @write_count, but as option descriptors
214 * don't produce completion events, they won't update this.
215 * Filled in iff @efx->type->option_descriptors; only used for PIO.
216 * Thus, this is written and used on EF10, and neither on farch.
217 * @old_read_count: The value of read_count when last checked.
218 * This is here for performance reasons. The xmit path will
219 * only get the up-to-date value of read_count if this
220 * variable indicates that the queue is full. This is to
221 * avoid cache-line ping-pong between the xmit path and the
223 * @tso_bursts: Number of times TSO xmit invoked by kernel
224 * @tso_long_headers: Number of packets with headers too long for standard
226 * @tso_packets: Number of packets via the TSO xmit path
227 * @tso_fallbacks: Number of times TSO fallback used
228 * @pushes: Number of times the TX push feature has been used
229 * @pio_packets: Number of times the TX PIO feature has been used
230 * @xmit_more_available: Are any packets waiting to be pushed to the NIC
231 * @cb_packets: Number of times the TX copybreak feature has been used
232 * @empty_read_count: If the completion path has seen the queue as empty
233 * and the transmission path has not yet checked this, the value of
234 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
236 struct efx_tx_queue {
237 /* Members which don't change on the fast path */
238 struct efx_nic *efx ____cacheline_aligned_in_smp;
240 unsigned int tso_version;
241 struct efx_channel *channel;
242 struct netdev_queue *core_txq;
243 struct efx_tx_buffer *buffer;
244 struct efx_buffer *cb_page;
245 struct efx_special_buffer txd;
246 unsigned int ptr_mask;
247 void __iomem *piobuf;
248 unsigned int piobuf_offset;
251 /* Function pointers used in the fast path. */
252 int (*handle_tso)(struct efx_tx_queue*, struct sk_buff*, bool *);
254 /* Members used mainly on the completion path */
255 unsigned int read_count ____cacheline_aligned_in_smp;
256 unsigned int old_write_count;
257 unsigned int merge_events;
258 unsigned int bytes_compl;
259 unsigned int pkts_compl;
261 /* Members used only on the xmit path */
262 unsigned int insert_count ____cacheline_aligned_in_smp;
263 unsigned int write_count;
264 unsigned int packet_write_count;
265 unsigned int old_read_count;
266 unsigned int tso_bursts;
267 unsigned int tso_long_headers;
268 unsigned int tso_packets;
269 unsigned int tso_fallbacks;
271 unsigned int pio_packets;
272 bool xmit_more_available;
273 unsigned int cb_packets;
274 /* Statistics to supplement MAC stats */
275 unsigned long tx_packets;
277 /* Members shared between paths and sometimes updated */
278 unsigned int empty_read_count ____cacheline_aligned_in_smp;
279 #define EFX_EMPTY_COUNT_VALID 0x80000000
280 atomic_t flush_outstanding;
283 #define EFX_TX_CB_ORDER 7
284 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
287 * struct efx_rx_buffer - An Efx RX data buffer
288 * @dma_addr: DMA base address of the buffer
289 * @page: The associated page buffer.
290 * Will be %NULL if the buffer slot is currently free.
291 * @page_offset: If pending: offset in @page of DMA base address.
292 * If completed: offset in @page of Ethernet header.
293 * @len: If pending: length for DMA descriptor.
294 * If completed: received length, excluding hash prefix.
295 * @flags: Flags for buffer and packet state. These are only set on the
296 * first buffer of a scattered packet.
298 struct efx_rx_buffer {
305 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
306 #define EFX_RX_PKT_CSUMMED 0x0002
307 #define EFX_RX_PKT_DISCARD 0x0004
308 #define EFX_RX_PKT_TCP 0x0040
309 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
312 * struct efx_rx_page_state - Page-based rx buffer state
314 * Inserted at the start of every page allocated for receive buffers.
315 * Used to facilitate sharing dma mappings between recycled rx buffers
316 * and those passed up to the kernel.
318 * @dma_addr: The dma address of this page.
320 struct efx_rx_page_state {
323 unsigned int __pad[0] ____cacheline_aligned;
327 * struct efx_rx_queue - An Efx RX queue
328 * @efx: The associated Efx NIC
329 * @core_index: Index of network core RX queue. Will be >= 0 iff this
330 * is associated with a real RX queue.
331 * @buffer: The software buffer ring
332 * @rxd: The hardware descriptor ring
333 * @ptr_mask: The size of the ring minus 1.
334 * @refill_enabled: Enable refill whenever fill level is low
335 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
336 * @rxq_flush_pending.
337 * @added_count: Number of buffers added to the receive queue.
338 * @notified_count: Number of buffers given to NIC (<= @added_count).
339 * @removed_count: Number of buffers removed from the receive queue.
340 * @scatter_n: Used by NIC specific receive code.
341 * @scatter_len: Used by NIC specific receive code.
342 * @page_ring: The ring to store DMA mapped pages for reuse.
343 * @page_add: Counter to calculate the write pointer for the recycle ring.
344 * @page_remove: Counter to calculate the read pointer for the recycle ring.
345 * @page_recycle_count: The number of pages that have been recycled.
346 * @page_recycle_failed: The number of pages that couldn't be recycled because
347 * the kernel still held a reference to them.
348 * @page_recycle_full: The number of pages that were released because the
349 * recycle ring was full.
350 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
351 * @max_fill: RX descriptor maximum fill level (<= ring size)
352 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
354 * @min_fill: RX descriptor minimum non-zero fill level.
355 * This records the minimum fill level observed when a ring
356 * refill was triggered.
357 * @recycle_count: RX buffer recycle counter.
358 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
360 struct efx_rx_queue {
363 struct efx_rx_buffer *buffer;
364 struct efx_special_buffer rxd;
365 unsigned int ptr_mask;
369 unsigned int added_count;
370 unsigned int notified_count;
371 unsigned int removed_count;
372 unsigned int scatter_n;
373 unsigned int scatter_len;
374 struct page **page_ring;
375 unsigned int page_add;
376 unsigned int page_remove;
377 unsigned int page_recycle_count;
378 unsigned int page_recycle_failed;
379 unsigned int page_recycle_full;
380 unsigned int page_ptr_mask;
381 unsigned int max_fill;
382 unsigned int fast_fill_trigger;
383 unsigned int min_fill;
384 unsigned int min_overfill;
385 unsigned int recycle_count;
386 struct timer_list slow_fill;
387 unsigned int slow_fill_count;
388 /* Statistics to supplement MAC stats */
389 unsigned long rx_packets;
392 enum efx_sync_events_state {
393 SYNC_EVENTS_DISABLED = 0,
394 SYNC_EVENTS_QUIESCENT,
395 SYNC_EVENTS_REQUESTED,
400 * struct efx_channel - An Efx channel
402 * A channel comprises an event queue, at least one TX queue, at least
403 * one RX queue, and an associated tasklet for processing the event
406 * @efx: Associated Efx NIC
407 * @channel: Channel instance number
408 * @type: Channel type definition
409 * @eventq_init: Event queue initialised flag
410 * @enabled: Channel enabled indicator
411 * @irq: IRQ number (MSI and MSI-X only)
412 * @irq_moderation_us: IRQ moderation value (in microseconds)
413 * @napi_dev: Net device used with NAPI
414 * @napi_str: NAPI control structure
415 * @state: state for NAPI vs busy polling
416 * @state_lock: lock protecting @state
417 * @eventq: Event queue buffer
418 * @eventq_mask: Event queue pointer mask
419 * @eventq_read_ptr: Event queue read pointer
420 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
421 * @irq_count: Number of IRQs since last adaptive moderation decision
422 * @irq_mod_score: IRQ moderation score
423 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
424 * indexed by filter ID
425 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
426 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
427 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
428 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
429 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
430 * @n_rx_overlength: Count of RX_OVERLENGTH errors
431 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
432 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
433 * lack of descriptors
434 * @n_rx_merge_events: Number of RX merged completion events
435 * @n_rx_merge_packets: Number of RX packets completed by merged events
436 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
437 * __efx_rx_packet(), or zero if there is none
438 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
439 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
440 * @rx_queue: RX queue for this channel
441 * @tx_queue: TX queues for this channel
442 * @sync_events_state: Current state of sync events on this channel
443 * @sync_timestamp_major: Major part of the last ptp sync event
444 * @sync_timestamp_minor: Minor part of the last ptp sync event
449 const struct efx_channel_type *type;
453 unsigned int irq_moderation_us;
454 struct net_device *napi_dev;
455 struct napi_struct napi_str;
456 #ifdef CONFIG_NET_RX_BUSY_POLL
457 unsigned long busy_poll_state;
459 struct efx_special_buffer eventq;
460 unsigned int eventq_mask;
461 unsigned int eventq_read_ptr;
464 unsigned int irq_count;
465 unsigned int irq_mod_score;
466 #ifdef CONFIG_RFS_ACCEL
467 unsigned int rfs_filters_added;
468 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
472 unsigned n_rx_tobe_disc;
473 unsigned n_rx_ip_hdr_chksum_err;
474 unsigned n_rx_tcp_udp_chksum_err;
475 unsigned n_rx_mcast_mismatch;
476 unsigned n_rx_frm_trunc;
477 unsigned n_rx_overlength;
478 unsigned n_skbuff_leaks;
479 unsigned int n_rx_nodesc_trunc;
480 unsigned int n_rx_merge_events;
481 unsigned int n_rx_merge_packets;
483 unsigned int rx_pkt_n_frags;
484 unsigned int rx_pkt_index;
486 struct efx_rx_queue rx_queue;
487 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
489 enum efx_sync_events_state sync_events_state;
490 u32 sync_timestamp_major;
491 u32 sync_timestamp_minor;
494 #ifdef CONFIG_NET_RX_BUSY_POLL
495 enum efx_channel_busy_poll_state {
496 EFX_CHANNEL_STATE_IDLE = 0,
497 EFX_CHANNEL_STATE_NAPI = BIT(0),
498 EFX_CHANNEL_STATE_NAPI_REQ_BIT = 1,
499 EFX_CHANNEL_STATE_NAPI_REQ = BIT(1),
500 EFX_CHANNEL_STATE_POLL_BIT = 2,
501 EFX_CHANNEL_STATE_POLL = BIT(2),
502 EFX_CHANNEL_STATE_DISABLE_BIT = 3,
505 static inline void efx_channel_busy_poll_init(struct efx_channel *channel)
507 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE);
510 /* Called from the device poll routine to get ownership of a channel. */
511 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
513 unsigned long prev, old = READ_ONCE(channel->busy_poll_state);
517 case EFX_CHANNEL_STATE_POLL:
518 /* Ensure efx_channel_try_lock_poll() wont starve us */
519 set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT,
520 &channel->busy_poll_state);
522 case EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_REQ:
527 prev = cmpxchg(&channel->busy_poll_state, old,
528 EFX_CHANNEL_STATE_NAPI);
529 if (unlikely(prev != old)) {
530 /* This is likely to mean we've just entered polling
531 * state. Go back round to set the REQ bit.
540 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
542 /* Make sure write has completed from efx_channel_lock_napi() */
544 WRITE_ONCE(channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE);
547 /* Called from efx_busy_poll(). */
548 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel)
550 return cmpxchg(&channel->busy_poll_state, EFX_CHANNEL_STATE_IDLE,
551 EFX_CHANNEL_STATE_POLL) == EFX_CHANNEL_STATE_IDLE;
554 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
556 clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state);
559 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
561 return test_bit(EFX_CHANNEL_STATE_POLL_BIT, &channel->busy_poll_state);
564 static inline void efx_channel_enable(struct efx_channel *channel)
566 clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT,
567 &channel->busy_poll_state);
570 /* Stop further polling or napi access.
571 * Returns false if the channel is currently busy polling.
573 static inline bool efx_channel_disable(struct efx_channel *channel)
575 set_bit(EFX_CHANNEL_STATE_DISABLE_BIT, &channel->busy_poll_state);
576 /* Implicit barrier in efx_channel_busy_polling() */
577 return !efx_channel_busy_polling(channel);
580 #else /* CONFIG_NET_RX_BUSY_POLL */
582 static inline void efx_channel_busy_poll_init(struct efx_channel *channel)
586 static inline bool efx_channel_lock_napi(struct efx_channel *channel)
591 static inline void efx_channel_unlock_napi(struct efx_channel *channel)
595 static inline bool efx_channel_try_lock_poll(struct efx_channel *channel)
600 static inline void efx_channel_unlock_poll(struct efx_channel *channel)
604 static inline bool efx_channel_busy_polling(struct efx_channel *channel)
609 static inline void efx_channel_enable(struct efx_channel *channel)
613 static inline bool efx_channel_disable(struct efx_channel *channel)
617 #endif /* CONFIG_NET_RX_BUSY_POLL */
620 * struct efx_msi_context - Context for each MSI
621 * @efx: The associated NIC
622 * @index: Index of the channel/IRQ
623 * @name: Name of the channel/IRQ
625 * Unlike &struct efx_channel, this is never reallocated and is always
626 * safe for the IRQ handler to access.
628 struct efx_msi_context {
631 char name[IFNAMSIZ + 6];
635 * struct efx_channel_type - distinguishes traffic and extra channels
636 * @handle_no_channel: Handle failure to allocate an extra channel
637 * @pre_probe: Set up extra state prior to initialisation
638 * @post_remove: Tear down extra state after finalisation, if allocated.
639 * May be called on channels that have not been probed.
640 * @get_name: Generate the channel's name (used for its IRQ handler)
641 * @copy: Copy the channel state prior to reallocation. May be %NULL if
642 * reallocation is not supported.
643 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
644 * @keep_eventq: Flag for whether event queue should be kept initialised
645 * while the device is stopped
647 struct efx_channel_type {
648 void (*handle_no_channel)(struct efx_nic *);
649 int (*pre_probe)(struct efx_channel *);
650 void (*post_remove)(struct efx_channel *);
651 void (*get_name)(struct efx_channel *, char *buf, size_t len);
652 struct efx_channel *(*copy)(const struct efx_channel *);
653 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
663 #define STRING_TABLE_LOOKUP(val, member) \
664 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
666 extern const char *const efx_loopback_mode_names[];
667 extern const unsigned int efx_loopback_mode_max;
668 #define LOOPBACK_MODE(efx) \
669 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
671 extern const char *const efx_reset_type_names[];
672 extern const unsigned int efx_reset_type_max;
673 #define RESET_TYPE(type) \
674 STRING_TABLE_LOOKUP(type, efx_reset_type)
677 /* Be careful if altering to correct macro below */
678 EFX_INT_MODE_MSIX = 0,
679 EFX_INT_MODE_MSI = 1,
680 EFX_INT_MODE_LEGACY = 2,
681 EFX_INT_MODE_MAX /* Insert any new items before this */
683 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
686 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
687 STATE_READY = 1, /* hardware ready and netdev registered */
688 STATE_DISABLED = 2, /* device disabled due to hardware errors */
689 STATE_RECOVERY = 3, /* device recovering from PCI error */
692 /* Forward declaration */
695 /* Pseudo bit-mask flow control field */
696 #define EFX_FC_RX FLOW_CTRL_RX
697 #define EFX_FC_TX FLOW_CTRL_TX
698 #define EFX_FC_AUTO 4
701 * struct efx_link_state - Current state of the link
703 * @fd: Link is full-duplex
704 * @fc: Actual flow control flags
705 * @speed: Link speed (Mbps)
707 struct efx_link_state {
714 static inline bool efx_link_state_equal(const struct efx_link_state *left,
715 const struct efx_link_state *right)
717 return left->up == right->up && left->fd == right->fd &&
718 left->fc == right->fc && left->speed == right->speed;
722 * struct efx_phy_operations - Efx PHY operations table
723 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
724 * efx->loopback_modes.
725 * @init: Initialise PHY
726 * @fini: Shut down PHY
727 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
728 * @poll: Update @link_state and report whether it changed.
729 * Serialised by the mac_lock.
730 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock.
731 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock.
732 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
733 * (only needed where AN bit is set in mmds)
734 * @test_alive: Test that PHY is 'alive' (online)
735 * @test_name: Get the name of a PHY-specific test/result
736 * @run_tests: Run tests and record results as appropriate (offline).
737 * Flags are the ethtool tests flags.
739 struct efx_phy_operations {
740 int (*probe) (struct efx_nic *efx);
741 int (*init) (struct efx_nic *efx);
742 void (*fini) (struct efx_nic *efx);
743 void (*remove) (struct efx_nic *efx);
744 int (*reconfigure) (struct efx_nic *efx);
745 bool (*poll) (struct efx_nic *efx);
746 void (*get_link_ksettings)(struct efx_nic *efx,
747 struct ethtool_link_ksettings *cmd);
748 int (*set_link_ksettings)(struct efx_nic *efx,
749 const struct ethtool_link_ksettings *cmd);
750 void (*set_npage_adv) (struct efx_nic *efx, u32);
751 int (*test_alive) (struct efx_nic *efx);
752 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
753 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
754 int (*get_module_eeprom) (struct efx_nic *efx,
755 struct ethtool_eeprom *ee,
757 int (*get_module_info) (struct efx_nic *efx,
758 struct ethtool_modinfo *modinfo);
762 * enum efx_phy_mode - PHY operating mode flags
763 * @PHY_MODE_NORMAL: on and should pass traffic
764 * @PHY_MODE_TX_DISABLED: on with TX disabled
765 * @PHY_MODE_LOW_POWER: set to low power through MDIO
766 * @PHY_MODE_OFF: switched off through external control
767 * @PHY_MODE_SPECIAL: on but will not pass traffic
771 PHY_MODE_TX_DISABLED = 1,
772 PHY_MODE_LOW_POWER = 2,
774 PHY_MODE_SPECIAL = 8,
777 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
779 return !!(mode & ~PHY_MODE_TX_DISABLED);
783 * struct efx_hw_stat_desc - Description of a hardware statistic
784 * @name: Name of the statistic as visible through ethtool, or %NULL if
785 * it should not be exposed
786 * @dma_width: Width in bits (0 for non-DMA statistics)
787 * @offset: Offset within stats (ignored for non-DMA statistics)
789 struct efx_hw_stat_desc {
795 /* Number of bits used in a multicast filter hash address */
796 #define EFX_MCAST_HASH_BITS 8
798 /* Number of (single-bit) entries in a multicast filter hash */
799 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
801 /* An Efx multicast filter hash */
802 union efx_multicast_hash {
803 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
804 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
810 * struct efx_nic - an Efx NIC
811 * @name: Device name (net device name or bus id before net device registered)
812 * @pci_dev: The PCI device
813 * @node: List node for maintaning primary/secondary function lists
814 * @primary: &struct efx_nic instance for the primary function of this
815 * controller. May be the same structure, and may be %NULL if no
816 * primary function is bound. Serialised by rtnl_lock.
817 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
818 * functions of the controller, if this is for the primary function.
819 * Serialised by rtnl_lock.
820 * @type: Controller type attributes
821 * @legacy_irq: IRQ number
822 * @workqueue: Workqueue for port reconfigures and the HW monitor.
823 * Work items do not hold and must not acquire RTNL.
824 * @workqueue_name: Name of workqueue
825 * @reset_work: Scheduled reset workitem
826 * @membase_phys: Memory BAR value as physical address
827 * @membase: Memory BAR value
828 * @interrupt_mode: Interrupt mode
829 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
830 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
831 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
832 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
833 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
834 * @msg_enable: Log message enable flags
835 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
836 * @reset_pending: Bitmask for pending resets
837 * @tx_queue: TX DMA queues
838 * @rx_queue: RX DMA queues
840 * @msi_context: Context for each MSI
841 * @extra_channel_types: Types of extra (non-traffic) channels that
842 * should be allocated for this NIC
843 * @rxq_entries: Size of receive queues requested by user.
844 * @txq_entries: Size of transmit queues requested by user.
845 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
846 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
847 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
848 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
849 * @sram_lim_qw: Qword address limit of SRAM
850 * @next_buffer_table: First available buffer table id
851 * @n_channels: Number of channels in use
852 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
853 * @n_tx_channels: Number of channels used for TX
854 * @rx_ip_align: RX DMA address offset to have IP header aligned in
855 * in accordance with NET_IP_ALIGN
856 * @rx_dma_len: Current maximum RX DMA length
857 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
858 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
859 * for use in sk_buff::truesize
860 * @rx_prefix_size: Size of RX prefix before packet data
861 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
862 * (valid only if @rx_prefix_size != 0; always negative)
863 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
864 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
865 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
866 * (valid only if channel->sync_timestamps_enabled; always negative)
867 * @rx_hash_key: Toeplitz hash key for RSS
868 * @rx_indir_table: Indirection table for RSS
869 * @rx_scatter: Scatter mode enabled for receives
870 * @rss_active: RSS enabled on hardware
871 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
872 * @int_error_count: Number of internal errors seen recently
873 * @int_error_expire: Time at which error count will be expired
874 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
875 * acknowledge but do nothing else.
876 * @irq_status: Interrupt status buffer
877 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
878 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
879 * @selftest_work: Work item for asynchronous self-test
880 * @mtd_list: List of MTDs attached to the NIC
881 * @nic_data: Hardware dependent state
882 * @mcdi: Management-Controller-to-Driver Interface state
883 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
884 * efx_monitor() and efx_reconfigure_port()
885 * @port_enabled: Port enabled indicator.
886 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
887 * efx_mac_work() with kernel interfaces. Safe to read under any
888 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
889 * be held to modify it.
890 * @port_initialized: Port initialized?
891 * @net_dev: Operating system network device. Consider holding the rtnl lock
892 * @fixed_features: Features which cannot be turned off
893 * @stats_buffer: DMA buffer for statistics
894 * @phy_type: PHY type
895 * @phy_op: PHY interface
896 * @phy_data: PHY private data (including PHY-specific stats)
897 * @mdio: PHY MDIO interface
898 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
899 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
900 * @link_advertising: Autonegotiation advertising flags
901 * @link_state: Current state of the link
902 * @n_link_state_changes: Number of times the link has changed state
903 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
904 * Protected by @mac_lock.
905 * @multicast_hash: Multicast hash table for Falcon-arch.
906 * Protected by @mac_lock.
907 * @wanted_fc: Wanted flow control flags
908 * @fc_disable: When non-zero flow control is disabled. Typically used to
909 * ensure that network back pressure doesn't delay dma queue flushes.
910 * Serialised by the rtnl lock.
911 * @mac_work: Work item for changing MAC promiscuity and multicast hash
912 * @loopback_mode: Loopback status
913 * @loopback_modes: Supported loopback mode bitmask
914 * @loopback_selftest: Offline self-test private state
915 * @filter_sem: Filter table rw_semaphore, for freeing the table
916 * @filter_lock: Filter table lock, for mere content changes
917 * @filter_state: Architecture-dependent filter table state
918 * @rps_expire_channel: Next channel to check for expiry
919 * @rps_expire_index: Next index to check for expiry in
920 * @rps_expire_channel's @rps_flow_id
921 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
922 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
923 * Decremented when the efx_flush_rx_queue() is called.
924 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
925 * completed (either success or failure). Not used when MCDI is used to
926 * flush receive queues.
927 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
928 * @vf_count: Number of VFs intended to be enabled.
929 * @vf_init_count: Number of VFs that have been fully initialised.
930 * @vi_scale: log2 number of vnics per VF.
931 * @ptp_data: PTP state data
932 * @vpd_sn: Serial number read from VPD
933 * @monitor_work: Hardware monitor workitem
934 * @biu_lock: BIU (bus interface unit) lock
935 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
936 * field is used by efx_test_interrupts() to verify that an
937 * interrupt has occurred.
938 * @stats_lock: Statistics update lock. Must be held when calling
939 * efx_nic_type::{update,start,stop}_stats.
940 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
942 * This is stored in the private area of the &struct net_device.
945 /* The following fields should be written very rarely */
948 struct list_head node;
949 struct efx_nic *primary;
950 struct list_head secondary_list;
951 struct pci_dev *pci_dev;
952 unsigned int port_num;
953 const struct efx_nic_type *type;
955 bool eeh_disabled_legacy_irq;
956 struct workqueue_struct *workqueue;
957 char workqueue_name[16];
958 struct work_struct reset_work;
959 resource_size_t membase_phys;
960 void __iomem *membase;
962 enum efx_int_mode interrupt_mode;
963 unsigned int timer_quantum_ns;
964 unsigned int timer_max_ns;
965 bool irq_rx_adaptive;
966 unsigned int irq_mod_step_us;
967 unsigned int irq_rx_moderation_us;
970 enum nic_state state;
971 unsigned long reset_pending;
973 struct efx_channel *channel[EFX_MAX_CHANNELS];
974 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
975 const struct efx_channel_type *
976 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
978 unsigned rxq_entries;
979 unsigned txq_entries;
980 unsigned int txq_stop_thresh;
981 unsigned int txq_wake_thresh;
985 unsigned sram_lim_qw;
986 unsigned next_buffer_table;
988 unsigned int max_channels;
989 unsigned int max_tx_channels;
991 unsigned n_rx_channels;
993 unsigned tx_channel_offset;
994 unsigned n_tx_channels;
995 unsigned int rx_ip_align;
996 unsigned int rx_dma_len;
997 unsigned int rx_buffer_order;
998 unsigned int rx_buffer_truesize;
999 unsigned int rx_page_buf_step;
1000 unsigned int rx_bufs_per_page;
1001 unsigned int rx_pages_per_batch;
1002 unsigned int rx_prefix_size;
1003 int rx_packet_hash_offset;
1004 int rx_packet_len_offset;
1005 int rx_packet_ts_offset;
1007 u32 rx_indir_table[128];
1010 bool rx_hash_udp_4tuple;
1012 unsigned int_error_count;
1013 unsigned long int_error_expire;
1015 bool irq_soft_enabled;
1016 struct efx_buffer irq_status;
1017 unsigned irq_zero_count;
1019 struct delayed_work selftest_work;
1021 #ifdef CONFIG_SFC_MTD
1022 struct list_head mtd_list;
1026 struct efx_mcdi_data *mcdi;
1028 struct mutex mac_lock;
1029 struct work_struct mac_work;
1032 bool mc_bist_for_other_fn;
1033 bool port_initialized;
1034 struct net_device *net_dev;
1036 netdev_features_t fixed_features;
1038 struct efx_buffer stats_buffer;
1039 u64 rx_nodesc_drops_total;
1040 u64 rx_nodesc_drops_while_down;
1041 bool rx_nodesc_drops_prev_state;
1043 unsigned int phy_type;
1044 const struct efx_phy_operations *phy_op;
1046 struct mdio_if_info mdio;
1047 unsigned int mdio_bus;
1048 enum efx_phy_mode phy_mode;
1050 u32 link_advertising;
1051 struct efx_link_state link_state;
1052 unsigned int n_link_state_changes;
1054 bool unicast_filter;
1055 union efx_multicast_hash multicast_hash;
1057 unsigned fc_disable;
1060 enum efx_loopback_mode loopback_mode;
1063 void *loopback_selftest;
1065 struct rw_semaphore filter_sem;
1066 spinlock_t filter_lock;
1068 #ifdef CONFIG_RFS_ACCEL
1069 unsigned int rps_expire_channel;
1070 unsigned int rps_expire_index;
1073 atomic_t active_queues;
1074 atomic_t rxq_flush_pending;
1075 atomic_t rxq_flush_outstanding;
1076 wait_queue_head_t flush_wq;
1078 #ifdef CONFIG_SFC_SRIOV
1080 unsigned vf_init_count;
1084 struct efx_ptp_data *ptp_data;
1088 /* The following fields may be written more often */
1090 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
1091 spinlock_t biu_lock;
1093 spinlock_t stats_lock;
1094 atomic_t n_rx_noskb_drops;
1097 static inline int efx_dev_registered(struct efx_nic *efx)
1099 return efx->net_dev->reg_state == NETREG_REGISTERED;
1102 static inline unsigned int efx_port_num(struct efx_nic *efx)
1104 return efx->port_num;
1107 struct efx_mtd_partition {
1108 struct list_head node;
1109 struct mtd_info mtd;
1110 const char *dev_type_name;
1111 const char *type_name;
1112 char name[IFNAMSIZ + 20];
1116 * struct efx_nic_type - Efx device type definition
1117 * @mem_bar: Get the memory BAR
1118 * @mem_map_size: Get memory BAR mapped size
1119 * @probe: Probe the controller
1120 * @remove: Free resources allocated by probe()
1121 * @init: Initialise the controller
1122 * @dimension_resources: Dimension controller resources (buffer table,
1123 * and VIs once the available interrupt resources are clear)
1124 * @fini: Shut down the controller
1125 * @monitor: Periodic function for polling link state and hardware monitor
1126 * @map_reset_reason: Map ethtool reset reason to a reset method
1127 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1128 * @reset: Reset the controller hardware and possibly the PHY. This will
1129 * be called while the controller is uninitialised.
1130 * @probe_port: Probe the MAC and PHY
1131 * @remove_port: Free resources allocated by probe_port()
1132 * @handle_global_event: Handle a "global" event (may be %NULL)
1133 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1134 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1135 * (for Falcon architecture)
1136 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1138 * @prepare_flr: Prepare for an FLR
1139 * @finish_flr: Clean up after an FLR
1140 * @describe_stats: Describe statistics for ethtool
1141 * @update_stats: Update statistics not provided by event handling.
1142 * Either argument may be %NULL.
1143 * @start_stats: Start the regular fetching of statistics
1144 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1145 * @stop_stats: Stop the regular fetching of statistics
1146 * @set_id_led: Set state of identifying LED or revert to automatic function
1147 * @push_irq_moderation: Apply interrupt moderation value
1148 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1149 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1150 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1151 * to the hardware. Serialised by the mac_lock.
1152 * @check_mac_fault: Check MAC fault state. True if fault present.
1153 * @get_wol: Get WoL configuration from driver state
1154 * @set_wol: Push WoL configuration to the NIC
1155 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1156 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1157 * expected to reset the NIC.
1158 * @test_nvram: Test validity of NVRAM contents
1159 * @mcdi_request: Send an MCDI request with the given header and SDU.
1160 * The SDU length may be any value from 0 up to the protocol-
1161 * defined maximum, but its buffer will be padded to a multiple
1163 * @mcdi_poll_response: Test whether an MCDI response is available.
1164 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1165 * be a multiple of 4. The length may not be, but the buffer
1166 * will be padded so it is safe to round up.
1167 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1168 * return an appropriate error code for aborting any current
1169 * request; otherwise return 0.
1170 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1171 * be separately enabled after this.
1172 * @irq_test_generate: Generate a test IRQ
1173 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1174 * queue must be separately disabled before this.
1175 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1176 * a pointer to the &struct efx_msi_context for the channel.
1177 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1178 * is a pointer to the &struct efx_nic.
1179 * @tx_probe: Allocate resources for TX queue
1180 * @tx_init: Initialise TX queue on the NIC
1181 * @tx_remove: Free resources for TX queue
1182 * @tx_write: Write TX descriptors and doorbell
1183 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1184 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1185 * @rx_probe: Allocate resources for RX queue
1186 * @rx_init: Initialise RX queue on the NIC
1187 * @rx_remove: Free resources for RX queue
1188 * @rx_write: Write RX descriptors and doorbell
1189 * @rx_defer_refill: Generate a refill reminder event
1190 * @ev_probe: Allocate resources for event queue
1191 * @ev_init: Initialise event queue on the NIC
1192 * @ev_fini: Deinitialise event queue on the NIC
1193 * @ev_remove: Free resources for event queue
1194 * @ev_process: Process events for a queue, up to the given NAPI quota
1195 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1196 * @ev_test_generate: Generate a test event
1197 * @filter_table_probe: Probe filter capabilities and set up filter software state
1198 * @filter_table_restore: Restore filters removed from hardware
1199 * @filter_table_remove: Remove filters from hardware and tear down software state
1200 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1201 * @filter_insert: add or replace a filter
1202 * @filter_remove_safe: remove a filter by ID, carefully
1203 * @filter_get_safe: retrieve a filter by ID, carefully
1204 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1205 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1206 * @filter_count_rx_used: Get the number of filters in use at a given priority
1207 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1208 * @filter_get_rx_ids: Get list of RX filters at a given priority
1209 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1210 * atomic. The hardware change may be asynchronous but should
1211 * not be delayed for long. It may fail if this can't be done
1213 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1214 * This must check whether the specified table entry is used by RFS
1215 * and that rps_may_expire_flow() returns true for it.
1216 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1217 * using efx_mtd_add()
1218 * @mtd_rename: Set an MTD partition name using the net device name
1219 * @mtd_read: Read from an MTD partition
1220 * @mtd_erase: Erase part of an MTD partition
1221 * @mtd_write: Write to an MTD partition
1222 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1223 * also notifies the driver that a writer has finished using this
1225 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1226 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1227 * timestamping, possibly only temporarily for the purposes of a reset.
1228 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1229 * and tx_type will already have been validated but this operation
1230 * must validate and update rx_filter.
1231 * @get_phys_port_id: Get the underlying physical port id.
1232 * @set_mac_address: Set the MAC address of the device
1233 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1234 * If %NULL, then device does not support any TSO version.
1235 * @revision: Hardware architecture revision
1236 * @txd_ptr_tbl_base: TX descriptor ring base address
1237 * @rxd_ptr_tbl_base: RX descriptor ring base address
1238 * @buf_tbl_base: Buffer table base address
1239 * @evq_ptr_tbl_base: Event queue pointer table base address
1240 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1241 * @max_dma_mask: Maximum possible DMA mask
1242 * @rx_prefix_size: Size of RX prefix before packet data
1243 * @rx_hash_offset: Offset of RX flow hash within prefix
1244 * @rx_ts_offset: Offset of timestamp within prefix
1245 * @rx_buffer_padding: Size of padding at end of RX packet
1246 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1247 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1248 * @option_descriptors: NIC supports TX option descriptors
1249 * @max_interrupt_mode: Highest capability interrupt mode supported
1250 * from &enum efx_init_mode.
1251 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1252 * @offload_features: net_device feature flags for protocol offload
1253 * features implemented in hardware
1254 * @mcdi_max_ver: Maximum MCDI version supported
1255 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1257 struct efx_nic_type {
1259 unsigned int mem_bar;
1260 unsigned int (*mem_map_size)(struct efx_nic *efx);
1261 int (*probe)(struct efx_nic *efx);
1262 void (*remove)(struct efx_nic *efx);
1263 int (*init)(struct efx_nic *efx);
1264 int (*dimension_resources)(struct efx_nic *efx);
1265 void (*fini)(struct efx_nic *efx);
1266 void (*monitor)(struct efx_nic *efx);
1267 enum reset_type (*map_reset_reason)(enum reset_type reason);
1268 int (*map_reset_flags)(u32 *flags);
1269 int (*reset)(struct efx_nic *efx, enum reset_type method);
1270 int (*probe_port)(struct efx_nic *efx);
1271 void (*remove_port)(struct efx_nic *efx);
1272 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1273 int (*fini_dmaq)(struct efx_nic *efx);
1274 void (*prepare_flush)(struct efx_nic *efx);
1275 void (*finish_flush)(struct efx_nic *efx);
1276 void (*prepare_flr)(struct efx_nic *efx);
1277 void (*finish_flr)(struct efx_nic *efx);
1278 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1279 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1280 struct rtnl_link_stats64 *core_stats);
1281 void (*start_stats)(struct efx_nic *efx);
1282 void (*pull_stats)(struct efx_nic *efx);
1283 void (*stop_stats)(struct efx_nic *efx);
1284 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1285 void (*push_irq_moderation)(struct efx_channel *channel);
1286 int (*reconfigure_port)(struct efx_nic *efx);
1287 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1288 int (*reconfigure_mac)(struct efx_nic *efx);
1289 bool (*check_mac_fault)(struct efx_nic *efx);
1290 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1291 int (*set_wol)(struct efx_nic *efx, u32 type);
1292 void (*resume_wol)(struct efx_nic *efx);
1293 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1294 int (*test_nvram)(struct efx_nic *efx);
1295 void (*mcdi_request)(struct efx_nic *efx,
1296 const efx_dword_t *hdr, size_t hdr_len,
1297 const efx_dword_t *sdu, size_t sdu_len);
1298 bool (*mcdi_poll_response)(struct efx_nic *efx);
1299 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1300 size_t pdu_offset, size_t pdu_len);
1301 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1302 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1303 void (*irq_enable_master)(struct efx_nic *efx);
1304 int (*irq_test_generate)(struct efx_nic *efx);
1305 void (*irq_disable_non_ev)(struct efx_nic *efx);
1306 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1307 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1308 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1309 void (*tx_init)(struct efx_tx_queue *tx_queue);
1310 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1311 void (*tx_write)(struct efx_tx_queue *tx_queue);
1312 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1313 dma_addr_t dma_addr, unsigned int len);
1314 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1315 const u32 *rx_indir_table, const u8 *key);
1316 int (*rx_pull_rss_config)(struct efx_nic *efx);
1317 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1318 void (*rx_init)(struct efx_rx_queue *rx_queue);
1319 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1320 void (*rx_write)(struct efx_rx_queue *rx_queue);
1321 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1322 int (*ev_probe)(struct efx_channel *channel);
1323 int (*ev_init)(struct efx_channel *channel);
1324 void (*ev_fini)(struct efx_channel *channel);
1325 void (*ev_remove)(struct efx_channel *channel);
1326 int (*ev_process)(struct efx_channel *channel, int quota);
1327 void (*ev_read_ack)(struct efx_channel *channel);
1328 void (*ev_test_generate)(struct efx_channel *channel);
1329 int (*filter_table_probe)(struct efx_nic *efx);
1330 void (*filter_table_restore)(struct efx_nic *efx);
1331 void (*filter_table_remove)(struct efx_nic *efx);
1332 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1333 s32 (*filter_insert)(struct efx_nic *efx,
1334 struct efx_filter_spec *spec, bool replace);
1335 int (*filter_remove_safe)(struct efx_nic *efx,
1336 enum efx_filter_priority priority,
1338 int (*filter_get_safe)(struct efx_nic *efx,
1339 enum efx_filter_priority priority,
1340 u32 filter_id, struct efx_filter_spec *);
1341 int (*filter_clear_rx)(struct efx_nic *efx,
1342 enum efx_filter_priority priority);
1343 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1344 enum efx_filter_priority priority);
1345 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1346 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1347 enum efx_filter_priority priority,
1348 u32 *buf, u32 size);
1349 #ifdef CONFIG_RFS_ACCEL
1350 s32 (*filter_rfs_insert)(struct efx_nic *efx,
1351 struct efx_filter_spec *spec);
1352 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1353 unsigned int index);
1355 #ifdef CONFIG_SFC_MTD
1356 int (*mtd_probe)(struct efx_nic *efx);
1357 void (*mtd_rename)(struct efx_mtd_partition *part);
1358 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1359 size_t *retlen, u8 *buffer);
1360 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1361 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1362 size_t *retlen, const u8 *buffer);
1363 int (*mtd_sync)(struct mtd_info *mtd);
1365 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1366 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1367 int (*ptp_set_ts_config)(struct efx_nic *efx,
1368 struct hwtstamp_config *init);
1369 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1370 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1371 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1372 int (*get_phys_port_id)(struct efx_nic *efx,
1373 struct netdev_phys_item_id *ppid);
1374 int (*sriov_init)(struct efx_nic *efx);
1375 void (*sriov_fini)(struct efx_nic *efx);
1376 bool (*sriov_wanted)(struct efx_nic *efx);
1377 void (*sriov_reset)(struct efx_nic *efx);
1378 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1379 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1380 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1382 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1384 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1385 struct ifla_vf_info *ivi);
1386 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1388 int (*vswitching_probe)(struct efx_nic *efx);
1389 int (*vswitching_restore)(struct efx_nic *efx);
1390 void (*vswitching_remove)(struct efx_nic *efx);
1391 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1392 int (*set_mac_address)(struct efx_nic *efx);
1393 u32 (*tso_versions)(struct efx_nic *efx);
1396 unsigned int txd_ptr_tbl_base;
1397 unsigned int rxd_ptr_tbl_base;
1398 unsigned int buf_tbl_base;
1399 unsigned int evq_ptr_tbl_base;
1400 unsigned int evq_rptr_tbl_base;
1402 unsigned int rx_prefix_size;
1403 unsigned int rx_hash_offset;
1404 unsigned int rx_ts_offset;
1405 unsigned int rx_buffer_padding;
1406 bool can_rx_scatter;
1407 bool always_rx_scatter;
1408 bool option_descriptors;
1409 unsigned int max_interrupt_mode;
1410 unsigned int timer_period_max;
1411 netdev_features_t offload_features;
1413 unsigned int max_rx_ip_filters;
1414 u32 hwtstamp_filters;
1415 unsigned int rx_hash_key_size;
1418 /**************************************************************************
1420 * Prototypes and inline functions
1422 *************************************************************************/
1424 static inline struct efx_channel *
1425 efx_get_channel(struct efx_nic *efx, unsigned index)
1427 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1428 return efx->channel[index];
1431 /* Iterate over all used channels */
1432 #define efx_for_each_channel(_channel, _efx) \
1433 for (_channel = (_efx)->channel[0]; \
1435 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1436 (_efx)->channel[_channel->channel + 1] : NULL)
1438 /* Iterate over all used channels in reverse */
1439 #define efx_for_each_channel_rev(_channel, _efx) \
1440 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1442 _channel = _channel->channel ? \
1443 (_efx)->channel[_channel->channel - 1] : NULL)
1445 static inline struct efx_tx_queue *
1446 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1448 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels ||
1449 type >= EFX_TXQ_TYPES);
1450 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1453 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1455 return channel->channel - channel->efx->tx_channel_offset <
1456 channel->efx->n_tx_channels;
1459 static inline struct efx_tx_queue *
1460 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1462 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_tx_queues(channel) ||
1463 type >= EFX_TXQ_TYPES);
1464 return &channel->tx_queue[type];
1467 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1469 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1470 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1473 /* Iterate over all TX queues belonging to a channel */
1474 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1475 if (!efx_channel_has_tx_queues(_channel)) \
1478 for (_tx_queue = (_channel)->tx_queue; \
1479 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1480 efx_tx_queue_used(_tx_queue); \
1483 /* Iterate over all possible TX queues belonging to a channel */
1484 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1485 if (!efx_channel_has_tx_queues(_channel)) \
1488 for (_tx_queue = (_channel)->tx_queue; \
1489 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1492 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1494 return channel->rx_queue.core_index >= 0;
1497 static inline struct efx_rx_queue *
1498 efx_channel_get_rx_queue(struct efx_channel *channel)
1500 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1501 return &channel->rx_queue;
1504 /* Iterate over all RX queues belonging to a channel */
1505 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1506 if (!efx_channel_has_rx_queue(_channel)) \
1509 for (_rx_queue = &(_channel)->rx_queue; \
1513 static inline struct efx_channel *
1514 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1516 return container_of(rx_queue, struct efx_channel, rx_queue);
1519 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1521 return efx_rx_queue_channel(rx_queue)->channel;
1524 /* Returns a pointer to the specified receive buffer in the RX
1527 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1530 return &rx_queue->buffer[index];
1534 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1536 * This calculates the maximum frame length that will be used for a
1537 * given MTU. The frame length will be equal to the MTU plus a
1538 * constant amount of header space and padding. This is the quantity
1539 * that the net driver will program into the MAC as the maximum frame
1542 * The 10G MAC requires 8-byte alignment on the frame
1543 * length, so we round up to the nearest 8.
1545 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1546 * XGMII cycle). If the frame length reaches the maximum value in the
1547 * same cycle, the XMAC can miss the IPG altogether. We work around
1548 * this by adding a further 16 bytes.
1550 #define EFX_FRAME_PAD 16
1551 #define EFX_MAX_FRAME_LEN(mtu) \
1552 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1554 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1556 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1558 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1560 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1563 /* Get all supported features.
1564 * If a feature is not fixed, it is present in hw_features.
1565 * If a feature is fixed, it does not present in hw_features, but
1566 * always in features.
1568 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1570 const struct net_device *net_dev = efx->net_dev;
1572 return net_dev->features | net_dev->hw_features;
1575 /* Get the current TX queue insert index. */
1576 static inline unsigned int
1577 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1579 return tx_queue->insert_count & tx_queue->ptr_mask;
1582 /* Get a TX buffer. */
1583 static inline struct efx_tx_buffer *
1584 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1586 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1589 /* Get a TX buffer, checking it's not currently in use. */
1590 static inline struct efx_tx_buffer *
1591 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1593 struct efx_tx_buffer *buffer =
1594 __efx_tx_queue_get_insert_buffer(tx_queue);
1596 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1597 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1598 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1603 #endif /* EFX_NET_DRIVER_H */