1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2022 Xilinx Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
17 #include "ef100_regs.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
25 #include "ef100_sriov.h"
26 #include "ef100_netdev.h"
27 #include "rx_common.h"
29 #define EF100_MAX_VIS 4096
30 #define EF100_NUM_MCDI_BUFFERS 1
31 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
33 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
37 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
39 struct ef100_nic_data *nic_data = efx->nic_data;
42 *dma_addr = nic_data->mcdi_buf.dma_addr +
43 bufid * ALIGN(MCDI_BUF_LEN, 256);
44 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
47 static int ef100_get_warm_boot_count(struct efx_nic *efx)
51 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
53 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
54 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
55 efx->state = STATE_DISABLED;
58 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
59 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
63 static void ef100_mcdi_request(struct efx_nic *efx,
64 const efx_dword_t *hdr, size_t hdr_len,
65 const efx_dword_t *sdu, size_t sdu_len)
68 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
70 memcpy(pdu, hdr, hdr_len);
71 memcpy(pdu + hdr_len, sdu, sdu_len);
74 /* The hardware provides 'low' and 'high' (doorbell) registers
75 * for passing the 64-bit address of an MCDI request to
76 * firmware. However the dwords are swapped by firmware. The
77 * least significant bits of the doorbell are then 0 for all
78 * MCDI requests due to alignment.
80 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
81 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
84 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
86 const efx_dword_t hdr =
87 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
90 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
93 static void ef100_mcdi_read_response(struct efx_nic *efx,
94 efx_dword_t *outbuf, size_t offset,
97 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
99 memcpy(outbuf, pdu + offset, outlen);
102 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
104 struct ef100_nic_data *nic_data = efx->nic_data;
107 rc = ef100_get_warm_boot_count(efx);
109 /* The firmware is presumably in the process of
110 * rebooting. However, we are supposed to report each
111 * reboot just once, so we must only do that once we
112 * can read and store the updated warm boot count.
117 if (rc == nic_data->warm_boot_count)
120 nic_data->warm_boot_count = rc;
125 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
131 static int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address)
133 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
137 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
139 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
140 outbuf, sizeof(outbuf), &outlen);
143 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
146 ether_addr_copy(mac_address,
147 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
151 int efx_ef100_init_datapath_caps(struct efx_nic *efx)
153 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
154 struct ef100_nic_data *nic_data = efx->nic_data;
159 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
161 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
162 outbuf, sizeof(outbuf), &outlen);
165 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
166 netif_err(efx, drv, efx->net_dev,
167 "unable to read datapath firmware capabilities\n");
171 nic_data->datapath_caps = MCDI_DWORD(outbuf,
172 GET_CAPABILITIES_OUT_FLAGS1);
173 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
174 GET_CAPABILITIES_V2_OUT_FLAGS2);
175 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
176 nic_data->datapath_caps3 = 0;
178 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
179 GET_CAPABILITIES_V7_OUT_FLAGS3);
181 vi_window_mode = MCDI_BYTE(outbuf,
182 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
183 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
187 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
188 struct net_device *net_dev = efx->net_dev;
189 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
190 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
191 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
193 net_dev->features |= tso;
194 net_dev->hw_features |= tso;
195 net_dev->hw_enc_features |= tso;
196 /* EF100 HW can only offload outer checksums if they are UDP,
197 * so for GRE_CSUM we have to use GSO_PARTIAL.
199 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
201 efx->num_mac_stats = MCDI_WORD(outbuf,
202 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
203 netif_dbg(efx, probe, efx->net_dev,
204 "firmware reports num_mac_stats = %u\n",
211 static int ef100_ev_probe(struct efx_channel *channel)
213 /* Allocate an extra descriptor for the QMDA status completion entry */
214 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
215 (channel->eventq_mask + 2) *
220 static int ef100_ev_init(struct efx_channel *channel)
222 struct ef100_nic_data *nic_data = channel->efx->nic_data;
224 /* initial phase is 0 */
225 clear_bit(channel->channel, nic_data->evq_phases);
227 return efx_mcdi_ev_init(channel, false, false);
230 static void ef100_ev_read_ack(struct efx_channel *channel)
232 efx_dword_t evq_prime;
234 EFX_POPULATE_DWORD_2(evq_prime,
235 ERF_GZ_EVQ_ID, channel->channel,
236 ERF_GZ_IDX, channel->eventq_read_ptr &
237 channel->eventq_mask);
239 efx_writed(channel->efx, &evq_prime,
240 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
243 static int ef100_ev_process(struct efx_channel *channel, int quota)
245 struct efx_nic *efx = channel->efx;
246 struct ef100_nic_data *nic_data;
247 bool evq_phase, old_evq_phase;
248 unsigned int read_ptr;
249 efx_qword_t *p_event;
254 if (unlikely(!channel->enabled))
257 nic_data = efx->nic_data;
258 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
259 old_evq_phase = evq_phase;
260 read_ptr = channel->eventq_read_ptr;
261 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
263 while (spent < quota) {
264 p_event = efx_event(channel, read_ptr);
266 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
267 if (ev_phase != evq_phase)
270 netif_vdbg(efx, drv, efx->net_dev,
271 "processing event on %d " EFX_QWORD_FMT "\n",
272 channel->channel, EFX_QWORD_VAL(*p_event));
274 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
277 case ESE_GZ_EF100_EV_RX_PKTS:
278 efx_ef100_ev_rx(channel, p_event);
281 case ESE_GZ_EF100_EV_MCDI:
282 efx_mcdi_process_event(channel, p_event);
284 case ESE_GZ_EF100_EV_TX_COMPLETION:
285 ef100_ev_tx(channel, p_event);
287 case ESE_GZ_EF100_EV_DRIVER:
288 netif_info(efx, drv, efx->net_dev,
289 "Driver initiated event " EFX_QWORD_FMT "\n",
290 EFX_QWORD_VAL(*p_event));
293 netif_info(efx, drv, efx->net_dev,
294 "Unhandled event " EFX_QWORD_FMT "\n",
295 EFX_QWORD_VAL(*p_event));
299 if ((read_ptr & channel->eventq_mask) == 0)
300 evq_phase = !evq_phase;
303 channel->eventq_read_ptr = read_ptr;
304 if (evq_phase != old_evq_phase)
305 change_bit(channel->channel, nic_data->evq_phases);
310 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
312 struct efx_msi_context *context = dev_id;
313 struct efx_nic *efx = context->efx;
315 netif_vdbg(efx, intr, efx->net_dev,
316 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
318 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
319 /* Note test interrupts */
320 if (context->index == efx->irq_level)
321 efx->last_irq_cpu = raw_smp_processor_id();
323 /* Schedule processing of the channel */
324 efx_schedule_channel_irq(efx->channel[context->index]);
330 int ef100_phy_probe(struct efx_nic *efx)
332 struct efx_mcdi_phy_data *phy_data;
335 /* Probe for the PHY */
336 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
340 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
344 /* Populate driver and ethtool settings */
345 phy_data = efx->phy_data;
346 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
347 efx->link_advertising);
348 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
351 /* Default to Autonegotiated flow control if the PHY supports it */
352 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
353 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
354 efx->wanted_fc |= EFX_FC_AUTO;
355 efx_link_set_wanted_fc(efx, efx->wanted_fc);
357 /* Push settings to the PHY. Failure is not fatal, the user can try to
358 * fix it using ethtool.
360 rc = efx_mcdi_port_reconfigure(efx);
361 if (rc && rc != -EPERM)
362 netif_warn(efx, drv, efx->net_dev,
363 "could not initialise PHY settings\n");
368 int ef100_filter_table_probe(struct efx_nic *efx)
370 return efx_mcdi_filter_table_probe(efx, true);
373 static int ef100_filter_table_up(struct efx_nic *efx)
377 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
379 efx_mcdi_filter_table_down(efx);
383 rc = efx_mcdi_filter_add_vlan(efx, 0);
385 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
386 efx_mcdi_filter_table_down(efx);
392 static void ef100_filter_table_down(struct efx_nic *efx)
394 efx_mcdi_filter_del_vlan(efx, 0);
395 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
396 efx_mcdi_filter_table_down(efx);
401 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
403 WARN_ON(!mutex_is_locked(&efx->mac_lock));
405 efx_mcdi_filter_sync_rx_mode(efx);
407 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
408 return efx_mcdi_set_mtu(efx);
409 return efx_mcdi_set_mac(efx);
412 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
414 if (reason == RESET_TYPE_TX_WATCHDOG)
416 return RESET_TYPE_DISABLE;
419 static int ef100_map_reset_flags(u32 *flags)
421 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
422 if ((*flags & EF100_RESET_PORT)) {
423 *flags &= ~EF100_RESET_PORT;
424 return RESET_TYPE_ALL;
426 if (*flags & ETH_RESET_MGMT) {
427 *flags &= ~ETH_RESET_MGMT;
428 return RESET_TYPE_DISABLE;
434 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
438 dev_close(efx->net_dev);
440 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
441 netif_device_attach(efx->net_dev);
442 __clear_bit(reset_type, &efx->reset_pending);
443 rc = dev_open(efx->net_dev, NULL);
444 } else if (reset_type == RESET_TYPE_ALL) {
445 rc = efx_mcdi_reset(efx, reset_type);
449 netif_device_attach(efx->net_dev);
451 rc = dev_open(efx->net_dev, NULL);
453 rc = 1; /* Leave the device closed */
458 static void ef100_common_stat_mask(unsigned long *mask)
460 __set_bit(EF100_STAT_port_rx_packets, mask);
461 __set_bit(EF100_STAT_port_tx_packets, mask);
462 __set_bit(EF100_STAT_port_rx_bytes, mask);
463 __set_bit(EF100_STAT_port_tx_bytes, mask);
464 __set_bit(EF100_STAT_port_rx_multicast, mask);
465 __set_bit(EF100_STAT_port_rx_bad, mask);
466 __set_bit(EF100_STAT_port_rx_align_error, mask);
467 __set_bit(EF100_STAT_port_rx_overflow, mask);
470 static void ef100_ethtool_stat_mask(unsigned long *mask)
472 __set_bit(EF100_STAT_port_tx_pause, mask);
473 __set_bit(EF100_STAT_port_tx_unicast, mask);
474 __set_bit(EF100_STAT_port_tx_multicast, mask);
475 __set_bit(EF100_STAT_port_tx_broadcast, mask);
476 __set_bit(EF100_STAT_port_tx_lt64, mask);
477 __set_bit(EF100_STAT_port_tx_64, mask);
478 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
479 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
480 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
481 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
482 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
483 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
484 __set_bit(EF100_STAT_port_rx_good, mask);
485 __set_bit(EF100_STAT_port_rx_pause, mask);
486 __set_bit(EF100_STAT_port_rx_unicast, mask);
487 __set_bit(EF100_STAT_port_rx_broadcast, mask);
488 __set_bit(EF100_STAT_port_rx_lt64, mask);
489 __set_bit(EF100_STAT_port_rx_64, mask);
490 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
491 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
492 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
493 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
494 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
495 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
496 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
497 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
498 __set_bit(EF100_STAT_port_rx_length_error, mask);
499 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
500 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
501 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
504 #define EF100_DMA_STAT(ext_name, mcdi_name) \
505 [EF100_STAT_ ## ext_name] = \
506 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
508 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
509 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
510 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
511 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
512 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
513 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
514 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
515 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
516 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
517 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
518 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
519 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
520 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
521 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
522 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
523 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
524 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
525 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
526 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
527 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
528 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
529 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
530 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
531 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
532 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
533 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
534 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
535 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
536 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
537 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
538 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
539 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
540 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
541 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
542 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
543 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
544 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
545 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
546 EFX_GENERIC_SW_STAT(rx_noskb_drops),
549 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
551 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
553 ef100_ethtool_stat_mask(mask);
554 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
558 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
559 struct rtnl_link_stats64 *core_stats)
561 struct ef100_nic_data *nic_data = efx->nic_data;
562 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
563 size_t stats_count = 0, index;
564 u64 *stats = nic_data->stats;
566 ef100_ethtool_stat_mask(mask);
569 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
570 if (ef100_stat_desc[index].name) {
571 *full_stats++ = stats[index];
580 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
581 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
582 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
583 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
584 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
585 stats[GENERIC_STAT_rx_nodesc_trunc] +
586 stats[GENERIC_STAT_rx_noskb_drops];
587 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
588 core_stats->rx_length_errors =
589 stats[EF100_STAT_port_rx_gtjumbo] +
590 stats[EF100_STAT_port_rx_length_error];
591 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
592 core_stats->rx_frame_errors =
593 stats[EF100_STAT_port_rx_align_error];
594 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
595 core_stats->rx_errors = (core_stats->rx_length_errors +
596 core_stats->rx_crc_errors +
597 core_stats->rx_frame_errors);
602 static size_t ef100_update_stats(struct efx_nic *efx,
604 struct rtnl_link_stats64 *core_stats)
606 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
607 struct ef100_nic_data *nic_data = efx->nic_data;
608 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
609 u64 *stats = nic_data->stats;
611 ef100_common_stat_mask(mask);
612 ef100_ethtool_stat_mask(mask);
617 efx_nic_copy_stats(efx, mc_stats);
618 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
619 stats, mc_stats, false);
623 return ef100_update_stats_common(efx, full_stats, core_stats);
626 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
627 struct netdev_phys_item_id *ppid)
629 struct ef100_nic_data *nic_data = efx->nic_data;
631 if (!is_valid_ether_addr(nic_data->port_id))
634 ppid->id_len = ETH_ALEN;
635 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
640 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
642 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
644 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
646 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
647 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
648 inbuf, sizeof(inbuf), NULL, 0, NULL);
651 #define EFX_EF100_TEST 1
653 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
655 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
656 struct efx_nic *efx = channel->efx;
660 EFX_POPULATE_QWORD_2(event,
661 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
662 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
664 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
666 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
667 * already swapped the data to little-endian order.
669 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
670 sizeof(efx_qword_t));
672 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
674 if (rc && (rc != -ENETDOWN))
681 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
684 static unsigned int ef100_check_caps(const struct efx_nic *efx,
687 const struct ef100_nic_data *nic_data = efx->nic_data;
690 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
691 return nic_data->datapath_caps & BIT_ULL(flag);
692 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
693 return nic_data->datapath_caps2 & BIT_ULL(flag);
694 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
695 return nic_data->datapath_caps3 & BIT_ULL(flag);
701 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
703 /* Maximum link speed for Riverhead is 100G */
704 return 10 * EFX_RECYCLE_RING_SIZE_10G;
707 static int compare_versions(const char *a, const char *b)
709 int a_major, a_minor, a_point, a_patch;
710 int b_major, b_minor, b_point, b_patch;
711 int a_matched, b_matched;
713 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
714 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
716 if (a_matched == 4 && b_matched != 4)
719 if (a_matched != 4 && b_matched == 4)
722 if (a_matched != 4 && b_matched != 4)
725 if (a_major != b_major)
726 return a_major - b_major;
728 if (a_minor != b_minor)
729 return a_minor - b_minor;
731 if (a_point != b_point)
732 return a_point - b_point;
734 return a_patch - b_patch;
737 enum ef100_tlv_state_machine {
744 struct ef100_tlv_state {
745 enum ef100_tlv_state_machine state;
752 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
754 switch (state->state) {
756 state->type = byte & 0x7f;
757 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
759 /* Clear ready to read in a new entry */
761 state->value_offset = 0;
763 case EF100_TLV_TYPE_CONT:
764 state->type |= byte << 7;
765 state->state = EF100_TLV_LENGTH;
767 case EF100_TLV_LENGTH:
769 /* We only handle TLVs that fit in a u64 */
770 if (state->len > sizeof(state->value))
772 /* len may be zero, implying a value of zero */
773 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
775 case EF100_TLV_VALUE:
776 state->value |= ((u64)byte) << (state->value_offset * 8);
777 state->value_offset++;
778 if (state->value_offset >= state->len)
779 state->state = EF100_TLV_TYPE;
781 default: /* state machine error, can't happen */
787 static int ef100_process_design_param(struct efx_nic *efx,
788 const struct ef100_tlv_state *reader)
790 struct ef100_nic_data *nic_data = efx->nic_data;
792 switch (reader->type) {
793 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
795 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
796 /* Driver doesn't support timestamping yet, so we don't care */
798 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
799 /* Driver doesn't support unsolicited-event credits yet, so
803 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
804 /* Driver doesn't manage the NMMU (so we don't care) */
806 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
807 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
808 * protocol checksum validation
811 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
812 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
814 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
815 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
816 if (!reader->value) {
817 netif_err(efx, probe, efx->net_dev,
818 "TSO_MAX_HDR_NUM_SEGS < 1\n");
822 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
823 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
824 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
825 * EFX_MIN_DMAQ_SIZE, so we just need to check that
826 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
827 * This is very unlikely to fail.
829 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
830 EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
831 netif_err(efx, probe, efx->net_dev,
832 "%s size granularity is %llu, can't guarantee safety\n",
833 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
838 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
839 nic_data->tso_max_payload_len = min_t(u64, reader->value,
840 GSO_LEGACY_MAX_SIZE);
841 netif_set_tso_max_size(efx->net_dev,
842 nic_data->tso_max_payload_len);
844 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
845 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
846 netif_set_tso_max_segs(efx->net_dev,
847 nic_data->tso_max_payload_num_segs);
849 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
850 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
852 case ESE_EF100_DP_GZ_COMPAT:
854 netif_err(efx, probe, efx->net_dev,
855 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
860 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
861 /* Driver doesn't use mem2mem transfers */
863 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
864 /* Driver doesn't currently use EVQ_TIMER */
866 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
867 /* Driver doesn't manage the NMMU (so we don't care) */
869 case ESE_EF100_DP_GZ_VI_STRIDES:
870 /* We never try to set the VI stride, and we don't rely on
871 * being able to find VIs past VI 0 until after we've learned
872 * the current stride from MC_CMD_GET_CAPABILITIES.
873 * So the value of this shouldn't matter.
875 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
876 netif_dbg(efx, probe, efx->net_dev,
877 "NIC has other than default VI_STRIDES (mask "
878 "%#llx), early probing might use wrong one\n",
881 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
882 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
883 * care whether it indicates runt or overlength for any given
884 * packet, so we don't care about this parameter.
888 /* Host interface says "Drivers should ignore design parameters
889 * that they do not recognise."
891 netif_dbg(efx, probe, efx->net_dev,
892 "Ignoring unrecognised design parameter %u\n",
898 static int ef100_check_design_params(struct efx_nic *efx)
900 struct ef100_tlv_state reader = {};
901 u32 total_len, offset = 0;
906 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN);
907 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
908 pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len);
909 while (offset < total_len) {
910 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset);
911 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
912 for (i = 0; i < sizeof(data); i++) {
913 rc = ef100_tlv_feed(&reader, data);
914 /* Got a complete value? */
915 if (!rc && reader.state == EF100_TLV_TYPE)
916 rc = ef100_process_design_param(efx, &reader);
923 /* Check we didn't end halfway through a TLV entry, which could either
924 * mean that the TLV stream is truncated or just that it's corrupted
925 * and our state machine is out of sync.
927 if (reader.state != EF100_TLV_TYPE) {
928 if (reader.state == EF100_TLV_TYPE_CONT)
929 netif_err(efx, probe, efx->net_dev,
930 "truncated design parameter (incomplete type %u)\n",
933 netif_err(efx, probe, efx->net_dev,
934 "truncated design parameter %u\n",
942 /* NIC probe and remove
944 static int ef100_probe_main(struct efx_nic *efx)
946 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
947 struct ef100_nic_data *nic_data;
951 if (WARN_ON(bar_size == 0))
954 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
957 efx->nic_data = nic_data;
959 efx->max_vis = EF100_MAX_VIS;
961 /* Populate design-parameter defaults */
962 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
963 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
964 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
965 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
967 /* Read design parameters */
968 rc = ef100_check_design_params(efx);
970 pci_err(efx->pci_dev, "Unsupported design parameters\n");
974 /* we assume later that we can copy from this buffer in dwords */
975 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
977 /* MCDI buffers must be 256 byte aligned. */
978 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
983 /* Get the MC's warm boot count. In case it's rebooting right
984 * now, be prepared to retry.
988 rc = ef100_get_warm_boot_count(efx);
995 nic_data->warm_boot_count = rc;
997 /* In case we're recovering from a crash (kexec), we want to
998 * cancel any outstanding request by the previous user of this
999 * function. We send a special message using the least
1000 * significant bits of the 'high' (doorbell) register.
1002 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1004 /* Post-IO section. */
1006 rc = efx_mcdi_init(efx);
1009 /* Reset (most) configuration for this function */
1010 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1013 /* Enable event logging */
1014 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1018 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1022 rc = efx_mcdi_port_get_number(efx);
1027 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1028 pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version);
1030 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1031 pci_info(efx->pci_dev, "Firmware uses old event descriptors\n");
1036 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1037 pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n");
1047 int ef100_probe_netdev_pf(struct efx_nic *efx)
1049 struct ef100_nic_data *nic_data = efx->nic_data;
1050 struct net_device *net_dev = efx->net_dev;
1053 rc = ef100_get_mac_address(efx, net_dev->perm_addr);
1056 /* Assign MAC address */
1057 eth_hw_addr_set(net_dev, net_dev->perm_addr);
1058 memcpy(nic_data->port_id, net_dev->perm_addr, ETH_ALEN);
1066 int ef100_probe_vf(struct efx_nic *efx)
1068 return ef100_probe_main(efx);
1071 void ef100_remove(struct efx_nic *efx)
1073 struct ef100_nic_data *nic_data = efx->nic_data;
1075 efx_mcdi_detach(efx);
1078 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1080 efx->nic_data = NULL;
1083 /* NIC level access functions
1085 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
1086 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
1087 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
1088 NETIF_F_HW_VLAN_CTAG_TX)
1090 const struct efx_nic_type ef100_pf_nic_type = {
1091 .revision = EFX_REV_EF100,
1093 .probe = ef100_probe_main,
1094 .offload_features = EF100_OFFLOAD_FEATURES,
1096 .mcdi_request = ef100_mcdi_request,
1097 .mcdi_poll_response = ef100_mcdi_poll_response,
1098 .mcdi_read_response = ef100_mcdi_read_response,
1099 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1100 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1101 .irq_enable_master = efx_port_dummy_op_void,
1102 .irq_test_generate = efx_ef100_irq_test_generate,
1103 .irq_disable_non_ev = efx_port_dummy_op_void,
1104 .push_irq_moderation = efx_channel_dummy_op_void,
1105 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1106 .map_reset_reason = ef100_map_reset_reason,
1107 .map_reset_flags = ef100_map_reset_flags,
1108 .reset = ef100_reset,
1110 .check_caps = ef100_check_caps,
1112 .ev_probe = ef100_ev_probe,
1113 .ev_init = ef100_ev_init,
1114 .ev_fini = efx_mcdi_ev_fini,
1115 .ev_remove = efx_mcdi_ev_remove,
1116 .irq_handle_msi = ef100_msi_interrupt,
1117 .ev_process = ef100_ev_process,
1118 .ev_read_ack = ef100_ev_read_ack,
1119 .ev_test_generate = efx_ef100_ev_test_generate,
1120 .tx_probe = ef100_tx_probe,
1121 .tx_init = ef100_tx_init,
1122 .tx_write = ef100_tx_write,
1123 .tx_enqueue = ef100_enqueue_skb,
1124 .rx_probe = efx_mcdi_rx_probe,
1125 .rx_init = efx_mcdi_rx_init,
1126 .rx_remove = efx_mcdi_rx_remove,
1127 .rx_write = ef100_rx_write,
1128 .rx_packet = __ef100_rx_packet,
1129 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1130 .fini_dmaq = efx_fini_dmaq,
1131 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1132 .filter_table_probe = ef100_filter_table_up,
1133 .filter_table_restore = efx_mcdi_filter_table_restore,
1134 .filter_table_remove = ef100_filter_table_down,
1135 .filter_insert = efx_mcdi_filter_insert,
1136 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1137 .filter_get_safe = efx_mcdi_filter_get_safe,
1138 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1139 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1140 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1141 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1142 #ifdef CONFIG_RFS_ACCEL
1143 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1146 .get_phys_port_id = efx_ef100_get_phys_port_id,
1148 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1149 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1150 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1151 .rx_hash_key_size = 40,
1152 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1153 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1154 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
1155 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
1156 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1157 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1159 .reconfigure_mac = ef100_reconfigure_mac,
1160 .reconfigure_port = efx_mcdi_port_reconfigure,
1161 .test_nvram = efx_new_mcdi_nvram_test_all,
1162 .describe_stats = ef100_describe_stats,
1163 .start_stats = efx_mcdi_mac_start_stats,
1164 .update_stats = ef100_update_stats,
1165 .pull_stats = efx_mcdi_mac_pull_stats,
1166 .stop_stats = efx_mcdi_mac_stop_stats,
1167 #ifdef CONFIG_SFC_SRIOV
1168 .sriov_configure = efx_ef100_sriov_configure,
1171 /* Per-type bar/size configuration not used on ef100. Location of
1172 * registers is defined by extended capabilities.
1175 .mem_map_size = NULL,
1179 const struct efx_nic_type ef100_vf_nic_type = {
1180 .revision = EFX_REV_EF100,
1182 .probe = ef100_probe_vf,
1183 .offload_features = EF100_OFFLOAD_FEATURES,
1185 .mcdi_request = ef100_mcdi_request,
1186 .mcdi_poll_response = ef100_mcdi_poll_response,
1187 .mcdi_read_response = ef100_mcdi_read_response,
1188 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1189 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1190 .irq_enable_master = efx_port_dummy_op_void,
1191 .irq_test_generate = efx_ef100_irq_test_generate,
1192 .irq_disable_non_ev = efx_port_dummy_op_void,
1193 .push_irq_moderation = efx_channel_dummy_op_void,
1194 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1195 .map_reset_reason = ef100_map_reset_reason,
1196 .map_reset_flags = ef100_map_reset_flags,
1197 .reset = ef100_reset,
1198 .check_caps = ef100_check_caps,
1199 .ev_probe = ef100_ev_probe,
1200 .ev_init = ef100_ev_init,
1201 .ev_fini = efx_mcdi_ev_fini,
1202 .ev_remove = efx_mcdi_ev_remove,
1203 .irq_handle_msi = ef100_msi_interrupt,
1204 .ev_process = ef100_ev_process,
1205 .ev_read_ack = ef100_ev_read_ack,
1206 .ev_test_generate = efx_ef100_ev_test_generate,
1207 .tx_probe = ef100_tx_probe,
1208 .tx_init = ef100_tx_init,
1209 .tx_write = ef100_tx_write,
1210 .tx_enqueue = ef100_enqueue_skb,
1211 .rx_probe = efx_mcdi_rx_probe,
1212 .rx_init = efx_mcdi_rx_init,
1213 .rx_remove = efx_mcdi_rx_remove,
1214 .rx_write = ef100_rx_write,
1215 .rx_packet = __ef100_rx_packet,
1216 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1217 .fini_dmaq = efx_fini_dmaq,
1218 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1219 .filter_table_probe = ef100_filter_table_up,
1220 .filter_table_restore = efx_mcdi_filter_table_restore,
1221 .filter_table_remove = ef100_filter_table_down,
1222 .filter_insert = efx_mcdi_filter_insert,
1223 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1224 .filter_get_safe = efx_mcdi_filter_get_safe,
1225 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1226 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1227 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1228 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1229 #ifdef CONFIG_RFS_ACCEL
1230 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1233 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1234 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1235 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1236 .rx_hash_key_size = 40,
1237 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1238 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1239 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1240 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1242 .reconfigure_mac = ef100_reconfigure_mac,
1243 .test_nvram = efx_new_mcdi_nvram_test_all,
1244 .describe_stats = ef100_describe_stats,
1245 .start_stats = efx_mcdi_mac_start_stats,
1246 .update_stats = ef100_update_stats,
1247 .pull_stats = efx_mcdi_mac_pull_stats,
1248 .stop_stats = efx_mcdi_mac_stop_stats,
1251 .mem_map_size = NULL,