drivers/net/ethernet/sfc/ef10.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2012-2013 Solarflare Communications Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published
   7  * by the Free Software Foundation, incorporated herein by reference.
   8  */
   9
  10 #include "net_driver.h"
  11 #include "ef10_regs.h"
  12 #include "io.h"
  13 #include "mcdi.h"
  14 #include "mcdi_pcol.h"
  15 #include "nic.h"
  16 #include "workarounds.h"
  17 #include "selftest.h"
  18 #include "ef10_sriov.h"
  19 #include <linux/in.h>
  20 #include <linux/jhash.h>
  21 #include <linux/wait.h>
  22 #include <linux/workqueue.h>
  23
  24 /* Hardware control for EF10 architecture including 'Huntington'. */
  25
  26 #define EFX_EF10_DRVGEN_EV              7
  27 enum {
  28         EFX_EF10_TEST = 1,
  29         EFX_EF10_REFILL,
  30 };
  31
  32 /* The reserved RSS context value */
  33 #define EFX_EF10_RSS_CONTEXT_INVALID    0xffffffff
  34 /* The maximum size of a shared RSS context */
  35 /* TODO: this should really be from the mcdi protocol export */
  36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
  37
  38 /* The filter table(s) are managed by firmware and we have write-only
  39  * access.  When removing filters we must identify them to the
  40  * firmware by a 64-bit handle, but this is too wide for Linux kernel
  41  * interfaces (32-bit for RX NFC, 16-bit for RFS).  Also, we need to
  42  * be able to tell in advance whether a requested insertion will
  43  * replace an existing filter.  Therefore we maintain a software hash
  44  * table, which should be at least as large as the hardware hash
  45  * table.
  46  *
  47  * Huntington has a single 8K filter table shared between all filter
  48  * types and both ports.
  49  */
  50 #define HUNT_FILTER_TBL_ROWS 8192
  51
  52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
  53
  54 #define EFX_EF10_FILTER_DEV_UC_MAX      32
  55 #define EFX_EF10_FILTER_DEV_MC_MAX      256
  56
  57 /* VLAN list entry */
  58 struct efx_ef10_vlan {
  59         struct list_head list;
  60         u16 vid;
  61 };
  62
  63 /* Per-VLAN filters information */
  64 struct efx_ef10_filter_vlan {
  65         struct list_head list;
  66         u16 vid;
  67         u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
  68         u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
  69         u16 ucdef;
  70         u16 bcast;
  71         u16 mcdef;
  72 };
  73
  74 struct efx_ef10_dev_addr {
  75         u8 addr[ETH_ALEN];
  76 };
  77
  78 struct efx_ef10_filter_table {
  79 /* The MCDI match masks supported by this fw & hw, in order of priority */
  80         u32 rx_match_mcdi_flags[
  81                 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
  82         unsigned int rx_match_count;
  83
  84         struct {
  85                 unsigned long spec;     /* pointer to spec plus flag bits */
  86 /* BUSY flag indicates that an update is in progress.  AUTO_OLD is
  87  * used to mark and sweep MAC filters for the device address lists.
  88  */
  89 #define EFX_EF10_FILTER_FLAG_BUSY       1UL
  90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD   2UL
  91 #define EFX_EF10_FILTER_FLAGS           3UL
  92                 u64 handle;             /* firmware handle */
  93         } *entry;
  94         wait_queue_head_t waitq;
  95 /* Shadow of net_device address lists, guarded by mac_lock */
  96         struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
  97         struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
  98         int dev_uc_count;
  99         int dev_mc_count;
 100         bool uc_promisc;
 101         bool mc_promisc;
 102 /* Whether in multicast promiscuous mode when last changed */
 103         bool mc_promisc_last;
 104         bool vlan_filter;
 105         struct list_head vlan_list;
 106 };
 107
 108 /* An arbitrary search limit for the software hash table */
 109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
 110
 111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
 112 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
 113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
 114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
 115                                               struct efx_ef10_filter_vlan *vlan);
 116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
 117
 118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
 119 {
 120         efx_dword_t reg;
 121
 122         efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
 123         return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
 124                 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
 125 }
 126
 127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
 128 {
 129         int bar;
 130
 131         bar = efx->type->mem_bar;
 132         return resource_size(&efx->pci_dev->resource[bar]);
 133 }
 134
 135 static bool efx_ef10_is_vf(struct efx_nic *efx)
 136 {
 137         return efx->type->is_vf;
 138 }
 139
 140 static int efx_ef10_get_pf_index(struct efx_nic *efx)
 141 {
 142         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 143         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 144         size_t outlen;
 145         int rc;
 146
 147         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 148                           sizeof(outbuf), &outlen);
 149         if (rc)
 150                 return rc;
 151         if (outlen < sizeof(outbuf))
 152                 return -EIO;
 153
 154         nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
 155         return 0;
 156 }
 157
 158 #ifdef CONFIG_SFC_SRIOV
 159 static int efx_ef10_get_vf_index(struct efx_nic *efx)
 160 {
 161         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
 162         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 163         size_t outlen;
 164         int rc;
 165
 166         rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
 167                           sizeof(outbuf), &outlen);
 168         if (rc)
 169                 return rc;
 170         if (outlen < sizeof(outbuf))
 171                 return -EIO;
 172
 173         nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
 174         return 0;
 175 }
 176 #endif
 177
 178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
 179 {
 180         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN);
 181         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 182         size_t outlen;
 183         int rc;
 184
 185         BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
 186
 187         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
 188                           outbuf, sizeof(outbuf), &outlen);
 189         if (rc)
 190                 return rc;
 191         if (outlen < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
 192                 netif_err(efx, drv, efx->net_dev,
 193                           "unable to read datapath firmware capabilities\n");
 194                 return -EIO;
 195         }
 196
 197         nic_data->datapath_caps =
 198                 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
 199
 200         if (outlen >= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
 201                 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
 202                                 GET_CAPABILITIES_V2_OUT_FLAGS2);
 203         else
 204                 nic_data->datapath_caps2 = 0;
 205
 206         /* record the DPCPU firmware IDs to determine VEB vswitching support.
 207          */
 208         nic_data->rx_dpcpu_fw_id =
 209                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
 210         nic_data->tx_dpcpu_fw_id =
 211                 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
 212
 213         if (!(nic_data->datapath_caps &
 214               (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
 215                 netif_err(efx, probe, efx->net_dev,
 216                           "current firmware does not support an RX prefix\n");
 217                 return -ENODEV;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
 224 {
 225         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
 226         int rc;
 227
 228         rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
 229                           outbuf, sizeof(outbuf), NULL);
 230         if (rc)
 231                 return rc;
 232         rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
 233         return rc > 0 ? rc : -ERANGE;
 234 }
 235
 236 static int efx_ef10_get_timer_workarounds(struct efx_nic *efx)
 237 {
 238         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 239         unsigned int implemented;
 240         unsigned int enabled;
 241         int rc;
 242
 243         nic_data->workaround_35388 = false;
 244         nic_data->workaround_61265 = false;
 245
 246         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
 247
 248         if (rc == -ENOSYS) {
 249                 /* Firmware without GET_WORKAROUNDS - not a problem. */
 250                 rc = 0;
 251         } else if (rc == 0) {
 252                 /* Bug61265 workaround is always enabled if implemented. */
 253                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG61265)
 254                         nic_data->workaround_61265 = true;
 255
 256                 if (enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 257                         nic_data->workaround_35388 = true;
 258                 } else if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG35388) {
 259                         /* Workaround is implemented but not enabled.
 260                          * Try to enable it.
 261                          */
 262                         rc = efx_mcdi_set_workaround(efx,
 263                                                      MC_CMD_WORKAROUND_BUG35388,
 264                                                      true, NULL);
 265                         if (rc == 0)
 266                                 nic_data->workaround_35388 = true;
 267                         /* If we failed to set the workaround just carry on. */
 268                         rc = 0;
 269                 }
 270         }
 271
 272         netif_dbg(efx, probe, efx->net_dev,
 273                   "workaround for bug 35388 is %sabled\n",
 274                   nic_data->workaround_35388 ? "en" : "dis");
 275         netif_dbg(efx, probe, efx->net_dev,
 276                   "workaround for bug 61265 is %sabled\n",
 277                   nic_data->workaround_61265 ? "en" : "dis");
 278
 279         return rc;
 280 }
 281
 282 static void efx_ef10_process_timer_config(struct efx_nic *efx,
 283                                           const efx_dword_t *data)
 284 {
 285         unsigned int max_count;
 286
 287         if (EFX_EF10_WORKAROUND_61265(efx)) {
 288                 efx->timer_quantum_ns = MCDI_DWORD(data,
 289                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS);
 290                 efx->timer_max_ns = MCDI_DWORD(data,
 291                         GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS);
 292         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
 293                 efx->timer_quantum_ns = MCDI_DWORD(data,
 294                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT);
 295                 max_count = MCDI_DWORD(data,
 296                         GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT);
 297                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 298         } else {
 299                 efx->timer_quantum_ns = MCDI_DWORD(data,
 300                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT);
 301                 max_count = MCDI_DWORD(data,
 302                         GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT);
 303                 efx->timer_max_ns = max_count * efx->timer_quantum_ns;
 304         }
 305
 306         netif_dbg(efx, probe, efx->net_dev,
 307                   "got timer properties from MC: quantum %u ns; max %u ns\n",
 308                   efx->timer_quantum_ns, efx->timer_max_ns);
 309 }
 310
 311 static int efx_ef10_get_timer_config(struct efx_nic *efx)
 312 {
 313         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN);
 314         int rc;
 315
 316         rc = efx_ef10_get_timer_workarounds(efx);
 317         if (rc)
 318                 return rc;
 319
 320         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES, NULL, 0,
 321                                 outbuf, sizeof(outbuf), NULL);
 322
 323         if (rc == 0) {
 324                 efx_ef10_process_timer_config(efx, outbuf);
 325         } else if (rc == -ENOSYS || rc == -EPERM) {
 326                 /* Not available - fall back to Huntington defaults. */
 327                 unsigned int quantum;
 328
 329                 rc = efx_ef10_get_sysclk_freq(efx);
 330                 if (rc < 0)
 331                         return rc;
 332
 333                 quantum = 1536000 / rc; /* 1536 cycles */
 334                 efx->timer_quantum_ns = quantum;
 335                 efx->timer_max_ns = efx->type->timer_period_max * quantum;
 336                 rc = 0;
 337         } else {
 338                 efx_mcdi_display_error(efx, MC_CMD_GET_EVQ_TMR_PROPERTIES,
 339                                        MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN,
 340                                        NULL, 0, rc);
 341         }
 342
 343         return rc;
 344 }
 345
 346 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
 347 {
 348         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
 349         size_t outlen;
 350         int rc;
 351
 352         BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
 353
 354         rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
 355                           outbuf, sizeof(outbuf), &outlen);
 356         if (rc)
 357                 return rc;
 358         if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
 359                 return -EIO;
 360
 361         ether_addr_copy(mac_address,
 362                         MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
 363         return 0;
 364 }
 365
 366 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
 367 {
 368         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
 369         MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
 370         size_t outlen;
 371         int num_addrs, rc;
 372
 373         MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
 374                        EVB_PORT_ID_ASSIGNED);
 375         rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
 376                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
 377
 378         if (rc)
 379                 return rc;
 380         if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
 381                 return -EIO;
 382
 383         num_addrs = MCDI_DWORD(outbuf,
 384                                VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
 385
 386         WARN_ON(num_addrs != 1);
 387
 388         ether_addr_copy(mac_address,
 389                         MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
 390
 391         return 0;
 392 }
 393
 394 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
 395                                                struct device_attribute *attr,
 396                                                char *buf)
 397 {
 398         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 399
 400         return sprintf(buf, "%d\n",
 401                        ((efx->mcdi->fn_flags) &
 402                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
 403                        ? 1 : 0);
 404 }
 405
 406 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
 407                                           struct device_attribute *attr,
 408                                           char *buf)
 409 {
 410         struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
 411
 412         return sprintf(buf, "%d\n",
 413                        ((efx->mcdi->fn_flags) &
 414                         (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
 415                        ? 1 : 0);
 416 }
 417
 418 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
 419 {
 420         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 421         struct efx_ef10_vlan *vlan;
 422
 423         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 424
 425         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
 426                 if (vlan->vid == vid)
 427                         return vlan;
 428         }
 429
 430         return NULL;
 431 }
 432
 433 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
 434 {
 435         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 436         struct efx_ef10_vlan *vlan;
 437         int rc;
 438
 439         mutex_lock(&nic_data->vlan_lock);
 440
 441         vlan = efx_ef10_find_vlan(efx, vid);
 442         if (vlan) {
 443                 /* We add VID 0 on init. 8021q adds it on module init
 444                  * for all interfaces with VLAN filtring feature.
 445                  */
 446                 if (vid == 0)
 447                         goto done_unlock;
 448                 netif_warn(efx, drv, efx->net_dev,
 449                            "VLAN %u already added\n", vid);
 450                 rc = -EALREADY;
 451                 goto fail_exist;
 452         }
 453
 454         rc = -ENOMEM;
 455         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
 456         if (!vlan)
 457                 goto fail_alloc;
 458
 459         vlan->vid = vid;
 460
 461         list_add_tail(&vlan->list, &nic_data->vlan_list);
 462
 463         if (efx->filter_state) {
 464                 mutex_lock(&efx->mac_lock);
 465                 down_write(&efx->filter_sem);
 466                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
 467                 up_write(&efx->filter_sem);
 468                 mutex_unlock(&efx->mac_lock);
 469                 if (rc)
 470                         goto fail_filter_add_vlan;
 471         }
 472
 473 done_unlock:
 474         mutex_unlock(&nic_data->vlan_lock);
 475         return 0;
 476
 477 fail_filter_add_vlan:
 478         list_del(&vlan->list);
 479         kfree(vlan);
 480 fail_alloc:
 481 fail_exist:
 482         mutex_unlock(&nic_data->vlan_lock);
 483         return rc;
 484 }
 485
 486 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
 487                                        struct efx_ef10_vlan *vlan)
 488 {
 489         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 490
 491         WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
 492
 493         if (efx->filter_state) {
 494                 down_write(&efx->filter_sem);
 495                 efx_ef10_filter_del_vlan(efx, vlan->vid);
 496                 up_write(&efx->filter_sem);
 497         }
 498
 499         list_del(&vlan->list);
 500         kfree(vlan);
 501 }
 502
 503 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
 504 {
 505         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 506         struct efx_ef10_vlan *vlan;
 507         int rc = 0;
 508
 509         /* 8021q removes VID 0 on module unload for all interfaces
 510          * with VLAN filtering feature. We need to keep it to receive
 511          * untagged traffic.
 512          */
 513         if (vid == 0)
 514                 return 0;
 515
 516         mutex_lock(&nic_data->vlan_lock);
 517
 518         vlan = efx_ef10_find_vlan(efx, vid);
 519         if (!vlan) {
 520                 netif_err(efx, drv, efx->net_dev,
 521                           "VLAN %u to be deleted not found\n", vid);
 522                 rc = -ENOENT;
 523         } else {
 524                 efx_ef10_del_vlan_internal(efx, vlan);
 525         }
 526
 527         mutex_unlock(&nic_data->vlan_lock);
 528
 529         return rc;
 530 }
 531
 532 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
 533 {
 534         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 535         struct efx_ef10_vlan *vlan, *next_vlan;
 536
 537         mutex_lock(&nic_data->vlan_lock);
 538         list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
 539                 efx_ef10_del_vlan_internal(efx, vlan);
 540         mutex_unlock(&nic_data->vlan_lock);
 541 }
 542
 543 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
 544                    NULL);
 545 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
 546
 547 static int efx_ef10_probe(struct efx_nic *efx)
 548 {
 549         struct efx_ef10_nic_data *nic_data;
 550         struct net_device *net_dev = efx->net_dev;
 551         int i, rc;
 552
 553         /* We can have one VI for each 8K region.  However, until we
 554          * use TX option descriptors we need two TX queues per channel.
 555          */
 556         efx->max_channels = min_t(unsigned int,
 557                                   EFX_MAX_CHANNELS,
 558                                   efx_ef10_mem_map_size(efx) /
 559                                   (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
 560         efx->max_tx_channels = efx->max_channels;
 561         if (WARN_ON(efx->max_channels == 0))
 562                 return -EIO;
 563
 564         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
 565         if (!nic_data)
 566                 return -ENOMEM;
 567         efx->nic_data = nic_data;
 568
 569         /* we assume later that we can copy from this buffer in dwords */
 570         BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
 571
 572         rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
 573                                   8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
 574         if (rc)
 575                 goto fail1;
 576
 577         /* Get the MC's warm boot count.  In case it's rebooting right
 578          * now, be prepared to retry.
 579          */
 580         i = 0;
 581         for (;;) {
 582                 rc = efx_ef10_get_warm_boot_count(efx);
 583                 if (rc >= 0)
 584                         break;
 585                 if (++i == 5)
 586                         goto fail2;
 587                 ssleep(1);
 588         }
 589         nic_data->warm_boot_count = rc;
 590
 591         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
 592
 593         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
 594
 595         /* In case we're recovering from a crash (kexec), we want to
 596          * cancel any outstanding request by the previous user of this
 597          * function.  We send a special message using the least
 598          * significant bits of the 'high' (doorbell) register.
 599          */
 600         _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
 601
 602         rc = efx_mcdi_init(efx);
 603         if (rc)
 604                 goto fail2;
 605
 606         /* Reset (most) configuration for this function */
 607         rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
 608         if (rc)
 609                 goto fail3;
 610
 611         /* Enable event logging */
 612         rc = efx_mcdi_log_ctrl(efx, true, false, 0);
 613         if (rc)
 614                 goto fail3;
 615
 616         rc = device_create_file(&efx->pci_dev->dev,
 617                                 &dev_attr_link_control_flag);
 618         if (rc)
 619                 goto fail3;
 620
 621         rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 622         if (rc)
 623                 goto fail4;
 624
 625         rc = efx_ef10_get_pf_index(efx);
 626         if (rc)
 627                 goto fail5;
 628
 629         rc = efx_ef10_init_datapath_caps(efx);
 630         if (rc < 0)
 631                 goto fail5;
 632
 633         efx->rx_packet_len_offset =
 634                 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
 635
 636         rc = efx_mcdi_port_get_number(efx);
 637         if (rc < 0)
 638                 goto fail5;
 639         efx->port_num = rc;
 640         net_dev->dev_port = rc;
 641
 642         rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
 643         if (rc)
 644                 goto fail5;
 645
 646         rc = efx_ef10_get_timer_config(efx);
 647         if (rc < 0)
 648                 goto fail5;
 649
 650         rc = efx_mcdi_mon_probe(efx);
 651         if (rc && rc != -EPERM)
 652                 goto fail5;
 653
 654         efx_ptp_probe(efx, NULL);
 655
 656 #ifdef CONFIG_SFC_SRIOV
 657         if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
 658                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
 659                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
 660
 661                 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
 662         } else
 663 #endif
 664                 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
 665
 666         INIT_LIST_HEAD(&nic_data->vlan_list);
 667         mutex_init(&nic_data->vlan_lock);
 668
 669         /* Add unspecified VID to support VLAN filtering being disabled */
 670         rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
 671         if (rc)
 672                 goto fail_add_vid_unspec;
 673
 674         /* If VLAN filtering is enabled, we need VID 0 to get untagged
 675          * traffic.  It is added automatically if 8021q module is loaded,
 676          * but we can't rely on it since module may be not loaded.
 677          */
 678         rc = efx_ef10_add_vlan(efx, 0);
 679         if (rc)
 680                 goto fail_add_vid_0;
 681
 682         return 0;
 683
 684 fail_add_vid_0:
 685         efx_ef10_cleanup_vlans(efx);
 686 fail_add_vid_unspec:
 687         mutex_destroy(&nic_data->vlan_lock);
 688         efx_ptp_remove(efx);
 689         efx_mcdi_mon_remove(efx);
 690 fail5:
 691         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 692 fail4:
 693         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 694 fail3:
 695         efx_mcdi_fini(efx);
 696 fail2:
 697         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 698 fail1:
 699         kfree(nic_data);
 700         efx->nic_data = NULL;
 701         return rc;
 702 }
 703
 704 static int efx_ef10_free_vis(struct efx_nic *efx)
 705 {
 706         MCDI_DECLARE_BUF_ERR(outbuf);
 707         size_t outlen;
 708         int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
 709                                     outbuf, sizeof(outbuf), &outlen);
 710
 711         /* -EALREADY means nothing to free, so ignore */
 712         if (rc == -EALREADY)
 713                 rc = 0;
 714         if (rc)
 715                 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
 716                                        rc);
 717         return rc;
 718 }
 719
 720 #ifdef EFX_USE_PIO
 721
 722 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 723 {
 724         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 725         MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
 726         unsigned int i;
 727         int rc;
 728
 729         BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
 730
 731         for (i = 0; i < nic_data->n_piobufs; i++) {
 732                 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
 733                                nic_data->piobuf_handle[i]);
 734                 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
 735                                   NULL, 0, NULL);
 736                 WARN_ON(rc);
 737         }
 738
 739         nic_data->n_piobufs = 0;
 740 }
 741
 742 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 743 {
 744         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 745         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
 746         unsigned int i;
 747         size_t outlen;
 748         int rc = 0;
 749
 750         BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
 751
 752         for (i = 0; i < n; i++) {
 753                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
 754                                         outbuf, sizeof(outbuf), &outlen);
 755                 if (rc) {
 756                         /* Don't display the MC error if we didn't have space
 757                          * for a VF.
 758                          */
 759                         if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
 760                                 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
 761                                                        0, outbuf, outlen, rc);
 762                         break;
 763                 }
 764                 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
 765                         rc = -EIO;
 766                         break;
 767                 }
 768                 nic_data->piobuf_handle[i] =
 769                         MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
 770                 netif_dbg(efx, probe, efx->net_dev,
 771                           "allocated PIO buffer %u handle %x\n", i,
 772                           nic_data->piobuf_handle[i]);
 773         }
 774
 775         nic_data->n_piobufs = i;
 776         if (rc)
 777                 efx_ef10_free_piobufs(efx);
 778         return rc;
 779 }
 780
 781 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 782 {
 783         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 784         _MCDI_DECLARE_BUF(inbuf,
 785                           max(MC_CMD_LINK_PIOBUF_IN_LEN,
 786                               MC_CMD_UNLINK_PIOBUF_IN_LEN));
 787         struct efx_channel *channel;
 788         struct efx_tx_queue *tx_queue;
 789         unsigned int offset, index;
 790         int rc;
 791
 792         BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
 793         BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
 794
 795         memset(inbuf, 0, sizeof(inbuf));
 796
 797         /* Link a buffer to each VI in the write-combining mapping */
 798         for (index = 0; index < nic_data->n_piobufs; ++index) {
 799                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
 800                                nic_data->piobuf_handle[index]);
 801                 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
 802                                nic_data->pio_write_vi_base + index);
 803                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 804                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 805                                   NULL, 0, NULL);
 806                 if (rc) {
 807                         netif_err(efx, drv, efx->net_dev,
 808                                   "failed to link VI %u to PIO buffer %u (%d)\n",
 809                                   nic_data->pio_write_vi_base + index, index,
 810                                   rc);
 811                         goto fail;
 812                 }
 813                 netif_dbg(efx, probe, efx->net_dev,
 814                           "linked VI %u to PIO buffer %u\n",
 815                           nic_data->pio_write_vi_base + index, index);
 816         }
 817
 818         /* Link a buffer to each TX queue */
 819         efx_for_each_channel(channel, efx) {
 820                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 821                         /* We assign the PIO buffers to queues in
 822                          * reverse order to allow for the following
 823                          * special case.
 824                          */
 825                         offset = ((efx->tx_channel_offset + efx->n_tx_channels -
 826                                    tx_queue->channel->channel - 1) *
 827                                   efx_piobuf_size);
 828                         index = offset / ER_DZ_TX_PIOBUF_SIZE;
 829                         offset = offset % ER_DZ_TX_PIOBUF_SIZE;
 830
 831                         /* When the host page size is 4K, the first
 832                          * host page in the WC mapping may be within
 833                          * the same VI page as the last TX queue.  We
 834                          * can only link one buffer to each VI.
 835                          */
 836                         if (tx_queue->queue == nic_data->pio_write_vi_base) {
 837                                 BUG_ON(index != 0);
 838                                 rc = 0;
 839                         } else {
 840                                 MCDI_SET_DWORD(inbuf,
 841                                                LINK_PIOBUF_IN_PIOBUF_HANDLE,
 842                                                nic_data->piobuf_handle[index]);
 843                                 MCDI_SET_DWORD(inbuf,
 844                                                LINK_PIOBUF_IN_TXQ_INSTANCE,
 845                                                tx_queue->queue);
 846                                 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
 847                                                   inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
 848                                                   NULL, 0, NULL);
 849                         }
 850
 851                         if (rc) {
 852                                 /* This is non-fatal; the TX path just
 853                                  * won't use PIO for this queue
 854                                  */
 855                                 netif_err(efx, drv, efx->net_dev,
 856                                           "failed to link VI %u to PIO buffer %u (%d)\n",
 857                                           tx_queue->queue, index, rc);
 858                                 tx_queue->piobuf = NULL;
 859                         } else {
 860                                 tx_queue->piobuf =
 861                                         nic_data->pio_write_base +
 862                                         index * EFX_VI_PAGE_SIZE + offset;
 863                                 tx_queue->piobuf_offset = offset;
 864                                 netif_dbg(efx, probe, efx->net_dev,
 865                                           "linked VI %u to PIO buffer %u offset %x addr %p\n",
 866                                           tx_queue->queue, index,
 867                                           tx_queue->piobuf_offset,
 868                                           tx_queue->piobuf);
 869                         }
 870                 }
 871         }
 872
 873         return 0;
 874
 875 fail:
 876         while (index--) {
 877                 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
 878                                nic_data->pio_write_vi_base + index);
 879                 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
 880                              inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
 881                              NULL, 0, NULL);
 882         }
 883         return rc;
 884 }
 885
 886 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 887 {
 888         struct efx_channel *channel;
 889         struct efx_tx_queue *tx_queue;
 890
 891         /* All our existing PIO buffers went away */
 892         efx_for_each_channel(channel, efx)
 893                 efx_for_each_channel_tx_queue(tx_queue, channel)
 894                         tx_queue->piobuf = NULL;
 895 }
 896
 897 #else /* !EFX_USE_PIO */
 898
 899 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
 900 {
 901         return n == 0 ? 0 : -ENOBUFS;
 902 }
 903
 904 static int efx_ef10_link_piobufs(struct efx_nic *efx)
 905 {
 906         return 0;
 907 }
 908
 909 static void efx_ef10_free_piobufs(struct efx_nic *efx)
 910 {
 911 }
 912
 913 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
 914 {
 915 }
 916
 917 #endif /* EFX_USE_PIO */
 918
 919 static void efx_ef10_remove(struct efx_nic *efx)
 920 {
 921         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 922         int rc;
 923
 924 #ifdef CONFIG_SFC_SRIOV
 925         struct efx_ef10_nic_data *nic_data_pf;
 926         struct pci_dev *pci_dev_pf;
 927         struct efx_nic *efx_pf;
 928         struct ef10_vf *vf;
 929
 930         if (efx->pci_dev->is_virtfn) {
 931                 pci_dev_pf = efx->pci_dev->physfn;
 932                 if (pci_dev_pf) {
 933                         efx_pf = pci_get_drvdata(pci_dev_pf);
 934                         nic_data_pf = efx_pf->nic_data;
 935                         vf = nic_data_pf->vf + nic_data->vf_index;
 936                         vf->efx = NULL;
 937                 } else
 938                         netif_info(efx, drv, efx->net_dev,
 939                                    "Could not get the PF id from VF\n");
 940         }
 941 #endif
 942
 943         efx_ef10_cleanup_vlans(efx);
 944         mutex_destroy(&nic_data->vlan_lock);
 945
 946         efx_ptp_remove(efx);
 947
 948         efx_mcdi_mon_remove(efx);
 949
 950         efx_ef10_rx_free_indir_table(efx);
 951
 952         if (nic_data->wc_membase)
 953                 iounmap(nic_data->wc_membase);
 954
 955         rc = efx_ef10_free_vis(efx);
 956         WARN_ON(rc != 0);
 957
 958         if (!nic_data->must_restore_piobufs)
 959                 efx_ef10_free_piobufs(efx);
 960
 961         device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
 962         device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
 963
 964         efx_mcdi_fini(efx);
 965         efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
 966         kfree(nic_data);
 967 }
 968
 969 static int efx_ef10_probe_pf(struct efx_nic *efx)
 970 {
 971         return efx_ef10_probe(efx);
 972 }
 973
 974 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
 975                             u32 *port_flags, u32 *vadaptor_flags,
 976                             unsigned int *vlan_tags)
 977 {
 978         struct efx_ef10_nic_data *nic_data = efx->nic_data;
 979         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
 980         MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
 981         size_t outlen;
 982         int rc;
 983
 984         if (nic_data->datapath_caps &
 985             (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
 986                 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
 987                                port_id);
 988
 989                 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
 990                                   outbuf, sizeof(outbuf), &outlen);
 991                 if (rc)
 992                         return rc;
 993
 994                 if (outlen < sizeof(outbuf)) {
 995                         rc = -EIO;
 996                         return rc;
 997                 }
 998         }
 999
1000         if (port_flags)
1001                 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
1002         if (vadaptor_flags)
1003                 *vadaptor_flags =
1004                         MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
1005         if (vlan_tags)
1006                 *vlan_tags =
1007                         MCDI_DWORD(outbuf,
1008                                    VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
1009
1010         return 0;
1011 }
1012
1013 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
1014 {
1015         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
1016
1017         MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
1018         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
1019                             NULL, 0, NULL);
1020 }
1021
1022 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
1023 {
1024         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
1025
1026         MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
1027         return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
1028                             NULL, 0, NULL);
1029 }
1030
1031 int efx_ef10_vport_add_mac(struct efx_nic *efx,
1032                            unsigned int port_id, u8 *mac)
1033 {
1034         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
1035
1036         MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
1037         ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
1038
1039         return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
1040                             sizeof(inbuf), NULL, 0, NULL);
1041 }
1042
1043 int efx_ef10_vport_del_mac(struct efx_nic *efx,
1044                            unsigned int port_id, u8 *mac)
1045 {
1046         MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
1047
1048         MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
1049         ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
1050
1051         return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
1052                             sizeof(inbuf), NULL, 0, NULL);
1053 }
1054
1055 #ifdef CONFIG_SFC_SRIOV
1056 static int efx_ef10_probe_vf(struct efx_nic *efx)
1057 {
1058         int rc;
1059         struct pci_dev *pci_dev_pf;
1060
1061         /* If the parent PF has no VF data structure, it doesn't know about this
1062          * VF so fail probe.  The VF needs to be re-created.  This can happen
1063          * if the PF driver is unloaded while the VF is assigned to a guest.
1064          */
1065         pci_dev_pf = efx->pci_dev->physfn;
1066         if (pci_dev_pf) {
1067                 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
1068                 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
1069
1070                 if (!nic_data_pf->vf) {
1071                         netif_info(efx, drv, efx->net_dev,
1072                                    "The VF cannot link to its parent PF; "
1073                                    "please destroy and re-create the VF\n");
1074                         return -EBUSY;
1075                 }
1076         }
1077
1078         rc = efx_ef10_probe(efx);
1079         if (rc)
1080                 return rc;
1081
1082         rc = efx_ef10_get_vf_index(efx);
1083         if (rc)
1084                 goto fail;
1085
1086         if (efx->pci_dev->is_virtfn) {
1087                 if (efx->pci_dev->physfn) {
1088                         struct efx_nic *efx_pf =
1089                                 pci_get_drvdata(efx->pci_dev->physfn);
1090                         struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
1091                         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1092
1093                         nic_data_p->vf[nic_data->vf_index].efx = efx;
1094                         nic_data_p->vf[nic_data->vf_index].pci_dev =
1095                                 efx->pci_dev;
1096                 } else
1097                         netif_info(efx, drv, efx->net_dev,
1098                                    "Could not get the PF id from VF\n");
1099         }
1100
1101         return 0;
1102
1103 fail:
1104         efx_ef10_remove(efx);
1105         return rc;
1106 }
1107 #else
1108 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1109 {
1110         return 0;
1111 }
1112 #endif
1113
1114 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1115                               unsigned int min_vis, unsigned int max_vis)
1116 {
1117         MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1118         MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1119         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1120         size_t outlen;
1121         int rc;
1122
1123         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1124         MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1125         rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1126                           outbuf, sizeof(outbuf), &outlen);
1127         if (rc != 0)
1128                 return rc;
1129
1130         if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1131                 return -EIO;
1132
1133         netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1134                   MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1135
1136         nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1137         nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1138         return 0;
1139 }
1140
1141 /* Note that the failure path of this function does not free
1142  * resources, as this will be done by efx_ef10_remove().
1143  */
1144 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1145 {
1146         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1147         unsigned int uc_mem_map_size, wc_mem_map_size;
1148         unsigned int min_vis = max(EFX_TXQ_TYPES,
1149                                    efx_separate_tx_channels ? 2 : 1);
1150         unsigned int channel_vis, pio_write_vi_base, max_vis;
1151         void __iomem *membase;
1152         int rc;
1153
1154         channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1155
1156 #ifdef EFX_USE_PIO
1157         /* Try to allocate PIO buffers if wanted and if the full
1158          * number of PIO buffers would be sufficient to allocate one
1159          * copy-buffer per TX channel.  Failure is non-fatal, as there
1160          * are only a small number of PIO buffers shared between all
1161          * functions of the controller.
1162          */
1163         if (efx_piobuf_size != 0 &&
1164             ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1165             efx->n_tx_channels) {
1166                 unsigned int n_piobufs =
1167                         DIV_ROUND_UP(efx->n_tx_channels,
1168                                      ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1169
1170                 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1171                 if (rc)
1172                         netif_err(efx, probe, efx->net_dev,
1173                                   "failed to allocate PIO buffers (%d)\n", rc);
1174                 else
1175                         netif_dbg(efx, probe, efx->net_dev,
1176                                   "allocated %u PIO buffers\n", n_piobufs);
1177         }
1178 #else
1179         nic_data->n_piobufs = 0;
1180 #endif
1181
1182         /* PIO buffers should be mapped with write-combining enabled,
1183          * and we want to make single UC and WC mappings rather than
1184          * several of each (in fact that's the only option if host
1185          * page size is >4K).  So we may allocate some extra VIs just
1186          * for writing PIO buffers through.
1187          *
1188          * The UC mapping contains (channel_vis - 1) complete VIs and the
1189          * first half of the next VI.  Then the WC mapping begins with
1190          * the second half of this last VI.
1191          */
1192         uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1193                                      ER_DZ_TX_PIOBUF);
1194         if (nic_data->n_piobufs) {
1195                 /* pio_write_vi_base rounds down to give the number of complete
1196                  * VIs inside the UC mapping.
1197                  */
1198                 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1199                 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1200                                                nic_data->n_piobufs) *
1201                                               EFX_VI_PAGE_SIZE) -
1202                                    uc_mem_map_size);
1203                 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1204         } else {
1205                 pio_write_vi_base = 0;
1206                 wc_mem_map_size = 0;
1207                 max_vis = channel_vis;
1208         }
1209
1210         /* In case the last attached driver failed to free VIs, do it now */
1211         rc = efx_ef10_free_vis(efx);
1212         if (rc != 0)
1213                 return rc;
1214
1215         rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1216         if (rc != 0)
1217                 return rc;
1218
1219         if (nic_data->n_allocated_vis < channel_vis) {
1220                 netif_info(efx, drv, efx->net_dev,
1221                            "Could not allocate enough VIs to satisfy RSS"
1222                            " requirements. Performance may not be optimal.\n");
1223                 /* We didn't get the VIs to populate our channels.
1224                  * We could keep what we got but then we'd have more
1225                  * interrupts than we need.
1226                  * Instead calculate new max_channels and restart
1227                  */
1228                 efx->max_channels = nic_data->n_allocated_vis;
1229                 efx->max_tx_channels =
1230                         nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1231
1232                 efx_ef10_free_vis(efx);
1233                 return -EAGAIN;
1234         }
1235
1236         /* If we didn't get enough VIs to map all the PIO buffers, free the
1237          * PIO buffers
1238          */
1239         if (nic_data->n_piobufs &&
1240             nic_data->n_allocated_vis <
1241             pio_write_vi_base + nic_data->n_piobufs) {
1242                 netif_dbg(efx, probe, efx->net_dev,
1243                           "%u VIs are not sufficient to map %u PIO buffers\n",
1244                           nic_data->n_allocated_vis, nic_data->n_piobufs);
1245                 efx_ef10_free_piobufs(efx);
1246         }
1247
1248         /* Shrink the original UC mapping of the memory BAR */
1249         membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1250         if (!membase) {
1251                 netif_err(efx, probe, efx->net_dev,
1252                           "could not shrink memory BAR to %x\n",
1253                           uc_mem_map_size);
1254                 return -ENOMEM;
1255         }
1256         iounmap(efx->membase);
1257         efx->membase = membase;
1258
1259         /* Set up the WC mapping if needed */
1260         if (wc_mem_map_size) {
1261                 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1262                                                   uc_mem_map_size,
1263                                                   wc_mem_map_size);
1264                 if (!nic_data->wc_membase) {
1265                         netif_err(efx, probe, efx->net_dev,
1266                                   "could not allocate WC mapping of size %x\n",
1267                                   wc_mem_map_size);
1268                         return -ENOMEM;
1269                 }
1270                 nic_data->pio_write_vi_base = pio_write_vi_base;
1271                 nic_data->pio_write_base =
1272                         nic_data->wc_membase +
1273                         (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1274                          uc_mem_map_size);
1275
1276                 rc = efx_ef10_link_piobufs(efx);
1277                 if (rc)
1278                         efx_ef10_free_piobufs(efx);
1279         }
1280
1281         netif_dbg(efx, probe, efx->net_dev,
1282                   "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1283                   &efx->membase_phys, efx->membase, uc_mem_map_size,
1284                   nic_data->wc_membase, wc_mem_map_size);
1285
1286         return 0;
1287 }
1288
1289 static int efx_ef10_init_nic(struct efx_nic *efx)
1290 {
1291         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1292         int rc;
1293
1294         if (nic_data->must_check_datapath_caps) {
1295                 rc = efx_ef10_init_datapath_caps(efx);
1296                 if (rc)
1297                         return rc;
1298                 nic_data->must_check_datapath_caps = false;
1299         }
1300
1301         if (nic_data->must_realloc_vis) {
1302                 /* We cannot let the number of VIs change now */
1303                 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1304                                         nic_data->n_allocated_vis);
1305                 if (rc)
1306                         return rc;
1307                 nic_data->must_realloc_vis = false;
1308         }
1309
1310         if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1311                 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1312                 if (rc == 0) {
1313                         rc = efx_ef10_link_piobufs(efx);
1314                         if (rc)
1315                                 efx_ef10_free_piobufs(efx);
1316                 }
1317
1318                 /* Log an error on failure, but this is non-fatal */
1319                 if (rc)
1320                         netif_err(efx, drv, efx->net_dev,
1321                                   "failed to restore PIO buffers (%d)\n", rc);
1322                 nic_data->must_restore_piobufs = false;
1323         }
1324
1325         /* don't fail init if RSS setup doesn't work */
1326         efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1327
1328         return 0;
1329 }
1330
1331 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1332 {
1333         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1334 #ifdef CONFIG_SFC_SRIOV
1335         unsigned int i;
1336 #endif
1337
1338         /* All our allocations have been reset */
1339         nic_data->must_realloc_vis = true;
1340         nic_data->must_restore_filters = true;
1341         nic_data->must_restore_piobufs = true;
1342         efx_ef10_forget_old_piobufs(efx);
1343         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1344
1345         /* Driver-created vswitches and vports must be re-created */
1346         nic_data->must_probe_vswitching = true;
1347         nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1348 #ifdef CONFIG_SFC_SRIOV
1349         if (nic_data->vf)
1350                 for (i = 0; i < efx->vf_count; i++)
1351                         nic_data->vf[i].vport_id = 0;
1352 #endif
1353 }
1354
1355 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1356 {
1357         if (reason == RESET_TYPE_MC_FAILURE)
1358                 return RESET_TYPE_DATAPATH;
1359
1360         return efx_mcdi_map_reset_reason(reason);
1361 }
1362
1363 static int efx_ef10_map_reset_flags(u32 *flags)
1364 {
1365         enum {
1366                 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1367                                    ETH_RESET_SHARED_SHIFT),
1368                 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1369                                   ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1370                                   ETH_RESET_PHY | ETH_RESET_MGMT) <<
1371                                  ETH_RESET_SHARED_SHIFT)
1372         };
1373
1374         /* We assume for now that our PCI function is permitted to
1375          * reset everything.
1376          */
1377
1378         if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1379                 *flags &= ~EF10_RESET_MC;
1380                 return RESET_TYPE_WORLD;
1381         }
1382
1383         if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1384                 *flags &= ~EF10_RESET_PORT;
1385                 return RESET_TYPE_ALL;
1386         }
1387
1388         /* no invisible reset implemented */
1389
1390         return -EINVAL;
1391 }
1392
1393 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1394 {
1395         int rc = efx_mcdi_reset(efx, reset_type);
1396
1397         /* Unprivileged functions return -EPERM, but need to return success
1398          * here so that the datapath is brought back up.
1399          */
1400         if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1401                 rc = 0;
1402
1403         /* If it was a port reset, trigger reallocation of MC resources.
1404          * Note that on an MC reset nothing needs to be done now because we'll
1405          * detect the MC reset later and handle it then.
1406          * For an FLR, we never get an MC reset event, but the MC has reset all
1407          * resources assigned to us, so we have to trigger reallocation now.
1408          */
1409         if ((reset_type == RESET_TYPE_ALL ||
1410              reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1411                 efx_ef10_reset_mc_allocations(efx);
1412         return rc;
1413 }
1414
1415 #define EF10_DMA_STAT(ext_name, mcdi_name)                      \
1416         [EF10_STAT_ ## ext_name] =                              \
1417         { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1418 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name)                \
1419         [EF10_STAT_ ## int_name] =                              \
1420         { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1421 #define EF10_OTHER_STAT(ext_name)                               \
1422         [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1423 #define GENERIC_SW_STAT(ext_name)                               \
1424         [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1425
1426 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1427         EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1428         EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1429         EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1430         EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1431         EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1432         EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1433         EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1434         EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1435         EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1436         EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1437         EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1438         EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1439         EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1440         EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1441         EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1442         EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1443         EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1444         EF10_OTHER_STAT(port_rx_good_bytes),
1445         EF10_OTHER_STAT(port_rx_bad_bytes),
1446         EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1447         EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1448         EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1449         EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1450         EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1451         EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1452         EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1453         EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1454         EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1455         EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1456         EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1457         EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1458         EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1459         EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1460         EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1461         EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1462         EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1463         EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1464         EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1465         EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1466         EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1467         EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1468         GENERIC_SW_STAT(rx_nodesc_trunc),
1469         GENERIC_SW_STAT(rx_noskb_drops),
1470         EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1471         EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1472         EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1473         EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1474         EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1475         EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1476         EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1477         EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1478         EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1479         EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1480         EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1481         EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1482         EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1483         EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1484         EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1485         EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1486         EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1487         EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1488         EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1489         EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1490         EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1491         EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1492         EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1493         EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1494         EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1495         EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1496         EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1497         EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1498         EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1499         EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1500 };
1501
1502 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) |      \
1503                                (1ULL << EF10_STAT_port_tx_packets) |    \
1504                                (1ULL << EF10_STAT_port_tx_pause) |      \
1505                                (1ULL << EF10_STAT_port_tx_unicast) |    \
1506                                (1ULL << EF10_STAT_port_tx_multicast) |  \
1507                                (1ULL << EF10_STAT_port_tx_broadcast) |  \
1508                                (1ULL << EF10_STAT_port_rx_bytes) |      \
1509                                (1ULL <<                                 \
1510                                 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1511                                (1ULL << EF10_STAT_port_rx_good_bytes) | \
1512                                (1ULL << EF10_STAT_port_rx_bad_bytes) |  \
1513                                (1ULL << EF10_STAT_port_rx_packets) |    \
1514                                (1ULL << EF10_STAT_port_rx_good) |       \
1515                                (1ULL << EF10_STAT_port_rx_bad) |        \
1516                                (1ULL << EF10_STAT_port_rx_pause) |      \
1517                                (1ULL << EF10_STAT_port_rx_control) |    \
1518                                (1ULL << EF10_STAT_port_rx_unicast) |    \
1519                                (1ULL << EF10_STAT_port_rx_multicast) |  \
1520                                (1ULL << EF10_STAT_port_rx_broadcast) |  \
1521                                (1ULL << EF10_STAT_port_rx_lt64) |       \
1522                                (1ULL << EF10_STAT_port_rx_64) |         \
1523                                (1ULL << EF10_STAT_port_rx_65_to_127) |  \
1524                                (1ULL << EF10_STAT_port_rx_128_to_255) | \
1525                                (1ULL << EF10_STAT_port_rx_256_to_511) | \
1526                                (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1527                                (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1528                                (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1529                                (1ULL << EF10_STAT_port_rx_gtjumbo) |    \
1530                                (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1531                                (1ULL << EF10_STAT_port_rx_overflow) |   \
1532                                (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1533                                (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1534                                (1ULL << GENERIC_STAT_rx_noskb_drops))
1535
1536 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1537  * For a 10G/40G switchable port we do not expose these because they might
1538  * not include all the packets they should.
1539  * On 8000 series NICs these statistics are always provided.
1540  */
1541 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) |  \
1542                                  (1ULL << EF10_STAT_port_tx_lt64) |     \
1543                                  (1ULL << EF10_STAT_port_tx_64) |       \
1544                                  (1ULL << EF10_STAT_port_tx_65_to_127) |\
1545                                  (1ULL << EF10_STAT_port_tx_128_to_255) |\
1546                                  (1ULL << EF10_STAT_port_tx_256_to_511) |\
1547                                  (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1548                                  (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1549                                  (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1550
1551 /* These statistics are only provided by the 40G MAC.  For a 10G/40G
1552  * switchable port we do expose these because the errors will otherwise
1553  * be silent.
1554  */
1555 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1556                                   (1ULL << EF10_STAT_port_rx_length_error))
1557
1558 /* These statistics are only provided if the firmware supports the
1559  * capability PM_AND_RXDP_COUNTERS.
1560  */
1561 #define HUNT_PM_AND_RXDP_STAT_MASK (                                    \
1562         (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) |              \
1563         (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) |            \
1564         (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) |               \
1565         (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) |             \
1566         (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) |                      \
1567         (1ULL << EF10_STAT_port_rx_pm_discard_qbb) |                    \
1568         (1ULL << EF10_STAT_port_rx_pm_discard_mapping) |                \
1569         (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) |             \
1570         (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) |             \
1571         (1ULL << EF10_STAT_port_rx_dp_streaming_packets) |              \
1572         (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) |                      \
1573         (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1574
1575 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1576 {
1577         u64 raw_mask = HUNT_COMMON_STAT_MASK;
1578         u32 port_caps = efx_mcdi_phy_get_caps(efx);
1579         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1580
1581         if (!(efx->mcdi->fn_flags &
1582               1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1583                 return 0;
1584
1585         if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
1586                 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1587                 /* 8000 series have everything even at 40G */
1588                 if (nic_data->datapath_caps2 &
1589                     (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN))
1590                         raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1591         } else {
1592                 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1593         }
1594
1595         if (nic_data->datapath_caps &
1596             (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1597                 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1598
1599         return raw_mask;
1600 }
1601
1602 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1603 {
1604         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1605         u64 raw_mask[2];
1606
1607         raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1608
1609         /* Only show vadaptor stats when EVB capability is present */
1610         if (nic_data->datapath_caps &
1611             (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1612                 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1613                 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1614         } else {
1615                 raw_mask[1] = 0;
1616         }
1617
1618 #if BITS_PER_LONG == 64
1619         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1620         mask[0] = raw_mask[0];
1621         mask[1] = raw_mask[1];
1622 #else
1623         BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1624         mask[0] = raw_mask[0] & 0xffffffff;
1625         mask[1] = raw_mask[0] >> 32;
1626         mask[2] = raw_mask[1] & 0xffffffff;
1627 #endif
1628 }
1629
1630 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1631 {
1632         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1633
1634         efx_ef10_get_stat_mask(efx, mask);
1635         return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1636                                       mask, names);
1637 }
1638
1639 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1640                                            struct rtnl_link_stats64 *core_stats)
1641 {
1642         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1643         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1644         u64 *stats = nic_data->stats;
1645         size_t stats_count = 0, index;
1646
1647         efx_ef10_get_stat_mask(efx, mask);
1648
1649         if (full_stats) {
1650                 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1651                         if (efx_ef10_stat_desc[index].name) {
1652                                 *full_stats++ = stats[index];
1653                                 ++stats_count;
1654                         }
1655                 }
1656         }
1657
1658         if (!core_stats)
1659                 return stats_count;
1660
1661         if (nic_data->datapath_caps &
1662                         1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1663                 /* Use vadaptor stats. */
1664                 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1665                                          stats[EF10_STAT_rx_multicast] +
1666                                          stats[EF10_STAT_rx_broadcast];
1667                 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1668                                          stats[EF10_STAT_tx_multicast] +
1669                                          stats[EF10_STAT_tx_broadcast];
1670                 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1671                                        stats[EF10_STAT_rx_multicast_bytes] +
1672                                        stats[EF10_STAT_rx_broadcast_bytes];
1673                 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1674                                        stats[EF10_STAT_tx_multicast_bytes] +
1675                                        stats[EF10_STAT_tx_broadcast_bytes];
1676                 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1677                                          stats[GENERIC_STAT_rx_noskb_drops];
1678                 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1679                 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1680                 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1681                 core_stats->rx_errors = core_stats->rx_crc_errors;
1682                 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1683         } else {
1684                 /* Use port stats. */
1685                 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1686                 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1687                 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1688                 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1689                 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1690                                          stats[GENERIC_STAT_rx_nodesc_trunc] +
1691                                          stats[GENERIC_STAT_rx_noskb_drops];
1692                 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1693                 core_stats->rx_length_errors =
1694                                 stats[EF10_STAT_port_rx_gtjumbo] +
1695                                 stats[EF10_STAT_port_rx_length_error];
1696                 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1697                 core_stats->rx_frame_errors =
1698                                 stats[EF10_STAT_port_rx_align_error];
1699                 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1700                 core_stats->rx_errors = (core_stats->rx_length_errors +
1701                                          core_stats->rx_crc_errors +
1702                                          core_stats->rx_frame_errors);
1703         }
1704
1705         return stats_count;
1706 }
1707
1708 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1709 {
1710         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1711         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1712         __le64 generation_start, generation_end;
1713         u64 *stats = nic_data->stats;
1714         __le64 *dma_stats;
1715
1716         efx_ef10_get_stat_mask(efx, mask);
1717
1718         dma_stats = efx->stats_buffer.addr;
1719
1720         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1721         if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1722                 return 0;
1723         rmb();
1724         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1725                              stats, efx->stats_buffer.addr, false);
1726         rmb();
1727         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1728         if (generation_end != generation_start)
1729                 return -EAGAIN;
1730
1731         /* Update derived statistics */
1732         efx_nic_fix_nodesc_drop_stat(efx,
1733                                      &stats[EF10_STAT_port_rx_nodesc_drops]);
1734         stats[EF10_STAT_port_rx_good_bytes] =
1735                 stats[EF10_STAT_port_rx_bytes] -
1736                 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1737         efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1738                              stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1739         efx_update_sw_stats(efx, stats);
1740         return 0;
1741 }
1742
1743
1744 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1745                                        struct rtnl_link_stats64 *core_stats)
1746 {
1747         int retry;
1748
1749         /* If we're unlucky enough to read statistics during the DMA, wait
1750          * up to 10ms for it to finish (typically takes <500us)
1751          */
1752         for (retry = 0; retry < 100; ++retry) {
1753                 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1754                         break;
1755                 udelay(100);
1756         }
1757
1758         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1759 }
1760
1761 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1762 {
1763         MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1764         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1765         DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1766         __le64 generation_start, generation_end;
1767         u64 *stats = nic_data->stats;
1768         u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1769         struct efx_buffer stats_buf;
1770         __le64 *dma_stats;
1771         int rc;
1772
1773         spin_unlock_bh(&efx->stats_lock);
1774
1775         if (in_interrupt()) {
1776                 /* If in atomic context, cannot update stats.  Just update the
1777                  * software stats and return so the caller can continue.
1778                  */
1779                 spin_lock_bh(&efx->stats_lock);
1780                 efx_update_sw_stats(efx, stats);
1781                 return 0;
1782         }
1783
1784         efx_ef10_get_stat_mask(efx, mask);
1785
1786         rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1787         if (rc) {
1788                 spin_lock_bh(&efx->stats_lock);
1789                 return rc;
1790         }
1791
1792         dma_stats = stats_buf.addr;
1793         dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1794
1795         MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1796         MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1797                               MAC_STATS_IN_DMA, 1);
1798         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1799         MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1800
1801         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1802                                 NULL, 0, NULL);
1803         spin_lock_bh(&efx->stats_lock);
1804         if (rc) {
1805                 /* Expect ENOENT if DMA queues have not been set up */
1806                 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1807                         efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1808                                                sizeof(inbuf), NULL, 0, rc);
1809                 goto out;
1810         }
1811
1812         generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1813         if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1814                 WARN_ON_ONCE(1);
1815                 goto out;
1816         }
1817         rmb();
1818         efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1819                              stats, stats_buf.addr, false);
1820         rmb();
1821         generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1822         if (generation_end != generation_start) {
1823                 rc = -EAGAIN;
1824                 goto out;
1825         }
1826
1827         efx_update_sw_stats(efx, stats);
1828 out:
1829         efx_nic_free_buffer(efx, &stats_buf);
1830         return rc;
1831 }
1832
1833 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1834                                        struct rtnl_link_stats64 *core_stats)
1835 {
1836         if (efx_ef10_try_update_nic_stats_vf(efx))
1837                 return 0;
1838
1839         return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1840 }
1841
1842 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1843 {
1844         struct efx_nic *efx = channel->efx;
1845         unsigned int mode, usecs;
1846         efx_dword_t timer_cmd;
1847
1848         if (channel->irq_moderation_us) {
1849                 mode = 3;
1850                 usecs = channel->irq_moderation_us;
1851         } else {
1852                 mode = 0;
1853                 usecs = 0;
1854         }
1855
1856         if (EFX_EF10_WORKAROUND_61265(efx)) {
1857                 MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_EVQ_TMR_IN_LEN);
1858                 unsigned int ns = usecs * 1000;
1859
1860                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_INSTANCE,
1861                                channel->channel);
1862                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, ns);
1863                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, ns);
1864                 MCDI_SET_DWORD(inbuf, SET_EVQ_TMR_IN_TMR_MODE, mode);
1865
1866                 efx_mcdi_rpc_async(efx, MC_CMD_SET_EVQ_TMR,
1867                                    inbuf, sizeof(inbuf), 0, NULL, 0);
1868         } else if (EFX_EF10_WORKAROUND_35388(efx)) {
1869                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1870
1871                 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1872                                      EFE_DD_EVQ_IND_TIMER_FLAGS,
1873                                      ERF_DD_EVQ_IND_TIMER_MODE, mode,
1874                                      ERF_DD_EVQ_IND_TIMER_VAL, ticks);
1875                 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1876                                 channel->channel);
1877         } else {
1878                 unsigned int ticks = efx_usecs_to_ticks(efx, usecs);
1879
1880                 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1881                                      ERF_DZ_TC_TIMER_VAL, ticks);
1882                 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1883                                 channel->channel);
1884         }
1885 }
1886
1887 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1888                                 struct ethtool_wolinfo *wol) {}
1889
1890 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1891 {
1892         return -EOPNOTSUPP;
1893 }
1894
1895 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1896 {
1897         wol->supported = 0;
1898         wol->wolopts = 0;
1899         memset(&wol->sopass, 0, sizeof(wol->sopass));
1900 }
1901
1902 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1903 {
1904         if (type != 0)
1905                 return -EINVAL;
1906         return 0;
1907 }
1908
1909 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1910                                   const efx_dword_t *hdr, size_t hdr_len,
1911                                   const efx_dword_t *sdu, size_t sdu_len)
1912 {
1913         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1914         u8 *pdu = nic_data->mcdi_buf.addr;
1915
1916         memcpy(pdu, hdr, hdr_len);
1917         memcpy(pdu + hdr_len, sdu, sdu_len);
1918         wmb();
1919
1920         /* The hardware provides 'low' and 'high' (doorbell) registers
1921          * for passing the 64-bit address of an MCDI request to
1922          * firmware.  However the dwords are swapped by firmware.  The
1923          * least significant bits of the doorbell are then 0 for all
1924          * MCDI requests due to alignment.
1925          */
1926         _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1927                     ER_DZ_MC_DB_LWRD);
1928         _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1929                     ER_DZ_MC_DB_HWRD);
1930 }
1931
1932 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1933 {
1934         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1935         const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1936
1937         rmb();
1938         return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1939 }
1940
1941 static void
1942 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1943                             size_t offset, size_t outlen)
1944 {
1945         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1946         const u8 *pdu = nic_data->mcdi_buf.addr;
1947
1948         memcpy(outbuf, pdu + offset, outlen);
1949 }
1950
1951 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1952 {
1953         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1954
1955         /* All our allocations have been reset */
1956         efx_ef10_reset_mc_allocations(efx);
1957
1958         /* The datapath firmware might have been changed */
1959         nic_data->must_check_datapath_caps = true;
1960
1961         /* MAC statistics have been cleared on the NIC; clear the local
1962          * statistic that we update with efx_update_diff_stat().
1963          */
1964         nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1965 }
1966
1967 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1968 {
1969         struct efx_ef10_nic_data *nic_data = efx->nic_data;
1970         int rc;
1971
1972         rc = efx_ef10_get_warm_boot_count(efx);
1973         if (rc < 0) {
1974                 /* The firmware is presumably in the process of
1975                  * rebooting.  However, we are supposed to report each
1976                  * reboot just once, so we must only do that once we
1977                  * can read and store the updated warm boot count.
1978                  */
1979                 return 0;
1980         }
1981
1982         if (rc == nic_data->warm_boot_count)
1983                 return 0;
1984
1985         nic_data->warm_boot_count = rc;
1986         efx_ef10_mcdi_reboot_detected(efx);
1987
1988         return -EIO;
1989 }
1990
1991 /* Handle an MSI interrupt
1992  *
1993  * Handle an MSI hardware interrupt.  This routine schedules event
1994  * queue processing.  No interrupt acknowledgement cycle is necessary.
1995  * Also, we never need to check that the interrupt is for us, since
1996  * MSI interrupts cannot be shared.
1997  */
1998 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1999 {
2000         struct efx_msi_context *context = dev_id;
2001         struct efx_nic *efx = context->efx;
2002
2003         netif_vdbg(efx, intr, efx->net_dev,
2004                    "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
2005
2006         if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
2007                 /* Note test interrupts */
2008                 if (context->index == efx->irq_level)
2009                         efx->last_irq_cpu = raw_smp_processor_id();
2010
2011                 /* Schedule processing of the channel */
2012                 efx_schedule_channel_irq(efx->channel[context->index]);
2013         }
2014
2015         return IRQ_HANDLED;
2016 }
2017
2018 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
2019 {
2020         struct efx_nic *efx = dev_id;
2021         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
2022         struct efx_channel *channel;
2023         efx_dword_t reg;
2024         u32 queues;
2025
2026         /* Read the ISR which also ACKs the interrupts */
2027         efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
2028         queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
2029
2030         if (queues == 0)
2031                 return IRQ_NONE;
2032
2033         if (likely(soft_enabled)) {
2034                 /* Note test interrupts */
2035                 if (queues & (1U << efx->irq_level))
2036                         efx->last_irq_cpu = raw_smp_processor_id();
2037
2038                 efx_for_each_channel(channel, efx) {
2039                         if (queues & 1)
2040                                 efx_schedule_channel_irq(channel);
2041                         queues >>= 1;
2042                 }
2043         }
2044
2045         netif_vdbg(efx, intr, efx->net_dev,
2046                    "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
2047                    irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
2048
2049         return IRQ_HANDLED;
2050 }
2051
2052 static int efx_ef10_irq_test_generate(struct efx_nic *efx)
2053 {
2054         MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
2055
2056         if (efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG41750, true,
2057                                     NULL) == 0)
2058                 return -ENOTSUPP;
2059
2060         BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
2061
2062         MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
2063         return efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
2064                             inbuf, sizeof(inbuf), NULL, 0, NULL);
2065 }
2066
2067 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
2068 {
2069         return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
2070                                     (tx_queue->ptr_mask + 1) *
2071                                     sizeof(efx_qword_t),
2072                                     GFP_KERNEL);
2073 }
2074
2075 /* This writes to the TX_DESC_WPTR and also pushes data */
2076 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
2077                                          const efx_qword_t *txd)
2078 {
2079         unsigned int write_ptr;
2080         efx_oword_t reg;
2081
2082         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2083         EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
2084         reg.qword[0] = *txd;
2085         efx_writeo_page(tx_queue->efx, &reg,
2086                         ER_DZ_TX_DESC_UPD, tx_queue->queue);
2087 }
2088
2089 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
2090 {
2091         MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2092                                                        EFX_BUF_SIZE));
2093         bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
2094         size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
2095         struct efx_channel *channel = tx_queue->channel;
2096         struct efx_nic *efx = tx_queue->efx;
2097         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2098         size_t inlen;
2099         dma_addr_t dma_addr;
2100         efx_qword_t *txd;
2101         int rc;
2102         int i;
2103         BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
2104
2105         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
2106         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
2107         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
2108         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
2109         MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
2110                               INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
2111                               INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
2112         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
2113         MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
2114
2115         dma_addr = tx_queue->txd.buf.dma_addr;
2116
2117         netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2118                   tx_queue->queue, entries, (u64)dma_addr);
2119
2120         for (i = 0; i < entries; ++i) {
2121                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2122                 dma_addr += EFX_BUF_SIZE;
2123         }
2124
2125         inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2126
2127         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2128                           NULL, 0, NULL);
2129         if (rc)
2130                 goto fail;
2131
2132         /* A previous user of this TX queue might have set us up the
2133          * bomb by writing a descriptor to the TX push collector but
2134          * not the doorbell.  (Each collector belongs to a port, not a
2135          * queue or function, so cannot easily be reset.)  We must
2136          * attempt to push a no-op descriptor in its place.
2137          */
2138         tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2139         tx_queue->insert_count = 1;
2140         txd = efx_tx_desc(tx_queue, 0);
2141         EFX_POPULATE_QWORD_4(*txd,
2142                              ESF_DZ_TX_DESC_IS_OPT, true,
2143                              ESF_DZ_TX_OPTION_TYPE,
2144                              ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2145                              ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2146                              ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2147         tx_queue->write_count = 1;
2148
2149         if (nic_data->datapath_caps &
2150             (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2151                 tx_queue->tso_version = 1;
2152         }
2153
2154         wmb();
2155         efx_ef10_push_tx_desc(tx_queue, txd);
2156
2157         return;
2158
2159 fail:
2160         netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2161                     tx_queue->queue);
2162 }
2163
2164 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2165 {
2166         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2167         MCDI_DECLARE_BUF_ERR(outbuf);
2168         struct efx_nic *efx = tx_queue->efx;
2169         size_t outlen;
2170         int rc;
2171
2172         MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2173                        tx_queue->queue);
2174
2175         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2176                           outbuf, sizeof(outbuf), &outlen);
2177
2178         if (rc && rc != -EALREADY)
2179                 goto fail;
2180
2181         return;
2182
2183 fail:
2184         efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2185                                outbuf, outlen, rc);
2186 }
2187
2188 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2189 {
2190         efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2191 }
2192
2193 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2194 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2195 {
2196         unsigned int write_ptr;
2197         efx_dword_t reg;
2198
2199         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2200         EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2201         efx_writed_page(tx_queue->efx, &reg,
2202                         ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2203 }
2204
2205 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2206 {
2207         unsigned int old_write_count = tx_queue->write_count;
2208         struct efx_tx_buffer *buffer;
2209         unsigned int write_ptr;
2210         efx_qword_t *txd;
2211
2212         tx_queue->xmit_more_available = false;
2213         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2214                 return;
2215
2216         do {
2217                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2218                 buffer = &tx_queue->buffer[write_ptr];
2219                 txd = efx_tx_desc(tx_queue, write_ptr);
2220                 ++tx_queue->write_count;
2221
2222                 /* Create TX descriptor ring entry */
2223                 if (buffer->flags & EFX_TX_BUF_OPTION) {
2224                         *txd = buffer->option;
2225                 } else {
2226                         BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2227                         EFX_POPULATE_QWORD_3(
2228                                 *txd,
2229                                 ESF_DZ_TX_KER_CONT,
2230                                 buffer->flags & EFX_TX_BUF_CONT,
2231                                 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2232                                 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2233                 }
2234         } while (tx_queue->write_count != tx_queue->insert_count);
2235
2236         wmb(); /* Ensure descriptors are written before they are fetched */
2237
2238         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2239                 txd = efx_tx_desc(tx_queue,
2240                                   old_write_count & tx_queue->ptr_mask);
2241                 efx_ef10_push_tx_desc(tx_queue, txd);
2242                 ++tx_queue->pushes;
2243         } else {
2244                 efx_ef10_notify_tx_desc(tx_queue);
2245         }
2246 }
2247
2248 #define RSS_MODE_HASH_ADDRS     (1 << RSS_MODE_HASH_SRC_ADDR_LBN |\
2249                                  1 << RSS_MODE_HASH_DST_ADDR_LBN)
2250 #define RSS_MODE_HASH_PORTS     (1 << RSS_MODE_HASH_SRC_PORT_LBN |\
2251                                  1 << RSS_MODE_HASH_DST_PORT_LBN)
2252 #define RSS_CONTEXT_FLAGS_DEFAULT       (1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN |\
2253                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN |\
2254                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN |\
2255                                          1 << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN |\
2256                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_LBN |\
2257                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN |\
2258                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_LBN |\
2259                                          (RSS_MODE_HASH_ADDRS | RSS_MODE_HASH_PORTS) << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_LBN |\
2260                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN |\
2261                                          RSS_MODE_HASH_ADDRS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_LBN)
2262
2263 static int efx_ef10_get_rss_flags(struct efx_nic *efx, u32 context, u32 *flags)
2264 {
2265         /* Firmware had a bug (sfc bug 61952) where it would not actually
2266          * fill in the flags field in the response to MC_CMD_RSS_CONTEXT_GET_FLAGS.
2267          * This meant that it would always contain whatever was previously
2268          * in the MCDI buffer.  Fortunately, all firmware versions with
2269          * this bug have the same default flags value for a newly-allocated
2270          * RSS context, and the only time we want to get the flags is just
2271          * after allocating.  Moreover, the response has a 32-bit hole
2272          * where the context ID would be in the request, so we can use an
2273          * overlength buffer in the request and pre-fill the flags field
2274          * with what we believe the default to be.  Thus if the firmware
2275          * has the bug, it will leave our pre-filled value in the flags
2276          * field of the response, and we will get the right answer.
2277          *
2278          * However, this does mean that this function should NOT be used if
2279          * the RSS context flags might not be their defaults - it is ONLY
2280          * reliably correct for a newly-allocated RSS context.
2281          */
2282         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2283         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN);
2284         size_t outlen;
2285         int rc;
2286
2287         /* Check we have a hole for the context ID */
2288         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN != MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST);
2289         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID, context);
2290         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS,
2291                        RSS_CONTEXT_FLAGS_DEFAULT);
2292         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_GET_FLAGS, inbuf,
2293                           sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
2294         if (rc == 0) {
2295                 if (outlen < MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN)
2296                         rc = -EIO;
2297                 else
2298                         *flags = MCDI_DWORD(outbuf, RSS_CONTEXT_GET_FLAGS_OUT_FLAGS);
2299         }
2300         return rc;
2301 }
2302
2303 /* Attempt to enable 4-tuple UDP hashing on the specified RSS context.
2304  * If we fail, we just leave the RSS context at its default hash settings,
2305  * which is safe but may slightly reduce performance.
2306  * Defaults are 4-tuple for TCP and 2-tuple for UDP and other-IP, so we
2307  * just need to set the UDP ports flags (for both IP versions).
2308  */
2309 static void efx_ef10_set_rss_flags(struct efx_nic *efx, u32 context)
2310 {
2311         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN);
2312         u32 flags;
2313
2314         BUILD_BUG_ON(MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN != 0);
2315
2316         if (efx_ef10_get_rss_flags(efx, context, &flags) != 0)
2317                 return;
2318         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID, context);
2319         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_LBN;
2320         flags |= RSS_MODE_HASH_PORTS << MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_LBN;
2321         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_SET_FLAGS_IN_FLAGS, flags);
2322         efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_FLAGS, inbuf, sizeof(inbuf),
2323                      NULL, 0, NULL);
2324 }
2325
2326 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2327                                       bool exclusive, unsigned *context_size)
2328 {
2329         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2330         MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2331         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2332         size_t outlen;
2333         int rc;
2334         u32 alloc_type = exclusive ?
2335                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2336                                 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2337         unsigned rss_spread = exclusive ?
2338                                 efx->rss_spread :
2339                                 min(rounddown_pow_of_two(efx->rss_spread),
2340                                     EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2341
2342         if (!exclusive && rss_spread == 1) {
2343                 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2344                 if (context_size)
2345                         *context_size = 1;
2346                 return 0;
2347         }
2348
2349         if (nic_data->datapath_caps &
2350             1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2351                 return -EOPNOTSUPP;
2352
2353         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2354                        nic_data->vport_id);
2355         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2356         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2357
2358         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2359                 outbuf, sizeof(outbuf), &outlen);
2360         if (rc != 0)
2361                 return rc;
2362
2363         if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2364                 return -EIO;
2365
2366         *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2367
2368         if (context_size)
2369                 *context_size = rss_spread;
2370
2371         if (nic_data->datapath_caps &
2372             1 << MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_LBN)
2373                 efx_ef10_set_rss_flags(efx, *context);
2374
2375         return 0;
2376 }
2377
2378 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2379 {
2380         MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2381         int rc;
2382
2383         MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2384                        context);
2385
2386         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2387                             NULL, 0, NULL);
2388         WARN_ON(rc != 0);
2389 }
2390
2391 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2392                                        const u32 *rx_indir_table)
2393 {
2394         MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2395         MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2396         int i, rc;
2397
2398         MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2399                        context);
2400         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2401                      MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2402
2403         for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2404                 MCDI_PTR(tablebuf,
2405                          RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2406                                 (u8) rx_indir_table[i];
2407
2408         rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2409                           sizeof(tablebuf), NULL, 0, NULL);
2410         if (rc != 0)
2411                 return rc;
2412
2413         MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2414                        context);
2415         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2416                      MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2417         for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2418                 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2419                         efx->rx_hash_key[i];
2420
2421         return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2422                             sizeof(keybuf), NULL, 0, NULL);
2423 }
2424
2425 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2426 {
2427         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2428
2429         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2430                 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2431         nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2432 }
2433
2434 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2435                                               unsigned *context_size)
2436 {
2437         u32 new_rx_rss_context;
2438         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2439         int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2440                                             false, context_size);
2441
2442         if (rc != 0)
2443                 return rc;
2444
2445         nic_data->rx_rss_context = new_rx_rss_context;
2446         nic_data->rx_rss_context_exclusive = false;
2447         efx_set_default_rx_indir_table(efx);
2448         return 0;
2449 }
2450
2451 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2452                                                  const u32 *rx_indir_table)
2453 {
2454         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2455         int rc;
2456         u32 new_rx_rss_context;
2457
2458         if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2459             !nic_data->rx_rss_context_exclusive) {
2460                 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2461                                                 true, NULL);
2462                 if (rc == -EOPNOTSUPP)
2463                         return rc;
2464                 else if (rc != 0)
2465                         goto fail1;
2466         } else {
2467                 new_rx_rss_context = nic_data->rx_rss_context;
2468         }
2469
2470         rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2471                                          rx_indir_table);
2472         if (rc != 0)
2473                 goto fail2;
2474
2475         if (nic_data->rx_rss_context != new_rx_rss_context)
2476                 efx_ef10_rx_free_indir_table(efx);
2477         nic_data->rx_rss_context = new_rx_rss_context;
2478         nic_data->rx_rss_context_exclusive = true;
2479         if (rx_indir_table != efx->rx_indir_table)
2480                 memcpy(efx->rx_indir_table, rx_indir_table,
2481                        sizeof(efx->rx_indir_table));
2482         return 0;
2483
2484 fail2:
2485         if (new_rx_rss_context != nic_data->rx_rss_context)
2486                 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2487 fail1:
2488         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2489         return rc;
2490 }
2491
2492 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2493                                           const u32 *rx_indir_table)
2494 {
2495         int rc;
2496
2497         if (efx->rss_spread == 1)
2498                 return 0;
2499
2500         rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2501
2502         if (rc == -ENOBUFS && !user) {
2503                 unsigned context_size;
2504                 bool mismatch = false;
2505                 size_t i;
2506
2507                 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2508                      i++)
2509                         mismatch = rx_indir_table[i] !=
2510                                 ethtool_rxfh_indir_default(i, efx->rss_spread);
2511
2512                 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2513                 if (rc == 0) {
2514                         if (context_size != efx->rss_spread)
2515                                 netif_warn(efx, probe, efx->net_dev,
2516                                            "Could not allocate an exclusive RSS"
2517                                            " context; allocated a shared one of"
2518                                            " different size."
2519                                            " Wanted %u, got %u.\n",
2520                                            efx->rss_spread, context_size);
2521                         else if (mismatch)
2522                                 netif_warn(efx, probe, efx->net_dev,
2523                                            "Could not allocate an exclusive RSS"
2524                                            " context; allocated a shared one but"
2525                                            " could not apply custom"
2526                                            " indirection.\n");
2527                         else
2528                                 netif_info(efx, probe, efx->net_dev,
2529                                            "Could not allocate an exclusive RSS"
2530                                            " context; allocated a shared one.\n");
2531                 }
2532         }
2533         return rc;
2534 }
2535
2536 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2537                                           const u32 *rx_indir_table
2538                                           __attribute__ ((unused)))
2539 {
2540         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2541
2542         if (user)
2543                 return -EOPNOTSUPP;
2544         if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2545                 return 0;
2546         return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2547 }
2548
2549 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2550 {
2551         return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2552                                     (rx_queue->ptr_mask + 1) *
2553                                     sizeof(efx_qword_t),
2554                                     GFP_KERNEL);
2555 }
2556
2557 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2558 {
2559         MCDI_DECLARE_BUF(inbuf,
2560                          MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2561                                                 EFX_BUF_SIZE));
2562         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2563         size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2564         struct efx_nic *efx = rx_queue->efx;
2565         struct efx_ef10_nic_data *nic_data = efx->nic_data;
2566         size_t inlen;
2567         dma_addr_t dma_addr;
2568         int rc;
2569         int i;
2570         BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2571
2572         rx_queue->scatter_n = 0;
2573         rx_queue->scatter_len = 0;
2574
2575         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2576         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2577         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2578         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2579                        efx_rx_queue_index(rx_queue));
2580         MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2581                               INIT_RXQ_IN_FLAG_PREFIX, 1,
2582                               INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2583         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2584         MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2585
2586         dma_addr = rx_queue->rxd.buf.dma_addr;
2587
2588         netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2589                   efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2590
2591         for (i = 0; i < entries; ++i) {
2592                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2593                 dma_addr += EFX_BUF_SIZE;
2594         }
2595
2596         inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2597
2598         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2599                           NULL, 0, NULL);
2600         if (rc)
2601                 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2602                             efx_rx_queue_index(rx_queue));
2603 }
2604
2605 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2606 {
2607         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2608         MCDI_DECLARE_BUF_ERR(outbuf);
2609         struct efx_nic *efx = rx_queue->efx;
2610         size_t outlen;
2611         int rc;
2612
2613         MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2614                        efx_rx_queue_index(rx_queue));
2615
2616         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2617                           outbuf, sizeof(outbuf), &outlen);
2618
2619         if (rc && rc != -EALREADY)
2620                 goto fail;
2621
2622         return;
2623
2624 fail:
2625         efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2626                                outbuf, outlen, rc);
2627 }
2628
2629 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2630 {
2631         efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2632 }
2633
2634 /* This creates an entry in the RX descriptor queue */
2635 static inline void
2636 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2637 {
2638         struct efx_rx_buffer *rx_buf;
2639         efx_qword_t *rxd;
2640
2641         rxd = efx_rx_desc(rx_queue, index);
2642         rx_buf = efx_rx_buffer(rx_queue, index);
2643         EFX_POPULATE_QWORD_2(*rxd,
2644                              ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2645                              ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2646 }
2647
2648 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2649 {
2650         struct efx_nic *efx = rx_queue->efx;
2651         unsigned int write_count;
2652         efx_dword_t reg;
2653
2654         /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2655         write_count = rx_queue->added_count & ~7;
2656         if (rx_queue->notified_count == write_count)
2657                 return;
2658
2659         do
2660                 efx_ef10_build_rx_desc(
2661                         rx_queue,
2662                         rx_queue->notified_count & rx_queue->ptr_mask);
2663         while (++rx_queue->notified_count != write_count);
2664
2665         wmb();
2666         EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2667                              write_count & rx_queue->ptr_mask);
2668         efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2669                         efx_rx_queue_index(rx_queue));
2670 }
2671
2672 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2673
2674 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2675 {
2676         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2677         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2678         efx_qword_t event;
2679
2680         EFX_POPULATE_QWORD_2(event,
2681                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2682                              ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2683
2684         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2685
2686         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2687          * already swapped the data to little-endian order.
2688          */
2689         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2690                sizeof(efx_qword_t));
2691
2692         efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2693                            inbuf, sizeof(inbuf), 0,
2694                            efx_ef10_rx_defer_refill_complete, 0);
2695 }
2696
2697 static void
2698 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2699                                   int rc, efx_dword_t *outbuf,
2700                                   size_t outlen_actual)
2701 {
2702         /* nothing to do */
2703 }
2704
2705 static int efx_ef10_ev_probe(struct efx_channel *channel)
2706 {
2707         return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2708                                     (channel->eventq_mask + 1) *
2709                                     sizeof(efx_qword_t),
2710                                     GFP_KERNEL);
2711 }
2712
2713 static void efx_ef10_ev_fini(struct efx_channel *channel)
2714 {
2715         MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2716         MCDI_DECLARE_BUF_ERR(outbuf);
2717         struct efx_nic *efx = channel->efx;
2718         size_t outlen;
2719         int rc;
2720
2721         MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2722
2723         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2724                           outbuf, sizeof(outbuf), &outlen);
2725
2726         if (rc && rc != -EALREADY)
2727                 goto fail;
2728
2729         return;
2730
2731 fail:
2732         efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2733                                outbuf, outlen, rc);
2734 }
2735
2736 static int efx_ef10_ev_init(struct efx_channel *channel)
2737 {
2738         MCDI_DECLARE_BUF(inbuf,
2739                          MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2740                                                    EFX_BUF_SIZE));
2741         MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_V2_OUT_LEN);
2742         size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2743         struct efx_nic *efx = channel->efx;
2744         struct efx_ef10_nic_data *nic_data;
2745         size_t inlen, outlen;
2746         unsigned int enabled, implemented;
2747         dma_addr_t dma_addr;
2748         int rc;
2749         int i;
2750
2751         nic_data = efx->nic_data;
2752
2753         /* Fill event queue with all ones (i.e. empty events) */
2754         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2755
2756         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2757         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2758         /* INIT_EVQ expects index in vector table, not absolute */
2759         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2760         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2761                        MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2762         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2763         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2764         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2765                        MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2766         MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2767
2768         if (nic_data->datapath_caps2 &
2769             1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN) {
2770                 /* Use the new generic approach to specifying event queue
2771                  * configuration, requesting lower latency or higher throughput.
2772                  * The options that actually get used appear in the output.
2773                  */
2774                 MCDI_POPULATE_DWORD_2(inbuf, INIT_EVQ_V2_IN_FLAGS,
2775                                       INIT_EVQ_V2_IN_FLAG_INTERRUPTING, 1,
2776                                       INIT_EVQ_V2_IN_FLAG_TYPE,
2777                                       MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO);
2778         } else {
2779                 bool cut_thru = !(nic_data->datapath_caps &
2780                         1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2781
2782                 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2783                                       INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2784                                       INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2785                                       INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2786                                       INIT_EVQ_IN_FLAG_CUT_THRU, cut_thru);
2787         }
2788
2789         dma_addr = channel->eventq.buf.dma_addr;
2790         for (i = 0; i < entries; ++i) {
2791                 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2792                 dma_addr += EFX_BUF_SIZE;
2793         }
2794
2795         inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2796
2797         rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2798                           outbuf, sizeof(outbuf), &outlen);
2799
2800         if (outlen >= MC_CMD_INIT_EVQ_V2_OUT_LEN)
2801                 netif_dbg(efx, drv, efx->net_dev,
2802                           "Channel %d using event queue flags %08x\n",
2803                           channel->channel,
2804                           MCDI_DWORD(outbuf, INIT_EVQ_V2_OUT_FLAGS));
2805
2806         /* IRQ return is ignored */
2807         if (channel->channel || rc)
2808                 return rc;
2809
2810         /* Successfully created event queue on channel 0 */
2811         rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2812         if (rc == -ENOSYS) {
2813                 /* GET_WORKAROUNDS was implemented before this workaround,
2814                  * thus it must be unavailable in this firmware.
2815                  */
2816                 nic_data->workaround_26807 = false;
2817                 rc = 0;
2818         } else if (rc) {
2819                 goto fail;
2820         } else {
2821                 nic_data->workaround_26807 =
2822                         !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2823
2824                 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2825                     !nic_data->workaround_26807) {
2826                         unsigned int flags;
2827
2828                         rc = efx_mcdi_set_workaround(efx,
2829                                                      MC_CMD_WORKAROUND_BUG26807,
2830                                                      true, &flags);
2831
2832                         if (!rc) {
2833                                 if (flags &
2834                                     1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2835                                         netif_info(efx, drv, efx->net_dev,
2836                                                    "other functions on NIC have been reset\n");
2837
2838                                         /* With MCFW v4.6.x and earlier, the
2839                                          * boot count will have incremented,
2840                                          * so re-read the warm_boot_count
2841                                          * value now to ensure this function
2842                                          * doesn't think it has changed next
2843                                          * time it checks.
2844                                          */
2845                                         rc = efx_ef10_get_warm_boot_count(efx);
2846                                         if (rc >= 0) {
2847                                                 nic_data->warm_boot_count = rc;
2848                                                 rc = 0;
2849                                         }
2850                                 }
2851                                 nic_data->workaround_26807 = true;
2852                         } else if (rc == -EPERM) {
2853                                 rc = 0;
2854                         }
2855                 }
2856         }
2857
2858         if (!rc)
2859                 return 0;
2860
2861 fail:
2862         efx_ef10_ev_fini(channel);
2863         return rc;
2864 }
2865
2866 static void efx_ef10_ev_remove(struct efx_channel *channel)
2867 {
2868         efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2869 }
2870
2871 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2872                                            unsigned int rx_queue_label)
2873 {
2874         struct efx_nic *efx = rx_queue->efx;
2875
2876         netif_info(efx, hw, efx->net_dev,
2877                    "rx event arrived on queue %d labeled as queue %u\n",
2878                    efx_rx_queue_index(rx_queue), rx_queue_label);
2879
2880         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2881 }
2882
2883 static void
2884 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2885                              unsigned int actual, unsigned int expected)
2886 {
2887         unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2888         struct efx_nic *efx = rx_queue->efx;
2889
2890         netif_info(efx, hw, efx->net_dev,
2891                    "dropped %d events (index=%d expected=%d)\n",
2892                    dropped, actual, expected);
2893
2894         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2895 }
2896
2897 /* partially received RX was aborted. clean up. */
2898 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2899 {
2900         unsigned int rx_desc_ptr;
2901
2902         netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2903                   "scattered RX aborted (dropping %u buffers)\n",
2904                   rx_queue->scatter_n);
2905
2906         rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2907
2908         efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2909                       0, EFX_RX_PKT_DISCARD);
2910
2911         rx_queue->removed_count += rx_queue->scatter_n;
2912         rx_queue->scatter_n = 0;
2913         rx_queue->scatter_len = 0;
2914         ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2915 }
2916
2917 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2918                                     const efx_qword_t *event)
2919 {
2920         unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2921         unsigned int n_descs, n_packets, i;
2922         struct efx_nic *efx = channel->efx;
2923         struct efx_rx_queue *rx_queue;
2924         bool rx_cont;
2925         u16 flags = 0;
2926
2927         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2928                 return 0;
2929
2930         /* Basic packet information */
2931         rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2932         next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2933         rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2934         rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2935         rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2936
2937         if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2938                 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2939                             EFX_QWORD_FMT "\n",
2940                             EFX_QWORD_VAL(*event));
2941
2942         rx_queue = efx_channel_get_rx_queue(channel);
2943
2944         if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2945                 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2946
2947         n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2948                    ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2949
2950         if (n_descs != rx_queue->scatter_n + 1) {
2951                 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2952
2953                 /* detect rx abort */
2954                 if (unlikely(n_descs == rx_queue->scatter_n)) {
2955                         if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2956                                 netdev_WARN(efx->net_dev,
2957                                             "invalid RX abort: scatter_n=%u event="
2958                                             EFX_QWORD_FMT "\n",
2959                                             rx_queue->scatter_n,
2960                                             EFX_QWORD_VAL(*event));
2961                         efx_ef10_handle_rx_abort(rx_queue);
2962                         return 0;
2963                 }
2964
2965                 /* Check that RX completion merging is valid, i.e.
2966                  * the current firmware supports it and this is a
2967                  * non-scattered packet.
2968                  */
2969                 if (!(nic_data->datapath_caps &
2970                       (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2971                     rx_queue->scatter_n != 0 || rx_cont) {
2972                         efx_ef10_handle_rx_bad_lbits(
2973                                 rx_queue, next_ptr_lbits,
2974                                 (rx_queue->removed_count +
2975                                  rx_queue->scatter_n + 1) &
2976                                 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2977                         return 0;
2978                 }
2979
2980                 /* Merged completion for multiple non-scattered packets */
2981                 rx_queue->scatter_n = 1;
2982                 rx_queue->scatter_len = 0;
2983                 n_packets = n_descs;
2984                 ++channel->n_rx_merge_events;
2985                 channel->n_rx_merge_packets += n_packets;
2986                 flags |= EFX_RX_PKT_PREFIX_LEN;
2987         } else {
2988                 ++rx_queue->scatter_n;
2989                 rx_queue->scatter_len += rx_bytes;
2990                 if (rx_cont)
2991                         return 0;
2992                 n_packets = 1;
2993         }
2994
2995         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2996                 flags |= EFX_RX_PKT_DISCARD;
2997
2998         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2999                 channel->n_rx_ip_hdr_chksum_err += n_packets;
3000         } else if (unlikely(EFX_QWORD_FIELD(*event,
3001                                             ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
3002                 channel->n_rx_tcp_udp_chksum_err += n_packets;
3003         } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
3004                    rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
3005                 flags |= EFX_RX_PKT_CSUMMED;
3006         }
3007
3008         if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
3009                 flags |= EFX_RX_PKT_TCP;
3010
3011         channel->irq_mod_score += 2 * n_packets;
3012
3013         /* Handle received packet(s) */
3014         for (i = 0; i < n_packets; i++) {
3015                 efx_rx_packet(rx_queue,
3016                               rx_queue->removed_count & rx_queue->ptr_mask,
3017                               rx_queue->scatter_n, rx_queue->scatter_len,
3018                               flags);
3019                 rx_queue->removed_count += rx_queue->scatter_n;
3020         }
3021
3022         rx_queue->scatter_n = 0;
3023         rx_queue->scatter_len = 0;
3024
3025         return n_packets;
3026 }
3027
3028 static int
3029 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
3030 {
3031         struct efx_nic *efx = channel->efx;
3032         struct efx_tx_queue *tx_queue;
3033         unsigned int tx_ev_desc_ptr;
3034         unsigned int tx_ev_q_label;
3035         int tx_descs = 0;
3036
3037         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
3038                 return 0;
3039
3040         if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
3041                 return 0;
3042
3043         /* Transmit completion */
3044         tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
3045         tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
3046         tx_queue = efx_channel_get_tx_queue(channel,
3047                                             tx_ev_q_label % EFX_TXQ_TYPES);
3048         tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
3049                     tx_queue->ptr_mask);
3050         efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
3051
3052         return tx_descs;
3053 }
3054
3055 static void
3056 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
3057 {
3058         struct efx_nic *efx = channel->efx;
3059         int subcode;
3060
3061         subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
3062
3063         switch (subcode) {
3064         case ESE_DZ_DRV_TIMER_EV:
3065         case ESE_DZ_DRV_WAKE_UP_EV:
3066                 break;
3067         case ESE_DZ_DRV_START_UP_EV:
3068                 /* event queue init complete. ok. */
3069                 break;
3070         default:
3071                 netif_err(efx, hw, efx->net_dev,
3072                           "channel %d unknown driver event type %d"
3073                           " (data " EFX_QWORD_FMT ")\n",
3074                           channel->channel, subcode,
3075                           EFX_QWORD_VAL(*event));
3076
3077         }
3078 }
3079
3080 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
3081                                                    efx_qword_t *event)
3082 {
3083         struct efx_nic *efx = channel->efx;
3084         u32 subcode;
3085
3086         subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
3087
3088         switch (subcode) {
3089         case EFX_EF10_TEST:
3090                 channel->event_test_cpu = raw_smp_processor_id();
3091                 break;
3092         case EFX_EF10_REFILL:
3093                 /* The queue must be empty, so we won't receive any rx
3094                  * events, so efx_process_channel() won't refill the
3095                  * queue. Refill it here
3096                  */
3097                 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
3098                 break;
3099         default:
3100                 netif_err(efx, hw, efx->net_dev,
3101                           "channel %d unknown driver event type %u"
3102                           " (data " EFX_QWORD_FMT ")\n",
3103                           channel->channel, (unsigned) subcode,
3104                           EFX_QWORD_VAL(*event));
3105         }
3106 }
3107
3108 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
3109 {
3110         struct efx_nic *efx = channel->efx;
3111         efx_qword_t event, *p_event;
3112         unsigned int read_ptr;
3113         int ev_code;
3114         int tx_descs = 0;
3115         int spent = 0;
3116
3117         if (quota <= 0)
3118                 return spent;
3119
3120         read_ptr = channel->eventq_read_ptr;
3121
3122         for (;;) {
3123                 p_event = efx_event(channel, read_ptr);
3124                 event = *p_event;
3125
3126                 if (!efx_event_present(&event))
3127                         break;
3128
3129                 EFX_SET_QWORD(*p_event);
3130
3131                 ++read_ptr;
3132
3133                 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
3134
3135                 netif_vdbg(efx, drv, efx->net_dev,
3136                            "processing event on %d " EFX_QWORD_FMT "\n",
3137                            channel->channel, EFX_QWORD_VAL(event));
3138
3139                 switch (ev_code) {
3140                 case ESE_DZ_EV_CODE_MCDI_EV:
3141                         efx_mcdi_process_event(channel, &event);
3142                         break;
3143                 case ESE_DZ_EV_CODE_RX_EV:
3144                         spent += efx_ef10_handle_rx_event(channel, &event);
3145                         if (spent >= quota) {
3146                                 /* XXX can we split a merged event to
3147                                  * avoid going over-quota?
3148                                  */
3149                                 spent = quota;
3150                                 goto out;
3151                         }
3152                         break;
3153                 case ESE_DZ_EV_CODE_TX_EV:
3154                         tx_descs += efx_ef10_handle_tx_event(channel, &event);
3155                         if (tx_descs > efx->txq_entries) {
3156                                 spent = quota;
3157                                 goto out;
3158                         } else if (++spent == quota) {
3159                                 goto out;
3160                         }
3161                         break;
3162                 case ESE_DZ_EV_CODE_DRIVER_EV:
3163                         efx_ef10_handle_driver_event(channel, &event);
3164                         if (++spent == quota)
3165                                 goto out;
3166                         break;
3167                 case EFX_EF10_DRVGEN_EV:
3168                         efx_ef10_handle_driver_generated_event(channel, &event);
3169                         break;
3170                 default:
3171                         netif_err(efx, hw, efx->net_dev,
3172                                   "channel %d unknown event type %d"
3173                                   " (data " EFX_QWORD_FMT ")\n",
3174                                   channel->channel, ev_code,
3175                                   EFX_QWORD_VAL(event));
3176                 }
3177         }
3178
3179 out:
3180         channel->eventq_read_ptr = read_ptr;
3181         return spent;
3182 }
3183
3184 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
3185 {
3186         struct efx_nic *efx = channel->efx;
3187         efx_dword_t rptr;
3188
3189         if (EFX_EF10_WORKAROUND_35388(efx)) {
3190                 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
3191                              (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
3192                 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
3193                              (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
3194
3195                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3196                                      EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
3197                                      ERF_DD_EVQ_IND_RPTR,
3198                                      (channel->eventq_read_ptr &
3199                                       channel->eventq_mask) >>
3200                                      ERF_DD_EVQ_IND_RPTR_WIDTH);
3201                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3202                                 channel->channel);
3203                 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
3204                                      EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
3205                                      ERF_DD_EVQ_IND_RPTR,
3206                                      channel->eventq_read_ptr &
3207                                      ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
3208                 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
3209                                 channel->channel);
3210         } else {
3211                 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
3212                                      channel->eventq_read_ptr &
3213                                      channel->eventq_mask);
3214                 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
3215         }
3216 }
3217
3218 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3219 {
3220         MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3221         struct efx_nic *efx = channel->efx;
3222         efx_qword_t event;
3223         int rc;
3224
3225         EFX_POPULATE_QWORD_2(event,
3226                              ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3227                              ESF_DZ_EV_DATA, EFX_EF10_TEST);
3228
3229         MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3230
3231         /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3232          * already swapped the data to little-endian order.
3233          */
3234         memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3235                sizeof(efx_qword_t));
3236
3237         rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3238                           NULL, 0, NULL);
3239         if (rc != 0)
3240                 goto fail;
3241
3242         return;
3243
3244 fail:
3245         WARN_ON(true);
3246         netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3247 }
3248
3249 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3250 {
3251         if (atomic_dec_and_test(&efx->active_queues))
3252                 wake_up(&efx->flush_wq);
3253
3254         WARN_ON(atomic_read(&efx->active_queues) < 0);
3255 }
3256
3257 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3258 {
3259         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3260         struct efx_channel *channel;
3261         struct efx_tx_queue *tx_queue;
3262         struct efx_rx_queue *rx_queue;
3263         int pending;
3264
3265         /* If the MC has just rebooted, the TX/RX queues will have already been
3266          * torn down, but efx->active_queues needs to be set to zero.
3267          */
3268         if (nic_data->must_realloc_vis) {
3269                 atomic_set(&efx->active_queues, 0);
3270                 return 0;
3271         }
3272
3273         /* Do not attempt to write to the NIC during EEH recovery */
3274         if (efx->state != STATE_RECOVERY) {
3275                 efx_for_each_channel(channel, efx) {
3276                         efx_for_each_channel_rx_queue(rx_queue, channel)
3277                                 efx_ef10_rx_fini(rx_queue);
3278                         efx_for_each_channel_tx_queue(tx_queue, channel)
3279                                 efx_ef10_tx_fini(tx_queue);
3280                 }
3281
3282                 wait_event_timeout(efx->flush_wq,
3283                                    atomic_read(&efx->active_queues) == 0,
3284                                    msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3285                 pending = atomic_read(&efx->active_queues);
3286                 if (pending) {
3287                         netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3288                                   pending);
3289                         return -ETIMEDOUT;
3290                 }
3291         }
3292
3293         return 0;
3294 }
3295
3296 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3297 {
3298         atomic_set(&efx->active_queues, 0);
3299 }
3300
3301 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3302                                   const struct efx_filter_spec *right)
3303 {
3304         if ((left->match_flags ^ right->match_flags) |
3305             ((left->flags ^ right->flags) &
3306              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3307                 return false;
3308
3309         return memcmp(&left->outer_vid, &right->outer_vid,
3310                       sizeof(struct efx_filter_spec) -
3311                       offsetof(struct efx_filter_spec, outer_vid)) == 0;
3312 }
3313
3314 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3315 {
3316         BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3317         return jhash2((const u32 *)&spec->outer_vid,
3318                       (sizeof(struct efx_filter_spec) -
3319                        offsetof(struct efx_filter_spec, outer_vid)) / 4,
3320                       0);
3321         /* XXX should we randomise the initval? */
3322 }
3323
3324 /* Decide whether a filter should be exclusive or else should allow
3325  * delivery to additional recipients.  Currently we decide that
3326  * filters for specific local unicast MAC and IP addresses are
3327  * exclusive.
3328  */
3329 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3330 {
3331         if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3332             !is_multicast_ether_addr(spec->loc_mac))
3333                 return true;
3334
3335         if ((spec->match_flags &
3336              (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3337             (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3338                 if (spec->ether_type == htons(ETH_P_IP) &&
3339                     !ipv4_is_multicast(spec->loc_host[0]))
3340                         return true;
3341                 if (spec->ether_type == htons(ETH_P_IPV6) &&
3342                     ((const u8 *)spec->loc_host)[0] != 0xff)
3343                         return true;
3344         }
3345
3346         return false;
3347 }
3348
3349 static struct efx_filter_spec *
3350 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3351                            unsigned int filter_idx)
3352 {
3353         return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3354                                           ~EFX_EF10_FILTER_FLAGS);
3355 }
3356
3357 static unsigned int
3358 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3359                            unsigned int filter_idx)
3360 {
3361         return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3362 }
3363
3364 static void
3365 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3366                           unsigned int filter_idx,
3367                           const struct efx_filter_spec *spec,
3368                           unsigned int flags)
3369 {
3370         table->entry[filter_idx].spec = (unsigned long)spec | flags;
3371 }
3372
3373 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3374                                       const struct efx_filter_spec *spec,
3375                                       efx_dword_t *inbuf, u64 handle,
3376                                       bool replacing)
3377 {
3378         struct efx_ef10_nic_data *nic_data = efx->nic_data;
3379         u32 flags = spec->flags;
3380
3381         memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3382
3383         /* Remove RSS flag if we don't have an RSS context. */
3384         if (flags & EFX_FILTER_FLAG_RX_RSS &&
3385             spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3386             nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3387                 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3388
3389         if (replacing) {
3390                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3391                                MC_CMD_FILTER_OP_IN_OP_REPLACE);
3392                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3393         } else {
3394                 u32 match_fields = 0;
3395
3396                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3397                                efx_ef10_filter_is_exclusive(spec) ?
3398                                MC_CMD_FILTER_OP_IN_OP_INSERT :
3399                                MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3400
3401                 /* Convert match flags and values.  Unlike almost
3402                  * everything else in MCDI, these fields are in
3403                  * network byte order.
3404                  */
3405                 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3406                         match_fields |=
3407                                 is_multicast_ether_addr(spec->loc_mac) ?
3408                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3409                                 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3410 #define COPY_FIELD(gen_flag, gen_field, mcdi_field)                          \
3411                 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) {     \
3412                         match_fields |=                                      \
3413                                 1 << MC_CMD_FILTER_OP_IN_MATCH_ ##           \
3414                                 mcdi_field ## _LBN;                          \
3415                         BUILD_BUG_ON(                                        \
3416                                 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3417                                 sizeof(spec->gen_field));                    \
3418                         memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3419                                &spec->gen_field, sizeof(spec->gen_field));   \
3420                 }
3421                 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3422                 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3423                 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3424                 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3425                 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3426                 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3427                 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3428                 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3429                 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3430                 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3431 #undef COPY_FIELD
3432                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3433                                match_fields);
3434         }
3435
3436         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3437         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3438                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3439                        MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3440                        MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3441         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3442         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3443                        MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3444         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3445                        spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3446                        0 : spec->dmaq_id);
3447         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3448                        (flags & EFX_FILTER_FLAG_RX_RSS) ?
3449                        MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3450                        MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3451         if (flags & EFX_FILTER_FLAG_RX_RSS)
3452                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3453                                spec->rss_context !=
3454                                EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3455                                spec->rss_context : nic_data->rx_rss_context);
3456 }
3457
3458 static int efx_ef10_filter_push(struct efx_nic *efx,
3459                                 const struct efx_filter_spec *spec,
3460                                 u64 *handle, bool replacing)
3461 {
3462         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3463         MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3464         int rc;
3465
3466         efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3467         rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3468                           outbuf, sizeof(outbuf), NULL);
3469         if (rc == 0)
3470                 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3471         if (rc == -ENOSPC)
3472                 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3473         return rc;
3474 }
3475
3476 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3477 {
3478         unsigned int match_flags = spec->match_flags;
3479         u32 mcdi_flags = 0;
3480
3481         if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3482                 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3483                 mcdi_flags |=
3484                         is_multicast_ether_addr(spec->loc_mac) ?
3485                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3486                         (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3487         }
3488
3489 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) {                 \
3490                 unsigned int old_match_flags = match_flags;             \
3491                 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag;          \
3492                 if (match_flags != old_match_flags)                     \
3493                         mcdi_flags |=                                   \
3494                                 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ##     \
3495                                  mcdi_field ## _LBN);                   \
3496         }
3497         MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3498         MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3499         MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3500         MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3501         MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3502         MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3503         MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3504         MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3505         MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3506         MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3507 #undef MAP_FILTER_TO_MCDI_FLAG
3508
3509         /* Did we map them all? */
3510         WARN_ON_ONCE(match_flags);
3511
3512         return mcdi_flags;
3513 }
3514
3515 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3516                                const struct efx_filter_spec *spec)
3517 {
3518         u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3519         unsigned int match_pri;
3520
3521         for (match_pri = 0;
3522              match_pri < table->rx_match_count;
3523              match_pri++)
3524                 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3525                         return match_pri;
3526
3527         return -EPROTONOSUPPORT;
3528 }
3529
3530 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3531                                   struct efx_filter_spec *spec,
3532                                   bool replace_equal)
3533 {
3534         struct efx_ef10_filter_table *table = efx->filter_state;
3535         DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3536         struct efx_filter_spec *saved_spec;
3537         unsigned int match_pri, hash;
3538         unsigned int priv_flags;
3539         bool replacing = false;
3540         int ins_index = -1;
3541         DEFINE_WAIT(wait);
3542         bool is_mc_recip;
3543         s32 rc;
3544
3545         /* For now, only support RX filters */
3546         if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3547             EFX_FILTER_FLAG_RX)
3548                 return -EINVAL;
3549
3550         rc = efx_ef10_filter_pri(table, spec);
3551         if (rc < 0)
3552                 return rc;
3553         match_pri = rc;
3554
3555         hash = efx_ef10_filter_hash(spec);
3556         is_mc_recip = efx_filter_is_mc_recipient(spec);
3557         if (is_mc_recip)
3558                 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3559
3560         /* Find any existing filters with the same match tuple or
3561          * else a free slot to insert at.  If any of them are busy,
3562          * we have to wait and retry.
3563          */
3564         for (;;) {
3565                 unsigned int depth = 1;
3566                 unsigned int i;
3567
3568                 spin_lock_bh(&efx->filter_lock);
3569
3570                 for (;;) {
3571                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3572                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3573
3574                         if (!saved_spec) {
3575                                 if (ins_index < 0)
3576                                         ins_index = i;
3577                         } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3578                                 if (table->entry[i].spec &
3579                                     EFX_EF10_FILTER_FLAG_BUSY)
3580                                         break;
3581                                 if (spec->priority < saved_spec->priority &&
3582                                     spec->priority != EFX_FILTER_PRI_AUTO) {
3583                                         rc = -EPERM;
3584                                         goto out_unlock;
3585                                 }
3586                                 if (!is_mc_recip) {
3587                                         /* This is the only one */
3588                                         if (spec->priority ==
3589                                             saved_spec->priority &&
3590                                             !replace_equal) {
3591                                                 rc = -EEXIST;
3592                                                 goto out_unlock;
3593                                         }
3594                                         ins_index = i;
3595                                         goto found;
3596                                 } else if (spec->priority >
3597                                            saved_spec->priority ||
3598                                            (spec->priority ==
3599                                             saved_spec->priority &&
3600                                             replace_equal)) {
3601                                         if (ins_index < 0)
3602                                                 ins_index = i;
3603                                         else
3604                                                 __set_bit(depth, mc_rem_map);
3605                                 }
3606                         }
3607
3608                         /* Once we reach the maximum search depth, use
3609                          * the first suitable slot or return -EBUSY if
3610                          * there was none
3611                          */
3612                         if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3613                                 if (ins_index < 0) {
3614                                         rc = -EBUSY;
3615                                         goto out_unlock;
3616                                 }
3617                                 goto found;
3618                         }
3619
3620                         ++depth;
3621                 }
3622
3623                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3624                 spin_unlock_bh(&efx->filter_lock);
3625                 schedule();
3626         }
3627
3628 found:
3629         /* Create a software table entry if necessary, and mark it
3630          * busy.  We might yet fail to insert, but any attempt to
3631          * insert a conflicting filter while we're waiting for the
3632          * firmware must find the busy entry.
3633          */
3634         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3635         if (saved_spec) {
3636                 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3637                     saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3638                         /* Just make sure it won't be removed */
3639                         if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3640                                 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3641                         table->entry[ins_index].spec &=
3642                                 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3643                         rc = ins_index;
3644                         goto out_unlock;
3645                 }
3646                 replacing = true;
3647                 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3648         } else {
3649                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3650                 if (!saved_spec) {
3651                         rc = -ENOMEM;
3652                         goto out_unlock;
3653                 }
3654                 *saved_spec = *spec;
3655                 priv_flags = 0;
3656         }
3657         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3658                                   priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3659
3660         /* Mark lower-priority multicast recipients busy prior to removal */
3661         if (is_mc_recip) {
3662                 unsigned int depth, i;
3663
3664                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3665                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3666                         if (test_bit(depth, mc_rem_map))
3667                                 table->entry[i].spec |=
3668                                         EFX_EF10_FILTER_FLAG_BUSY;
3669                 }
3670         }
3671
3672         spin_unlock_bh(&efx->filter_lock);
3673
3674         rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3675                                   replacing);
3676
3677         /* Finalise the software table entry */
3678         spin_lock_bh(&efx->filter_lock);
3679         if (rc == 0) {
3680                 if (replacing) {
3681                         /* Update the fields that may differ */
3682                         if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3683                                 saved_spec->flags |=
3684                                         EFX_FILTER_FLAG_RX_OVER_AUTO;
3685                         saved_spec->priority = spec->priority;
3686                         saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3687                         saved_spec->flags |= spec->flags;
3688                         saved_spec->rss_context = spec->rss_context;
3689                         saved_spec->dmaq_id = spec->dmaq_id;
3690                 }
3691         } else if (!replacing) {
3692                 kfree(saved_spec);
3693                 saved_spec = NULL;
3694         }
3695         efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3696
3697         /* Remove and finalise entries for lower-priority multicast
3698          * recipients
3699          */
3700         if (is_mc_recip) {
3701                 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3702                 unsigned int depth, i;
3703
3704                 memset(inbuf, 0, sizeof(inbuf));
3705
3706                 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3707                         if (!test_bit(depth, mc_rem_map))
3708                                 continue;
3709
3710                         i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3711                         saved_spec = efx_ef10_filter_entry_spec(table, i);
3712                         priv_flags = efx_ef10_filter_entry_flags(table, i);
3713
3714                         if (rc == 0) {
3715                                 spin_unlock_bh(&efx->filter_lock);
3716                                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3717                                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3718                                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3719                                                table->entry[i].handle);
3720                                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3721                                                   inbuf, sizeof(inbuf),
3722                                                   NULL, 0, NULL);
3723                                 spin_lock_bh(&efx->filter_lock);
3724                         }
3725
3726                         if (rc == 0) {
3727                                 kfree(saved_spec);
3728                                 saved_spec = NULL;
3729                                 priv_flags = 0;
3730                         } else {
3731                                 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3732                         }
3733                         efx_ef10_filter_set_entry(table, i, saved_spec,
3734                                                   priv_flags);
3735                 }
3736         }
3737
3738         /* If successful, return the inserted filter ID */
3739         if (rc == 0)
3740                 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3741
3742         wake_up_all(&table->waitq);
3743 out_unlock:
3744         spin_unlock_bh(&efx->filter_lock);
3745         finish_wait(&table->waitq, &wait);
3746         return rc;
3747 }
3748
3749 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3750 {
3751         /* no need to do anything here on EF10 */
3752 }
3753
3754 /* Remove a filter.
3755  * If !by_index, remove by ID
3756  * If by_index, remove by index
3757  * Filter ID may come from userland and must be range-checked.
3758  */
3759 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3760                                            unsigned int priority_mask,
3761                                            u32 filter_id, bool by_index)
3762 {
3763         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3764         struct efx_ef10_filter_table *table = efx->filter_state;
3765         MCDI_DECLARE_BUF(inbuf,
3766                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3767                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3768         struct efx_filter_spec *spec;
3769         DEFINE_WAIT(wait);
3770         int rc;
3771
3772         /* Find the software table entry and mark it busy.  Don't
3773          * remove it yet; any attempt to update while we're waiting
3774          * for the firmware must find the busy entry.
3775          */
3776         for (;;) {
3777                 spin_lock_bh(&efx->filter_lock);
3778                 if (!(table->entry[filter_idx].spec &
3779                       EFX_EF10_FILTER_FLAG_BUSY))
3780                         break;
3781                 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3782                 spin_unlock_bh(&efx->filter_lock);
3783                 schedule();
3784         }
3785
3786         spec = efx_ef10_filter_entry_spec(table, filter_idx);
3787         if (!spec ||
3788             (!by_index &&
3789              efx_ef10_filter_pri(table, spec) !=
3790              filter_id / HUNT_FILTER_TBL_ROWS)) {
3791                 rc = -ENOENT;
3792                 goto out_unlock;
3793         }
3794
3795         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3796             priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3797                 /* Just remove flags */
3798                 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3799                 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3800                 rc = 0;
3801                 goto out_unlock;
3802         }
3803
3804         if (!(priority_mask & (1U << spec->priority))) {
3805                 rc = -ENOENT;
3806                 goto out_unlock;
3807         }
3808
3809         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3810         spin_unlock_bh(&efx->filter_lock);
3811
3812         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3813                 /* Reset to an automatic filter */
3814
3815                 struct efx_filter_spec new_spec = *spec;
3816
3817                 new_spec.priority = EFX_FILTER_PRI_AUTO;
3818                 new_spec.flags = (EFX_FILTER_FLAG_RX |
3819                                   (efx_rss_enabled(efx) ?
3820                                    EFX_FILTER_FLAG_RX_RSS : 0));
3821                 new_spec.dmaq_id = 0;
3822                 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3823                 rc = efx_ef10_filter_push(efx, &new_spec,
3824                                           &table->entry[filter_idx].handle,
3825                                           true);
3826
3827                 spin_lock_bh(&efx->filter_lock);
3828                 if (rc == 0)
3829                         *spec = new_spec;
3830         } else {
3831                 /* Really remove the filter */
3832
3833                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3834                                efx_ef10_filter_is_exclusive(spec) ?
3835                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
3836                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3837                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3838                                table->entry[filter_idx].handle);
3839                 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3840                                   inbuf, sizeof(inbuf), NULL, 0, NULL);
3841
3842                 spin_lock_bh(&efx->filter_lock);
3843                 if (rc == 0) {
3844                         kfree(spec);
3845                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3846                 }
3847         }
3848
3849         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3850         wake_up_all(&table->waitq);
3851 out_unlock:
3852         spin_unlock_bh(&efx->filter_lock);
3853         finish_wait(&table->waitq, &wait);
3854         return rc;
3855 }
3856
3857 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3858                                        enum efx_filter_priority priority,
3859                                        u32 filter_id)
3860 {
3861         return efx_ef10_filter_remove_internal(efx, 1U << priority,
3862                                                filter_id, false);
3863 }
3864
3865 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3866 {
3867         return filter_id % HUNT_FILTER_TBL_ROWS;
3868 }
3869
3870 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3871                                           enum efx_filter_priority priority,
3872                                           u32 filter_id)
3873 {
3874         if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3875                 return;
3876         efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
3877 }
3878
3879 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3880                                     enum efx_filter_priority priority,
3881                                     u32 filter_id, struct efx_filter_spec *spec)
3882 {
3883         unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3884         struct efx_ef10_filter_table *table = efx->filter_state;
3885         const struct efx_filter_spec *saved_spec;
3886         int rc;
3887
3888         spin_lock_bh(&efx->filter_lock);
3889         saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3890         if (saved_spec && saved_spec->priority == priority &&
3891             efx_ef10_filter_pri(table, saved_spec) ==
3892             filter_id / HUNT_FILTER_TBL_ROWS) {
3893                 *spec = *saved_spec;
3894                 rc = 0;
3895         } else {
3896                 rc = -ENOENT;
3897         }
3898         spin_unlock_bh(&efx->filter_lock);
3899         return rc;
3900 }
3901
3902 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3903                                      enum efx_filter_priority priority)
3904 {
3905         unsigned int priority_mask;
3906         unsigned int i;
3907         int rc;
3908
3909         priority_mask = (((1U << (priority + 1)) - 1) &
3910                          ~(1U << EFX_FILTER_PRI_AUTO));
3911
3912         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3913                 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3914                                                      i, true);
3915                 if (rc && rc != -ENOENT)
3916                         return rc;
3917         }
3918
3919         return 0;
3920 }
3921
3922 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3923                                          enum efx_filter_priority priority)
3924 {
3925         struct efx_ef10_filter_table *table = efx->filter_state;
3926         unsigned int filter_idx;
3927         s32 count = 0;
3928
3929         spin_lock_bh(&efx->filter_lock);
3930         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3931                 if (table->entry[filter_idx].spec &&
3932                     efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3933                     priority)
3934                         ++count;
3935         }
3936         spin_unlock_bh(&efx->filter_lock);
3937         return count;
3938 }
3939
3940 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3941 {
3942         struct efx_ef10_filter_table *table = efx->filter_state;
3943
3944         return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3945 }
3946
3947 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3948                                       enum efx_filter_priority priority,
3949                                       u32 *buf, u32 size)
3950 {
3951         struct efx_ef10_filter_table *table = efx->filter_state;
3952         struct efx_filter_spec *spec;
3953         unsigned int filter_idx;
3954         s32 count = 0;
3955
3956         spin_lock_bh(&efx->filter_lock);
3957         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3958                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3959                 if (spec && spec->priority == priority) {
3960                         if (count == size) {
3961                                 count = -EMSGSIZE;
3962                                 break;
3963                         }
3964                         buf[count++] = (efx_ef10_filter_pri(table, spec) *
3965                                         HUNT_FILTER_TBL_ROWS +
3966                                         filter_idx);
3967                 }
3968         }
3969         spin_unlock_bh(&efx->filter_lock);
3970         return count;
3971 }
3972
3973 #ifdef CONFIG_RFS_ACCEL
3974
3975 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3976
3977 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3978                                       struct efx_filter_spec *spec)
3979 {
3980         struct efx_ef10_filter_table *table = efx->filter_state;
3981         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3982         struct efx_filter_spec *saved_spec;
3983         unsigned int hash, i, depth = 1;
3984         bool replacing = false;
3985         int ins_index = -1;
3986         u64 cookie;
3987         s32 rc;
3988
3989         /* Must be an RX filter without RSS and not for a multicast
3990          * destination address (RFS only works for connected sockets).
3991          * These restrictions allow us to pass only a tiny amount of
3992          * data through to the completion function.
3993          */
3994         EFX_WARN_ON_PARANOID(spec->flags !=
3995                              (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3996         EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3997         EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3998
3999         hash = efx_ef10_filter_hash(spec);
4000
4001         spin_lock_bh(&efx->filter_lock);
4002
4003         /* Find any existing filter with the same match tuple or else
4004          * a free slot to insert at.  If an existing filter is busy,
4005          * we have to give up.
4006          */
4007         for (;;) {
4008                 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
4009                 saved_spec = efx_ef10_filter_entry_spec(table, i);
4010
4011                 if (!saved_spec) {
4012                         if (ins_index < 0)
4013                                 ins_index = i;
4014                 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
4015                         if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
4016                                 rc = -EBUSY;
4017                                 goto fail_unlock;
4018                         }
4019                         if (spec->priority < saved_spec->priority) {
4020                                 rc = -EPERM;
4021                                 goto fail_unlock;
4022                         }
4023                         ins_index = i;
4024                         break;
4025                 }
4026
4027                 /* Once we reach the maximum search depth, use the
4028                  * first suitable slot or return -EBUSY if there was
4029                  * none
4030                  */
4031                 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
4032                         if (ins_index < 0) {
4033                                 rc = -EBUSY;
4034                                 goto fail_unlock;
4035                         }
4036                         break;
4037                 }
4038
4039                 ++depth;
4040         }
4041
4042         /* Create a software table entry if necessary, and mark it
4043          * busy.  We might yet fail to insert, but any attempt to
4044          * insert a conflicting filter while we're waiting for the
4045          * firmware must find the busy entry.
4046          */
4047         saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
4048         if (saved_spec) {
4049                 replacing = true;
4050         } else {
4051                 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
4052                 if (!saved_spec) {
4053                         rc = -ENOMEM;
4054                         goto fail_unlock;
4055                 }
4056                 *saved_spec = *spec;
4057         }
4058         efx_ef10_filter_set_entry(table, ins_index, saved_spec,
4059                                   EFX_EF10_FILTER_FLAG_BUSY);
4060
4061         spin_unlock_bh(&efx->filter_lock);
4062
4063         /* Pack up the variables needed on completion */
4064         cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
4065
4066         efx_ef10_filter_push_prep(efx, spec, inbuf,
4067                                   table->entry[ins_index].handle, replacing);
4068         efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
4069                            MC_CMD_FILTER_OP_OUT_LEN,
4070                            efx_ef10_filter_rfs_insert_complete, cookie);
4071
4072         return ins_index;
4073
4074 fail_unlock:
4075         spin_unlock_bh(&efx->filter_lock);
4076         return rc;
4077 }
4078
4079 static void
4080 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
4081                                     int rc, efx_dword_t *outbuf,
4082                                     size_t outlen_actual)
4083 {
4084         struct efx_ef10_filter_table *table = efx->filter_state;
4085         unsigned int ins_index, dmaq_id;
4086         struct efx_filter_spec *spec;
4087         bool replacing;
4088
4089         /* Unpack the cookie */
4090         replacing = cookie >> 31;
4091         ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
4092         dmaq_id = cookie & 0xffff;
4093
4094         spin_lock_bh(&efx->filter_lock);
4095         spec = efx_ef10_filter_entry_spec(table, ins_index);
4096         if (rc == 0) {
4097                 table->entry[ins_index].handle =
4098                         MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
4099                 if (replacing)
4100                         spec->dmaq_id = dmaq_id;
4101         } else if (!replacing) {
4102                 kfree(spec);
4103                 spec = NULL;
4104         }
4105         efx_ef10_filter_set_entry(table, ins_index, spec, 0);
4106         spin_unlock_bh(&efx->filter_lock);
4107
4108         wake_up_all(&table->waitq);
4109 }
4110
4111 static void
4112 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4113                                     unsigned long filter_idx,
4114                                     int rc, efx_dword_t *outbuf,
4115                                     size_t outlen_actual);
4116
4117 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
4118                                            unsigned int filter_idx)
4119 {
4120         struct efx_ef10_filter_table *table = efx->filter_state;
4121         struct efx_filter_spec *spec =
4122                 efx_ef10_filter_entry_spec(table, filter_idx);
4123         MCDI_DECLARE_BUF(inbuf,
4124                          MC_CMD_FILTER_OP_IN_HANDLE_OFST +
4125                          MC_CMD_FILTER_OP_IN_HANDLE_LEN);
4126
4127         if (!spec ||
4128             (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
4129             spec->priority != EFX_FILTER_PRI_HINT ||
4130             !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
4131                                  flow_id, filter_idx))
4132                 return false;
4133
4134         MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4135                        MC_CMD_FILTER_OP_IN_OP_REMOVE);
4136         MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4137                        table->entry[filter_idx].handle);
4138         if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
4139                                efx_ef10_filter_rfs_expire_complete, filter_idx))
4140                 return false;
4141
4142         table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4143         return true;
4144 }
4145
4146 static void
4147 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
4148                                     unsigned long filter_idx,
4149                                     int rc, efx_dword_t *outbuf,
4150                                     size_t outlen_actual)
4151 {
4152         struct efx_ef10_filter_table *table = efx->filter_state;
4153         struct efx_filter_spec *spec =
4154                 efx_ef10_filter_entry_spec(table, filter_idx);
4155
4156         spin_lock_bh(&efx->filter_lock);
4157         if (rc == 0) {
4158                 kfree(spec);
4159                 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4160         }
4161         table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
4162         wake_up_all(&table->waitq);
4163         spin_unlock_bh(&efx->filter_lock);
4164 }
4165
4166 #endif /* CONFIG_RFS_ACCEL */
4167
4168 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
4169 {
4170         int match_flags = 0;
4171
4172 #define MAP_FLAG(gen_flag, mcdi_field) {                                \
4173                 u32 old_mcdi_flags = mcdi_flags;                        \
4174                 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ##      \
4175                                 mcdi_field ## _LBN);                    \
4176                 if (mcdi_flags != old_mcdi_flags)                       \
4177                         match_flags |= EFX_FILTER_MATCH_ ## gen_flag;   \
4178         }
4179         MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
4180         MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
4181         MAP_FLAG(REM_HOST, SRC_IP);
4182         MAP_FLAG(LOC_HOST, DST_IP);
4183         MAP_FLAG(REM_MAC, SRC_MAC);
4184         MAP_FLAG(REM_PORT, SRC_PORT);
4185         MAP_FLAG(LOC_MAC, DST_MAC);
4186         MAP_FLAG(LOC_PORT, DST_PORT);
4187         MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
4188         MAP_FLAG(INNER_VID, INNER_VLAN);
4189         MAP_FLAG(OUTER_VID, OUTER_VLAN);
4190         MAP_FLAG(IP_PROTO, IP_PROTO);
4191 #undef MAP_FLAG
4192
4193         /* Did we map them all? */
4194         if (mcdi_flags)
4195                 return -EINVAL;
4196
4197         return match_flags;
4198 }
4199
4200 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
4201 {
4202         struct efx_ef10_filter_table *table = efx->filter_state;
4203         struct efx_ef10_filter_vlan *vlan, *next_vlan;
4204
4205         /* See comment in efx_ef10_filter_table_remove() */
4206         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4207                 return;
4208
4209         if (!table)
4210                 return;
4211
4212         list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
4213                 efx_ef10_filter_del_vlan_internal(efx, vlan);
4214 }
4215
4216 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
4217                                             enum efx_filter_match_flags match_flags)
4218 {
4219         unsigned int match_pri;
4220         int mf;
4221
4222         for (match_pri = 0;
4223              match_pri < table->rx_match_count;
4224              match_pri++) {
4225                 mf = efx_ef10_filter_match_flags_from_mcdi(
4226                                 table->rx_match_mcdi_flags[match_pri]);
4227                 if (mf == match_flags)
4228                         return true;
4229         }
4230
4231         return false;
4232 }
4233
4234 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4235 {
4236         MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4237         MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4238         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4239         struct net_device *net_dev = efx->net_dev;
4240         unsigned int pd_match_pri, pd_match_count;
4241         struct efx_ef10_filter_table *table;
4242         struct efx_ef10_vlan *vlan;
4243         size_t outlen;
4244         int rc;
4245
4246         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4247                 return -EINVAL;
4248
4249         if (efx->filter_state) /* already probed */
4250                 return 0;
4251
4252         table = kzalloc(sizeof(*table), GFP_KERNEL);
4253         if (!table)
4254                 return -ENOMEM;
4255
4256         /* Find out which RX filter types are supported, and their priorities */
4257         MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4258                        MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4259         rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4260                           inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4261                           &outlen);
4262         if (rc)
4263                 goto fail;
4264         pd_match_count = MCDI_VAR_ARRAY_LEN(
4265                 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4266         table->rx_match_count = 0;
4267
4268         for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4269                 u32 mcdi_flags =
4270                         MCDI_ARRAY_DWORD(
4271                                 outbuf,
4272                                 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4273                                 pd_match_pri);
4274                 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4275                 if (rc < 0) {
4276                         netif_dbg(efx, probe, efx->net_dev,
4277                                   "%s: fw flags %#x pri %u not supported in driver\n",
4278                                   __func__, mcdi_flags, pd_match_pri);
4279                 } else {
4280                         netif_dbg(efx, probe, efx->net_dev,
4281                                   "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4282                                   __func__, mcdi_flags, pd_match_pri,
4283                                   rc, table->rx_match_count);
4284                         table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4285                         table->rx_match_count++;
4286                 }
4287         }
4288
4289         if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4290             !(efx_ef10_filter_match_supported(table,
4291                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4292               efx_ef10_filter_match_supported(table,
4293                 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4294                 netif_info(efx, probe, net_dev,
4295                            "VLAN filters are not supported in this firmware variant\n");
4296                 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4297                 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4298                 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4299         }
4300
4301         table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4302         if (!table->entry) {
4303                 rc = -ENOMEM;
4304                 goto fail;
4305         }
4306
4307         table->mc_promisc_last = false;
4308         table->vlan_filter =
4309                 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4310         INIT_LIST_HEAD(&table->vlan_list);
4311
4312         efx->filter_state = table;
4313         init_waitqueue_head(&table->waitq);
4314
4315         list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4316                 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4317                 if (rc)
4318                         goto fail_add_vlan;
4319         }
4320
4321         return 0;
4322
4323 fail_add_vlan:
4324         efx_ef10_filter_cleanup_vlans(efx);
4325         efx->filter_state = NULL;
4326 fail:
4327         kfree(table);
4328         return rc;
4329 }
4330
4331 /* Caller must hold efx->filter_sem for read if race against
4332  * efx_ef10_filter_table_remove() is possible
4333  */
4334 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4335 {
4336         struct efx_ef10_filter_table *table = efx->filter_state;
4337         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4338         struct efx_filter_spec *spec;
4339         unsigned int filter_idx;
4340         bool failed = false;
4341         int rc;
4342
4343         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4344
4345         if (!nic_data->must_restore_filters)
4346                 return;
4347
4348         if (!table)
4349                 return;
4350
4351         spin_lock_bh(&efx->filter_lock);
4352
4353         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4354                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4355                 if (!spec)
4356                         continue;
4357
4358                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4359                 spin_unlock_bh(&efx->filter_lock);
4360
4361                 rc = efx_ef10_filter_push(efx, spec,
4362                                           &table->entry[filter_idx].handle,
4363                                           false);
4364                 if (rc)
4365                         failed = true;
4366
4367                 spin_lock_bh(&efx->filter_lock);
4368                 if (rc) {
4369                         kfree(spec);
4370                         efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4371                 } else {
4372                         table->entry[filter_idx].spec &=
4373                                 ~EFX_EF10_FILTER_FLAG_BUSY;
4374                 }
4375         }
4376
4377         spin_unlock_bh(&efx->filter_lock);
4378
4379         if (failed)
4380                 netif_err(efx, hw, efx->net_dev,
4381                           "unable to restore all filters\n");
4382         else
4383                 nic_data->must_restore_filters = false;
4384 }
4385
4386 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4387 {
4388         struct efx_ef10_filter_table *table = efx->filter_state;
4389         MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4390         struct efx_filter_spec *spec;
4391         unsigned int filter_idx;
4392         int rc;
4393
4394         efx_ef10_filter_cleanup_vlans(efx);
4395         efx->filter_state = NULL;
4396         /* If we were called without locking, then it's not safe to free
4397          * the table as others might be using it.  So we just WARN, leak
4398          * the memory, and potentially get an inconsistent filter table
4399          * state.
4400          * This should never actually happen.
4401          */
4402         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4403                 return;
4404
4405         if (!table)
4406                 return;
4407
4408         for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4409                 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4410                 if (!spec)
4411                         continue;
4412
4413                 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4414                                efx_ef10_filter_is_exclusive(spec) ?
4415                                MC_CMD_FILTER_OP_IN_OP_REMOVE :
4416                                MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4417                 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4418                                table->entry[filter_idx].handle);
4419                 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4420                                         sizeof(inbuf), NULL, 0, NULL);
4421                 if (rc)
4422                         netif_info(efx, drv, efx->net_dev,
4423                                    "%s: filter %04x remove failed\n",
4424                                    __func__, filter_idx);
4425                 kfree(spec);
4426         }
4427
4428         vfree(table->entry);
4429         kfree(table);
4430 }
4431
4432 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4433 {
4434         struct efx_ef10_filter_table *table = efx->filter_state;
4435         unsigned int filter_idx;
4436
4437         if (*id != EFX_EF10_FILTER_ID_INVALID) {
4438                 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4439                 if (!table->entry[filter_idx].spec)
4440                         netif_dbg(efx, drv, efx->net_dev,
4441                                   "marked null spec old %04x:%04x\n", *id,
4442                                   filter_idx);
4443                 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4444                 *id = EFX_EF10_FILTER_ID_INVALID;
4445         }
4446 }
4447
4448 /* Mark old per-VLAN filters that may need to be removed */
4449 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4450                                            struct efx_ef10_filter_vlan *vlan)
4451 {
4452         struct efx_ef10_filter_table *table = efx->filter_state;
4453         unsigned int i;
4454
4455         for (i = 0; i < table->dev_uc_count; i++)
4456                 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4457         for (i = 0; i < table->dev_mc_count; i++)
4458                 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4459         efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4460         efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4461         efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4462 }
4463
4464 /* Mark old filters that may need to be removed.
4465  * Caller must hold efx->filter_sem for read if race against
4466  * efx_ef10_filter_table_remove() is possible
4467  */
4468 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4469 {
4470         struct efx_ef10_filter_table *table = efx->filter_state;
4471         struct efx_ef10_filter_vlan *vlan;
4472
4473         spin_lock_bh(&efx->filter_lock);
4474         list_for_each_entry(vlan, &table->vlan_list, list)
4475                 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4476         spin_unlock_bh(&efx->filter_lock);
4477 }
4478
4479 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4480 {
4481         struct efx_ef10_filter_table *table = efx->filter_state;
4482         struct net_device *net_dev = efx->net_dev;
4483         struct netdev_hw_addr *uc;
4484         int addr_count;
4485         unsigned int i;
4486
4487         addr_count = netdev_uc_count(net_dev);
4488         table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4489         table->dev_uc_count = 1 + addr_count;
4490         ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4491         i = 1;
4492         netdev_for_each_uc_addr(uc, net_dev) {
4493                 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4494                         table->uc_promisc = true;
4495                         break;
4496                 }
4497                 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4498                 i++;
4499         }
4500 }
4501
4502 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4503 {
4504         struct efx_ef10_filter_table *table = efx->filter_state;
4505         struct net_device *net_dev = efx->net_dev;
4506         struct netdev_hw_addr *mc;
4507         unsigned int i, addr_count;
4508
4509         table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4510
4511         addr_count = netdev_mc_count(net_dev);
4512         i = 0;
4513         netdev_for_each_mc_addr(mc, net_dev) {
4514                 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4515                         table->mc_promisc = true;
4516                         break;
4517                 }
4518                 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4519                 i++;
4520         }
4521
4522         table->dev_mc_count = i;
4523 }
4524
4525 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4526                                             struct efx_ef10_filter_vlan *vlan,
4527                                             bool multicast, bool rollback)
4528 {
4529         struct efx_ef10_filter_table *table = efx->filter_state;
4530         struct efx_ef10_dev_addr *addr_list;
4531         enum efx_filter_flags filter_flags;
4532         struct efx_filter_spec spec;
4533         u8 baddr[ETH_ALEN];
4534         unsigned int i, j;
4535         int addr_count;
4536         u16 *ids;
4537         int rc;
4538
4539         if (multicast) {
4540                 addr_list = table->dev_mc_list;
4541                 addr_count = table->dev_mc_count;
4542                 ids = vlan->mc;
4543         } else {
4544                 addr_list = table->dev_uc_list;
4545                 addr_count = table->dev_uc_count;
4546                 ids = vlan->uc;
4547         }
4548
4549         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4550
4551         /* Insert/renew filters */
4552         for (i = 0; i < addr_count; i++) {
4553                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4554                 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4555                 rc = efx_ef10_filter_insert(efx, &spec, true);
4556                 if (rc < 0) {
4557                         if (rollback) {
4558                                 netif_info(efx, drv, efx->net_dev,
4559                                            "efx_ef10_filter_insert failed rc=%d\n",
4560                                            rc);
4561                                 /* Fall back to promiscuous */
4562                                 for (j = 0; j < i; j++) {
4563                                         efx_ef10_filter_remove_unsafe(
4564                                                 efx, EFX_FILTER_PRI_AUTO,
4565                                                 ids[j]);
4566                                         ids[j] = EFX_EF10_FILTER_ID_INVALID;
4567                                 }
4568                                 return rc;
4569                         } else {
4570                                 /* mark as not inserted, and carry on */
4571                                 rc = EFX_EF10_FILTER_ID_INVALID;
4572                         }
4573                 }
4574                 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4575         }
4576
4577         if (multicast && rollback) {
4578                 /* Also need an Ethernet broadcast filter */
4579                 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4580                 eth_broadcast_addr(baddr);
4581                 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4582                 rc = efx_ef10_filter_insert(efx, &spec, true);
4583                 if (rc < 0) {
4584                         netif_warn(efx, drv, efx->net_dev,
4585                                    "Broadcast filter insert failed rc=%d\n", rc);
4586                         /* Fall back to promiscuous */
4587                         for (j = 0; j < i; j++) {
4588                                 efx_ef10_filter_remove_unsafe(
4589                                         efx, EFX_FILTER_PRI_AUTO,
4590                                         ids[j]);
4591                                 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4592                         }
4593                         return rc;
4594                 } else {
4595                         EFX_WARN_ON_PARANOID(vlan->bcast !=
4596                                              EFX_EF10_FILTER_ID_INVALID);
4597                         vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4598                 }
4599         }
4600
4601         return 0;
4602 }
4603
4604 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4605                                       struct efx_ef10_filter_vlan *vlan,
4606                                       bool multicast, bool rollback)
4607 {
4608         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4609         enum efx_filter_flags filter_flags;
4610         struct efx_filter_spec spec;
4611         u8 baddr[ETH_ALEN];
4612         int rc;
4613
4614         filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4615
4616         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4617
4618         if (multicast)
4619                 efx_filter_set_mc_def(&spec);
4620         else
4621                 efx_filter_set_uc_def(&spec);
4622
4623         if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4624                 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4625
4626         rc = efx_ef10_filter_insert(efx, &spec, true);
4627         if (rc < 0) {
4628                 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4629                              efx->net_dev,
4630                              "%scast mismatch filter insert failed rc=%d\n",
4631                              multicast ? "Multi" : "Uni", rc);
4632         } else if (multicast) {
4633                 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4634                 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4635                 if (!nic_data->workaround_26807) {
4636                         /* Also need an Ethernet broadcast filter */
4637                         efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4638                                            filter_flags, 0);
4639                         eth_broadcast_addr(baddr);
4640                         efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4641                         rc = efx_ef10_filter_insert(efx, &spec, true);
4642                         if (rc < 0) {
4643                                 netif_warn(efx, drv, efx->net_dev,
4644                                            "Broadcast filter insert failed rc=%d\n",
4645                                            rc);
4646                                 if (rollback) {
4647                                         /* Roll back the mc_def filter */
4648                                         efx_ef10_filter_remove_unsafe(
4649                                                         efx, EFX_FILTER_PRI_AUTO,
4650                                                         vlan->mcdef);
4651                                         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4652                                         return rc;
4653                                 }
4654                         } else {
4655                                 EFX_WARN_ON_PARANOID(vlan->bcast !=
4656                                                      EFX_EF10_FILTER_ID_INVALID);
4657                                 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4658                         }
4659                 }
4660                 rc = 0;
4661         } else {
4662                 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4663                 vlan->ucdef = rc;
4664                 rc = 0;
4665         }
4666         return rc;
4667 }
4668
4669 /* Remove filters that weren't renewed.  Since nothing else changes the AUTO_OLD
4670  * flag or removes these filters, we don't need to hold the filter_lock while
4671  * scanning for these filters.
4672  */
4673 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4674 {
4675         struct efx_ef10_filter_table *table = efx->filter_state;
4676         int remove_failed = 0;
4677         int remove_noent = 0;
4678         int rc;
4679         int i;
4680
4681         for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4682                 if (ACCESS_ONCE(table->entry[i].spec) &
4683                     EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4684                         rc = efx_ef10_filter_remove_internal(efx,
4685                                         1U << EFX_FILTER_PRI_AUTO, i, true);
4686                         if (rc == -ENOENT)
4687                                 remove_noent++;
4688                         else if (rc)
4689                                 remove_failed++;
4690                 }
4691         }
4692
4693         if (remove_failed)
4694                 netif_info(efx, drv, efx->net_dev,
4695                            "%s: failed to remove %d filters\n",
4696                            __func__, remove_failed);
4697         if (remove_noent)
4698                 netif_info(efx, drv, efx->net_dev,
4699                            "%s: failed to remove %d non-existent filters\n",
4700                            __func__, remove_noent);
4701 }
4702
4703 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4704 {
4705         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4706         u8 mac_old[ETH_ALEN];
4707         int rc, rc2;
4708
4709         /* Only reconfigure a PF-created vport */
4710         if (is_zero_ether_addr(nic_data->vport_mac))
4711                 return 0;
4712
4713         efx_device_detach_sync(efx);
4714         efx_net_stop(efx->net_dev);
4715         down_write(&efx->filter_sem);
4716         efx_ef10_filter_table_remove(efx);
4717         up_write(&efx->filter_sem);
4718
4719         rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4720         if (rc)
4721                 goto restore_filters;
4722
4723         ether_addr_copy(mac_old, nic_data->vport_mac);
4724         rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4725                                     nic_data->vport_mac);
4726         if (rc)
4727                 goto restore_vadaptor;
4728
4729         rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4730                                     efx->net_dev->dev_addr);
4731         if (!rc) {
4732                 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4733         } else {
4734                 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4735                 if (rc2) {
4736                         /* Failed to add original MAC, so clear vport_mac */
4737                         eth_zero_addr(nic_data->vport_mac);
4738                         goto reset_nic;
4739                 }
4740         }
4741
4742 restore_vadaptor:
4743         rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4744         if (rc2)
4745                 goto reset_nic;
4746 restore_filters:
4747         down_write(&efx->filter_sem);
4748         rc2 = efx_ef10_filter_table_probe(efx);
4749         up_write(&efx->filter_sem);
4750         if (rc2)
4751                 goto reset_nic;
4752
4753         rc2 = efx_net_open(efx->net_dev);
4754         if (rc2)
4755                 goto reset_nic;
4756
4757         netif_device_attach(efx->net_dev);
4758
4759         return rc;
4760
4761 reset_nic:
4762         netif_err(efx, drv, efx->net_dev,
4763                   "Failed to restore when changing MAC address - scheduling reset\n");
4764         efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4765
4766         return rc ? rc : rc2;
4767 }
4768
4769 /* Caller must hold efx->filter_sem for read if race against
4770  * efx_ef10_filter_table_remove() is possible
4771  */
4772 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4773                                               struct efx_ef10_filter_vlan *vlan)
4774 {
4775         struct efx_ef10_filter_table *table = efx->filter_state;
4776         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4777
4778         /* Do not install unspecified VID if VLAN filtering is enabled.
4779          * Do not install all specified VIDs if VLAN filtering is disabled.
4780          */
4781         if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4782                 return;
4783
4784         /* Insert/renew unicast filters */
4785         if (table->uc_promisc) {
4786                 efx_ef10_filter_insert_def(efx, vlan, false, false);
4787                 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4788         } else {
4789                 /* If any of the filters failed to insert, fall back to
4790                  * promiscuous mode - add in the uc_def filter.  But keep
4791                  * our individual unicast filters.
4792                  */
4793                 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4794                         efx_ef10_filter_insert_def(efx, vlan, false, false);
4795         }
4796
4797         /* Insert/renew multicast filters */
4798         /* If changing promiscuous state with cascaded multicast filters, remove
4799          * old filters first, so that packets are dropped rather than duplicated
4800          */
4801         if (nic_data->workaround_26807 &&
4802             table->mc_promisc_last != table->mc_promisc)
4803                 efx_ef10_filter_remove_old(efx);
4804         if (table->mc_promisc) {
4805                 if (nic_data->workaround_26807) {
4806                         /* If we failed to insert promiscuous filters, rollback
4807                          * and fall back to individual multicast filters
4808                          */
4809                         if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4810                                 /* Changing promisc state, so remove old filters */
4811                                 efx_ef10_filter_remove_old(efx);
4812                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4813                                                                  true, false);
4814                         }
4815                 } else {
4816                         /* If we failed to insert promiscuous filters, don't
4817                          * rollback.  Regardless, also insert the mc_list
4818                          */
4819                         efx_ef10_filter_insert_def(efx, vlan, true, false);
4820                         efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4821                 }
4822         } else {
4823                 /* If any filters failed to insert, rollback and fall back to
4824                  * promiscuous mode - mc_def filter and maybe broadcast.  If
4825                  * that fails, roll back again and insert as many of our
4826                  * individual multicast filters as we can.
4827                  */
4828                 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4829                         /* Changing promisc state, so remove old filters */
4830                         if (nic_data->workaround_26807)
4831                                 efx_ef10_filter_remove_old(efx);
4832                         if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4833                                 efx_ef10_filter_insert_addr_list(efx, vlan,
4834                                                                  true, false);
4835                 }
4836         }
4837 }
4838
4839 /* Caller must hold efx->filter_sem for read if race against
4840  * efx_ef10_filter_table_remove() is possible
4841  */
4842 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4843 {
4844         struct efx_ef10_filter_table *table = efx->filter_state;
4845         struct net_device *net_dev = efx->net_dev;
4846         struct efx_ef10_filter_vlan *vlan;
4847         bool vlan_filter;
4848
4849         if (!efx_dev_registered(efx))
4850                 return;
4851
4852         if (!table)
4853                 return;
4854
4855         efx_ef10_filter_mark_old(efx);
4856
4857         /* Copy/convert the address lists; add the primary station
4858          * address and broadcast address
4859          */
4860         netif_addr_lock_bh(net_dev);
4861         efx_ef10_filter_uc_addr_list(efx);
4862         efx_ef10_filter_mc_addr_list(efx);
4863         netif_addr_unlock_bh(net_dev);
4864
4865         /* If VLAN filtering changes, all old filters are finally removed.
4866          * Do it in advance to avoid conflicts for unicast untagged and
4867          * VLAN 0 tagged filters.
4868          */
4869         vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4870         if (table->vlan_filter != vlan_filter) {
4871                 table->vlan_filter = vlan_filter;
4872                 efx_ef10_filter_remove_old(efx);
4873         }
4874
4875         list_for_each_entry(vlan, &table->vlan_list, list)
4876                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4877
4878         efx_ef10_filter_remove_old(efx);
4879         table->mc_promisc_last = table->mc_promisc;
4880 }
4881
4882 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4883 {
4884         struct efx_ef10_filter_table *table = efx->filter_state;
4885         struct efx_ef10_filter_vlan *vlan;
4886
4887         WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4888
4889         list_for_each_entry(vlan, &table->vlan_list, list) {
4890                 if (vlan->vid == vid)
4891                         return vlan;
4892         }
4893
4894         return NULL;
4895 }
4896
4897 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4898 {
4899         struct efx_ef10_filter_table *table = efx->filter_state;
4900         struct efx_ef10_filter_vlan *vlan;
4901         unsigned int i;
4902
4903         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4904                 return -EINVAL;
4905
4906         vlan = efx_ef10_filter_find_vlan(efx, vid);
4907         if (WARN_ON(vlan)) {
4908                 netif_err(efx, drv, efx->net_dev,
4909                           "VLAN %u already added\n", vid);
4910                 return -EALREADY;
4911         }
4912
4913         vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4914         if (!vlan)
4915                 return -ENOMEM;
4916
4917         vlan->vid = vid;
4918
4919         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4920                 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4921         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4922                 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4923         vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4924         vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4925         vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4926
4927         list_add_tail(&vlan->list, &table->vlan_list);
4928
4929         if (efx_dev_registered(efx))
4930                 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4931
4932         return 0;
4933 }
4934
4935 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4936                                               struct efx_ef10_filter_vlan *vlan)
4937 {
4938         unsigned int i;
4939
4940         /* See comment in efx_ef10_filter_table_remove() */
4941         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4942                 return;
4943
4944         list_del(&vlan->list);
4945
4946         for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4947                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4948                                               vlan->uc[i]);
4949         for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4950                 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4951                                               vlan->mc[i]);
4952         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4953         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4954         efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
4955
4956         kfree(vlan);
4957 }
4958
4959 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4960 {
4961         struct efx_ef10_filter_vlan *vlan;
4962
4963         /* See comment in efx_ef10_filter_table_remove() */
4964         if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4965                 return;
4966
4967         vlan = efx_ef10_filter_find_vlan(efx, vid);
4968         if (!vlan) {
4969                 netif_err(efx, drv, efx->net_dev,
4970                           "VLAN %u not found in filter state\n", vid);
4971                 return;
4972         }
4973
4974         efx_ef10_filter_del_vlan_internal(efx, vlan);
4975 }
4976
4977 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4978 {
4979         MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4980         struct efx_ef10_nic_data *nic_data = efx->nic_data;
4981         bool was_enabled = efx->port_enabled;
4982         int rc;
4983
4984         efx_device_detach_sync(efx);
4985         efx_net_stop(efx->net_dev);
4986
4987         mutex_lock(&efx->mac_lock);
4988         down_write(&efx->filter_sem);
4989         efx_ef10_filter_table_remove(efx);
4990
4991         ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4992                         efx->net_dev->dev_addr);
4993         MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4994                        nic_data->vport_id);
4995         rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4996                                 sizeof(inbuf), NULL, 0, NULL);
4997
4998         efx_ef10_filter_table_probe(efx);
4999         up_write(&efx->filter_sem);
5000         mutex_unlock(&efx->mac_lock);
5001
5002         if (was_enabled)
5003                 efx_net_open(efx->net_dev);
5004         netif_device_attach(efx->net_dev);
5005
5006 #ifdef CONFIG_SFC_SRIOV
5007         if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
5008                 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
5009
5010                 if (rc == -EPERM) {
5011                         struct efx_nic *efx_pf;
5012
5013                         /* Switch to PF and change MAC address on vport */
5014                         efx_pf = pci_get_drvdata(pci_dev_pf);
5015
5016                         rc = efx_ef10_sriov_set_vf_mac(efx_pf,
5017                                                        nic_data->vf_index,
5018                                                        efx->net_dev->dev_addr);
5019                 } else if (!rc) {
5020                         struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
5021                         struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
5022                         unsigned int i;
5023
5024                         /* MAC address successfully changed by VF (with MAC
5025                          * spoofing) so update the parent PF if possible.
5026                          */
5027                         for (i = 0; i < efx_pf->vf_count; ++i) {
5028                                 struct ef10_vf *vf = nic_data->vf + i;
5029
5030                                 if (vf->efx == efx) {
5031                                         ether_addr_copy(vf->mac,
5032                                                         efx->net_dev->dev_addr);
5033                                         return 0;
5034                                 }
5035                         }
5036                 }
5037         } else
5038 #endif
5039         if (rc == -EPERM) {
5040                 netif_err(efx, drv, efx->net_dev,
5041                           "Cannot change MAC address; use sfboot to enable"
5042                           " mac-spoofing on this interface\n");
5043         } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
5044                 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
5045                  * fall-back to the method of changing the MAC address on the
5046                  * vport.  This only applies to PFs because such versions of
5047                  * MCFW do not support VFs.
5048                  */
5049                 rc = efx_ef10_vport_set_mac_address(efx);
5050         } else {
5051                 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
5052                                        sizeof(inbuf), NULL, 0, rc);
5053         }
5054
5055         return rc;
5056 }
5057
5058 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
5059 {
5060         efx_ef10_filter_sync_rx_mode(efx);
5061
5062         return efx_mcdi_set_mac(efx);
5063 }
5064
5065 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
5066 {
5067         efx_ef10_filter_sync_rx_mode(efx);
5068
5069         return 0;
5070 }
5071
5072 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
5073 {
5074         MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
5075
5076         MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
5077         return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
5078                             NULL, 0, NULL);
5079 }
5080
5081 /* MC BISTs follow a different poll mechanism to phy BISTs.
5082  * The BIST is done in the poll handler on the MC, and the MCDI command
5083  * will block until the BIST is done.
5084  */
5085 static int efx_ef10_poll_bist(struct efx_nic *efx)
5086 {
5087         int rc;
5088         MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
5089         size_t outlen;
5090         u32 result;
5091
5092         rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
5093                            outbuf, sizeof(outbuf), &outlen);
5094         if (rc != 0)
5095                 return rc;
5096
5097         if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
5098                 return -EIO;
5099
5100         result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
5101         switch (result) {
5102         case MC_CMD_POLL_BIST_PASSED:
5103                 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
5104                 return 0;
5105         case MC_CMD_POLL_BIST_TIMEOUT:
5106                 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
5107                 return -EIO;
5108         case MC_CMD_POLL_BIST_FAILED:
5109                 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
5110                 return -EIO;
5111         default:
5112                 netif_err(efx, hw, efx->net_dev,
5113                           "BIST returned unknown result %u", result);
5114                 return -EIO;
5115         }
5116 }
5117
5118 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
5119 {
5120         int rc;
5121
5122         netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
5123
5124         rc = efx_ef10_start_bist(efx, bist_type);
5125         if (rc != 0)
5126                 return rc;
5127
5128         return efx_ef10_poll_bist(efx);
5129 }
5130
5131 static int
5132 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
5133 {
5134         int rc, rc2;
5135
5136         efx_reset_down(efx, RESET_TYPE_WORLD);
5137
5138         rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
5139                           NULL, 0, NULL, 0, NULL);
5140         if (rc != 0)
5141                 goto out;
5142
5143         tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
5144         tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
5145
5146         rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
5147
5148 out:
5149         if (rc == -EPERM)
5150                 rc = 0;
5151         rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
5152         return rc ? rc : rc2;
5153 }
5154
5155 #ifdef CONFIG_SFC_MTD
5156
5157 struct efx_ef10_nvram_type_info {
5158         u16 type, type_mask;
5159         u8 port;
5160         const char *name;
5161 };
5162
5163 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
5164         { NVRAM_PARTITION_TYPE_MC_FIRMWARE,        0,    0, "sfc_mcfw" },
5165         { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0,    0, "sfc_mcfw_backup" },
5166         { NVRAM_PARTITION_TYPE_EXPANSION_ROM,      0,    0, "sfc_exp_rom" },
5167         { NVRAM_PARTITION_TYPE_STATIC_CONFIG,      0,    0, "sfc_static_cfg" },
5168         { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG,     0,    0, "sfc_dynamic_cfg" },
5169         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0,   0, "sfc_exp_rom_cfg" },
5170         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0,   1, "sfc_exp_rom_cfg" },
5171         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0,   2, "sfc_exp_rom_cfg" },
5172         { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0,   3, "sfc_exp_rom_cfg" },
5173         { NVRAM_PARTITION_TYPE_LICENSE,            0,    0, "sfc_license" },
5174         { NVRAM_PARTITION_TYPE_PHY_MIN,            0xff, 0, "sfc_phy_fw" },
5175 };
5176
5177 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
5178                                         struct efx_mcdi_mtd_partition *part,
5179                                         unsigned int type)
5180 {
5181         MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
5182         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
5183         const struct efx_ef10_nvram_type_info *info;
5184         size_t size, erase_size, outlen;
5185         bool protected;
5186         int rc;
5187
5188         for (info = efx_ef10_nvram_types; ; info++) {
5189                 if (info ==
5190                     efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
5191                         return -ENODEV;
5192                 if ((type & ~info->type_mask) == info->type)
5193                         break;
5194         }
5195         if (info->port != efx_port_num(efx))
5196                 return -ENODEV;
5197
5198         rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
5199         if (rc)
5200                 return rc;
5201         if (protected)
5202                 return -ENODEV; /* hide it */
5203
5204         part->nvram_type = type;
5205
5206         MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
5207         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
5208                           outbuf, sizeof(outbuf), &outlen);
5209         if (rc)
5210                 return rc;
5211         if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
5212                 return -EIO;
5213         if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
5214             (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
5215                 part->fw_subtype = MCDI_DWORD(outbuf,
5216                                               NVRAM_METADATA_OUT_SUBTYPE);
5217
5218         part->common.dev_type_name = "EF10 NVRAM manager";
5219         part->common.type_name = info->name;
5220
5221         part->common.mtd.type = MTD_NORFLASH;
5222         part->common.mtd.flags = MTD_CAP_NORFLASH;
5223         part->common.mtd.size = size;
5224         part->common.mtd.erasesize = erase_size;
5225
5226         return 0;
5227 }
5228
5229 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5230 {
5231         MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5232         struct efx_mcdi_mtd_partition *parts;
5233         size_t outlen, n_parts_total, i, n_parts;
5234         unsigned int type;
5235         int rc;
5236
5237         ASSERT_RTNL();
5238
5239         BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5240         rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5241                           outbuf, sizeof(outbuf), &outlen);
5242         if (rc)
5243                 return rc;
5244         if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5245                 return -EIO;
5246
5247         n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5248         if (n_parts_total >
5249             MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5250                 return -EIO;
5251
5252         parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5253         if (!parts)
5254                 return -ENOMEM;
5255
5256         n_parts = 0;
5257         for (i = 0; i < n_parts_total; i++) {
5258                 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5259                                         i);
5260                 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5261                 if (rc == 0)
5262                         n_parts++;
5263                 else if (rc != -ENODEV)
5264                         goto fail;
5265         }
5266
5267         rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5268 fail:
5269         if (rc)
5270                 kfree(parts);
5271         return rc;
5272 }
5273
5274 #endif /* CONFIG_SFC_MTD */
5275
5276 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5277 {
5278         _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5279 }
5280
5281 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5282                                             u32 host_time) {}
5283
5284 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5285                                            bool temp)
5286 {
5287         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5288         int rc;
5289
5290         if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5291             channel->sync_events_state == SYNC_EVENTS_VALID ||
5292             (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5293                 return 0;
5294         channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5295
5296         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5297         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5298         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5299                        channel->channel);
5300
5301         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5302                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5303
5304         if (rc != 0)
5305                 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5306                                                     SYNC_EVENTS_DISABLED;
5307
5308         return rc;
5309 }
5310
5311 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5312                                             bool temp)
5313 {
5314         MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5315         int rc;
5316
5317         if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5318             (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5319                 return 0;
5320         if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5321                 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5322                 return 0;
5323         }
5324         channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5325                                             SYNC_EVENTS_DISABLED;
5326
5327         MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5328         MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5329         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5330                        MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5331         MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5332                        channel->channel);
5333
5334         rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5335                           inbuf, sizeof(inbuf), NULL, 0, NULL);
5336
5337         return rc;
5338 }
5339
5340 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5341                                            bool temp)
5342 {
5343         int (*set)(struct efx_channel *channel, bool temp);
5344         struct efx_channel *channel;
5345
5346         set = en ?
5347               efx_ef10_rx_enable_timestamping :
5348               efx_ef10_rx_disable_timestamping;
5349
5350         efx_for_each_channel(channel, efx) {
5351                 int rc = set(channel, temp);
5352                 if (en && rc != 0) {
5353                         efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5354                         return rc;
5355                 }
5356         }
5357
5358         return 0;
5359 }
5360
5361 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5362                                          struct hwtstamp_config *init)
5363 {
5364         return -EOPNOTSUPP;
5365 }
5366
5367 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5368                                       struct hwtstamp_config *init)
5369 {
5370         int rc;
5371
5372         switch (init->rx_filter) {
5373         case HWTSTAMP_FILTER_NONE:
5374                 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5375                 /* if TX timestamping is still requested then leave PTP on */
5376                 return efx_ptp_change_mode(efx,
5377                                            init->tx_type != HWTSTAMP_TX_OFF, 0);
5378         case HWTSTAMP_FILTER_ALL:
5379         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5380         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5381         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5382         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5383         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5384         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5385         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5386         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5387         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5388         case HWTSTAMP_FILTER_PTP_V2_EVENT:
5389         case HWTSTAMP_FILTER_PTP_V2_SYNC:
5390         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5391                 init->rx_filter = HWTSTAMP_FILTER_ALL;
5392                 rc = efx_ptp_change_mode(efx, true, 0);
5393                 if (!rc)
5394                         rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5395                 if (rc)
5396                         efx_ptp_change_mode(efx, false, 0);
5397                 return rc;
5398         default:
5399                 return -ERANGE;
5400         }
5401 }
5402
5403 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5404 {
5405         if (proto != htons(ETH_P_8021Q))
5406                 return -EINVAL;
5407
5408         return efx_ef10_add_vlan(efx, vid);
5409 }
5410
5411 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5412 {
5413         if (proto != htons(ETH_P_8021Q))
5414                 return -EINVAL;
5415
5416         return efx_ef10_del_vlan(efx, vid);
5417 }
5418
5419 #define EF10_OFFLOAD_FEATURES           \
5420         (NETIF_F_IP_CSUM |              \
5421          NETIF_F_HW_VLAN_CTAG_FILTER |  \
5422          NETIF_F_IPV6_CSUM |            \
5423          NETIF_F_RXHASH |               \
5424          NETIF_F_NTUPLE)
5425
5426 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5427         .is_vf = true,
5428         .mem_bar = EFX_MEM_VF_BAR,
5429         .mem_map_size = efx_ef10_mem_map_size,
5430         .probe = efx_ef10_probe_vf,
5431         .remove = efx_ef10_remove,
5432         .dimension_resources = efx_ef10_dimension_resources,
5433         .init = efx_ef10_init_nic,
5434         .fini = efx_port_dummy_op_void,
5435         .map_reset_reason = efx_ef10_map_reset_reason,
5436         .map_reset_flags = efx_ef10_map_reset_flags,
5437         .reset = efx_ef10_reset,
5438         .probe_port = efx_mcdi_port_probe,
5439         .remove_port = efx_mcdi_port_remove,
5440         .fini_dmaq = efx_ef10_fini_dmaq,
5441         .prepare_flr = efx_ef10_prepare_flr,
5442         .finish_flr = efx_port_dummy_op_void,
5443         .describe_stats = efx_ef10_describe_stats,
5444         .update_stats = efx_ef10_update_stats_vf,
5445         .start_stats = efx_port_dummy_op_void,
5446         .pull_stats = efx_port_dummy_op_void,
5447         .stop_stats = efx_port_dummy_op_void,
5448         .set_id_led = efx_mcdi_set_id_led,
5449         .push_irq_moderation = efx_ef10_push_irq_moderation,
5450         .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5451         .check_mac_fault = efx_mcdi_mac_check_fault,
5452         .reconfigure_port = efx_mcdi_port_reconfigure,
5453         .get_wol = efx_ef10_get_wol_vf,
5454         .set_wol = efx_ef10_set_wol_vf,
5455         .resume_wol = efx_port_dummy_op_void,
5456         .mcdi_request = efx_ef10_mcdi_request,
5457         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5458         .mcdi_read_response = efx_ef10_mcdi_read_response,
5459         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5460         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5461         .irq_enable_master = efx_port_dummy_op_void,
5462         .irq_test_generate = efx_ef10_irq_test_generate,
5463         .irq_disable_non_ev = efx_port_dummy_op_void,
5464         .irq_handle_msi = efx_ef10_msi_interrupt,
5465         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5466         .tx_probe = efx_ef10_tx_probe,
5467         .tx_init = efx_ef10_tx_init,
5468         .tx_remove = efx_ef10_tx_remove,
5469         .tx_write = efx_ef10_tx_write,
5470         .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5471         .rx_probe = efx_ef10_rx_probe,
5472         .rx_init = efx_ef10_rx_init,
5473         .rx_remove = efx_ef10_rx_remove,
5474         .rx_write = efx_ef10_rx_write,
5475         .rx_defer_refill = efx_ef10_rx_defer_refill,
5476         .ev_probe = efx_ef10_ev_probe,
5477         .ev_init = efx_ef10_ev_init,
5478         .ev_fini = efx_ef10_ev_fini,
5479         .ev_remove = efx_ef10_ev_remove,
5480         .ev_process = efx_ef10_ev_process,
5481         .ev_read_ack = efx_ef10_ev_read_ack,
5482         .ev_test_generate = efx_ef10_ev_test_generate,
5483         .filter_table_probe = efx_ef10_filter_table_probe,
5484         .filter_table_restore = efx_ef10_filter_table_restore,
5485         .filter_table_remove = efx_ef10_filter_table_remove,
5486         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5487         .filter_insert = efx_ef10_filter_insert,
5488         .filter_remove_safe = efx_ef10_filter_remove_safe,
5489         .filter_get_safe = efx_ef10_filter_get_safe,
5490         .filter_clear_rx = efx_ef10_filter_clear_rx,
5491         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5492         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5493         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5494 #ifdef CONFIG_RFS_ACCEL
5495         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5496         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5497 #endif
5498 #ifdef CONFIG_SFC_MTD
5499         .mtd_probe = efx_port_dummy_op_int,
5500 #endif
5501         .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5502         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5503         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5504         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5505 #ifdef CONFIG_SFC_SRIOV
5506         .vswitching_probe = efx_ef10_vswitching_probe_vf,
5507         .vswitching_restore = efx_ef10_vswitching_restore_vf,
5508         .vswitching_remove = efx_ef10_vswitching_remove_vf,
5509         .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5510 #endif
5511         .get_mac_address = efx_ef10_get_mac_address_vf,
5512         .set_mac_address = efx_ef10_set_mac_address,
5513
5514         .revision = EFX_REV_HUNT_A0,
5515         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5516         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5517         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5518         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5519         .can_rx_scatter = true,
5520         .always_rx_scatter = true,
5521         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5522         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5523         .offload_features = EF10_OFFLOAD_FEATURES,
5524         .mcdi_max_ver = 2,
5525         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5526         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5527                             1 << HWTSTAMP_FILTER_ALL,
5528 };
5529
5530 const struct efx_nic_type efx_hunt_a0_nic_type = {
5531         .is_vf = false,
5532         .mem_bar = EFX_MEM_BAR,
5533         .mem_map_size = efx_ef10_mem_map_size,
5534         .probe = efx_ef10_probe_pf,
5535         .remove = efx_ef10_remove,
5536         .dimension_resources = efx_ef10_dimension_resources,
5537         .init = efx_ef10_init_nic,
5538         .fini = efx_port_dummy_op_void,
5539         .map_reset_reason = efx_ef10_map_reset_reason,
5540         .map_reset_flags = efx_ef10_map_reset_flags,
5541         .reset = efx_ef10_reset,
5542         .probe_port = efx_mcdi_port_probe,
5543         .remove_port = efx_mcdi_port_remove,
5544         .fini_dmaq = efx_ef10_fini_dmaq,
5545         .prepare_flr = efx_ef10_prepare_flr,
5546         .finish_flr = efx_port_dummy_op_void,
5547         .describe_stats = efx_ef10_describe_stats,
5548         .update_stats = efx_ef10_update_stats_pf,
5549         .start_stats = efx_mcdi_mac_start_stats,
5550         .pull_stats = efx_mcdi_mac_pull_stats,
5551         .stop_stats = efx_mcdi_mac_stop_stats,
5552         .set_id_led = efx_mcdi_set_id_led,
5553         .push_irq_moderation = efx_ef10_push_irq_moderation,
5554         .reconfigure_mac = efx_ef10_mac_reconfigure,
5555         .check_mac_fault = efx_mcdi_mac_check_fault,
5556         .reconfigure_port = efx_mcdi_port_reconfigure,
5557         .get_wol = efx_ef10_get_wol,
5558         .set_wol = efx_ef10_set_wol,
5559         .resume_wol = efx_port_dummy_op_void,
5560         .test_chip = efx_ef10_test_chip,
5561         .test_nvram = efx_mcdi_nvram_test_all,
5562         .mcdi_request = efx_ef10_mcdi_request,
5563         .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5564         .mcdi_read_response = efx_ef10_mcdi_read_response,
5565         .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5566         .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5567         .irq_enable_master = efx_port_dummy_op_void,
5568         .irq_test_generate = efx_ef10_irq_test_generate,
5569         .irq_disable_non_ev = efx_port_dummy_op_void,
5570         .irq_handle_msi = efx_ef10_msi_interrupt,
5571         .irq_handle_legacy = efx_ef10_legacy_interrupt,
5572         .tx_probe = efx_ef10_tx_probe,
5573         .tx_init = efx_ef10_tx_init,
5574         .tx_remove = efx_ef10_tx_remove,
5575         .tx_write = efx_ef10_tx_write,
5576         .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5577         .rx_probe = efx_ef10_rx_probe,
5578         .rx_init = efx_ef10_rx_init,
5579         .rx_remove = efx_ef10_rx_remove,
5580         .rx_write = efx_ef10_rx_write,
5581         .rx_defer_refill = efx_ef10_rx_defer_refill,
5582         .ev_probe = efx_ef10_ev_probe,
5583         .ev_init = efx_ef10_ev_init,
5584         .ev_fini = efx_ef10_ev_fini,
5585         .ev_remove = efx_ef10_ev_remove,
5586         .ev_process = efx_ef10_ev_process,
5587         .ev_read_ack = efx_ef10_ev_read_ack,
5588         .ev_test_generate = efx_ef10_ev_test_generate,
5589         .filter_table_probe = efx_ef10_filter_table_probe,
5590         .filter_table_restore = efx_ef10_filter_table_restore,
5591         .filter_table_remove = efx_ef10_filter_table_remove,
5592         .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5593         .filter_insert = efx_ef10_filter_insert,
5594         .filter_remove_safe = efx_ef10_filter_remove_safe,
5595         .filter_get_safe = efx_ef10_filter_get_safe,
5596         .filter_clear_rx = efx_ef10_filter_clear_rx,
5597         .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5598         .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5599         .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5600 #ifdef CONFIG_RFS_ACCEL
5601         .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5602         .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5603 #endif
5604 #ifdef CONFIG_SFC_MTD
5605         .mtd_probe = efx_ef10_mtd_probe,
5606         .mtd_rename = efx_mcdi_mtd_rename,
5607         .mtd_read = efx_mcdi_mtd_read,
5608         .mtd_erase = efx_mcdi_mtd_erase,
5609         .mtd_write = efx_mcdi_mtd_write,
5610         .mtd_sync = efx_mcdi_mtd_sync,
5611 #endif
5612         .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5613         .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5614         .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5615         .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5616         .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5617 #ifdef CONFIG_SFC_SRIOV
5618         .sriov_configure = efx_ef10_sriov_configure,
5619         .sriov_init = efx_ef10_sriov_init,
5620         .sriov_fini = efx_ef10_sriov_fini,
5621         .sriov_wanted = efx_ef10_sriov_wanted,
5622         .sriov_reset = efx_ef10_sriov_reset,
5623         .sriov_flr = efx_ef10_sriov_flr,
5624         .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5625         .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5626         .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5627         .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5628         .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5629         .vswitching_probe = efx_ef10_vswitching_probe_pf,
5630         .vswitching_restore = efx_ef10_vswitching_restore_pf,
5631         .vswitching_remove = efx_ef10_vswitching_remove_pf,
5632 #endif
5633         .get_mac_address = efx_ef10_get_mac_address_pf,
5634         .set_mac_address = efx_ef10_set_mac_address,
5635
5636         .revision = EFX_REV_HUNT_A0,
5637         .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5638         .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5639         .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5640         .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5641         .can_rx_scatter = true,
5642         .always_rx_scatter = true,
5643         .max_interrupt_mode = EFX_INT_MODE_MSIX,
5644         .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5645         .offload_features = EF10_OFFLOAD_FEATURES,
5646         .mcdi_max_ver = 2,
5647         .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5648         .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5649                             1 << HWTSTAMP_FILTER_ALL,
5650 };